WO2017053473A1 - Prévention de mélange dans des dispositifs électrochimiques - Google Patents

Prévention de mélange dans des dispositifs électrochimiques Download PDF

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Publication number
WO2017053473A1
WO2017053473A1 PCT/US2016/052946 US2016052946W WO2017053473A1 WO 2017053473 A1 WO2017053473 A1 WO 2017053473A1 US 2016052946 W US2016052946 W US 2016052946W WO 2017053473 A1 WO2017053473 A1 WO 2017053473A1
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WO
WIPO (PCT)
Prior art keywords
layer
intermixing
barrier layer
substrate
current collector
Prior art date
Application number
PCT/US2016/052946
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English (en)
Inventor
Lizhong Sun
Miaojun WANG
Byung-Sung Leo Kwak
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Applied Materials, Inc.
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Publication date
Application filed by Applied Materials, Inc. filed Critical Applied Materials, Inc.
Priority to US15/389,050 priority Critical patent/US20170149093A1/en
Publication of WO2017053473A1 publication Critical patent/WO2017053473A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M4/00—Electrodes
    • H01M4/02—Electrodes composed of, or comprising, active material
    • H01M4/36—Selection of substances as active materials, active masses, active liquids
    • H01M4/48—Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides
    • H01M4/52—Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron
    • H01M4/525—Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M10/00—Secondary cells; Manufacture thereof
    • H01M10/04—Construction or manufacture in general
    • H01M10/0436—Small-sized flat cells or batteries for portable equipment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M10/00—Secondary cells; Manufacture thereof
    • H01M10/05—Accumulators with non-aqueous electrolyte
    • H01M10/052—Li-accumulators
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M10/00—Secondary cells; Manufacture thereof
    • H01M10/05—Accumulators with non-aqueous electrolyte
    • H01M10/056—Accumulators with non-aqueous electrolyte characterised by the materials used as electrolytes, e.g. mixed inorganic/organic electrolytes
    • H01M10/0561—Accumulators with non-aqueous electrolyte characterised by the materials used as electrolytes, e.g. mixed inorganic/organic electrolytes the electrolyte being constituted of inorganic materials only
    • H01M10/0562—Solid materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M10/00—Secondary cells; Manufacture thereof
    • H01M10/05—Accumulators with non-aqueous electrolyte
    • H01M10/058—Construction or manufacture
    • H01M10/0585—Construction or manufacture of accumulators having only flat construction elements, i.e. flat positive electrodes, flat negative electrodes and flat separators
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M4/00—Electrodes
    • H01M4/02—Electrodes composed of, or comprising, active material
    • H01M4/04—Processes of manufacture in general
    • H01M4/0471—Processes of manufacture in general involving thermal treatment, e.g. firing, sintering, backing particulate active material, thermal decomposition, pyrolysis
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M4/00—Electrodes
    • H01M4/02—Electrodes composed of, or comprising, active material
    • H01M4/13—Electrodes for accumulators with non-aqueous electrolyte, e.g. for lithium-accumulators; Processes of manufacture thereof
    • H01M4/139—Processes of manufacture
    • H01M4/1391—Processes of manufacture of electrodes based on mixed oxides or hydroxides, or on mixtures of oxides or hydroxides, e.g. LiCoOx
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M6/00—Primary cells; Manufacture thereof
    • H01M6/40—Printed batteries, e.g. thin film batteries
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/10—Energy storage using batteries

Definitions

  • Thin film batteries may comprise a thin film stack of layers including anode and cathode current collectors (ACC, CCC), a cathode (positive electrode), a solid state electrolyte, an anode (negative electrode) and encapsulation layers or packaging.
  • ACC anode and cathode current collectors
  • CCC cathode current collectors
  • solid state electrolyte an anode (negative electrode)
  • encapsulation layers or packaging may comprise a thin film stack of layers including anode and cathode current collectors (ACC, CCC), a cathode (positive electrode), a solid state electrolyte, an anode (negative electrode) and encapsulation layers or packaging.
  • the positive electrode typically formed of a material such as lithium cobalt oxide (LCO) which needs to be annealed, at relatively high temperature, to form an electrode with desirable materials properties - such as having a high percentage (greater than 90%) of high temperature phase LiCoO 2 (HT-LCO).
  • LCO lithium cobalt oxide
  • HT-LCO high temperature phase LiCoO 2
  • This intermixing may be observed visually through the backside of an optically transparent/translucent substrate - as discussed in more detail below - and results in deterioration of device performance, due to increased resistance of the CCC (due to LCO in the CCC) and/or reduced ef fectiveness of the positive electrode (due to CCC material in the positive electrode), which is measureable during battery cell cycling tests as lower battery cell capacity utilization, higher IR drop, etc. Furthermore, the intermixing may reduce mechanical yield of TFBs and be manifest in wafer/substrate curvature.
  • a thin substrate is a polycrystalline ceramic substrate such as yttria-stabilized zirconium oxide (YSZ). While these YSZ substrates can withstand much higher thermal budget, including annealing beyond 600 °C to form a higher quality LCO with purer phase and greater crystallinity (greater than 90% HT-LiCO, by weight or by volume), the present inventors found that the intermixing of the CCC layers and the LiCoO 2 layer during the LCO annealing process is quite significant leading to device stability and performance issues, as indicated above.
  • YSZ yttria-stabilized zirconium oxide
  • a thin film battery may comprise: an intermixing barrier layer on a thin substrate with a substrate thickness in the range of 10 microns to 100 microns, the intermixing barrier layer comprising an electrically insulating material, the intermixing barrier layer having a thickness in the range of 50 nm to 5,000 nm; a patterned current collector layer on the intermixing barrier layer; and a cathode layer on the patterned current collector layer, wherein the intermixing barrier layer, the patterned current collector layer and the cathode layer form a stack on the thin substrate, the cathode layer having been annealed at a temperature in the range of 500 °C to 800 °C, with a soak time in the range of 2 to 30 hours; wherein the intermixing barrier layer prevents intermixing of the current collector layer and the cathode layer during the annealing of the cathode layer.
  • a method for manufacturing thin film batteries may comprise: depositing an intermixing barrier layer on a thin substrate with a substrate thickness in the range of 10 microns to 100 microns, the intermixing barrier layer comprising an electrically insulating material, the intermixing barrier layer having a thickness in the range of 50 nm to 5,000 nm; depositing a current collector layer on the intermixing barrier layer and patterning the current collector layer; depositing a cathode layer on the patterned current collector layer to form a stack on the thin substrate; and annealing the stack, at a temperature in the range of 500 °C to 800 °C; wherein the intermixing barrier layer prevents intermixing of the patterned current collector layer and the cathode layer.
  • an apparatus for manufacturing thin film batteries may comprise: a first system for depositing an intermixing barrier layer on a thin substrate with a substrate thickness in the range of 10 microns to 1 00 microns, the intermixing barrier layer comprising an electrically insulating material, the intermixing barrier layer having a thickness in the range of 50 nm to 5,000 nm; a second system for depositing a current collector layer on the intermixing barrier layer and patterning the current collector layer; a third system for depositing a cathode layer on the patterned current collector layer to form a stack on the thin substrate; and a fourth system for annealing the stack, at a temperature in the range of 500 °C to 800 °C; wherein the intermixing barrier layer prevents intermixing of the patterned current collector layer and the cathode layer.
  • FIG. 1 is a cross-sectional representation of a thin film battery including an intermixing barrier layer between the substrate and adhesion and current collector layers, according to some embodiments;
  • FIG. 2 is a schematic illustration of a cluster tool for TFB fabrication, according to some embodiments.
  • FIG. 3 is a representation of a TFB fabrication system with multiple in-line tools, according to some embodiments.
  • FIG. 4 is a representation of an in-line tool of FIG. 3, according to some embodiments.
  • F1G.1 shows an example of a TFB device 100 according to some embodiments comprising: a substrate 1 10 (such as YSZ ceramic, with 2 to 8 weight percent yttria and other minor impurities), an intermixing barrier layer 120 over the top substrate surface, an adhesion layer 130 (e.g. Ti) and cathode current collector (CCC) 140 (e.g. Au, Pt) on the top surface of the intermixing barrier layer, a cathode 150 (a layer of LCO, for example) on the CCC, an electrolyte 160 covering the cathode and portions of the CCC, isolating the CCC from any other electrodes, an anode 1 70 (e.g.
  • the adhesion layer 130 is also provided between the intermixing barrier layer and the ACC if needed, but may not be needed in all embodiments.
  • TFB device of FIG. 1 An example of the TFB device of FIG. 1 is described in more detail, as follows.
  • the TFB of FIG. 1 would ordinarily be fabricated using shadow masks, and is described as such below, although it is appreciated by persons of ordinary skill in the art that a maskless fabrication process may be used to fabricate TFBs with the same materials and order of layers in the device stack, just with a slightly different layout,
  • the thin substrate for example a glass, ceramic, metal or silicon substrate may have a thickness within the range from 10 ⁇ m to 700 ⁇ m. The layers deposited on the substrate are described next.
  • the intermixing barrier layer may comprise one or more of AI2O3, S13N4 and other electrically insulating layers (including suboxides, stoichiometric and nonstoichiometric variations, and crystalline, amorphous and mixed phase versions of the same) with a thickness in the range of 50 nm to 5000 nm, in embodiments in the range of 50 nm to 500 nm, and in embodiments in the range of 100 nm to 300 nm, deposited on the surface of the thin substrate, An adhesion metal layer (e.g., Ti, Ta, TaN) with an area larger than that of the cathode layer with thickness ranging from 10 nm to 1000 nm is deposited on the substrate barrier layer.
  • AI2O3, S13N4 and other electrically insulating layers including suboxides, stoichiometric and nonstoichiometric variations, and crystalline, amorphous and mixed phase versions of the same
  • An adhesion metal layer e.
  • a cathode current collector e.g., Au, Pt
  • a cathode layer e.g., LiCoO 2
  • the stack is thermalfy treated to anneal the cathode layer, as needed, before further deposition steps.
  • a solid state electrolyte layer (e.g., UPON) having a larger area than and extending beyond the cathode and the cathode current collector (except for the electrical contact area, where the CCC is left uncovered) with thickness ranging from 0.5 ⁇ m to 4 ,um is deposited on top of the interlayer.
  • An anode current collector e.g., Cu, Au, Pt
  • anode current collector with no overlap with the cathode layer and the cathode current collector and with thickness ranging from 100 nm to 1000 nm is deposited on top of the solid state electrolyte;
  • an adhesion metal layer may be deposited before the anode current collector, if needed, in a manner similar to that used for the cathode current collector layer.
  • An anode e.g., Li metal
  • An encapsulation layer of varying functions with an area larger than that of the anode layer and smaller than that of the electrolyte layer, with thickness ranging from 400 nm to 3 ⁇ m is deposited on top of the anode layer; the encapsulation layer can be a combination of a metal layer (e.g. Cu, Au, Pt) and a dielectric layer (such as LiPON, A1 2 O 3 , ZrO 2, SiO 2 , Si 3 N4, planarizing polymer layers, etc.).
  • a metal layer e.g. Cu, Au, Pt
  • a dielectric layer such as LiPON, A1 2 O 3 , ZrO 2, SiO 2 , Si 3 N4, planarizing polymer layers, etc.
  • the intermixing barrier layer of FIG. 1 is incorporated in embodiments into the device stack to overcome problems due to intermixing of the adhesion layer and current collector layers with the LCO cathode observed in devices without the intermixing barrier layer as described in more detail below.
  • the present disclosure provides that the substrate surface is modified by the addition of a layer with a high ion packing density, which creates a smoother surface and/or less porous layer, over which a smooth and dense CCC layer (CCC with a smooth surface and/or less porous layer) may be formed and at the same time exhibit better adhesion properties between the substrate and the CCC, bi-directionally.
  • a layer with a high ion packing density which creates a smoother surface and/or less porous layer
  • a smooth and dense CCC layer CCC with a smooth surface and/or less porous layer
  • the intermixing barrier layer may in embodiments function to limit interdiffusion of atoms/ions between the substrate and the CCC layer.
  • a thin, dense and electrically insulating (with a resistance greater than 30 ⁇ , for example) intermixing barrier layer e.g., AI 2 O 3 with a 65.6% ion packing density
  • intermixing barrier layer e.g., AI 2 O 3 with a 65.6% ion packing density
  • Deposition of alumina films optimized for intermixing prevention with smoother surfaces and/or less porous bulk may be achieved using physical vapor deposition (PVD) at higher areal power densities (greater than 3.5 W/cm 2 , for example) in an argon/oxygen gas plasma environment, for example, It is expected that alumina with composition AIO x where x is in the range of 1.2 to 1.5 may have the desired properties for some embodiments.
  • PVD physical vapor deposition
  • the intermixing barrier layer could be AI 2 O 3 , S13N4 and other electrically insulating layers (including suboxides, stoichiometric and nonstoichiometric variations, and crystalline, amorphous and mixed phase versions of the same) with higher cation packing density than Zr ions in the ZrO 2 unit cell of the YSZ substrate and stability (maintains mechanical strength, stable chemical composition, for example) at temperatures in excess of 700 °C.
  • the thickness of the intermixing barrier layer is in the range of 50 nm to 5000 nm, in embodiments in the range of 50 nm to 500 nm, and in embodiments in the range of 100 nm to 300 nm.
  • the stack was annealed at 650 °C and no intermixing of the LCO and CCC layers was observed through the transparent substrate - there was no discoloration or signs of delamination of the layers.
  • the YSZ substrate with alumina intermixing barrier layer does not show discoloration, while the YSZ substrate without the intermixing barrier iayer does show discoloration (the gold color of the CCC is severely disrupted by black (LCO) material), demonstrating the effectiveness of the alumina intermixing barrier layer for preventing intermixing of layers of the stack deposited on the surface of the YSZ substrate.
  • alumina intermixing barrier layer on the YSZ substrate effectively prevents intermixing of the LCO cathode material and the gold current collector during annealing of the LCO cathode, and therefore maintains ( 1 ) layer integrity without or with minimal intermixing, (2) good electric conductivity of the CCC layer, (3) robustness of the device architecture, and (4) phase/effective mass/composition integrity of the cathode layer. Furthermore, even though the intermixing barrier layer has been demonstrated to be effective at stopping intermixing of CCC and cathode layers it should be noted that the intermixing barrier layer may be effective in stopping intermixing of all layers in the TFB stack.
  • FIG. 2 is a schematic illustration of a processing system 500 for fabricating a TFB, according to some embodiments.
  • the processing system 500 includes a standard mechanical interface (SMIF) 501 to a cluster tool 502 equipped with a reactive plasma clean (RPC) chamber 503 and process chambers C 1 -C4 (504, 505, 506 and 507), which may be utilized in the process steps described above.
  • RPC reactive plasma clean
  • a glovebox 508 may also be attached to the cluster tool,
  • the glovebox can store substrates in an inert environment (for example, under a noble gas such as He, Ne or Ar), which is useful after alkali metal/alkaline earth metal deposition.
  • An ante chamber 509 to the glovebox may also be used if needed - the ante chamber is a gas exchange chamber (inert gas to air and vice versa) which allows substrates to be transferred in and out of the glovebox without contaminating the inert environment in the glovebox, (Note that a glovebox can be replaced with a dry room ambient of sufficiently low dew point as such is used by lithium foil manufacturers.)
  • the chambers C 1-C4 can be configured for process steps for manufacturing TFBs which may include, for example: deposition of an alumina intermixing barrier layer on a YSZ substrate, a CCC on the intermixing barrier layer, followed by an LCO cathode, as described above.
  • suitable cluster tool platforms include display cluster tools. It is to be understood that while a cluster arrangement has been shown for the processing system 500, a linear system may be utilized in which the processing chambers are arranged in a line without a transfer chamber so that the substrate continuously moves from one chamber to the next chamber.
  • FIG. 3 shows a representation of an in-line fabrication system 600 with multiple in-line tools 601 through 699, including tools 630, 640, 650, according to some embodiments.
  • In-line tools may include tools for depositing all the layers of a TFB.
  • the in-line tools may include pre- and post-conditioning chambers.
  • tool 601 may be a pump down chamber for establishing a vacuum prior to the substrate moving through a vacuum airlock 602 into a deposition tool.
  • Some or all of the in-line tools may be vacuum tools separated by vacuum airlocks. Note that the order of process tools and specific process tools in the process line will be determined by the particular TFB fabrication method being used, for example, as specified in the process flows described above.
  • substrates may be moved through the in-line fabrication system oriented either horizontally or vertically.
  • FIG. 4 In order to illustrate the movement of a substrate through an in-line fabrication system such as shown in FIG. 3, in FIG. 4 a substrate conveyer 701 is shown with only one in-line tool 630 in place.
  • a substrate holder 702 containing a substrate 703 (the substrate holder is shown partially cut-away so that the substrate can be seen) is mounted on the conveyer 701 , or equivalent device, for moving the holder and substrate through the in-line tool 630, as indicated.
  • An in-line platform for processing tool 630 may in some embodiments be configured for vertical substrates, and in some embodiments configured for horizontal substrates.
  • a first apparatus for manufacturing TFBs may include: a first system for depositing an intermixing barrier layer on a thin substrate with substrate thickness in the range of 10 microns to 100 microns, and in embodiments 20 microns to 40 microns; a second system for depositing a current collector layer on the intermixing barrier layer and patterning said current collector layer to form a CCC and an ACC; a third system for depositing a cathode layer - such as an LCO layer - on the CCC layer to form a stack on the substrate; and a fourth system for annealing the stack; wherein the intermixing barrier layer prevents intermixing of the CCC and cathode layers.
  • the apparatus may further comprise: a fifth system for depositing an electrolyte layer on the annealed cathode layer, a sixth system for depositing an anode layer on the electrolyte layer to form a second stack on the substrate, and a seventh system for depositing an encapsulation layer over the second stack.
  • the apparatus may also comprise systems for patterning the various layers, and in embodiments shadow masks may be used in one or more of the aforesaid deposition systems.
  • the systems may be cluster tools, in-line tools, stand-alone tools, or a combination of one or more of the aforesaid tools.
  • the systems may include some tools which are common to one or more of the other systems.
  • a second apparatus for manufacturing TFBs may include: a first system for depositing an intermixing barrier layer on a thin substrate, with substrate thickness in the range of 10 microns to 100 microns, and in embodiments 20 microns to 40 microns; a second system for depositing a CCC layer on the intermixing barrier layer; a third system for depositing a cathode layer - such as an LCO layer - on the CCC layer to form a stack on the substrate; and a fourth system for annealing the stack; wherein the intermixing barrier layer prevents intermixing of the CCC and cathode layers.
  • the apparatus may further comprise: a fifth system for depositing an electrolyte layer on the annealed cathode layer, a sixth system for depositing an anode layer on the electrolyte layer, a seventh system to deposit an ACC on the anode layer to form a second stack on the substrate, and an eighth system for depositing an encapsulation layer over the second stack.
  • the apparatus may also comprise systems for patterning the various layers, and in embodiments shadow masks may be used in one or more of the aforesaid deposition systems.
  • the systems may be cluster tools, in-line tools, stand-alone tools, or a combination of one or more of the aforesaid tools.
  • the systems may include some tools which are common to one or more of the other systems,
  • LiMnO 2 and LiFePCv may be annealed at a temperature in the range of 500 °C to 800 °C, with a soak time in the range of 4 to 15 hours, and in embodiments in the range of 2 to 30 hours, depending on the thickness of the layer to be annealed, for example,

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Inorganic Chemistry (AREA)
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Abstract

Une batterie à couches minces peut comprendre : une couche barrière de mélange sur un substrat mince, tel qu'un substrat YSZ, avec une épaisseur de substrat dans une fourchette de 10 à 100 microns, la couche barrière de mélange comprenant un ou plusieurs éléments parmi AI2O3, Si3N4 et d'autres couches électro-isolantes, et selon des modes de réalisation ayant une plus grande densité de tassement de cations que le substrat; une couche de collecteur de courant à motifs sur la couche barrière de mélange; et une couche de cathode, par exemple LCO, sur la couche de collecteur de courant, laquelle couche barrière de mélange, lequel collecteur de courant à motifs et laquelle couche de cathode forment un empilement sur le substrat; laquelle couche barrière de mélange empêche le mélange du collecteur de courant et des couches de cathode, et de n'importe quelles autres couches de l'empilement pendant le recuit, à une température dans la plage allant de 500 °C à 800 °C, avec un temps d'exposition dans la plage allant de 2 à 30 heures.
PCT/US2016/052946 2015-09-21 2016-09-21 Prévention de mélange dans des dispositifs électrochimiques WO2017053473A1 (fr)

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Citations (5)

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US20080032236A1 (en) * 2006-07-18 2008-02-07 Wallace Mark A Method and apparatus for solid-state microbattery photolithographic manufacture, singulation and passivation
US20090311591A1 (en) * 2002-08-09 2009-12-17 Snyder Shawn W Electrochemical Apparatus With Barrier Layer Protected Substrate
US20110123862A1 (en) * 2009-11-23 2011-05-26 Gsnanotech Co., Ltd. Thin film battery having improved efficiency of collecting electric current
US20120040233A1 (en) * 2011-10-27 2012-02-16 Sakti3, Inc. Barrier for thin film lithium batteries made on flexible substrates and related methods
US20130266741A1 (en) * 2008-05-21 2013-10-10 Applied Materials, Inc. Microwave Rapid Thermal Processing of Electrochemical Devices

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090311591A1 (en) * 2002-08-09 2009-12-17 Snyder Shawn W Electrochemical Apparatus With Barrier Layer Protected Substrate
US20080032236A1 (en) * 2006-07-18 2008-02-07 Wallace Mark A Method and apparatus for solid-state microbattery photolithographic manufacture, singulation and passivation
US20130266741A1 (en) * 2008-05-21 2013-10-10 Applied Materials, Inc. Microwave Rapid Thermal Processing of Electrochemical Devices
US20110123862A1 (en) * 2009-11-23 2011-05-26 Gsnanotech Co., Ltd. Thin film battery having improved efficiency of collecting electric current
US20120040233A1 (en) * 2011-10-27 2012-02-16 Sakti3, Inc. Barrier for thin film lithium batteries made on flexible substrates and related methods

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