WO2017053473A1

WO2017053473A1 - Intermixing prevention in electrochemical devices

Info

Publication number: WO2017053473A1
Application number: PCT/US2016/052946
Authority: WO
Inventors: Lizhong Sun; Miaojun WANG; Byung-Sung Leo Kwak
Original assignee: Applied Materials Inc
Current assignee: Applied Materials Inc
Priority date: 2015-09-21
Filing date: 2016-09-21
Publication date: 2017-03-30
Anticipated expiration: 2018-03-21
Also published as: TW201725776A

Abstract

A thin film battery may comprise: an intermixing barrier layer on a thin substrate, such as a YSZ substrate, with a substrate thickness in the range of 10 microns to 100 microns, the intermixing barrier layer comprising one or more of AI₂O₃, Si₃N₄ and other electrically insulating layers, and in embodiments having a higher cation packing density than the substrate; a patterned current collector layer on the intermixing barrier layer; and a cathode layer, such as LCO, on the current collector layer, wherein the intermixing barrier layer, the patterned current collector and the cathode layer form a stack on the substrate; wherein the intermixing barrier layer prevents intermixing of the current collector and cathode layers, and any other layers in the stack during annealing, at a temperature in the range of 500 °C to 800 °C, with a soak time in the range of 2 to 30 hours.

Description

INTERMIXING PREVENTION IN ELECTROCHEMICAL DEVICES

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Application No.

62/221 ,573 filed Sept. 21, 2015, incorporated in its entirety herein.

FIELD

[0001] Embodiments of the present disclosure relate generally to electrochemical devices and methods of making the same, and more specifically, although not exclusively, to thin film batteries with an intermixing barrier layer deposited on the substrate - between the substrate and current collector layers.

BACKGROUND

[0002] Thin film batteries (TFBs) may comprise a thin film stack of layers including anode and cathode current collectors (ACC, CCC), a cathode (positive electrode), a solid state electrolyte, an anode (negative electrode) and encapsulation layers or packaging.

During the fabrication process of thin film batteries, one of the layers, the positive electrode (referred to herein as the cathode), typically formed of a material such as lithium cobalt oxide (LCO) which needs to be annealed, at relatively high temperature, to form an electrode with desirable materials properties - such as having a high percentage (greater than 90%) of high temperature phase LiCoO₂ (HT-LCO). To form a robust and well-functioning device structure, there are a number of aspects of the fabrication process that have to be controlled and optimized, especially as the positive electrode undergoes this relatively high temperature (within a range of 500 °C to 800 °C, for example) thermal treatment.

[0003] In addition, there is a need to improve the device metrics of which energy density is one of the key metrics. In order to increase the energy density and further improve the form factor of thin film solid state batteries, use of thinner substrates is one of the most effective and necessary methods. However, use of thinner (10 microns to 100 microns thick, for example) substrates brings many challenges related to making devices with satisfactory operational characteristics and robustness. One of the key issues that the present inventors have observed is the intermixing of the cathode layer (LiCoO₂) and the CCC layers during the LCO thermal annealing which can lead to higher resistance of the current collectors and loss of the active material (LiCoO₂), in which the severity of the intermixing is dependent on the substrate material, the L1C0O2 deposition process and the annealing temperature, The intermixing of the LiCoO₂ layer could lead to: poorer adhesion of the structure/CCC to the substrate; impurity in the LCO layer and loss of the active material; not to mention the stress at the location of the intermixing, dependent on the severity. This intermixing may be observed visually through the backside of an optically transparent/translucent substrate - as discussed in more detail below - and results in deterioration of device performance, due to increased resistance of the CCC (due to LCO in the CCC) and/or reduced ef fectiveness of the positive electrode (due to CCC material in the positive electrode), which is measureable during battery cell cycling tests as lower battery cell capacity utilization, higher IR drop, etc. Furthermore, the intermixing may reduce mechanical yield of TFBs and be manifest in wafer/substrate curvature.

[0004] One example of such a thin substrate is a polycrystalline ceramic substrate such as yttria-stabilized zirconium oxide (YSZ). While these YSZ substrates can withstand much higher thermal budget, including annealing beyond 600 °C to form a higher quality LCO with purer phase and greater crystallinity (greater than 90% HT-LiCO, by weight or by volume), the present inventors found that the intermixing of the CCC layers and the LiCoO₂ layer during the LCO annealing process is quite significant leading to device stability and performance issues, as indicated above.

[0005] Clearly, there is a need for fabrication processes and electrochemical device structures that reduce intermixing of the device layers during high temperature annealing (such as an LCO anneal) and thus maintain: the function (adhesion and conductance) of the CCC; purity, phase and effective mass of the cathode layer; the integrity of the whole electrochemical device structure (avoiding delamination of device layers by controlling stress between device layers and/or the stack of device layers and the substrate,).

SUMMARY

[0006] According to some embodiments, a thin film battery may comprise: an intermixing barrier layer on a thin substrate with a substrate thickness in the range of 10 microns to 100 microns, the intermixing barrier layer comprising an electrically insulating material, the intermixing barrier layer having a thickness in the range of 50 nm to 5,000 nm; a patterned current collector layer on the intermixing barrier layer; and a cathode layer on the patterned current collector layer, wherein the intermixing barrier layer, the patterned current collector layer and the cathode layer form a stack on the thin substrate, the cathode layer having been annealed at a temperature in the range of 500 °C to 800 °C, with a soak time in the range of 2 to 30 hours; wherein the intermixing barrier layer prevents intermixing of the current collector layer and the cathode layer during the annealing of the cathode layer.

[0007] According to some embodiments, a method for manufacturing thin film batteries may comprise: depositing an intermixing barrier layer on a thin substrate with a substrate thickness in the range of 10 microns to 100 microns, the intermixing barrier layer comprising an electrically insulating material, the intermixing barrier layer having a thickness in the range of 50 nm to 5,000 nm; depositing a current collector layer on the intermixing barrier layer and patterning the current collector layer; depositing a cathode layer on the patterned current collector layer to form a stack on the thin substrate; and annealing the stack, at a temperature in the range of 500 °C to 800 °C; wherein the intermixing barrier layer prevents intermixing of the patterned current collector layer and the cathode layer.

[0008] According to some embodiments, an apparatus for manufacturing thin film batteries may comprise: a first system for depositing an intermixing barrier layer on a thin substrate with a substrate thickness in the range of 10 microns to 1 00 microns, the intermixing barrier layer comprising an electrically insulating material, the intermixing barrier layer having a thickness in the range of 50 nm to 5,000 nm; a second system for depositing a current collector layer on the intermixing barrier layer and patterning the current collector layer; a third system for depositing a cathode layer on the patterned current collector layer to form a stack on the thin substrate; and a fourth system for annealing the stack, at a temperature in the range of 500 °C to 800 °C; wherein the intermixing barrier layer prevents intermixing of the patterned current collector layer and the cathode layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] These and other aspects and features of the present disclosure will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments in conjunction with the accompanying figures, wherein;

[0010] FIG. 1 is a cross-sectional representation of a thin film battery including an intermixing barrier layer between the substrate and adhesion and current collector layers, according to some embodiments;

[0011] FIG. 2 is a schematic illustration of a cluster tool for TFB fabrication, according to some embodiments;

[0012] FIG. 3 is a representation of a TFB fabrication system with multiple in-line tools, according to some embodiments; and

[0013] FIG. 4 is a representation of an in-line tool of FIG. 3, according to some embodiments.

DETAILED DESCRIPTION

[0014] Embodiments of the present disclosure will now be described in detail with reference to the drawings, which are provided as illustrative examples of the disclosure so as to enable those skilled in the art to practice the disclosure. Notably, the figures and examples below are not meant to limit the scope of the present disclosure to a single embodiment, but other embodiments are possible by way of interchange of some or all of the described or illustrated elements. Moreover, where certain elements of the present disclosure can be partially or fully implemented using known components, only those portions of such known components that are necessary for an understanding of the present disclosure will be described, and detailed descriptions of other portions of such known components will be omitted so as not to obscure the disclosure. In the present specification, an embodiment showing a singular component should not be considered limiting; rather, the disclosure is intended to encompass other embodiments including a plurality of the same component, and vice-versa, unless explicitly stated otherwise herein. Moreover, applicants do not intend for any term in the specification or claims to be ascribed an uncommon or special meaning unless explicitly set forth as such. Further, the present disclosure encompasses present and future known equivalents to the known components referred to herein by way of illustration.

[0015] F1G.1 shows an example of a TFB device 100 according to some embodiments comprising: a substrate 1 10 (such as YSZ ceramic, with 2 to 8 weight percent yttria and other minor impurities), an intermixing barrier layer 120 over the top substrate surface, an adhesion layer 130 (e.g. Ti) and cathode current collector (CCC) 140 (e.g. Au, Pt) on the top surface of the intermixing barrier layer, a cathode 150 (a layer of LCO, for example) on the CCC, an electrolyte 160 covering the cathode and portions of the CCC, isolating the CCC from any other electrodes, an anode 1 70 (e.g. Li) on portions of the top surface of the electrolyte and the anode current collector (ACC) 1 80 (e.g. Au), and encapsulation layer(s) 190 covering the exposed surfaces of the anode and electrolyte and portions of the current collectors. It is noted that the adhesion layer 130 is also provided between the intermixing barrier layer and the ACC if needed, but may not be needed in all embodiments.

[0016] An example of the TFB device of FIG. 1 is described in more detail, as follows. The TFB of FIG. 1 would ordinarily be fabricated using shadow masks, and is described as such below, although it is appreciated by persons of ordinary skill in the art that a maskless fabrication process may be used to fabricate TFBs with the same materials and order of layers in the device stack, just with a slightly different layout, The thin substrate, for example a glass, ceramic, metal or silicon substrate may have a thickness within the range from 10 μm to 700 μm. The layers deposited on the substrate are described next. The intermixing barrier layer, may comprise one or more of AI2O3, S13N4 and other electrically insulating layers (including suboxides, stoichiometric and nonstoichiometric variations, and crystalline, amorphous and mixed phase versions of the same) with a thickness in the range of 50 nm to 5000 nm, in embodiments in the range of 50 nm to 500 nm, and in embodiments in the range of 100 nm to 300 nm, deposited on the surface of the thin substrate, An adhesion metal layer (e.g., Ti, Ta, TaN) with an area larger than that of the cathode layer with thickness ranging from 10 nm to 1000 nm is deposited on the substrate barrier layer. A cathode current collector (e.g., Au, Pt) with an area the same as the adhesion layer with thickness ranging from 50 nm to 1000 nm is deposited on top of the adhesion layer. A cathode layer (e.g., LiCoO₂) with thickness ranging from 0.5 μm to 40 μm is deposited on top of the cathode current collector layer. The stack is thermalfy treated to anneal the cathode layer, as needed, before further deposition steps. A solid state electrolyte layer (e.g., UPON) having a larger area than and extending beyond the cathode and the cathode current collector (except for the electrical contact area, where the CCC is left uncovered) with thickness ranging from 0.5 μm to 4 ,um is deposited on top of the interlayer. An anode current collector (e.g., Cu, Au, Pt) with no overlap with the cathode layer and the cathode current collector and with thickness ranging from 100 nm to 1000 nm is deposited on top of the solid state electrolyte;

additionally, an adhesion metal layer may be deposited before the anode current collector, if needed, in a manner similar to that used for the cathode current collector layer. An anode (e.g., Li metal) with an area larger than that of the cathode and smaller than that of the electrolyte layer and with thickness ranging from 1 μηι to 15 μm, overlapping partially with the anode current collector layer, is deposited on the electrolyte and a portion of the ACC, An encapsulation layer of varying functions with an area larger than that of the anode layer and smaller than that of the electrolyte layer, with thickness ranging from 400 nm to 3 μm is deposited on top of the anode layer; the encapsulation layer can be a combination of a metal layer (e.g. Cu, Au, Pt) and a dielectric layer (such as LiPON, A1₂O₃, ZrO_2, SiO₂, Si₃N4, planarizing polymer layers, etc.).

[0017] The intermixing barrier layer of FIG. 1 is incorporated in embodiments into the device stack to overcome problems due to intermixing of the adhesion layer and current collector layers with the LCO cathode observed in devices without the intermixing barrier layer as described in more detail below. It is conjectured that the root cause of the intermixing during LCO annealing is that the thin flexible substrate sheets (e.g., YSZ ceramic) with thickness in the range of 10 microns to 100 microns, and in embodiments 20 microns to 40 microns, may have a rougher surface (as compared to smoother glass and mica substrates), which may result in rougher (surface roughness is characterized by Rms = 32.2 nm measured over a 5 μm x 5 μm area in a first example and by Rms = 28.5 nm over a 5 micron x 5 micron area in a second example, where Rms is the root mean square surface roughness measured by calculating the root mean square of the surface peaks and valleys), more porous, and varying thicknesses of the current collector layers that are built on top of it - i.e., lower thickness in the "valleys" of the rougher surface, In addition, the Zr ion packing density in the ZrO₂ unit cell with a fluorite structure is 58.8%, indicating a porous lattice structure. Thus, during the cathode (e.g., LiCoO₂) deposition with PVD sputtering, there may be plasma damage on the porous and thinner regions of the CCC films, resulting in initial penetration of the CCC by the L1CoO₂ layer and intermixing of LCO with the CCC materials. Such a situation is expected to be further aggravated during the post-deposition, high temperature annealing of the cathode material, thus leading to the observed intermixing phenomena,

[0018] Given such a hypothesis, the present disclosure provides that the substrate surface is modified by the addition of a layer with a high ion packing density, which creates a smoother surface and/or less porous layer, over which a smooth and dense CCC layer (CCC with a smooth surface and/or less porous layer) may be formed and at the same time exhibit better adhesion properties between the substrate and the CCC, bi-directionally. Herein "bi- directionally" is used to mean that adhesion promotion occurs at both interfaces - the substrate/intermixing barrier layer interface and the intermixing barrier layer/metal adhesion layer interface. In addition, the intermixing barrier layer may in embodiments function to limit interdiffusion of atoms/ions between the substrate and the CCC layer.

[0019] In embodiments a thin, dense and electrically insulating (with a resistance greater than 30 ΜΩ, for example) intermixing barrier layer (e.g., AI₂O₃ with a 65.6% ion packing density) is deposited between the substrate and the adhesion and current collector layers. Deposition of a 200 nm thick alumina film can reduce the surface roughness of a YSZ substrate in a first example from Rms = 32.2 nm over a 5 micron x 5 micron area to Rms = 28.2 over a 5 micron x 5 micron area, and in a second example from Rms = 28.5 nm over a 5 micron x 5 micron area to Rms = 26.6 over a 5 micron x 5 micron area, Deposition of alumina films optimized for intermixing prevention with smoother surfaces and/or less porous bulk may be achieved using physical vapor deposition (PVD) at higher areal power densities (greater than 3.5 W/cm², for example) in an argon/oxygen gas plasma environment, for example, It is expected that alumina with composition AIO_x where x is in the range of 1.2 to 1.5 may have the desired properties for some embodiments. The intermixing barrier layer could be AI₂O₃, S13N4 and other electrically insulating layers (including suboxides, stoichiometric and nonstoichiometric variations, and crystalline, amorphous and mixed phase versions of the same) with higher cation packing density than Zr ions in the ZrO₂ unit cell of the YSZ substrate and stability (maintains mechanical strength, stable chemical composition, for example) at temperatures in excess of 700 °C. The thickness of the intermixing barrier layer is in the range of 50 nm to 5000 nm, in embodiments in the range of 50 nm to 500 nm, and in embodiments in the range of 100 nm to 300 nm. [0020] Furthermore, even though the intermixing barrier layer has been demonstrated to be effective at stopping intermixing of CCC and cathode layers it should be noted that the substrate barrier layer may be effective in stopping Intermixing of all layers in the TFB stack.

[0021] While the demonstration of an intermixing barrier layer was with a PVD (physical vapor deposition) sputtered interlayer, it is expected that the concept is agnostic to the method of deposition - for example the deposition technique for the interlayer may be any deposition technique that is capable of providing the desired composition, phase and crystallinity, and may include deposition techniques such as PVD, reactive sputtering, non- reactive sputtering, RF (radio frequency) sputtering, multi-frequency sputtering, evaporation, CVD (chemical vapor deposition), ALD (atomic Iayer deposition), etc.. The deposition method can also be non-vacuum based, such as plasma spray, spray pyrolysis, slot die coating, screen printing, etc.

[0022] To demonstrate the efficacy of the intermixing barrier Iayer, the following experiments were conducted. As a control a stack was fabricated: adhesion layer/CCC (Ti/Au) and LCO layers were deposited on a YSZ substrate (the substrate was without an intermixing barrier layer). The stack was annealed at 650 °C and intermixing of the LCO and CCC layers was observed through the transparent substrate - clearly seen as a darkening of the stack. A second stack was fabricated: adhesion/CCC (Ti/Au) and LCO layers on a YSZ substrate coated with an alumina intermixing barrier iayer. The stack was annealed at 650 °C and no intermixing of the LCO and CCC layers was observed through the transparent substrate - there was no discoloration or signs of delamination of the layers. The YSZ substrate with alumina intermixing barrier layer does not show discoloration, while the YSZ substrate without the intermixing barrier iayer does show discoloration (the gold color of the CCC is severely disrupted by black (LCO) material), demonstrating the effectiveness of the alumina intermixing barrier layer for preventing intermixing of layers of the stack deposited on the surface of the YSZ substrate. The addition of the alumina intermixing barrier layer on the YSZ substrate effectively prevents intermixing of the LCO cathode material and the gold current collector during annealing of the LCO cathode, and therefore maintains ( 1 ) layer integrity without or with minimal intermixing, (2) good electric conductivity of the CCC layer, (3) robustness of the device architecture, and (4) phase/effective mass/composition integrity of the cathode layer. Furthermore, even though the intermixing barrier layer has been demonstrated to be effective at stopping intermixing of CCC and cathode layers it should be noted that the intermixing barrier layer may be effective in stopping intermixing of all layers in the TFB stack.

[0023] Although embodiments of the present disclosure have been particularly described with reference to planar TFBs (with ACC and CCC in the same plane), the principles and teaching of the present disclosure may be applied to other TFB configurations, including a vertical stack configuration where ACC and CCC are parallel, but on opposite sides of the stack.

[0024] FIG. 2 is a schematic illustration of a processing system 500 for fabricating a TFB, according to some embodiments. The processing system 500 includes a standard mechanical interface (SMIF) 501 to a cluster tool 502 equipped with a reactive plasma clean (RPC) chamber 503 and process chambers C 1 -C4 (504, 505, 506 and 507), which may be utilized in the process steps described above. A glovebox 508 may also be attached to the cluster tool, The glovebox can store substrates in an inert environment (for example, under a noble gas such as He, Ne or Ar), which is useful after alkali metal/alkaline earth metal deposition. An ante chamber 509 to the glovebox may also be used if needed - the ante chamber is a gas exchange chamber (inert gas to air and vice versa) which allows substrates to be transferred in and out of the glovebox without contaminating the inert environment in the glovebox, (Note that a glovebox can be replaced with a dry room ambient of sufficiently low dew point as such is used by lithium foil manufacturers.) The chambers C 1-C4 can be configured for process steps for manufacturing TFBs which may include, for example: deposition of an alumina intermixing barrier layer on a YSZ substrate, a CCC on the intermixing barrier layer, followed by an LCO cathode, as described above. Examples of suitable cluster tool platforms include display cluster tools. It is to be understood that while a cluster arrangement has been shown for the processing system 500, a linear system may be utilized in which the processing chambers are arranged in a line without a transfer chamber so that the substrate continuously moves from one chamber to the next chamber.

[0025] FIG. 3 shows a representation of an in-line fabrication system 600 with multiple in-line tools 601 through 699, including tools 630, 640, 650, according to some embodiments. In-line tools may include tools for depositing all the layers of a TFB. Furthermore, the in-line tools may include pre- and post-conditioning chambers. For example, tool 601 may be a pump down chamber for establishing a vacuum prior to the substrate moving through a vacuum airlock 602 into a deposition tool. Some or all of the in-line tools may be vacuum tools separated by vacuum airlocks. Note that the order of process tools and specific process tools in the process line will be determined by the particular TFB fabrication method being used, for example, as specified in the process flows described above. Furthermore, substrates may be moved through the in-line fabrication system oriented either horizontally or vertically.

[0026] In order to illustrate the movement of a substrate through an in-line fabrication system such as shown in FIG. 3, in FIG. 4 a substrate conveyer 701 is shown with only one in-line tool 630 in place. A substrate holder 702 containing a substrate 703 (the substrate holder is shown partially cut-away so that the substrate can be seen) is mounted on the conveyer 701 , or equivalent device, for moving the holder and substrate through the in-line tool 630, as indicated. An in-line platform for processing tool 630 may in some embodiments be configured for vertical substrates, and in some embodiments configured for horizontal substrates.

[0027] Some examples of apparatus for fabricating a TFB according to certain embodiments are as follows. A first apparatus for manufacturing TFBs according to some embodiments may include: a first system for depositing an intermixing barrier layer on a thin substrate with substrate thickness in the range of 10 microns to 100 microns, and in embodiments 20 microns to 40 microns; a second system for depositing a current collector layer on the intermixing barrier layer and patterning said current collector layer to form a CCC and an ACC; a third system for depositing a cathode layer - such as an LCO layer - on the CCC layer to form a stack on the substrate; and a fourth system for annealing the stack; wherein the intermixing barrier layer prevents intermixing of the CCC and cathode layers. Furthermore, in embodiments the apparatus may further comprise: a fifth system for depositing an electrolyte layer on the annealed cathode layer, a sixth system for depositing an anode layer on the electrolyte layer to form a second stack on the substrate, and a seventh system for depositing an encapsulation layer over the second stack. The apparatus may also comprise systems for patterning the various layers, and in embodiments shadow masks may be used in one or more of the aforesaid deposition systems. The systems may be cluster tools, in-line tools, stand-alone tools, or a combination of one or more of the aforesaid tools. Furthermore, the systems may include some tools which are common to one or more of the other systems. [0028] Furthermore, a second apparatus for manufacturing TFBs according to some embodiments may include: a first system for depositing an intermixing barrier layer on a thin substrate, with substrate thickness in the range of 10 microns to 100 microns, and in embodiments 20 microns to 40 microns; a second system for depositing a CCC layer on the intermixing barrier layer; a third system for depositing a cathode layer - such as an LCO layer - on the CCC layer to form a stack on the substrate; and a fourth system for annealing the stack; wherein the intermixing barrier layer prevents intermixing of the CCC and cathode layers. Furthermore, in embodiments the apparatus may further comprise: a fifth system for depositing an electrolyte layer on the annealed cathode layer, a sixth system for depositing an anode layer on the electrolyte layer, a seventh system to deposit an ACC on the anode layer to form a second stack on the substrate, and an eighth system for depositing an encapsulation layer over the second stack. The apparatus may also comprise systems for patterning the various layers, and in embodiments shadow masks may be used in one or more of the aforesaid deposition systems. The systems may be cluster tools, in-line tools, stand-alone tools, or a combination of one or more of the aforesaid tools. Furthermore, the systems may include some tools which are common to one or more of the other systems,

[0029] Although embodiments of the present disclosure have been particularly described with reference to TFBs with LCO cathodes, the principles and teaching of the present disclosure may be applied to TFBs with other cathode materials, including LiMO₂ (M=Co, Ni, Mn, etc.). Where, for example LiMnO₂ and LiFePCv may be annealed at a temperature in the range of 500 °C to 800 °C, with a soak time in the range of 4 to 15 hours, and in embodiments in the range of 2 to 30 hours, depending on the thickness of the layer to be annealed, for example,

[0030] Although embodiments of the present disclosure have been particularly described with reference to TFBs, the principles and teaching of the present disclosure may be applied to other electrochemical devices, including energy storage devices generally, and also to electrochromic devices,

[0031) Although embodiments of the present disclosure have been particularly described with reference to single-sided TFBs, the principles and teaching of the present disclosure may be applied to double-sided TFBs. [0032] Although embodiments of the present disclosure have been particularly described with reference to certain embodiments thereof, it should be readily apparent to those of ordinary skill in the art that changes and modifications in the form and details may be made without departing from the spirit and scope of the disclosure.

Claims

WHAT IS CLAIMED IS:

1. A thin film battery (TFB) comprising:

an intermixing barrier layer on a thin substrate with a substrate thickness in the range of 10 microns to 100 microns, said intermixing barrier layer comprising an electrically insulating material, said intermixing barrier layer having a thickness in the range of 50 nm to 5,000 nm;

a patterned current collector layer on said intermixing barrier layer; and

a cathode layer on said patterned current collector layer, wherein said intermixing barrier layer, said patterned current collector layer and said cathode layer form a stack on said thin substrate, said cathode layer having been annealed at a temperature in the range of 500

°C to 800 °C, with a soak time in the range of 2 to 30 hours;

wherein said intermixing barrier layer prevents intermixing of said current collector layer and said cathode layer during the annealing of said cathode layer.

2. The TFB of claim 1, wherein said intermixing barrier layer has a higher cation packing density than said thin substrate.

3. The TFB of claim I , wherein said thin substrate is a yttria-stabilized zirconium oxide substrate,

4. The TFB of claim 3, wherein said thin substrate has a root mean square surface roughness of great than about 28 nm.

5. The TFB of claim 1 , wherein said cathode layer is a lithium cobalt oxide (LCO) layer having greater than 90% by volume of high temperature phase LCO.

6. The TFB of claim 1 , wherein said intermixing barrier layer is an alumina layer.

7. A method for manufacturing thin film batteries comprising:

depositing an intermixing barrier layer on a thin substrate with a substrate thickness in the range of 10 microns to 100 microns, said intermixing barrier layer comprising an electrically insulating material, said intermixing barrier layer having a thickness in the range of 50 nm to 5,000 nm; depositing a current collector layer on said intermixing barrier layer and patterning said current collector layer;

depositing a cathode layer on the patterned current collector layer to form a stack on said thin substrate; and

annealing said stack, at a temperature in the range of 500 °C to 800 °C;

wherein said intermixing barrier layer prevents intermixing of said patterned current collector layer and said cathode layer.

8. The method of claim 7, wherein said thin substrate is a yttria-stabilized zirconium oxide substrate.

9. The method of claim 8, wherein said thin substrate has a root mean square surface roughness of greater than about 28 nm.

10. The method of claim 7, wherein said cathode layer is a lithium cobalt oxide (LCO) layer having greater than 90% by volume of high temperature phase LCO after said annealing.

1 1. The method of claim 10, wherein said annealing is for a time in the range of 4 to 15 hours.

12. The method of claim 7, wherein said intermixing barrier layer is an alumina layer.

13. The method of claim 12, wherein said alumina layer is deposited by physical vapor deposition at an areal power density greater than 3.5 W/cm² in an argon/oxygen gas plasma environment.

14. An apparatus for manufacturing thin film batteries comprising:

a first system for depositing an intermixing barrier layer on a thin substrate with a substrate thickness in the range of 10 microns to 100 microns, said intermixing barrier layer comprising an electrically insulating material, the intermixing barrier layer having a thickness in the range of 50 nm to 5,000 nm;

a second system for depositing a current collector layer on said intermixing barrier layer and patterning said current collector layer; a third system for depositing a cathode layer on the patterned current collector layer to form a stack on said thin substrate; and

a fourth system for annealing said stack, at a temperature in the range of 500 °C to

800 °C;

wherein said intermixing barrier layer prevents intermixing of said patterned current collector layer and said cathode layer,

15 , The apparatus of claim 14, wherein said first system comprises a physical vapor deposition tool for deposition of an alumina intermixing barrier layer at an areal power density greater than 3.5 W/cm² in an argon/oxygen gas plasma environment.