WO2017053150A1 - Procédé et système de commande de traitement avec échantillonnage souple - Google Patents

Procédé et système de commande de traitement avec échantillonnage souple Download PDF

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Publication number
WO2017053150A1
WO2017053150A1 PCT/US2016/051743 US2016051743W WO2017053150A1 WO 2017053150 A1 WO2017053150 A1 WO 2017053150A1 US 2016051743 W US2016051743 W US 2016051743W WO 2017053150 A1 WO2017053150 A1 WO 2017053150A1
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WO
WIPO (PCT)
Prior art keywords
metrology
wafer
controller
sub
wafers
Prior art date
Application number
PCT/US2016/051743
Other languages
English (en)
Inventor
Onur DEMIRER
Roie VOLKOVICH
William Pierson
Mark Wagner
Dana Klein
Original Assignee
Kla-Tencor Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US15/184,612 external-priority patent/US10754260B2/en
Application filed by Kla-Tencor Corporation filed Critical Kla-Tencor Corporation
Priority to KR1020187010680A priority Critical patent/KR102351636B1/ko
Priority to CN201680052263.4A priority patent/CN108028210B/zh
Publication of WO2017053150A1 publication Critical patent/WO2017053150A1/fr

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Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line

Definitions

  • the present invention generally relates to wafer metrology for lithography process control, and, in particular, to the generation of flexible sampling plans for reducing noise and improving feedback process tool feedback correction.
  • Fabricating semiconductor devices such as logic and memory devices typically includes processing a substrate, such as a wafer, using a large number of fabrication processes to form various features and multiple levels of the devices.
  • lithography is a fabrication process that involves transferring a pattern from a reticle/mask to a resist arranged on a wafer. Additional examples of fabrication processes include, but are not limited to, chemical-mechanical polishing (CMP), etching, deposition, and ion implantation.
  • CMP chemical-mechanical polishing
  • etching etching
  • deposition deposition
  • ion implantation ion implantation
  • wafer generally refers to substrates formed of a semiconductor or non-semiconductor material.
  • a semiconductor or non-semiconductor material may include, but is not limited to, monocrystaliine silicon, gallium arsenide or indium phosphide.
  • a wafer may include one or more layers.
  • such layers may include, but are not limited to, a resist, a dielectric material, a conductive material, and a semiconductive material. Many different types of such layers are known in the art, and the term wafer as used herein is intended to encompass a wafer on which ail types of such layers may be formed.
  • One or more layers formed on a wafer may be patterned or unpatterned.
  • a wafer may include a plurality of dies, each having repeafable patterned features. Formation and processing of such layers of material may ultimately result in completed devices.
  • Many different types of devices may be formed on a wafer, and the term wafer as used herein is intended to encompass a wafer on which any type of device known in the art may be fabricated.
  • Metrology processes are used at various steps during a semiconductor manufacturing process to monitor process control during device fabrication. Types of metrology process used for process control include overlay metrology, critical dimension (CD) metrology, wafer geometry metrology and etc.
  • overlay error may occur between a current and previous layer of the semiconductor device.
  • Overlay is defined as the misregistration between the current layer of a semiconductor device and one or multiple previous layers of the semiconductor device. Overlay errors can arise for various reasons, including lithography tool (scanner) errors, wafer geometry induced errors, etch induced errors and the like.
  • lithography tool scanner
  • etch induced errors can arise for various reasons, including lithography tool (scanner) errors, wafer geometry induced errors, etch induced errors and the like.
  • a feedback control system is applied. Feedback control system rely on i) measuring overlay using a metrology tool; ii) calculating the scanner correctables that would minimize overlay; and iii) feeding these corrections back through an advanced process control (APC) algorithm.
  • APC advanced process control
  • Conventional overlay control schemes rely on measuring a fixed subset of overlay targets (i.e., static sample plan) on the wafers for modeling overlay errors and calculating the scanner correctables.
  • Additional approaches includes relying on an advanced fieid-by-field extrapolated modeling technique, where information from the static sample plan is used to calculate field-by- field corrections without relying on periodic dense map measurements. Such an approach requires extensive optimization and a careful setup. In addition, extrapolation techniques are less useful for some irregular overlay signatures. [ ⁇ ?] As the dimensions of semiconductor devices decrease, metrology processes become even more important to the successful manufacture of acceptable semiconductor devices. As such, it would be advantageous to provide a system and method that provides improved metrology capabilities and cures the deficiencies of prior approaches as identified above.
  • the system includes a metrology subsystem configured to perform one or more metrology measurements on one or more wafers of a lot of wafers.
  • the system includes a controller communicatively coupled to one or more portions of the metrology sub-system.
  • the controller includes one or more processors configured to execute program instructions configured to cause the one or more processors to: generate a plurality of flexible sparse sampling plans based on the one or more metrology measurements of the one or more wafers received from the metrology subsystem; direct the metrology sub-system to perform metrology measurements on two or more wafers at the locations of the plurality of flexible sparse sampling plans, wherein each flexible sparse sampling plan is associated with one of the two or more wafers; form a virtual dense map of metrology signals by combining results from the metrology measurements performed at the locations of the plurality of flexible sample plans; and calculate a set of process tool correctables based on the virtual dense map of metrology signals.
  • the system includes a metrology sub-system configured to perform one or more metrology measurements on one or more wafers.
  • the system includes a controller communicatively coupled to one or more portions of the metrology sub-system.
  • the controller includes one or more processors configured to execute program instructions configured to cause the one or more processors to: receive a full set of metrology signals from the one or more wafers from the metrology sub-system.
  • a system for generating one or more flexible sparse sample plans includes a metrology sub-system configured to perform one or more metrology measurements on one or more wafers.
  • the system includes a controller communicatively coupled to one or more portions of the metrology sub-system.
  • the controller includes one or more processors configured to execute program instructions configured to cause the one or more processors to: receive a full set of metrology signals from the one or more wafers from the metrology sub-system; determine a set of wafer properties based on the full set of metrology signals and calculate a set of accuracy merits for the set of wafer properties; calculate a statistical metric associated with each of the set of accuracy merits for the set of wafer properties; and generate a flexible sparse sampling plan based on the statistical metrics associated with each of the set of accuracy merits.
  • a system for generating one or more flexible sparse sample plans includes a metrology sub-system configured to perform one or more metrology measurements on one or more wafers, !n another embodiment, the system includes a controller communicatively coupled to one or more portions of the metrology sub-system.
  • the controller includes one or more processors configured to execute program instructions configured to cause the one or more processors to: receive a full set of metrology signals from the one or more wafers from the metrology sub-system; determine a set of wafer properties based on the full set of metrology signals and calculate a set of accuracy merits for the set of wafer properties; and generate a flexible sparse sampling plan based on the set of accuracy merits, wherein the flexible sparse sampling plan is generated by identifying target locations within the full sampling plan displaying accuracy merit values below a selected threshold.
  • FIG. 1A is a conceptual block diagram view of a metrology system for measuring metrology targets of a semiconductor wafer, in accordance with one embodiment of the present disclosure.
  • FIG. 1 B illustrates a top plan view of a semiconductor wafer with demarked fields, in accordance with one embodiment of the present disclosure.
  • FIG. 1 C illustrates a top plan view of an individual field of a semiconductor wafer showing a plurality of targets within the field, in accordance with one embodiment of the present disclosure.
  • FIG. 1 D is a block diagram view of an imaging-based metrology system for measuring metrology targets of a semiconductor wafer, in accordance with one embodiment of the present disclosure.
  • FIG. 1 E is a block diagram view of a scaiierometry-based metrology system for measuring metroiogy targets of a semiconductor wafer, in accordance with one embodiment of the present disclosure.
  • FIG. 2 is a flow diagram illustrating steps performed in a method of providing process too! correctables via multiple flexible sparse sample plans, in accordance with one embodiment of the present disclosure.
  • FIG. 3A is a flow diagram illustrating steps performed in a method of generating one or more flexible sparse sample plans, in accordance with one embodiment of the present disclosure.
  • FIG. 3B is a top plan view of a full sample plan and a flexible sparse sample plan, in accordance with one embodiment of the present disclosure.
  • FIG. 4 is a flow diagram illustrating steps performed in a method of generating one or more flexible sparse sample plans, in accordance with one embodiment of the present disclosure.
  • Embodiments of the present disclosure are directed to the generation of flexible sparse sample plans, which represent a sub-set of the available metrology target locations of one or more wafers of a lot of wafers. Additional embodiments of the present disclosure are directed to the generation of composite wafer corrections using metrology data obtained using multiple flexible sparse plans.
  • the flexible sparse sampling plans may be generated based on the analysis of one or more independent metrics (e.g., accuracy merits), such as, but not limited to, a process signature metric (e.g., PSQ), a patterned wafer geometry metric (e.g., PWG), an overlay target asymmetry metric (e.g., Qmerit) or overlay target accuracy metric (e.g., overlay target accuracy flag).
  • a process signature metric e.g., PSQ
  • a patterned wafer geometry metric e.g., PWG
  • an overlay target asymmetry metric e.g., Qmerit
  • overlay target accuracy metric e.g., overlay target accuracy flag
  • FIG. 1A illustrates a conceptual block diagram view of a metrology system 100 for performing one or more metrology measurements in accordance with one or more embodiments of the present disclosure
  • the system 100 includes a metrology sub-system 102.
  • the metrology sub-system 102 is configured to measure one or more characteristics of one or more metrology targets 1 1 1 of wafer 1 12.
  • the metrology sub-system 102 may be configured for measuring/characterizing one or more of overlay metrology targets, optical critical dimension (CD) targets or focus/dose targets.
  • the metrology sub-system 102 may measure one or more metrology targets 1 16 in one or more fields 1 13 of a wafer, as depicted in FIGS. 1 B-1 C.
  • the metrology system 100 has been depicted in a simplified block diagram. This depiction, including the components and geometrical configuration, is not limiting and is provided for illustrative purposes only. It is recognized herein that the metrology system may include any number of optical elements, illumination sources and detectors to carry out the metrology processes described herein (e.g., overlay metrology, CD metrology, focus/dose metrology), which may be based on metrology measurement techniques, such as contrast-based imaging, scatterometry, eliipsometry, SEM and/or AFM techniques.
  • overlay metrology e.g., CD metrology, focus/dose metrology
  • metrology measurement techniques such as contrast-based imaging, scatterometry, eliipsometry, SEM and/or AFM techniques.
  • the metrology sub-system 102 includes an overlay metrology sub-system or tool.
  • the metrology sub-system 102 is an imaging-based metrology sub-system.
  • the imaging- based metrology sub-system is configured to measure one or more contrast-based field images of one or more targets 1 1 1 of wafer 1 12 disposed on stage 136.
  • the system 100 may include an illumination source 122 configured to generate illumination 134, a detector 130 configured to collect light reflected from one or more metrology targets 1 1 1 of one or more wafers 122 (e.g., one or more wafers of one or more wafer lots) and one or more optical elements.
  • the one or more optical elements e.g., beam splitter 126 and the like
  • the one or more optical elements are configured to direct a first portion of illumination from the illumination source 122 along an object path 132 to one or more metrology targets 1 1 1 1 disposed on one or more process layers of a wafer 1 12 disposed on stage 136.
  • a second portion of light from the illumination source 122 is directed along reference path 138 to the one or more reference optics 140.
  • the illumination source 122 of the system 100 may include any illumination source known in the art.
  • the illumination source 122 may include a broadband light source.
  • the illumination source 122 may include, but is not limited to, a halogen light source (HLS), an arc lamp or a laser sustained plasma light source.
  • the illumination source 122 may include a narrowband light source.
  • the illumination source 122 may include, but is not limited to, one or more lasers.
  • the one or more optical elements of the system 100 may include, but are not limited to, one or more beam splitters 126.
  • the beam splitter 126 may split the light beam 134 emanating from the illumination source 122 into two paths: an object path 132 and a reference path 138.
  • the object path 132 and the reference path 138 may form a portion of a two beam interference optical system.
  • the beam splitter 126 may direct a first portion of the beam of light from the illumination path 134 along the object path 132, while allowing a second portion of the beam of light from the illumination path 134 to be transmitted along the reference path 138.
  • the beam splitter 126 may transmit a portion of light from the illumination path 134 along the reference path 138 to reference optics 140, such as, but not limited to, a reference mirror.
  • the reference path 138 and reference optics 140 may include any optic elements known in the art of image-based overlay metrology including, but not limited to, a reference mirror, a reference objective, and a shutter configured to selectively block the reference path 138.
  • a two-beam interference optical system may be configured as a Linnik interferometer. Linnik interferometry is described generally in U.S. Patent No. 4,818,1 10, issued on April 4, 1989, and U.S. Patent No. 6, 172,349, issued on January 9, 2001 , which are incorporated herein by reference in their entirety.
  • the system 100 may include an objective lens 128.
  • the objective lens 128 may aid in directing light along the object path 132 to the surface of the wafer 1 12 disposed on the stage 136. Following the splitting process by the beam splitter 126, the objective lens 128 may focus light from the object path 132, which may be coliinear with the primary optical axis, onto the metrology targets 1 1 1 of the wafer 1 12. Any objective lens known in the art may be suitable for implementation in this embodiment.
  • a portion of the light impinging on the surface of the wafer 1 12 may be reflected, scattered or diffracted by the metrology targets 1 1 1 of the wafer 1 12 and directed along the primary optical axis 124 via the objective 128 and the beam splitter 126 toward the detector 130.
  • intermediate optical devices such as intermediate lenses, mirrors, additional beam splitters, filters, polarizers, imaging lenses and the like may be placed between the objective 128 and the detector 130.
  • the detector 130 may be arranged to collect imagery data from the surface of the wafer 1 12. For example, after reflecting or scattering from the surface of the wafer 1 12, light may travel along the primary optical axis 124 to the detector 130. It is recognized that any detector system known in the art is suitable for implementation in this embodiment.
  • the detector 130 may include a charge coupled device (CCD) based camera system.
  • the detector 130 may include a time delay integration (TDI)-CCD based camera system.
  • the detector 130 may be communicatively coupled with controller 104.
  • digitized imagery data may be transmitted from the detector 130 to the controller 104 via a signal, such as a wireline signal (e.g., copper line, fiber optic cable, and the like) or a wireless signal (e.g., wireless RF signal).
  • a signal such as a wireline signal (e.g., copper line, fiber optic cable, and the like) or a wireless signal (e.g., wireless RF signal).
  • the controller 104 may calculate a set of process tool correciables based on the metrology measurements received from detector 130 and feed the corrections back to a process too! 105 (e.g., scanner).
  • the metrology sub-system 102 is a scatterometry-based metrology sub-system.
  • the scatterometry-based metrology sub-system is a scatterometry-based overlay metrology tool and is configured to measure a pupil image of one or more targets 1 1 1 of wafer 1 12.
  • the metrology sub-system 102 includes a CD metrology tool suitable for measuring one or more CD parameters from one or more CD targets disposed on the wafer 1 12.
  • the CD metrology tool may be configured to measure any CD parameter known in the art.
  • the CD metrology tool may measure one or more of the following parameters from one or more CD targets: height, CD (e.g., bottom CD, middle CD or top CD) and side wail angle (SWA) (e.g., bottom SWA, middle SWA or top SWA).
  • the metrology sub-system 102 may be configured in any manner for carrying out scatterometry or el!ipsometry measurements.
  • the metrology sub-system 102 may include illumination source 150, polarizing element 152, analyzer 154 and detector 160.
  • the metrology sub-system 102 may include additional optical elements 156 and 158.
  • the optical elements 156 and 158 may include, but are not limited to, one or more lenses (e.g., focusing lenses), one or more mirrors, one or more filters and/or or one or more collimators.
  • the system 100 includes a controller 104.
  • the controller 104 is communicatively coupled to the metrology sub-system 102,
  • the controller 104 may be coupled to the output of a detector 130, 160 of the metrology sub-system 102.
  • the controller 104 may be coupled to the detector in any suitable manner (e.g., by one or more transmission media indicated by the dotted line) such that the controller 104 can receive the output generated by the metrology sub-system 102.
  • the controller 104 includes one or more processors 106.
  • the one or more processors 106 are configured to execute a set of program instructions.
  • the program instructions may carry out any of the process steps described throughout the present disclosure,
  • the one or more processors 106 of controller 104 may include any one or more processing elements known in the art. In this sense, the one or more processors 106 may include any microprocessor-type device configured to execute software algorithms and/or instructions. In one embodiment, the one or more processors 106 may consist of a desktop computer, mainframe computer system, workstation, image computer, parallel processor, or other computer system (e.g., networked computer) configured to execute a program configured to operate the system 100, as described throughout the present disclosure. It should be recognized that the steps described throughout the present disclosure may be carried out by a single computer system or, alternatively, multiple computer systems.
  • processor may be broadly defined to encompass any device having one or more processing elements, which execute program instructions from a non-transitory memory medium 108.
  • different subsystems of the system 100 e.g., metrology sub-system, display or user interface
  • the memory medium 108 may include any storage medium known in the art suitable for storing program instructions executable by the associated one or more processors 106.
  • the memory medium 108 may include a non- transitory memory medium.
  • the memory medium 108 may include, but is not limited to, a read-only memory, a random access memory, a magnetic or optical memory device (e.g., disk), a magnetic tape, a solid state drive and the like.
  • the memory 108 is configured to store one or more results from the metrology sub-system 102 and/or the output of the various steps described herein. It is further noted that memory 108 may be housed in a common controller housing with the one or more processors 106.
  • the memory 108 may be located remotely with respect to the physical location of the processors 106.
  • the one or more processors 106 of controller 104 may access a remote memory (e.g., server), accessible through a network (e.g., internet, intranet and the like).
  • the memory medium 108 includes program instructions for causing the one or more processors 106 carry out the various steps described through the present disclosure.
  • the controller 104 of the system 100 may be configured to receive and/or acquire data or information from other systems (e.g., inspection results from an inspection system or metrology results from a metrology system) by a transmission medium that may include wireline and/or wireless portions. In this manner, the transmission medium may serve as a data link between the controller 104 and other subsystems of the system 100. Moreover, the controller 104 may send data to external systems via a transmission medium (e.g., network connection).
  • a transmission medium e.g., network connection
  • the system 100 includes a user interface (not shown).
  • the user interface is communicatively coupled to the one or more processors 106 of controller 104.
  • the user interface device may be utilized by controller 104 to accept selections and/or instructions from a user.
  • a display may be used to display data to a user (not shown), !n turn, a user may input selection and/or instructions (e.g., a user selection of measured field sites or field sites for regression process) responsive to data displayed to the user via the display device.
  • the user interface device may include any user interface known in the art.
  • the user interface may include, but is not limited to, a keyboard, a keypad, a touchscreen, a lever, a knob, a scroll wheel, a track ball, a switch, a dial, a sliding bar, a scroll bar, a slide, a handle, a touch pad, a paddle, a steering wheel, a joystick, a bezel input device or the like.
  • a touchscreen interface device those skilled in the art should recognize that a large number of touchscreen interface devices may be suitable for implementation in the present invention.
  • the display device may be integrated with a touchscreen interface, such as, but not limited to, a capacitive touchscreen, a resistive touchscreen, a surface acoustic based touchscreen, an infrared based touchscreen, or the like.
  • a touchscreen interface such as, but not limited to, a capacitive touchscreen, a resistive touchscreen, a surface acoustic based touchscreen, an infrared based touchscreen, or the like.
  • the user interface may include, but is not limited to, a bezel mounted interface.
  • the display device may include any display device known in the art.
  • the display device may include, but is not limited to, a liquid crystal display (LCD).
  • the display device may include, but is not limited to, an organic light-emitting diode (OLED) based display.
  • the display device may include, but is not limited to a CRT display.
  • any display device capable of integration with a user interface device e.g., touchscreen, bezel mounted interface, keyboard, mouse, trackpad, and the like
  • a user interface device e.g., touchscreen, bezel mounted interface, keyboard, mouse, trackpad, and the like
  • FIGS. 1A-1 E may be further configured as described herein, !n addition, the system 100 may be configured to perform any other step(s) of any of the method embodiment(s) described herein.
  • FIG. 2 is a flow diagram illustrating steps performed in a method 200 of process control with multiple flexible sparse sampling plans, in accordance with one more embodiments of the present disclosure.
  • step 202 multiple flexible sparse sampling plans are generated.
  • the utilization of flexible sparse sampling plans allows for the optimization (or at least improvement) of sampling based on accuracy/independent metric information collection from the metrology sub-system 102.
  • the metrology sub-system 102 may be a standalone metrology tool, an integrated metrology tool (e.g., scatterometry or imaging based metrology tool) or a combination thereof.
  • the accuracy/independent metric information based optimization of this approach serves to reduce sampling size and metrology measurement duration by selecting a sub-set of measured targets that represent the full or sufficient set of targets.
  • Approaches for generating the flexible sparse sampling plans based on independent metric information, such as accuracy merit values, are described in additional detail further herein.
  • step 204 metrology measurements are performed on one or more wafers at the locations of the multiple flexible sampling plans.
  • step 206 a virtual dense map of metrology measurements is formed by combining results from the metrology measurements performed at the locations of the multiple flexible sampling plans.
  • the application of the flexible sample plans of the present disclosure allows for the creation of field-by ⁇ fieid corrections from the virtual dense map generated in step 206. Such an approach does not require a periodic dense map measurement.
  • the formation of the virtual grid map of step 206 does not merely involve a composite of the multiple flexible sample plans. Rather, the formation of the virtual dense map first includes the removal of the grid signature from each flexible sampled wafer via controller 104. Then, one or more algorithms executed by controller 104 may apply a weighted combination of neighboring field info for each field, thereby filtering out noise.
  • the noise filtering capabilities of method 200 become particularly useful as wafer-to-wafer and !ot-to-iot variations increase. By using such an approach, zonal variations over the wafer 1 12 may be captured more accurately and field-by-field corrections may be calculated using the virtual dense map.
  • process tool correctables are calculated based on virtual dense map of metrology measurements. For example, upon formation of the virtual dense sample map including the various metrology signals associated with the locations of the virtual dense sample map, the controller 104 may calculate one or more correctables based on the virtual dense sample map. The correctables may be calculated utilizing any known correctable calculation procedure known in the art of process tool correction.
  • the process tool correctables are used to adjust one or more process tools 105. For example, as shown in FIG. 1A, once the process tool correctables are calculated with controller 104, the controller 104 may adjust one or more operational parameters of the process tool 105 (e.g., scanner).
  • FIG. 3A is a flow diagram illustrating steps performed in a method 300 of generating a flexible sparse metrology sampling plan, in accordance with one embodiment of the present disclosure. It is noted herein that the steps of method 300 may be implemented all or in part by the system 100. It is further recognized, however, that the method 300 is not limited to the system 100 in that additional or alternative system-level embodiments may carry out all or part of the steps of method 300. Further, it is noted herein that the steps and embodiments associated with method 200 described previously herein are interpreted to extend to method 300. In this regard, the steps of method 200 and method 300 may be combined in any suitable manner.
  • step 302 a full set of metrology signals from the one or more wafers 1 12 is acquired.
  • metrology sub-system 102 acquires one or more metrology measurements from one or more wafers 1 12 and transmits the measurements to controller 104,
  • the metrology sub-system 102 may collect a full or sufficient set of metrology signals from a representative set of wafers 1 12 of a lot of wafers. It is noted that the full sampling of step 302 is not bounded to measuring a single wafer, but can be composed of sub-sampling from different wafers.
  • the metrology sub-system 102 may include an imaging- based metrology tool (see FIG. 1 D) configured to collect one or more images of one or more targets 1 1 1.
  • the metrology sub-system 102 may include a scatterometry-based metrology tool (see FIG. 1 E) configured to collect light scattered or reflected (or otherwise emanating) from the wafer 1 12.
  • the metrology signals collected by the metrology sub-system 102 may include one or more scatterometry-based pupil images collected from scatterometry overlay (SCOL) targets and/or multi-layer SCOL targets via the metrology sub-system 102.
  • the metrology signals collected by the metrology sub-system 102 may include one or more contrast-based field images collected from image based overlay (IBO) targets and/or multi-layer IBO targets via the metrology sub-system 102.
  • IBO image based overlay
  • the metrology signals acquired in step 302 may be acquired from any number of locations on the wafer 1 12.
  • the metrology signals may be collected from any of the targets 1 1 1 of the wafer 1 12.
  • the metrology signals may be collected from a set of like targets.
  • the metrology signals may be collected from different types of targets.
  • a portion of the metrology signals may be collected from a first type of overlay metrology target, while a second portion of the metrology signals are collected from a second type of overlay metrology target and so on.
  • a portion of the metrology signals may be collected from an overlay metrology target, while a second portion of the metrology signals are collected from an optical CD and/or focus/dose targets,
  • full set of metrology signals and “sufficient set of metrology signals” are used interchangeably herein and are interpreted to describe the level of signal acquisition in which the addition of one or more metrology signals would not improve process control or tracking.
  • a set of wafer properties are determined and a wafer property metric associated with the set of wafer properties is calculated.
  • the controller 104 after receiving the full set of metrology signals from the metrology subsystem 102, may determine a set of wafer properties from the full set of metrology signals. In turn, the controller 104 may calculate one or more wafer property metrics associated with the set of wafer properties. For example, the controller 104 may determine a set of overlay values corresponding with each location of the full set of metrology signals. In turn, the controller 104 may calculate one or more metrics associated with the set of overlay values. For instance, the controller 104 may determine one or more statistical metrics associated with the distribution of overlay values acquired with the full sample plan.
  • the one or more statistical metrics may include any statistical metric known in the art.
  • the controller 104 may calculate a mean, standard deviation ( ⁇ ) or a multiple thereof (e.g., 3 ⁇ ) and etc. associated with the overlay value distribution obtained with the full sample plan.
  • the controller 104 may determine a set of SWA values corresponding with the targets at the locations of the full set of metrology signals from a previous layer, !n turn, the controller 104 may calculate one or more metrics associated with the set of SWA values. For instance, the controller 104 may determine one or more statistical metrics associated with the distribution of SWA values acquired with the full sample plan. For example, the controller 104 may calculate a mean, standard deviation ( ⁇ ) or a multiple thereof (e.g., 3 ⁇ ) and etc. associated with the SWA value distribution obtained with the full sample plan. It is noted that the scope of the present disclosure is not limited to the examples provided above. It is recognized herein that the present disclosure may be extended to any wafer property known in the art (e.g., CD values) and any wafer property metric (e.g., statistical metrics) known in the art.
  • any wafer property known in the art e.g., CD values
  • any wafer property metric e.g., statistical metrics
  • one or more independent characterization metrics are calculated.
  • the term "independent characterization metric” is interpreted to mean a characterization metric that is independent of the wafer property selected for control (e.g., overlay, SWA, CD and etc.) calculated in step 304, but provides additional information about the given wafer property.
  • the one or more independent characterization metrics may include one or more accuracy merits.
  • the one or more accuracy merits may include, but are not limited to, an overlay target accuracy metric, such as an overlay target accuracy flag.
  • one such overlay target accuracy flag is the Pupil 3 ⁇ accuracy flag.
  • the pupil 3 ⁇ flag is derived by measuring a pupil image and calculating 3 ⁇ for all pixels in the pupil.
  • the pupil 3 ⁇ flag is representative of the target quality and other accuracy related issues, such as arcs.
  • the relationship between overlay and the Pupil 3 ⁇ accuracy flag is described by Gutjahr et ai. in Root cause analysis of overlay metrology excursions with scatterometry overlay technology (SCOL), Proc. SPIE 9778, Metrology, Inspection, and Process Control for IVlicroiithography (March 24, 2016).
  • the one or more independent characterization metrics of step 306 may extend to any characterization metric or accuracy merit known in the art of wafer metrology, such as, but not limited to, a process signature metric (e.g., PSQ), a patterned wafer geometry metric (e.g. , PWG), an overlay target asymmetry metric (e.g., Qmerit) and overlay target accuracy metric (e.g., overlay target accuracy flag).
  • a process signature metric e.g., PSQ
  • a patterned wafer geometry metric e.g., PWG
  • an overlay target asymmetry metric e.g., Qmerit
  • overlay target accuracy metric e.g., overlay target accuracy flag
  • step 308 one or more flexible sparse sample plans are generated.
  • FIG. 3B illustrates a conceptual view of a full sample plan 310 and a flexible sparse sample plan 320.
  • the one or more flexible sparse sample plans are generated based on the set of wafer properties, the wafer property metric, and/or the one or more independent characterization metrics,
  • the one or more flexible sparse sample plans are generated such that the one or more independent characterization metrics of the one or more wafer properties acquired with the flexible sparse sampling plan are equivalent (within a selected tolerance level) to the one or more independent characterization metrics of the one or more wafer properties acquired with the full set of metrology signals.
  • the one or more flexible sparse sample plans are generated such that the one or more independent characterization metrics of the one or more wafer properties acquired with the flexible sparse sampling plan and the one or more independent characterization metrics of the one or more wafer properties acquired with the full set of metrology signals are defined as equivalent if within a selected threshold of one another.
  • the one or more flexible sparse sample plans are generated such that the one or more independent characterization metrics of the one or more wafer properties acquired with the flexible sparse sampling plan and the one or more independent characterization metrics of the one or more wafer properties acquired with the full set of metrology signals are defined as equivalent if within a statistical parameter of one another (e.g., multiple of ⁇ ).
  • the one or more flexible sparse sample plans are generated by co-optimizing all of the wafer properties simultaneously.
  • the wafer properties, corresponding accuracy metric, target layout and signal parameters e.g., intensity, sensitivity and etc.
  • target layout and signal parameters e.g., intensity, sensitivity and etc.
  • at least one wafer property at least one wafer property metric is involved in the co-optimization of the wafer properties.
  • the multiple flexible sparse sampling plans are generated so that each of the wafers within in a wafer lot, or each consecutive lot, uses a different sample plan from the other wafers.
  • the flexible sparse plans are generated such that they are distributed uniformly over the one or more wafers 1 12 and meet local and global test balancing criteria (i.e., balanced test repeats). It is noted that, in the case of overlay measurements, these properties give flexible sparse sample plans the capability to accurately model grid overlay.
  • the flexible sparse sample plans generated in step 308 may be used to filter grid noise out of the metrology signals measured from each wafer. It is noted that grid overlay is representative of the degree by which exposure fields are misregistered.
  • the one or more flexible sparse sample plans 320 provide accuracy and robustness at small sample sizes.
  • flexible sparse sample plans 320 can be used with integrated metrology tools at very small sample sizes (e.g., 20-50 target/wafer) to measure each wafer within a given wafer lot and filter out wafer to wafer grid variation before calculating composite field-by-field corrections for the next lot.
  • Flexible sparse sample plans 320 can be generated such that each flexible sparse sample plan has a specific amount of overlap with the remaining samples plans, while meeting the same balancing criteria as static sample plans.
  • a user can minimize overlap between flexible sparse sample plans 320 in order to maximize (or at least increase) the total targets measured by different sample plans.
  • a use may utilize some overlap between flexible sparse sample plans 320 to consistently compare multiple wafers within each other.
  • the flexible sampling approach of the present disclosure also includes run-time updates to the flexible sparse sample plans 320 based on the independent characterization metrics, such as, but not limited to, a process signature metric (e.g., PSQ), a patterned wafer geometry metric (e.g., PWG), an overlay target asymmetry metric (e.g., Qmerit) and overlay target accuracy metric (e.g., overlay target accuracy flag).
  • a process signature metric e.g., PSQ
  • a patterned wafer geometry metric e.g., PWG
  • overlay target asymmetry metric e.g., Qmerit
  • overlay target accuracy metric e.g., overlay target accuracy flag.
  • FIG. 4 is a flow diagram illustrating steps performed in a method 400 of generating a flexible sparse metrology sampling plan, in accordance with one embodiment of the present disclosure. If is noted herein that the steps of method 400 may be implemented ail or in part by the system 100. It is further recognized, however, that the method 400 is not limited to the system 100 in that additional or alternative system-level embodiments may carry out all or part of the steps of method 400. Further, it is noted herein that the steps and embodiments associated with method 200 and 300 described previously herein are interpreted to extend to method 400. In this regard, the steps of methods 200, 300 and 400 may be combined in any suitable manner.
  • step 402 a full set of metrology signals from the one or more wafers 1 12 is acquired.
  • step 404 a set of wafer properties are determined and a set of accuracy merits associated with the set of wafer properties is calculated.
  • step 406 a statistical metric associated with each of the set of accuracy merits for the set of wafer properties is calculated.
  • step 408 a flexible sparse sampling plan based on the statistical metrics associated with each of the set of accuracy merits is generated.
  • the calculated accuracy merit may be represented symbolically as follows:
  • OVL__A represents an accuracy merit associated with overlay
  • m represents the type of accuracy merit
  • /, j represent target locations on the wafer.
  • the above description is not limited to overlay and may be extended to any type of wafer property, such as, but not limited to, one or more CD parameters (e.g., SWA).
  • the types of accuracy merits may include, but are not limited to, a process signature metric (e.g., PSQ), a patterned wafer geometry metric (e.g., PWG), an overlay target asymmetry metric (e.g., Qmerit) and overlay target accuracy metric (e.g., overlay target accuracy flag).
  • the statistical metric associated with each of the set of accuracy merits for the set of wafer properties may include any statistical metric known in the art.
  • the statistical metric calculated in step 406 may include, but is not limited to, a mean value of the wafer property distribution (e.g., normal distribution), the standard deviation or the like.
  • the flexible sparse sampling plan of step 408 is generated by identifying target locations within the full sampling plan displaying accuracy merit values below a statistically defined threshold.
  • the statistically defined threshold may include a multiple of ⁇ above the mean value of the accuracy merit.
  • the statistically defined threshold may include the following:
  • the flexible sparse sample plan will consist of the target locations having an accuracy merit that is below the sum provided above.
  • the calculation of one or more statistical metrics of step 404 may include calculating one or more statistical metrics associated with each of the set of accuracy merits for the set of wafer properties for at least one of the center of the one or more wafers or the edges of the one or more wafers.
  • a statistically defined threshold may be applied to the set of accuracy merits using the one or more statistical metrics associated with the accuracy merits acquired from the center and/or edges of one or more wafers.
  • the flexible sparse sampling plan may be generated using a selected threshold level.
  • the method 400 may be executed without step 406.
  • a flexible sparse sampling plan may be generated by identifying target locations within the full sampling plan displaying accuracy merit values below a selected threshold for each accuracy type.
  • All of the methods described herein may include storing results of one or more steps of the method embodiments in a storage medium.
  • the results may include any of the results described herein and may be stored in any manner known in the art.
  • the storage medium may include any storage medium described herein or any other suitable storage medium known in the art.
  • the results can be accessed in the storage medium and used by any of the method or system embodiments described herein, formatted for display to a user, used by another software module, method, or system, etc.
  • the results may be stored "permanently,” “semi-permanent!y,” temporarily, or for some period of time.
  • the storage medium may be random access memory (RAM), and the results may not necessarily persist indefinitely in the storage medium.

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Abstract

La génération de plans d'échantillonnage métrologique épars souple consiste à recevoir d'un outil métrologique un ensemble complet de signaux métrologiques émis par une ou plusieurs tranches; à déterminer un ensemble de propriétés de tranches sur la base de l'ensemble complet de signaux métrologiques, et à calculer une métrique de propriétés des tranches associée à l'ensemble de propriétés de tranches; à calculer une ou plusieurs métriques de caractérisation indépendante sur la base de l'ensemble complet de signaux métrologiques; et à générer un plan d'échantillonnage épars souple basé sur: l'ensemble de propriétés de tranches, la métrique de propriétés de tranches, et lesdites une ou plusieurs métriques de caractérisation indépendante. Lesdites une ou plusieurs métriques de caractérisation indépendante desdites une ou plusieurs propriétés calculées avec des signaux métrologiques à partir du plan d'échantillonnage épars souple se situent dans un seuil choisi parmi une ou plusieurs métriques de caractérisation indépendante desdites une ou plusieurs propriétés calculées avec l'ensemble complet de signaux métrologiques.
PCT/US2016/051743 2015-09-21 2016-09-14 Procédé et système de commande de traitement avec échantillonnage souple WO2017053150A1 (fr)

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