WO2017052573A1

WO2017052573A1 - Stepped magnetic tunnel junction devices, methods of forming the same, and devices including the same

Info

Publication number: WO2017052573A1
Application number: PCT/US2015/052148
Authority: WO
Inventors: Charles C. Kuo; Satyarth Suri; Kaan OGUZ; Mark L. Doczy; Kevin P. O'brien; Brian S. Doyle
Original assignee: Intel Corporation
Priority date: 2015-09-25
Filing date: 2015-09-25
Publication date: 2017-03-30
Also published as: TW201724593A

Abstract

Technologies for manufacturing spin transfer torque memory (STTM) elements are disclosed. In some embodiments, the technologies include methods for forming a step proximate an interface between a free magnetic layer and a dielectric layer of a magnetic tunnel junction. In some embodiments, the step may be defined by a spacer material, which may also serve to control the slope of the sidewalls of the dielectric layer and a fixed magnetic layer during the production of the device. As a result, an offset field exhibited by the STTM element may be reduced or even eliminated. Devices and systems including such STTM elements are also described.

Description

STEPPED MAGNETIC TUNNEL JUNCTION DEVICES, METHODS OF FORMING THE SAME, AND DEVICES INCLUDING THE SAME

FIELD

[0001] The present disclosure generally relates to magnetic tunnel junction devices, and, in particular, to memory devices such as spin transfer torque memory (STTM) devices. Methods of forming magnetic tunnel junction devices for various end uses (e.g, STTM elements) and devices including such magnetic tunnel junction devices are also described.

BACKGROUND

[0002] Magnetic random access memory (MRAM) is gaining increased attention due to its potential for replacing conventional memory. In general MRAM may include a series of magnetic tunnel junctions (MTJs) which operate to store information. Such MTJs generally include a plurality of layers (e.g., a fixed magnetic layer, a dielectric (tunneling) layer on the fixed magnetic layer, and a free magnetic layer on the dielectric layer), which collectively determine the magnetic behavior of the device.

[0003] Spin transfer torque memory (STTM) is a type of MRAM memory device that is becoming of increasing interest in the semiconductor industry, due to the relatively small size of its elements, its potential for low power operation, and its potential for direct integration with other elements on a semiconductor chip, such as transistors. Generally, the operation of STTM elements/devices is predicated on the phenomenon of spin transfer torque. When a current is passed through a

magnetization layer of such devices, called the fixed magnetic layer, the current will come out spin polarized. With the passing of each electron in the current through the fixed magnetic layer, the resulting spin (angular momentum) may be transferred to the magnetization of another magnetic layer in the device, called the free magnetic layer, resulting in a small change in the magnetization of the free magnetic layer. In effect, this is a torque which causes precession of the magnetization of the free magnetic layer. Likewise, a torque may be applied to an associated fixed magnetic layer, e.g., due to the reflection of electrons.

[0004] Ultimately when an applied current (e.g., a pulse) exceeds a threshold value (which may be defined at least in part by damping caused by the magnetic material and its environment) the orientation of the magnetization of the free magnetic layer may be switched between a state that is parallel with the orientation of the magnetization of the fixed magnetic layer, and a state that is antiparallel with the orientation of the magnetization of the fixed magnetic layer. The orientation of the magnetization of the fixed magnetic layer may remain unchanged by the applied current, e.g., because the applied current is below a threshold for the fixed magnetic layer and/or because the orientation of the magnetization of the fixed magnetic layer may be "pinned" by one or more adjacent layers, such as a synthetic

antiferromagnetic layer. As such, spin transfer torque can be used to flip the active elements in a random access memory, such as an STTM device.

[0005] The fixed magnetic layer(s) in various MTJ devices such as STTM devices generate magnetic fields (primarily magneto static fields) in the free magnetic layer(s) of the device, e.g., in the perpendicular and/or horizontal direction. When the magnetizations of the fixed layers are anti-parallel, the magnetizations of such layers experienced at free layer may cancel each other to some degree. In an ideal device, the magnetization of such layers is perfectly cancelled when the magnetizations are oriented anti-parallel. However in various real world cases the field cancellation between the free and fixed magnetic layer(s) is not perfect. In such instances a net external field called offset field (H₀ff_set) will exist in the device. Such an offset field may cause the magnetization of the free layer to exhibit asymmetric switching by an applied magnetic field and/or current, which may be undesirable for some applications, such as in STTM devices.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Features and advantages of embodiments of the claimed subject matter will become apparent as the following Detailed Description proceeds, and upon reference to the Drawings, wherein like numerals depict like parts, and in which:

[0007] FIGS. 1A and IB are flow charts of operations of example methods of forming a spin transfer torque memory (STTM) element consistent with embodiments of the present disclosure. [0008] FIGS. 2A-2G stepwise illustrate cross sectional views of various operations in accordance with a method of forming a STTM element consistent with embodiments of the present disclosure.

[0009] FIG. 3 illustrates a cross sectional view of one example of a perpendicular STTM device consistent with embodiments of the present disclosure

[0010] FIG. 4 is a block diagram of an electronic system consistent with embodiments of the present disclosure.

[0011] FIG. 5 is a block diagram of a computing device consistent with embodiments of the present disclosure.

DETAILED DESCRIPTION

[0012] Spin transfer torque memory (STTM) elements and methods of forming such elements are described herein. Devices and systems including STTM elements consistent with the present disclosure are also described. It is noted that for the sake of clarity and ease of understanding the following Detailed Description will proceed with reference being made to illustrative embodiments as shown in the accompanying figures (FIGS), in order to provide a thorough understanding thereof. It will be apparent to one of ordinary skill in the art however that the technologies described herein are not limited to the illustrated embodiments, and may be practiced in other contexts and/or without certain specific details included in the illustrated

embodiments. It should also be appreciated that the various embodiments shown in the FIGS, are illustrative embodiments and are not drawn to scale.

[0013] It is noted that in the context of the present disclosure the terms "on" is used in various instances to denote that one element (e.g., a first layer) is located above another element (e.g., a second layer), but does not require the first element to be in contact with the second element. Rather it should be understood that the term "on," when used in the context of the positional relationship of two elements, means that a first element is formed above a second element, but that other (e.g., third) elements may be present between the first and second elements. In contrast, the term "directly on" is used herein to denote that a first element is in contact with a surface (e.g., an upper surface) of another element, with no intervening elements therebetween.

[0014] It is also noted that in the context of the present disclosure, the terms

"substantially" and "about" when used in connection with a value or range of values mean plus or minus 5% of the denoted value or the end points of the denoted range. When such terms are used in the context of the orientation of an element (e.g., relative to another element), they should be understood as encompassing plus or minus 5 degrees of the indicated orientation. For example, an first element having sidewalls that are oriented "vertical" to a plane of a second element should be understood as being oriented 90 degrees (vertical) to the plane of the second element. In contrast, a first element having sidewalls that are oriented "substantially vertical" with regard to the plane of a second element should be understood as being oriented at an angle ranging from about 85 to about 95 degrees, relative to the plane of the second element.

[0015] In many instances MTJ devices such as STTM elements are formed on a dielectric or other substrate via a multistep process. For example, some processes for forming STTM elements include forming a material stack on a substrate and/or a conductive element/layer thereon (e.g., an interconnect, bond pad, trace, etc. that is present on or within a dielectric substrate). The material stack may include various layers for forming the STTM element. For example, the material stack may include one or more "fixed" magnetic layers, one or more dielectric (e.g., tunnel oxide) layers on the fixed magnetic layer, one or more "free" magnetic layers on the dielectric layer, etc.

[0016] Various other layers may also be included in the material stack, as would be understood by those of ordinary skill in the art. One example of such other layers are pinning layers for the fixed magnetic layer, e.g., one or more synthetic

antiferromagnetic layers that may underlie the fixed magnetic layer and may function to pin the magnetization of the fixed magnetic layer in a particular orientation.

Further examples of other layers that may be included in the material stack include electrodes (contacts) for the fixed and free magnetic layers. For example, in some embodiments the material stack may include a first contact layer for the fixed magnetic layer, and a second contact layer coupled to the free magnetic layer. Of course, various additional layers may also be used.

[0017] With the foregoing in mind, in some processes portions of the material layer stack may be selectively removed to produce an STTM element with a desired geometry. For example, regions of the free magnetic layer may be selectively removed (e.g., using etching, lithography or another suitable process) to result in the production of a workpiece of the structure similar to the structure shown in FIG. 2E. While such processes can successfully remove select portions of the free magnetic layer, the sidewalls of the free magnetic layer may not be oriented vertical relative to the plane of the dielectric layer of the device.

[0018] Indeed as shown in FIG. 2E, the free magnetic layer (and in some instances, an associated mask) may have sidewalls that are sloped relative to the plane of an underlying dielectric layer and fixed magnetic layer. More specifically, the free magnetic layer may exhibit a first slope defined by the equation S = h/w, wherein S is the slope, h is the rise of the free magnetic layer (corresponding to its thickness), and w is the run of the free magnetic layer and is defined by the equation w = w_t - Wb, wherein w_t is the width of the top surface of the free magnetic layer and Wb is the width of the bottom surface of the free magnetic layer.

[0019] The remainder of the STTM element may then be defined, e.g., by selectively removing portions of the dielectric layer and the fixed magnetic layer. For example, portions of the dielectric layer and the fixed magnetic layer may be removed via etching to produce a discrete STTM element on the surface of a substrate. Due to the slope of the free magnetic layer and/or other reasons, however, the sidewalls of the dielectric layer and the fixed magnetic layer may also be sloped relative to the plane of the device.

[0020] The inventors have observed that when operations are carried out to selectively remove portions of the dielectric layer and/or the fixed magnetic layer from a workpiece having a structure similar to FIG. 2E, the end result may be the production of a device having a dielectric layer and a fixed magnetic layer that have sloped sidewalls. Without wishing to be bound by theory, it is believed that the etched sidewalls of the fixed magnetic layer in such devices can result in the production of stray magnetic fields in the fixed magnetic layer, and ultimately to a device that exhibits a relatively high offset field H₀ff_set. Indeed, the inventors have observed in some instances such operations may result in the production of STTM elements that exhibit an H₀ff_set ranging from +/- 100 to about +/- 400 Oersted (Oe), such as from about +/- 100 to about +/- 350 Oe. As noted above, the presence of such an offset field may cause the magnetization of the free layer to exhibit asymmetric switching, which may be undesirable for some applications.

[0021] With the foregoing in mind, one aspect of the present disclosure relates to methods for forming MTJ devices, such as spin transfer torque memory (STTM) elements. As will be appreciated, such methods may be useful in forming MTJ devices such as STTM elements in the context of a wide variety of devices. For example, the technologies described herein may be useful for forming STTM elements in the context of non- volatile memory (NVM), magnetic random access memory (MRAM), magnetic tunnel junction (MTJ) devices including but not limited to perpendicular MTJ devices, STTM devices (e.g., perpendicular STTM devices), non-embedded or stand-alone memory devices, combinations thereof, and the like. Of course such end uses are enumerated for the sake of example only, and it should be understood that the technologies described herein may be used in the context of other devices (or the formation thereof).

[0022] As will be appreciated from the following discussion, some embodiments of the present disclosure relate to the production of STTM elements and other MTJ devices that exhibit little or no offset field (H₀ff_set). As will be explained in detail, the technologies of the present disclosure may accomplish that goal through the use of a spacer that defines a step between the sidewall(s) of a free magnetic layer of an MTJ device (e.g., an STTM element) and the sidewalls of an associated dielectric

(tunneling) and/or fixed magnetic layer. In various embodiments, the spacer may have a re-entrant or other profile that compensates for the slope of the sidewalls of the free magnetic layer (and in some cases an overlying hardmask layer), enabling the production of a well-defined step having desired geometric characteristics. In particular, in some embodiiments the technologies described herein can result in an MTJ having a step size that is at least about 2 to about 5 nm wide or more, as discussed below. In general, Hoff_set may decrease with increasing step size, with the maximum step size being bounded by the largest layout area that may be acceptable for an MTJ in a given application.

[0023] Moreover, the sidewalls of the spacer may have a slope that differs from the slope of the sidewalls of the free magnetic layer in such a device. For example where the sidewalls of the free magnetic layer have a first slope that is positive, the sidewalls of the spacer may have a second slope that is greater than the first slope, and in some instances approaches positive infinity. Alternatively in instances where the first slope of the free magnetic layer sidewalls is negative, the second slope of the spacer may be more negative (i.e., less than) the first slope, and in some instances may approach negative infinity. Put in other terms, in some embodiments the sidewalls of the spacer are oriented vertical or substantially vertical relative to a horizontal plane of a dielectric layer and/or fixed magnetic layer of the device, even if the sidewalls of the free magnetic layer are sloped (i.e., not vertical or substantially vertical) relative to the horizontal plane of the dielectric and/or fixed magnetic layer.

[0024] Reference is therefore made to FIGS. 1A and IB, which are flow charts of example operations in accordance with example methods of forming a magnetic tunnel junction device (e.g., an STTM element/device) consistent with the present disclosure. For the sake of convenience and ease of understanding, the operations of FIG. 1 A and IB will be described in conjunction with FIGS. 2A-2G, which stepwise the formation of one non-limiting example of an STTM element consistent with the present disclosure. It should be understood of course that FIGS. 2A-2G are for the sake of illustration and that the geometry, scale, and/or general configuration of various features shown therein are for the sake of example only. Indeed and as will be appreciated by one of ordinary skill in the art, the methods described herein may be usefully applied to form a wide variety of MTJ devices such but not limited to STTM elements, and are not limited to the formation of devices having the specific configuration shown FIG. 2G.

[0025] Returning to FIG. 1A, method 100 may begin at block 101. The method may proceed to optional block 110, pursuant to which a predecessor of an STTM element (hereinafter, a "workpiece") may be provided. For the sake of clarity and

completeness, the present disclosure will proceed to describe example operations of one non-limiting method of providing a workpiece having the structure shown in FIG. 2E. It should be understood however that workpieces having other structures may also be used, and that the methods described herein are not conditioned on a specific manner of preparing a workpiece, such as the operations described below in conjunction with block 110 and FIGS. 2A-2D. Moreover, it should be understood that in some embodiments a workpiece may be obtained or otherwise provided (e.g., in pre-constructed form), thereby obviating the need for the operations of block 110.

[0026] That being said, pursuant to optional block 110 a workpiece may be provided. In this regard reference is made to FIG. IB, which illustrates various example operations that may be carried out in accordance with one example method of providing an Workpiece. As shown in FIG. IB, the operations of block 110 may begin at block 111, pursuant to which a substrate may be provided.

[0027] The type and nature of the substrate is not limited, provided that it is suitable for the formation and/or support of an STTM element. Non-limiting examples of suitable substrates include but are not limited to dielectric substrates/layers such as those that may be found in various components of semiconductor devices, e.g., interconnect layers, bump over metallization layers, or other components in which dielectric interlayers may be used. Without limitation, in some embodiments the substrate may be an interlayer dielectric (ILD), e.g., which may be located in or proximate to one or more interconnects of a semiconductor device. Of course, such substrates are enumerated for the sake of example only, and other suitable types of substrates may be used and are envisioned by the present disclosure.

[0028] As one example of a substrate that may be used in accordance with the present disclosure reference is made to FIG. 2A, which illustrates a substrate 201. As will be described later, substrate 201 may be used to support various elements of an STTM element/device, including various conductive elements (e.g., interconnects, traces, etc.), a material stack for the formation of a magnetic tunnel junction, etc. It is noted that for the sake of illustration and ease of understanding, FIGS. 2A-2G provide a "zoomed in" view of the production of a single STTM element on substrate 201. It should be understood however, that the technologies described herein may be equally applied to produce a plurality of STTM elements or other MTJ devices on substrate 201. Moreover, it should be understood that substrate 201 is illustrated without topography (i.e., as being flat) and without other features (e.g., trenches, grooves, etc.), for the sake of clarity and ease of understanding. However, one of ordinary skill in the art will understand that such features are encompassed herein.

[0029] Returning to FIG. IB, once an appropriate substrate is provided, the method may advance from block 111 to block 112. Pursuant to block 112, a material stack may be formed. As used herein, the term "material stack" is used to refer to a series of material layers which may be subsequently processed to form all or a portion of an MTJ element/device, such as an STTM element/device. With that in mind the present disclosure will proceed to describe the production of one example of a material stack which may be used to form a magnetic tunnel junction (MTJ) of an STTM element. [0030] It is noted that for the sake of illustration and ease of understanding, the description is limited to the production of an MTJ from a material stack that includes a single fixed magnetic layer, a single dielectric (e.g., tunnel oxide) layer, and a single free magnetic layer. It should be understood however that additional layers may also be included. Indeed as noted above, the material stack in some embodiments may include one or more additional layers, such as one or more underlayers beneath the fixed magnetic layer. Such underlayers may include, for example, pinning layers such as synthetic antiferromagnetic layers, electrical contacts such as a first contact layer, etc., combinations thereof, and the like, as would be understood by those of skill in the art.

[0031] Moreover in some embodiments (though not shown in the FIGS.), a material stack may include a conductive layer on substrate, a first contact layer on the conductive layer, one or more underlayers (e.g., antiferromagnetic layers) on the first contact layer, and a fixed magnetic layer on the underlayers. Alternatively or additionally, the material stack may also include one or more over layers, i.e., layers which may be formed over the free magnetic layer of the MTJ. Such over layers may include, for example, a second contact layer as described above, either alone or in combination with other over layers as would be understood by those of skill in the art. Likewise, it should be understood that the fixed magnetic layer, free magnetic layer, and dielectric (e.g. tunnel oxide) layer of the MTJ's described herein may each be formed of one or multiple layers.

[0032] Reference is therefore made to FIG. 2B, which illustrates one example of a material stack 203 as formed on the upper surface of substrate 201. As shown, material stack 203 includes fixed magnetic layer 204, dielectric layer 205, and free magnetic layer 206. In the illustrated embodiment, fixed magnetic layer 204 is formed on (e.g., directly on) the upper of substrate 201, but as noted previously other layers (e.g., a conductive layer, first contact layer, one or more underlayers, etc.) may be present between fixed magnetic layer 204 and the upper surface of substrate 201.

[0033] In any case, fixed magnetic layer 204 may be formed of any suitable materials that may be used in an STTM element, and may include one or more than one layer, as previously described. Non- limiting examples of suitable materials that may be used to form fixed magnetic layer include magnetic alloys of cobalt, such as but not limited to alloys of cobalt, iron, and boron (e.g., CoFeB), one or multiple alternating iron and platinum layers, one or multiple alternating cobalt (Co) and platinum (Pt) layers (Co/Pt), one or multiple alternating cobalt iron alloy (CoFe) and Pt layers (CoFe/Pt), one or multiple alternating iron platinum (FePt) alloy and Pt layers (FePt/Pt), one or multiple layers of a metal X doped with a dopant Y, where x is iron, cobalt, and/or nickel, and Y is boron, phosphorous, carbon, or silicon, one or more iron platinum (FePt) alloy layers, one or multiple alternating layers of CoFeB and a heavy metal, J, wherein J is tungsten, tantalum (Ta), molybdenum (Mo), niobium (Nb), chromium (Cr), or a combination thereof (e.g., (e.g., CoFeB/J/CoFeB), rare earth/transition metal alloys such as terbium iron cobalt (TbFeCo), gadolinium iron cobalt (GdFeCo), combinations thereof, and the like.

[0034] Without limitation, in some embodiments fixed magnetic layer 204 may be formed from one or more layers of CoFeB. In other embodiments, fixed magnetic layer 204 is formed from a stack including a first layer of CoFeB or CoFe, a second layer of ruthenium on the first layer, and a third layer of CoFeB on the ruthenium layer. In such embodiments, fixed magnetic layer 204 may be or include an antiferromagnetic stack of CoFe, ruthernium, and CoFeB, wherein the thickness of the second layer (i.e., the ruthenium layer) may be very specific, e.g., ranging from about 8 to about 9 nanometers (nm)

[0035] Regardless of its composition or configuration, fixed magnetic layer 204 may be formed of a material or stack of materials that are suitable for maintaining a fixed majority spin. Thus, fixed magnetic layer 204 in some embodiments may be referred to as a synthetic anti-ferromagnetic layer. For example in some embodiments fixed magnetic layer 204 is configured to maintain a fixed majority spin that is substantially aligned with the plane of substrate 201 and/or which is perpendicular or substantially perpendicular to the plane substrate 201. Without limitation, in some embodiments material stack 203 is for forming a perpendicular STTM element, in which case fixed magnetic layer 204 may be configured to maintain a majority spin that is

perpendicular to the plane of substrate 201 or, more generally, perpendicular to the plane of the STTM element.

[0036] The total thickness the one or more layers within fixed magnetic layer 204 may vary considerably, depending on the application and the nature of the materials used in material stack 203. For example, in some embodiments the thickness of one or more of the layer(s) in fixed magnetic layer 204 may range from about 3 angstroms to about 14 angstroms. In some embodiments, the total thickness of the magnetic layer(s) within fixed magnetic layer may range from about 100 to about 200 angstroms.

[0001] Dielectric layer 205 in some embodiments is composed of a material that is suitable for allowing current of a majority spin to pass through it, while impeding at least to some extent the passage of current of a minority spin. Dielectric layer 205 may therefore be understood as a tunneling layer, and may be referred to herein as such. In some embodiments, dielectric layer 205 may be a tunnel oxide layer which is formed from one or more oxides. Non-limiting examples of oxides which may be used to form dielectric layer 205 include magnesium oxide (MgO), aluminum oxide (AI2O₃), europium oxide (EuO), europium magnesium oxide (EuMgO), europium sulfide (EuS), europium selenide (EuSe), bismuth manganate (BiMnC ), nickel iron oxide (NiFe₂0₄), cobalt iron oxide (CoFe₂0₄), gallium arsenide (GaAs), europium oxide (EuO), strontium titanate (SrTiC ), magnesium aluminum oxide (MgAlO), combinations thereof, and the like. Of course, other suitable materials may also be used to form dielectric layer 205. Without limitation, in some embodiments dielectric layer 205 is formed from MgO.

[0002] The total thickness of the dielectric layer 205 may vary considerably, depending on the application and the nature of the materials used in material stack 203. For example, in some embodiments the thickness of dielectric layer 205 may range from about 6 angstroms to about 12 angstroms. As may be appreciated, the thickness of dielectric layer 205 may impact the resistance area produce (RA) of the film, as measured in ohms per square micron ((Ω/μ²). It may therefore be desirable ot control the thickness of dielectric layer 205 to achieve a desired RA, such as from about 1 to about 20 Ω/μ². Without limitation, in some embodiments dielectric layer 205 has a thickness of about 9 angstroms.

[0003] Material stack 203 may be generally configured to provide a planar or a perpendicular STTM element. Depending on the desired configuration, the configuration of fixed magnetic layer 204 and free magnetic layer 206 may be altered. Without limitation, in some embodiments material stack 206 is configured to provide a perpendicular STTM element. In this regard, the free magnetic layer may be configured such that a perpendicular component of the magnetic orientation dominates over an in-plane component of the magnetic orientation of the layer. For example, where free magnetic layer is or includes one or more layers of CoFeB alloy, the perpendicular component of magnetization obtained from the iron of the layer interacting with oxygen in dielectric layer 205 (e.g., MgO) may dominate over the horizontal component of magnetization provided in the layer. As may be appreciated, the degree of oxidation of surface (Fe) atoms in free magnetic layer 206 at the interface with the dielectric (MgO) layer 205 may cause free magnetic layer 206 to have perpendicular-dominated spin states.

[0004] As noted previously, in some embodiments one or more layers of a CoFeB alloy may be used to form free magnetic layer 206. Although CoFeB may be particularly suitable in some applications, it should be understood that other materials may be used to form free magnetic layer 206. In this regard, free magnetic layer 206 may be formed from one or more layers of magnetic alloys of cobalt, such as but not limited to alloys of cobalt, iron, and boron (e.g., CoFeB), one or multiple alternating iron and platinum layers, one or multiple alternating cobalt (Co) and platinum (Pt) layers (Co/Pt), one or multiple alternating cobalt iron alloy (CoFe) and Pt layers (CoFe/Pt), one or multiple alternating iron platinum (FePt) alloy and Pt layers (FePt/Pt), one or multiple layers of a metal X doped with a dopant Y, where x is iron, cobalt, and/or nickel, and Y is boron, phosphorous, carbon, or silicon, one or more iron platinum (FePt) alloy layers, one or multiple alternating layers of CoFeB and a heavy metal, J, wherein J is defined above, or a combination thereof (e.g., (e.g., CoFeB/H/CoFeB), combinations thereof, and the like..

[0005] The thickness of the one or more layers within free magnetic layer 206 may vary considerably, depending on the application and the nature of the materials used in material stack 203. For example, in some embodiments the thickness of one or more of the layer(s) in free magnetic layer 206 may range from about 1 to about 30 angstroms, such as about 10 to about 20 angstroms.

[0006] The various layers of material stack 203 may be formed on substrate 201 in any suitable manner, such as by sputtering, physical vapor deposition, chemical vapor deposition, atomic layer deposition, combinations thereof, and the like, as would be understood by one of ordinary skill in the art.

[0007] Returning to FIG. IB, once a material stack has been formed pursuant to block 112 the method may advance to block 113, pursuant to which the free magnetic layer may be processed into a desired geometry for its end use in an STTM element/device. In this regard it is noted that a wide variety of processing techniques may be employed to selectively remove portions free magnetic layer into a desired geometry. With that in mind, for the sake of completeness and ease of understanding the present disclosure will proceed to describe a process in which material stack 203 is processed via lithography into a desired geometry.

[0008] Attention is therefore drawn to FIGS. 2C to 2E, which depict operations of a lithographic process for processing a free magnetic layer of a material stack, specifically free magnetic layer 206. As shown in FIG. 2C, processing of free magnetic layer 206 may begin with the deposition of a mask 207 on the upper surface of free magnetic layer 206. In the illustrated embodiment, mask 207 is shown as being formed directly on the upper surface of free magnetic layer 206. However it should be understood that such a configuration is not required, and that one or more interlayers (e.g., electrical contacts, other layers, etc.) may be present between free magnetic layer 206 and mask 207.

[0009] Mask 207 may be formed from or include any suitable material which may serve to mask one or more regions of free magnetic layer 206, e.g., during a subsequent etching or other selective removal process. Without limitation, in some embodiments mask 207 is a hard mask that may be resistant to removal by operations that are subsequently designed to selectively remove portions of material stack 203, and specifically portions of free magnetic layer 206. In this regard, mask 207 in some embodiments mask 207 is a heavy metal hard mask, such as hard mask formed from or containing tantalum, tungsten, hafnium, molybdenum, ruthenium, titanium, titanium nitride, tantalum nitride, combinations and/or alloys thereof, and the like. Without limitation, in some embodiments mask 207 is a tantalum hard mask.

[0010] After mask 207 is deposited, it may be patterned (e.g., via a lithographic or other process) to define a protected region (not labeled) of free magnetic layer 206. For example and as shown in FIG. 2D, regions of mask 207 may be removed such that a portion of mask 207 remains to protect underlying portions of material stack 203 (and particularly free magnetic layer 206) during subsequent processing steps.

[0011] Once mask 207 has been patterned or is otherwise defined over one or more regions of free magnetic layer 206, processing of material stack 203 may proceed by selectively removing portions of free magnetic layer 206. More specifically, regions of free magnetic layer 206 that are not protected by mask 207 may be selectively removed. In this regard, selective removal of the unprotected regions of free magnetic layer 206 may proceed in any suitable manner, such as by an etching or other suitable process. Without limitation, in some embodiments selectively removal of unprotected regions of free magnetic layer 206 may be performed via plasma etching, though of course other selective removal processes may be used. For example, selective removal of unprotected regions of free magnetic layer 206 may in some embodiments be accomplished by exposing the structure of FIG. 2D to an etching chemistry that is selective to mask 207 and dielectric layer 205, i.e., which etches unprotected portions of free magnetic layer 206, while leaving mask 207 and dielectric layer unaffected or substantially unaffected.

[0012] In the case of plasma etching, during such a process the structure of FIG. 2D may be exposed to ions in a plasma. Those ions may contact unprotected regions of layer stack 203, thereby removing unprotected regions of free magnetic layer 206. Control may be exercised over process parameters (e.g., time, temperature, etc.) to ensure that etching is concluded at the upper surface of dielectric layer 205.

Alternatively as noted above, a wet etchant that is selective to dielectric layer 205 and mask 207 may be used, resulting in the complete removal of unprotected regions of free magnetic layer 206.

[0013] In any case, the selective removal of unprotected regions of free magnetic layer 206 may result in the production of a workpiece 290 of the structure shown in FIG. 2E. As shown, workpiece 290 includes substrate 201, fixed magnetic layer 204, dielectric layer 205, free magnetic layer 206, and mask 207, wherein free magnetic layer 206 has a width Wl that is less than a width W2 of dielectric layer 205 and a width W3 of fixed magnetic layer 204. In that regard Wl may be any suitable width, so long as it is less than W2 and W3.

[0014] Moreover and as further shown in FIG. 2E, free magnetic layer 206 and mask layer 207 may have sidewalls 212, 214, respectively, either or both of which may exhibit a slope relative to the plane of workpiece 290 or, more specifically, to the plane of dielectric layer 205 and/or fixed magnetic layer 204. In particular, sidewalls 212 of free magnetic layer 212 may exhibit a first slope, SLi, wherein SLi = h/w, in which h corresponds to the thickness of free magnetic layer 206, and w corresponds to the difference between the width of free magnetic layer 206 at the top and bottom surface proximate a common sidewall 212, as shown in FIG. 2E. Alternatively, SLI may be defined as the angle of a sidewall of free magnetic layer 206, relative to the horizontal plane of dielectric layer 205. In that regard, SL1 may range from about 75 to less than 90 degrees, such as from about 80 to less than 90 degrees, or even from about 85 to less than 90 degrees. Alternatively in some embodiments SL1 may range from less than about 115 to greater than 90 degrees, less than about 100 to less greater than 90 degrees, or even less than about 95 to greater than 90 degrees.

[0015] Returning to FIG. 1A, at this point the operations of optional block 110 may be considered complete, and workpiece 290 (shown in FIG. 2E may be formed. More particularly, the operations through optional block 11 may result in a workpiece 290 that includes a substrate 201, a fixed layer 204 on substrate 201, a dielectric layer 205 on fixed layer 204, a free layer 206 on dielectric layer 205, and an optional hardmask layer 207 on free layer 206, wherein the dielectric layer has a width W2, the free layer has a width Wl, and Wl < W2. Put in other terms, free magnetic layer 206 and optional hardmask layer 207 have been patterned such that at least a portion of the upper surface of dielectric layer 205 is exposed.

[0016] At that point (or if a workpiece has been previously provided), the method may proceed to block 120, pursuant to which a spacer predecessor may be formed. In this regard reference is made to FIG. 2F, which depicts one example of a modified workpiece 290' , which includes a spacer predecessor 215 as deposited on the exposed upper surfaces of dielectric layer 205, the sidewalls 212, 214 of free magnetic layer 206 and mask 207, and on the upper surface of mask 207.

[0017] A wide variety of materials may be used to form spacer predecessor 215. With this in mind and as will be discussed below, the material of spacer 215 may be selected such that it can protect mask 207 and free magnetic layer 206, e.g., during subsequent processing steps that result in the removal of regions of dielectric layer 205 and the fixed magnetic layer 204. For example in some embodiments the material of spacer predecessor 215 is selected such that it may be anisotropically etched by a wet or dry etching chemistry that may be applied to selectively remove regions of dielectric layer 205 and fixed magnetic layer 204. More specifically, in some embodiments the material of spacer predecessor may be selected such that it may be etched (e.g., by a wet or dry etching chemistry) vertically at a greater rate than it is etched horizontally. [0018] With the foregoing in mind, non-limiting examples of suitable materials that may be used to form spacer predecessor 215 include oxides, nitrides, and oxynitrides, such as but not limited to titanium oxide, titanium nitride, tantalum nitride, silicon oxynitride, silicon oxide, silicon dixodie, combinations thereof, and the liked.

[0019] Spacer predecessor 215 may be formed on workpiece 290 in any suitable manner. For example, spacer predecessor 215 may be formed by depositing the material thereof on workpiece 290 via sputtering, physical vapor deposition, chemical vapor deposition, atomic layer deposition, combinations thereof, and the like. Without limitation, in some embodiments spacer predecessor 215 is formed on workpiece 290 via sputtering of physical vapor deposition.

[0020] In any case, the formation of spacer predecessor 215 may be carried out such that the material thereof is deposited in a non-conformal manner on the exposed surfaces of workpiece 290. That is, the formation of spacer predecessor 215 may be carried out such that the material thereof builds up on different surfaces of workpiece at different rates. For example, the formation of spacer predecessor 215 may be carried out such that spacer material builds up on surfaces that are generally horizontal (e.g., the upper surface of dielectric layer 205 and the upper surface of mask 207) at a greater rate than it does on surfaces that are generally vertical (e.g., the sidewalls of free layer 206 and mask 207).

[0021] For example and as shown in FIG. 2F, non-conformal deposition of spacer material on workpiece 290 may result in the formation of a spacer predecessor 215 having non-uniform thickness. In some embodiments and as illustrated in FIG. 2F, spacer predecessor 215 may have a first average thickness, a, on the upper surface of the dielectric layer, a second average thickness, b, on the upper surface of the mask layer, and a third average thickness, c, on the sidewalls of the mask and free layers, wherein a, b, and c are different. Without limitation, in some embodiments non- conformal deposition of spacer material may be carried out such that the third thickness, c, is less than the second thickness, b, which in turn is less than the first thickness, a (i.e., wherein c < b < a).

[0022] In some embodiments the first average thickness, a, may be defined as the average thickness of spacer predecessor 215 in a first region, I, above the upper surface of dielectric layer 205. In contrast, the second average thickness, b, may be defined as the average thickness of spacer predecessor 215 in a second region, II, above the upper surface of mask 207. And the third average thickness, c, may be defined as the average thickness of spacer predecessor 215 in a third region, III, proximate the sidewalls of free magnetic layer 206 and mask 207. Without limitation, in some embodiments thickness a, b, and c may be selected so as to provide a step, s, having a desired width.

[0023] With the foregoing in mind the cross-sectional geometry of spacer predecessor 215 may vary considerably depending on the application, and therefore the present disclosure envisions the use of spacer predecessors having a wide variety of geometries. Without limitation, in some embodiments spacer predecessor 215 may have a re-entrant cross sectional geometry, as generally shown in FIG. 2F. As may be appreciated, when spacer predecessor 215 has a re-entrant profile, it may include sidewalls 216 that have a second slope, SL2, that differs from the first slope, SL1, of the sidewalls 212, 214 of free magnetic layer 205 and mask 207. For example and as shown in FIG. 2F, in some embodiments SL2 may be of an opposite sign as SL1. For example where SL1 is positive (as in the case with the left sidewall of mask 207 and free magnetic layer 206, SL2 may be negative. Alternatively where SL1 is negative (as in the case with the right sidewall of mask 207 and free magnetic layer 206), SL2 may be positive. Alternatively, sidewalls 216 may be vertical or substantially vertical, in which case SL2 may be or approach positive or negative infinity.

[0024] At this point the operations of block 120 may be considered complete, and method 100 may proceed to block 130. Pursuant to block 130, the remainder of the MTJ element/device (e.g., the STTM element/device) may be formed. In this regard, the operations pursuant to block 130 may include the execution of a etching process to remove portions of spacer predecessor 215, as well as regions of dielectric layer 205 and fixed magnetic layer 204. For example, in some embodiments a workpiece 290' of the structure shown in FIG. 2F may be exposed to a wet or dry etching chemistry that is configured to remove regions of spacer predecessor 215, dielectric layer 205, and fixed magnetic layer 204, while leaving at least a portion of spacer predecessor intact in a should region proximate the sidewalls 212, 214, of free magnetic layer 206 and mask 207, respectively. The remaining portion of spacer predecessor 215 may define a spacer 215', which in turn may define a step, s, between the sidewall of free magnetic layer 206 proximate an interface with dielectric layer 205 (e.g., at point 217), and an outer edge of dielectric layer 205 (e.g., at point 218), as explained further below.

[0025] Without limitation, in some embodiments an anisotropic etching process is carried out on workpiece 290', so as to selectively remove regions of spacer predecessor 215, dielectric layer 205, and fixed magnetic layer 204. In particular, the anisotropic etching process may be configured such that the etch proceeds vertically through spacer predecessor 215, dielectric layer 205, and fixed magnetic layer 204 at a greater rate than it proceeds horizontally through such elements. For example, in some embodiments anisotropic etching may be carried out by exposing the workpiece 290' to a wet etchant that etches vertically through the above mentioned structures at rate that is one to several times greater than the rate at which it etches horizontally through such structures. Alternatively or additionally, ion milling or another suitable process may be used to physically remove portions of spacer predecessor 215 from workpiece 290'.

[0026] In any case, the outcome of the operations of block 130 may be the production of a MTJ device (e.g., an STTM element/device) that includes a spacer defining a step, s, proximate an interface between free magnetic layer and dielectric layer. In some instances and as will be described below, the spacer may include one or more sidewalls having a slope SL3, which SL3 is different from the slope, SL1, of the sidewalls of the free magnetic layer. Moreover, the slope SL3 may be carried through to the sidewalls of the dielectric layer and/or the fixed magnetic layer. That is like the sidewalls of the spacer, the sidewalls of the dielectric layer and/or the fixed magnetic layer may also have sidewalls exhibiting a slope, SL3.

[0027] As one example of a MTJ device that may be produced in the above manner, reference is made to FIG. 2G. As shown, FIG. 2G depicts an MTK device 291 (e.g., an STTM element/device) that includes substrate 201, fixed magnetic layer 204 on substrate 201, dielectric layer 205 on fixed magnetic layer 204, free magnetic layer 206 on dielectric layer 205, and mask 207 on free magnetic layer 206. In addition, device 291 includes a spacer 215', which is disposed at shoulder regions Al (e.g. proximate the sidewalls 212, 214 of free magnetic layer 206 and mask 207, respectively).

[0028] As further shown in FIG. 2G, spacer 215' may define a step, s, proximate the interface between the bottom surface of free magnetic layer 206 and dielectric layer 205. More particularly, spacer 215 ' may define a step that extends from a point 217 on sidewall 212 proximate the bottom surface of free magnetic layer 206 to a point 218 at an outer edge of the sidewalls 220 of dielectric layer 205 proximate an upper surface thereof. As further shown, step s may be carried through to fixed magnetic layer 204, i.e., such that the sidewalls 221 of fixed magnetic layer 204 are aligned or substantially aligned with sidewalls 220 of dielectric layer 205.

[0029] One function of the step, s, may be to compensate for stray fields that may be produced by fixed magnetic layer 204. In this regard, the width of the step, s, may have an impact on the magnitude of such stray fields. It may therefore be desireable to control the width of the step, s, to a desired value. With that in mind, the width of step, s, may vary considerably depending on the application, geometry of device 291 , the composition of dielectric layer 205 and/or fixed magnetic layer 204, or a combination thereof. That being said, in some embodiments the width of the step, s, may range from greater than 0 to about 15nm, such as about 1 to about 10 nm, about 2 to about 7.5 nm, or even about 5 to about 7.5nm. In some embodiments, the width of step s is about 5 nm.

[0030] As further shown in FIG. 2G, spacer 215' may include sidewalls 219 that have are oriented vertical or substantially vertical in a region proximate the sidewalls 212 of free magnetic layer 206. Alternatively or additionally, sidewalls 219 may have a slope SL3 relative to the plane of fixed magnetic layer 204, wherein the slope is representative of a vertical or substantially vertical orientation (e.g., is or approaches positive or negative infinity or, in other terms, is substantially 90 degrees relative to the horizontal plane of dielectric layer 205). With this in mind, in some embodiments the sidewalls 220, 221 of dielectric layer 205 and fixed magnetic layer 204 may have a slope (not labeled) that is the same or substantially the same as SL3, albeit relative to the plane of substrate 201 , fixed magnetic layer 204, or dielectric layer 205.

[0031] In some embodiments, the MTJ devices described herein (e.g., MTJ device 291) may exhibit no offset field H₀ff_set, or may exhibit an H₀ff_set that is relatively low. For example, in some embodiments MTJ device 291 may exhibit an offset field that is less than about 100 Oe, such as less than about 50 Oe, less than about 25 Oe, or even about 0 Oe. Without limitation, in some embodiments the MTJ devices described herein exhibit an H₀ff_set of O Oe. [0032] Returning to FIG. 1A, following the production of a structure consistent with FIG. 2G, the method 100 may proceed from block 130 to block 140 and end.

[0033] Another aspect of the present disclosure relates to STTM devices including one or more STTM elements, such as those having the structure shown in FIG. 2G described above. It is noted that while the present disclosure focuses on perpendicular STTM devices and elements, horizontal or planar STTM elements/devices are also contemplated.

[0034] In this regard reference is made to FIG. 3, which illustrates one example of an STTM element/device consistent with the present disclosure. As shown, STTM element/device 300 may include material stack (not labeled), which may be formed on a substrate (not illustrated for clarity). As shown, the material stack may include a fixed magnetic layer 204, a dielectric layer 205 on fixed magnetic layer 204, and a free magnetic layer 206 on dielectric layer 205, and a mask 207 on free magnetic layer 206. In addition, STTM element/device 300 may include a spacer 215' located at regions Al, i.e., proximate the sidewalls of free magnetic layer 206 and mask 207. Spacer 215' may define a step, s, as previously described. In addition, spacer 215' may include sidewalls 222 having a slope SL3 that differs from the slope SL1 of the sidewalls 212 of free magnetic layer 206, as previously described. Further description of the nature and characteristics of such layers is not reiterated, as it has been previously described in conjunction with FIG. 2G.

[0035] As noted above fixed magnetic layer 204 may have a magnetic orientation that is pinned in a direction that is perpendicular to the plane of substrate 201. This concept is shown in FIG. 3, wherein the orientation 305 of the magnetization of fixed magnetic layer is shown with an arrow directed perpendicular to the plane of substrate 201. As previously explained and as would be understood by those of skill in the art of STTM devices, free magnetic layer 206 may have an orientation 303 of magnetization that may be also be perpendicular to the plane of substrate 201 , but which may be aligned parallel or antiparallel with the orientation of magnetization 305 of fixed magnetic layer 204. As shown in FIG. 3, when the orientation 303 of magnetization of free magnetic layer 206 is aligned parallel with the orientation 305 of magnetization of fixed magnetic layer 206, element/device 300 may be in a low resistance state, i.e., a state in which electrons may tunnel relatively easily through dielectric layer 205. In instances where orientation 303 is aligned antiparallel to orientation 305, however, element 300 may be in a high resistance state, i.e., a state in which it is relatively more difficult for electrons to tunnel through dielectric layer 205.

[0036] Consistent with the previous description, although not shown in FIG. 3 the material stack may include additional layers above and/or below free magnetic layer 206, fixed magnetic layer 204, or both. For example, in some embodiments a first contact (electrode), e.g., of tantalum, is formed as a layer below fixed magnetic layer 204, and a second contact (electrode), e.g., of tantalum, is formed as a layer above free magnetic layer 206. Alternatively or additionally, in some embodiments a synthetic antiferromagnetic layer is formed below fixed magnetic layer 204.

[0037] As further shown in FIG. 3, in some embodiments a first electrode 301 (e.g. a first trace) may be used to couple free magnetic layer 206, e.g., to another component such as a voltage source. Similarly, a second electrode 302 (e.g., a second trace) may be coupled to conductive material 202, e.g., so as to electrically couple fixed magnetic layer to another component. Via first and second electrodes 301, 302, voltage may be applied to device/element 300, causing orientation 303 to switch from a direction that is parallel with orientation 305 to a direction that is anti -parallel with orientation 305, and vice versa.

[0038] FIG. 4 illustrates a block diagram of an electronic system 400 in accordance with embodiments of the present disclosure. Electronic system 400 may correspond to, for example, a portable system, a computer system, a process control system, or any other system that uses a processor and associated memory. Electronic system 400 may include, for example, a processor 402, a controller 404, a memory device 406, and an input/output device (I/O) 410. While system 400 is depicted in FIG. 4 with limited components, it should be understood that it may include a plurality of processors, memory devices, controllers, I/O's and other elements that may be found in integrated circuits. In some embodiments, system 400 may be configured to execute instructions which define operations which are to be performed on data by processor 402, as well as other transactions between processor 402, memory device 406, controller 404, and/or I/O 410.

[0039] In general, controller 404 may function to coordinate the operations of processor 404, memory device 406, and I/O 410 by cycling through a set of operations that cause instructions to be retrieved from memory device 708 and executed. In this regard, memory device 406 may include a STTM element and/or device, such as those described above. In some embodiments, memory device 406 includes a plurality of in-plane or perpendicular STTM elements. Alternatively or additionally, one or more STTM elements/devices consistent with the present disclosure may be embedded in processor 402, controller 404, and/or I/O 410, e.g., a local memory,

[0040] Another aspect of the present disclosure relates to a computing device including STTM elements/devices consistent with the present disclosure. In this regard reference is made to FIG, 5, which illustrates a computing device 500 in accordance with various embodiments of the present disclosure. As shown, computing device 500 includes motherboard 802, which may include various components such as but not limited a processor 404, communications circuitry (COMMS) 506, any or all of which may be physically and electronically coupled with motherboard 502.

[0041] Depending on its application, computing device 500 may also include other components, such as but not limited to volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen controller, a battery, various codecs, various sensors (e.g., a global positioning system (GPS),

acceierometer, gyroscope, etc.), one or more speakers, a camera, and/or a mass storage device,

[0042] COMMS 506 may be configured to enable wired or wireless communication for the transfer of data to and from the computing device 400. In some embodiments, COMMS 506 may be configured to enable wireless communications via any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802, 11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.

[0043] STTM elements/devices may be included in integrated circuit dies that may be present in various components of computing device 500. For example, in some embodiments processor 504 may include an integrated circuit die that includes one or more memory devices, such as one or more STTM elements/devices described herein. Likewise, COMMS 506 may include an integrated circuit die that may include one or more STTM elements/devices consistent with the present disclosure. Moreover, various other memories of computing device 500 (e.g., DRAM, ROM, mass storage, etc.) may be made up of or include STTM elements/devices consistent with the present disclosure.

[0044] Computing device 500 may any or a wide variety of computing devices, including but not limited to a laptop computer, a netbook computer, a notebook computer, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder, combinations thereof, and the like. Of course such devices are enumerated for the sake of example only, and computing device 500 may be any suitable type of mobile or stationary electronic device.

[0045] As may be appreciated from the foregoing, the technologies described herein may enable the production STTM elements/devices, and integrated circuits including such components, wherein the electrical continuity of a re-deposited layer on the sidewalls of the STTM element/device is interrupted. In this way, the technologies described herein may enable and/or facilitate mass production of STTM

elements/devices while reducing or even eliminating electrical shorts that may result from the presence of the re-deposited layer.

[0046] ADDITIONAL EMBODIMENTS

[0047] The following examples represent additional non-limiting embodiments of the present disclosure.

[0048] Example 1: Accoriding to this example there is provided a method of forming a spin transfer torque memory (STTM) element, including: providing a workpiece including a substrate and a material stack on the substrate, the material stack to define a magnetic tunnel junction (MTJ) including a fixed magnetic layer, a dielectric layer on the fixed magnetic layer, and a free magnetic layer on the dielectric layer, wherein in the workpiece the free magnetic layer has a first width Wl, the dielectric layer has a second width, W2, and Wl < W2, such that at least a portion of an upper surface of the dielectric layer is exposed and the free magnetic layer includes at least one sidewall having a first slope, SL1 , relative to a plane of the dielectric layer; depositing a spacer material on the dielectric layer and the free magnetic layer of the workpiece, so as to form a non-conformal spacer predecessor; and forming an STTM element including a step at least in part by selectively removing at least a portion of the non-conformal spacer predecessor, at least a portion of the dielectric layer, and at least a portion of the fixed magnetic layer, wherein the step extends between a first point proximate an interface of a sidewall and a bottom surface of the free magnetic layer to a second point at an outer edge of an upper surface of the dielectric layer in the STTM element.

[0049] Example 2: This example includes any or all of the elements of example 1, wherein a remaining portion of the spacer material defines the step in the STTM element.

[0050] Example 3: This example includes any or all of the elements of 1, wherein SL1 is non-vertical, relative to the plane of the dielectric layer.

[0051] Example 4: This example includes any or all of the elements of 1, wherein: the non-conformal spacer predecessor has a first average thickness, a, in a region above the upper surface of the dielectric layer, a second average thickness, b, in a region above an upper surface of the free magnetic layer, and a third average thickness, c, on the sidewalls of the free magnetic layer; wherein a, b, and c are different.

[0052] Example 5: This example includes any or all of the elements of example 4, wherein c < a < b.

[0053] Example 6: This example includes any or all of the elements of any one of examples 1 to 5, wherein: the workpiece further includes a hard mask layer disposed on the free magnetic layer; and the spacer material is deposited such that at least a portion of the non-conformal spacer is on an upper surface of the hard mask layer.

[0054] Example 7: This example includes any or all of the elements of example 6, wherein a remaining portion of the spacer material defines the step in the STTM element.

[0055] Example 8: This example includes any or all of the elements of example 7, wherein an upper surface of the remaining portion of the spacer material is substantially coplanar with an upper surface of the hard mask layer.

[0056] Example 9: This example includes any or all of the elements of any one of examples 1 to 8, wherein a width of the step between the first and second points ranges from greater than 0 to about 15 nanometers (nm). [0057] Example 10: This example includes any or all of the elements of example 9, wherein the width of the step between the first and second points ranges from greater than 0 to about 10 nm.

[0058] Example 11: This example includes any or all of the elements of any one of examples 1 to 10, wherein the non-conformal spacer predecessor has a re-entrant cross sectional profile.

[0059] Example 12: This example includes any or all of the elements of any one of examples 1 to 10, wherein SL1 ranges from about 70 to less than 90 degrees, relative to a horizontal plane of the dielectric layer.

[0060] Example 13: This example includes any or all of the elements of example 12, wherein: a remaining portion of the spacer material defines the step, the remaining portion including at least one sidewall having a second slope, SL2, relative to the horizontal plane of the dielectric layer; and SL2 > SL1.

[0061] Example 14: This example includes any or all of the elements of example 13, wherein SL2 ranges from about 85 to 90 degrees, relative to the horizontal plane of the dielectric layer.

[0062] Example 15: This example includes any or all of the elements of example 14, wherein SL2 is 90 degrees, relative to the horizontal plane of the dielectric layer.

[0063] Example 16: This example includes any or all of the elements of any one of examples 1 to 15, wherein the STTM element exhibits an offset field, Ho_ffset that is less than about 100 oersted (Oe).

[0064] Example 17: This example includes any or all of the elements of example 16, wherein H_0ffset is less than about 50 Oe.

[0065] Example 18: This example includes any or all of the elements of example 17, wherein Hoffset is 0 Oe.

[0066] Example 19: This example includes any or all of the elements of any one of examples 1 to 18, wherein the MTJ is a perpendicular MTJ.

[0067] Example 20: According to this example there is provided an integrated circuit device, including an spin transfer torque memory (STTM) element, the STTM element including: a substrate; and a material stack on the substrate, the material stack defining a magnetic tunnel junction (MTJ) including a fixed magnetic layer, a dielectric layer on the fixed magnetic layer, and a free magnetic layer on the dielectric layer; wherein: the free magnetic layer has a first width Wl, the dielectric layer has a second width, W2, and Wl < W2; the free magnetic layer includes at least one sidewall having a first slope, SL1, relative to a plane of the dielectric layer; and the MTJ includes a step extending between a first point proximate an interface of a sidewall and a bottom surface of the free magnetic layer to a second point at an outer edge of an upper surface of the dielectric layer in the STTM element.

[0068] Example 21: This example includes any or all of the elements of example 21, wherein the step is defined at least in part by regions of the upper surface of the dielectric layer, and the integrated circuit further includes a spacer on the regions.

[0069] Example 22: This example includes any or all of the elements of example 21, wherein the spacer includes a dielectric material.

[0070] Example 23: This example includes any or all of the elements of any one of examples 21 and 22, wherein the step is at least partially defined by the spacer.

[0071] Example 24: This example includes any or all of the elements of any one of examples 21 to 24, further including a hard mask layer disposed on the free magnetic layer.

[0072] Example 25: This example includes any or all of the elements of example 24, wherein an upper surface of the spacer is substantially coplanar with an upper surface of the hard mask layer.

[0073] Example 26: This example includes any or all of the elements of any one of examples 20 to 25, wherein SL1 is non- vertical, relative to the plane of the dielectric layer.

[0074] Example 27: This example includes any or all of the elements of any one of examples 20 to 26, wherein a width of the step between the first and second points ranges from greater than 0 to about 15 nanometers (nm).

[0075] Example 28: This example includes any or all of the elements of example 27, wherein the width of the step between the first and second points ranges from greater than 0 to about 10 nm.

[0076] Example 29: This example includes any or all of the elements of any one of examples 20 to 28, wherein SL1 ranges from about 70 to less than 90 degrees, relative to a horizontal plane of the dielectric layer. [0077] Example 30: This example includes any or all of the elements of any one of examples 22 to 25, wherein the spacer includes at least one sidewall having a second slope, SL2, relative to the horizontal plane of the dielectric layer; and SL2 > SL1.

[0078] Example 31: This example includes any or all of the elements of example 30, wherein SL2 ranges from about 85 to 90 degrees, relative to the horizontal plane of the dielectric layer.

[0079] Example 32: This example includes any or all of the elements of example 31, wherein SL2 is 90 degrees, relative to the horizontal plane of the dielectric layer.

[0080] Example 33: This example includes any or all of the elements of any one of examples 20 to 32, wherein the STTM element exhibits an offset field, Ho_ffset that is less than about 100 oersted (Oe).

[0081] Example 34: This example includes any or all of the elements of 33, wherein Ho_ffset is less than about 50 Oe.

[0082] Example 35: This example includes any or all of the elements of example 34, wherein Hoffset is 0 Oe.

[0083] Example 36: This example includes any or all of the elements of any one of examples 20 to 24, wherein the MTJ is a perpendicular MTJ.

[0084] The terms and expressions which have been employed herein are used as terms of description and not of limitation, and there is no intention, in the use of such terms and expressions, of excluding any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible within the scope of the claims. Accordingly, the claims are intended to cover all such equivalents. Various features, aspects, and embodiments have been described herein. The features, aspects, and embodiments are susceptible to combination with one another as well as to variation and modification, as will be understood by those having skill in the art. The present disclosure should, therefore, be considered to encompass such combinations, variations, and modifications.

Claims

1. A method of forming a spin transfer torque memory (STTM) element, comprising:

providing an workpiece comprising a substrate and a material stack on the substrate, the material stack to define a magnetic tunnel junction (MTJ) including a fixed magnetic layer, a dielectric layer on the fixed magnetic layer, and a free magnetic layer on the dielectric layer, wherein in said workpiece the free magnetic layer has a first width Wl, the dielectric layer has a second width, W2, and Wl < W2, such that at least a portion of an upper surface of the dielectric layer is exposed and said free magnetic layer comprises at least one sidewall having a first slope, SL1, relative to a plane of said dielectric layer;

depositing a spacer material on the dielectric layer and the free magnetic layer of said workpiece, so as to form a non-conformal spacer predecessor; and

forming an STTM element including a step at least in part by selectively removing at least a portion of said non-conformal spacer predecessor, at least a portion of said dielectric layer, and at least a portion of said fixed magnetic layer, wherein the step extends between a first point proximate an interface of a sidewall and a bottom surface of said free magnetic layer to a second point at an outer edge of an upper surface of the dielectric layer in said STTM element.

2. The method of claim 1, wherein a remaining portion of the spacer material defines said step in said STTM element.

3. The method of claim 1, wherein SL1 is non- vertical, relative to the plane of said dielectric layer.

4. The method of claim 1 , wherein:

the non-conformal spacer predecessor has a first average thickness, a, in a region above the upper surface of said dielectric layer, a second average thickness, b, in a region above an upper surface of the free magnetic layer, and a third average thickness, c, on the sidewalls of the free magnetic layer;

wherein a, b, and c are different.

5. The method of claim 4, wherein c < a < b.

6. The method of any one of claims 1 to 5, wherein:

the workpiece further comprises a hard mask layer disposed on the free magnetic layer; and

the spacer material is deposited such that at least a portion of the non- conformal spacer is on an upper surface of the hard mask layer.

7. The method of claim 6, wherein a remaining portion of the spacer material defines said step in said STTM element.

8. The method of any one of claims 1 to 5, wherein a width of said step between said first and second points ranges from greater than 0 to about 15 nanometers (nm).

9. The method of any one of claims 1 to 5, wherein said non-conformal spacer predecessor has a re-entrant cross sectional profile.

10. The method of any one of claims 1 to 5, wherein SLl ranges from about 70 to less than 90 degrees, relative to a horizontal plane of said dielectric layer.

11. The method of claim 10, wherein:

a remaining portion of said spacer material defines said step, the remaining portion comprising at least one sidewall having a second slope, SL2, relative to the horizontal plane of said dielectric layer; and

SL2 > SL1.

12. The method of any one of claims 1 to 5, wherein said STTM element exhibits an offset field, Hoff_set that is less than about 100 oersted (Oe).

13. The method of any one of claims 1 to 5, wherein said MTJ is a perpendicular MTJ.

14. An integrated circuit device, comprising an spin transfer torque memory (STTM) element, the STTM element comprising: a substrate; and

a material stack on the substrate, the material stack defining a magnetic tunnel junction (MTJ) including a fixed magnetic layer, a dielectric layer on the fixed magnetic layer, and a free magnetic layer on the dielectric layer;

wherein:

the free magnetic layer has a first width Wl, the dielectric layer has a second width, W2, and Wl < W2;

said free magnetic layer comprises at least one sidewall having a first slope, SL1, relative to a plane of said dielectric layer; and

the MTJ includes a step extending between a first point proximate an interface of a sidewall and a bottom surface of said free magnetic layer to a second point at an outer edge of an upper surface of the dielectric layer in said STTM element.

15. The integrated circuit device of claim 14, wherein the step is defined at least in part by regions of the upper surface of said dielectric layer, and the integrated circuit further comprises a spacer on said regions.

16. The integrated circuit device of claim 15, wherein the step is at least partially defined by said spacer.

17. The integrated circuit device of claim 15, further comprising a hard mask layer disposed on the free magnetic layer.

18. The integrated circuit device of claim 17, wherein an upper surface of said spacer is substantially coplanar with an upper surface of said hard mask layer.

19. The integrated circuit device of any one of claims 14 to 18, wherein SL1 is non- vertical, relative to the plane of said dielectric layer.

20. The integrated circuit device of any one of claims 14 to 18, wherein a width of said step between said first and second points ranges from greater than 0 to about 15 nanometers (nm).

21. The integrated circuit device of any one of claims 14 to 18, wherein SL1 ranges from about 70 to less than 90 degrees, relative to a horizontal plane of said dielectric layer.

22. The integrated circuit device of any one of claims 14 to 18, wherein said spacer comprises at least one sidewall having a second slope, SL2, relative to the horizontal plane of said dielectric layer; and

SL2 > SL1.

23. The integrated circuit device of any one of claims 14 to 18, wherein the STTM element exhibits an offset field, Hoff_set that is less than about 100 oersted (Oe).

24. The integrated circuit device of any one of claims 14 to 18, wherein the STTM element exhibits an offset field, Hoff_set that is less than about 50 oersted (Oe).

25. The integrated circuit device of any one of claims 14 to 18, wherein said MTJ is a perpendicular MTJ.