WO2017052553A1

WO2017052553A1 - Silicon controlled rectifier with reverse breakdown trigger

Info

Publication number: WO2017052553A1
Application number: PCT/US2015/051978
Authority: WO
Inventors: Nathan Jack; Steven S. Poon
Original assignee: Intel Corporation
Priority date: 2015-09-24
Filing date: 2015-09-24
Publication date: 2017-03-30

Abstract

A silicon controlled rectifier may be used to protect an integrated circuit from excessive voltage encountered during an electrostatic discharge event. The SCR may be triggered using a trigger circuit that includes a number of reverse breakdown diodes. The reverse breakdown diodes may include a number of inherent reverse breakdown diodes provided by the PN junctions in an N-type metal oxide semiconductor (NMOS) device.

Description

SILICON CONTROLLED RECTIFIER WITH REVERSE BREAKDOWN

TRIGGER

NATHAN D. JACK

STEVEN S. POON

TECHNICAL FIELD

The present disclosure relates to electrostatic discharge protection of integrated circuits. BACKGROUND

Electrostatic discharges (ESDs) can range from tens of volts to thousands of volts. Even relatively low voltage ESD events can damage or destroy an integrated circuit. With the ubiquity of portable electronic devices such as smartphones, handheld computers, and wearable computers, ESD events have become commonplace and the system design incorporates some level of ESD handling to protect sensitive system components. Some system manufacturers now require a "fail-safe" type of input output in which integrated circuit "pins" must maintain a high impedance state even when power is removed from the integrated circuit. Many current ESD protection systems fail to satisfy the fail-safe I/O requirement in that a low impedance path exists when a power supply is unpowered.

Silicon controlled rectifiers (SCRs) have been used to provide ESD protection of failsafe I/O pins. An SCR is engineered to remain in a high-impedance state until triggered by a voltage that exceeds the normal operating voltage of the I/O pin to which the SCR is coupled. Such SCRs typically rely upon a trigger circuit to provide a path to ground for triggering a first bipolar junction transistor (BJT - e.g. , a PNP transistor) in the SCR. Once triggered, the first BJT triggers a second BJT (e.g. , an NPN transistor) in the SCR that "latches" the SCR in a conductive state and provides a low-resistance, electrically conductive, path to one or more dissipative structures (e.g. , ground) capable of safely dissipating the ESD.

Typically, a forward-biased series of diodes provides a trigger circuit for low voltage I/O (e.g. , 1.8V or less) applications. However, at higher operating voltages (e.g. , 3V to 5V), the leakage through such as forward biased diode string may be excessive. For higher voltage applications, a grounded gate N-type metal oxide semiconductor (ggNMOS) may be used as a low-leakage trigger circuit. BRIEF DESCRIPTION OF THE DRAWINGS

Features and advantages of various embodiments of the claimed subject matter will become apparent as the following Detailed Description proceeds, and upon reference to the Drawings, wherein like numerals designate like parts, and in which:

FIG. 1 A is a partial schematic of an example trigger circuit conductively coupled to a silicon controlled rectifier that provides electrostatic discharge protection for an integrated circuit pad, in accordance with at least one embodiment of the present disclosure;

FIG. IB is a partial cross-section of an example N-type metal oxide semiconductor trigger circuit disposed on a substrate and an example N-type metal oxide semiconductor trigger circuit converted to a trigger circuit that includes a plurality of reverse breakdown diodes, in accordance with at least one embodiment of the present disclosure;

FIG. 1 C is a partial schematic of an example trigger circuit that includes a number of reverse breakdown diodes conductively coupled to a silicon controlled rectifier, in accordance with at least one embodiment of the present disclosure;

FIG. 2 is a plan view of an illustrative finned field effect transistor (FINFET) layout for a trigger circuit that includes a number of reverse breakdown diodes conductively coupled to a silicon controlled rectifier such as that depicted in FIG. 1C, in accordance with at least one embodiment of the present disclosure;

FIG. 3 is a high-level flow diagram of an example silicon controlled rectifier trigger circuit that includes one or more reverse breakdown diodes, in accordance with at least one embodiment of the present disclosure;

FIG. 4 is a high-level flow diagram of an example method for providing an electrostatic discharge protection circuit using a silicon controlled rectifier and a trigger circuit such as that depicted in FIG. 3, in accordance with at least one embodiment of the present disclosure;

FIG. 5 is a high-level flow diagram of an example silicon controlled rectifier trigger circuit that includes one or more reverse breakdown diodes provided by an N-type mixed oxide semiconductor (NMOS), in accordance with at least one embodiment of the present disclosure; and

FIG. 6 is a high-level flow diagram of an example silicon controlled rectifier trigger circuit that includes one or more reverse breakdown diodes provided by an N-type mixed oxide semiconductor (NMOS), in accordance with at least one embodiment of the present disclosure.

Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications and variations thereof will be apparent to those skilled in the art.

DETAILED DESCRIPTION

Typically, a forward-biased series of diodes provides a trigger circuit for low voltage I O (e.g. , 1.8V or less) applications. However, at higher operating voltages (e.g. , 3V to 5V), the leakage through such as forward biased diode string may be excessive. For higher voltage applications, a grounded gate N-type metal oxide semiconductor (ggNMOS) may be used as a low-leakage trigger circuit. On occasion, multiple NMOS devices may be stacked to relieve the drain-gate voltage across the oxide used in fabricating the NMOS devices. A parasitic NPN BJT is formed by the source and drain diffusions within the P-well of the ggNMOS device. When the drain is sufficiently reverse-biased avalanching occurs and a substrate current is generated and flows to the nearest P+ tap. The substrate current, flowing through a substrate resistance R_SUb forward biases the base-emitter junction of the parasitic NPN BJT. When the substrate voltage drop exceeds VBE, the NPN BJT will enter a conductive state and form a low impedance current path through the substrate. Upon entering the conductive state, the ggNMOS causes the SCR to enter a conductive state and dissipate an ESD.

Conventionally, large arrays of ggNMOS fingers coupled in parallel may be used to handle the currents typically encountered during ESD events. Such arrays may rely on the synergistic effect of the substrate current by "sharing" the current among a number of ggNMOS devices - in essence, the ggNMOS fingers effectively assist in triggering each other. However, the increasing reliance on finned field effect transistors (FINFETs) may discourage such sharing of substrate current (and consequently of uniform triggering of the ggNMOS) due at least in part to the increased fin-fin isolation in FINFET devices.

A ggNMOS trigger circuit typically relies upon avalanching the reverse-biased drain to place the parasitic BJT in a conductive state. Since the parasitic BJT may not conduct uniformly in FINFET processes, it is advantageous to discourage bipolar operation of the parasitic BJT and instead rely solely upon reverse-biased junction breakdown to trigger the SCR. The failure current of a large ggNMOS array may be less than that of the reverse-biased diffusion junctions. Thus, the failure current may be improved by discouraging or even disabling bipolar operation. A reverse breakdown diode may be used in lieu of a ggNMOS device to trigger an SCR. The avalanching voltage of the reverse breakdown diode is approximately the same as the ggNMOS trigger voltage, thus the SCR will trigger at approximately the same voltage when either a reverse breakdown diode or a ggNMOS device provides the trigger circuit. However, because the parasitic NPN device in the ggNMOS is disabled, the device failure current equals that of the reverse-biased junction in the reverse breakdown diode which is generally greater than the failure current of the original ggNMOS device in FINFET technology.

By connecting all source and drain nodes (i.e. , the NMOS device source and drain nodes) to the SCR trigger node, the parasitic NPN device may be disabled. For stacked NMOS devices, connecting all source and drain nodes to the SCR trigger node effectively quadruples the reverse-biased diode (i.e., P-N junction) area. Further, the series resistance of the reverse-breakdown diode may be decreased by making the area of the P+ tap

approximately equal the area of the N+ diffusion region. Additionally, the P+ tap and the N+ diffusion region may be more closely spaced when using a reverse breakdown diode as opposed to a ggNMOS; the ggNMOS layout often requires wide P+ tap to N+ spacing to promote higher well resistance and a lower trigger current. An SCR triggered by a reverse biased diode may have considerably less leakage and a lower capacitance than an SCR triggered using a forward-biased diode string. As an added benefit, the area needed to sink the trigger current of an SCR is significantly smaller for the reverse-biased diode than for a ggNMOS.

An ESD protected I/O circuit should be sufficiently robust to permit the ESD protection to trigger prior to any damage to the I/O circuit. Output driver NMOS devices have parasitic NPN BJTs and output driver PMOS devices have parasitic PNP BJTs.

Conventionally, an I/O circuit may be sized such that they are semi- or fully self-protecting (i.e., intrinsically self-protecting) through these parasitic BJTs. Other methods may also ensure the output driver is sufficiently robust to survive an ESD event for a duration that permits the SCR protecting the output driver to trip. The use of FINFET devices likely requires an alternative to leveraging BJT conduction in the output drier.

To protect an integrated circuit I/O from damage due to overvoltage seen during ESD events, the SCR should trigger at a voltage lower than the breakdown voltage of the input/output circuits coupled to the pad. Assuming the SCR and the output driver transistors share a similar junction profile, the breakdown voltage should be similar between the two. Without precaution, the output driver drain will begin to avalanche with the SCR under similar stress conditions. The output driver may fail prematurely due to non-uniform conduction if permitted to enter bipolar conduction mode (similar to the ggNMOS). A ballast resistance may be placed between the drain and output nodes to protect the output driver. The presence of the ballast resistance causes a voltage drop which reduces the voltage on the drain and may prevent the output driver from entering the bipolar conduction mode. In such instances, the resistance is typically quite large to achieve the needed voltage drop since little current maybe drawn through the output driver in an OFF state.

While prior ESD protection regimes may have included triggering the transistor in the output driver as a means of self-protection, intrinsic robustness of the output driver may be increased by discouraging or even preventing bipolar action of the output driver. The amount of current needed to trigger bipolar operation of the output driver is dependent on the substrate or well resistance R_weii. Decreasing R_weu requires greater quantities of avalanching current before the threshold voltage is reached. From a layout perspective, such reduction in Rweii may be accomplished by placing taps close together and having junction areas equal to that of the drain.

An electrostatic discharge protection system is provided. The ESD protection system may include a silicon controlled rectifier (SCR). The SCR may include an anode that, in operation, receives a voltage from a circuit that includes an integrated circuit input/output (I/O) pad. The SCR may further include a cathode that, in operation, discharges the voltage to a low potential structure and a gate. The ESD protection system may additionally include a trigger circuit. The trigger circuit may include at least one metal-oxide semiconductor (MOS) device. The MOS device may include a source conductively coupled to the SCR gate, a drain conductively coupled to the SCR gate, and at least one well tap that, in operation, conductively couples to the low potential structure. An electrostatic discharge protection method is provided. The method may include conductively coupling a cathode of at least one reverse breakdown diode to a silicon controlled rectifier (SCR) trigger node and conductively coupling an anode of the at least one reverse breakdown diode to a low potential structure.

An electrostatic discharge protection system is provided. The system may include a means for conductively coupling a cathode of at least one reverse breakdown diode to a silicon controlled rectifier (SCR) trigger node and a means for conductively coupling an anode of the at least one reverse breakdown diode to a low potential structure.

FIG. 1 A is a partial schematic diagram of an illustrative electrostatic discharge (ESD) protection system 100, in accordance with at least one embodiment of the present disclosure. The system 100 includes an I/O pad 102 conductively coupled to a silicon controlled rectifier (SCR) 110 that provides protection for the pad 102 against damaging voltage surges such as those encountered during an ESD event. The SCR 110 may be triggered, transitioned, or changed from a high-impedance state to a low-impedance state, upon receipt of a defined voltage signal at the SCR trigger node 132. In embodiments, one or more trigger circuits 140 capable of generating such a defined voltage signal upon receipt of an input indicative of an occurrence of an ESD event may be coupled to the SCR trigger node 132.

In embodiments, the SCR 110 may include a PNP transistor 112 having a collector 114 conductively coupled to the I/O pad 102, a base 118 conductively coupled to the SCR trigger node 132 that is, in turn, coupleable to the one or more trigger circuits 140, and an emitter 116 conductively coupled to a base 126 of an NPN transistor 120. The NPN transistor 120 further includes a collector 122 conductively coupled to the base 118 of the PNP transistor 112 and a collector 124 conductively coupled to a low voltage structure or ground (V_ss) 130. The trigger circuit 140 may include any number or combination of systems or devices capable of providing a voltage to the base 118 of the PNP transistor 112 that is of sufficient duration and/or magnitude to place the PNP transistor 112 in a conductive state, causing the SCR 110 to latch-up and conduct an ESD event to the low voltage structure or ground 130.

In operation, responsive to an occurrence of an ESD event, the trigger circuit 140 supplies a voltage to the SCR trigger node 132 that is sufficient to place both the PNP transistor 112 and the NPN transistor 120 in conductive states. The SCR 110 then provides a low resistance path to ground to discharge the ESD event. Once placed in the forward- conducting state, the SCR 110 remains in the forward-conducting state regardless of the presence or absence of the trigger signal, and will only return to the forward-blocking or non- conductive state when the voltage supplied to the collector of the PNP transistor 112 is sufficiently low (e.g., a zero voltage level) that the PNP transistor 112 returns to a non- conductive state.

FIG. IB is schematic diagram depicting conversion of a conventional grounded-gate NMOS (ggNMOS) device to a reverse junction breakdown trigger circuit 140 that may be used in conjunction with the SCR 110 depicted in FIG. 1 A, in accordance with at least one embodiment of the present disclosure. A conventional trigger circuit may include a number of field effect transistors (FETs). The one or more FETs may include one or more N-type metal oxide semiconductor (NMOS) devices 142. The one or more NMOS devices 142 may include one or more grounded-gate NMOS devices (ggNMOS) 150.

A ggNMOS 150 includes an NMOS device in which the gate 152, the source 156, and the bulk or body 158 are conductively coupled to low potential or ground 130 (e.g. , V_ss). The drain 154 of the ggNMOS is conductively coupled to the I/O pad 102. An inherent parasitic NPN BJT 160 may be formed in the P-well 180 by the ggNMOS 150. In the parasitic NPN BJT 160, the ggNMOS drain 154 acts as the collector 164, the ggNMOS base/source 152/156 combination acts as the emitter 166, and the bulk substrate acts as the base 162 of the BJT 160. A parasitic resistance 168 (R_weii) exists between the emitter 166 and base 162 of the parasitic NPN BJT. The value of the parasitic resistance (Rweii) 168 is dependent on the conductivity of the P-well 180 on which the ggNMOS 150 has been deposited. The ggNMOS 150 may be modified to provide the reverse junction breakdown trigger circuit 140 depicted in FIG. 1A, in accordance with at least one embodiment of the present disclosure

A trigger circuit 140 that includes a modified ggNMOS device 150 is depicted in the image labeled "MODIFIED" in FIG. IB. As depicted in FIG. IB, the ggNMOS drain 154 and the ggNMOS source 156 may be conductively coupled to the SCR trigger node 132, thereby disabling the inherent NPN BJT 160. Conductively coupling the ggNMOS drain 154 and the ggNMOS source 156 to the SCR trigger node 132 provides a pair of reverse biased, inherent, parasitic diodes 170 between the SCR trigger node 132 and the grounded well tap 158 (i.e. , the PN junction).

Turning to FIG. 1C, the modified ggNMOS device 150 described above with regard to FIG. IB is depicted as included in the trigger circuit 140 coupled to the SCR trigger node 132. The reverse-breakdown diodes 170 may be used to trigger the SCR 110. At relatively low voltages (e.g. , in the absence of an ESD event occurrence), little current (i.e. , breakthrough current only) flows through the reverse-breakdown diodes 170. As the voltage across the reverse-breakdown diodes 170 increases (e.g., in response to an occurrence of an ESD event) and exceeds the reverse breakdown voltage (VBE) of the reverse-breakdown diodes 170, the reverse-breakdown diodes 170 may enter a conductive state in which current flow through the reverse-breakdown diodes 170 may dramatically increase. In embodiments, the avalanching voltage of the reverse-breakdown diodes 170 may be similar to the ggNMOS trigger voltage - thus, the SCR will tend to trigger at about the same voltage regardless of whether a ggNMOS 150 or a reverse-breakdown diodes 170 provides the trigger circuit 140. However, because the parasitic NPN BJT 160 has been disabled, the failure current of the trigger circuit 140 equals the current flowing through the reverse-breakdown diodes 170 which may be significantly increased over the current that formerly flowed through the ggNMOS 150.

In embodiments, the pad 102 may be coupled to one or more input circuits or devices or one or more output circuits or devices. If the transistors conductively coupled to the pad 102 share similar junction profiles with the reverse-breakdown diodes 170, the transistors coupled to the pad 102 and the reverse-breakdown diodes 170 may have a similar reverse breakdown voltage. Under such circumstances, the transistors coupled to the pad 102 may enter bipolar conduction mode, placing the transistors in the I/O circuit at risk for premature failure due to non-uniform conduction. The reverse-breakdown diodes 170 may

advantageously provide reduced leakage and capacitance over conventional forward-biased diode string trigger circuits.

FIG. 2 depicts an illustrative transistor layout 200 that may decrease the value of the substrate resistance (R_weu) and may consequently discourage bipolar triggering of the I/O circuit transistors, in accordance with at least one embodiment of the present disclosure. The voltage to trip the transistors included in a circuit communicably coupled to the pad 102 depends upon the amount of current flowing the through the substrate resistance, R_weu. Since voltage is directly proportional to current and resistance, smaller values of R_weu tend to increase the current required to trip any NPN or PNP transistors (e.g., NPN or PNP field effect transistors) included in the circuit communicably coupled to the pad 102.

Typically, a lower substrate or well resistance increases the avalanche current needed to trigger a transistor. ESD protection regimes in which bipolar operation of transistors coupled to the pad 102 frequently employed small well taps or widely spaced well taps to increase the substrate or well resistance and thereby encouraging bipolar operation of the transistors by reducing the substrate current needed to cause bipolar operation. In contrast, as depicted in FIG. 2, bipolar operation of the transistors coupled to the pad 102 may be discouraged by reducing the distance between well taps 158. Bipolar operation of the transistors coupled to the pad 102 may be further discouraged by increasing the junction area of the well tap 158 to approximately equal the area of the drain 154. The resultant reduction in substrate or well resistance attributable to the reduced distance between taps and increased junction area of the taps may reduce the substrate current. Reducing the substrate current may minimize or even eliminate the possibility of bipolar operation (and subsequent failure) of the transistors coupled to the pad 102. Beneficially, such results may be obtained without increasing the layout cost of the die since such modifications require no additional devices or metal layers.

FIG. 3 is a high-level flow diagram of an illustrative method 300 of protecting an I/O pad 102 from the dangerous voltages associated with an ESD event using at least one reverse breakdown diode 170, in accordance with one or more embodiments described herein. ESD events may generate voltages ranging from tens to thousands of volts, which easily exceed the voltage limitations of semiconductor devices found in modern integrated circuits.

In some implementations, one or more silicon controlled rectifiers (SCRs) 110 may be conductively coupled to an integrated circuit (IC) pad 102. A high voltage, such as those typically encountered during ESD events, can trigger the SCR 110, causing the SCR 110 to transition from a high- impedance state (i.e. , a forward-blocking state) to a low-impedance state (i.e. , a forward-conducting state). Once triggered the SCR 110 remains "latched- in" to the low-impedance state until the voltage supplied to the anode of the SCR 110 falls below a defined level. In the low-impedance state, the SCR 110 provides a low-impedance path for the high voltage to dissipate to a low potential structure (e.g. , a chassis ground) or to a ground (i.e. , an earth ground) 130.

A trigger circuit 140 may supply a voltage to the trigger node 132 of the SCR 110. When the voltage supplied by the trigger circuit 140 exceeds a defined value, the SCR 110 may trip from a high-impedance state (i.e. , a forward-blocking state) to a low-impedance state (i.e. , a forward-conducting state). In various embodiments, the trigger circuit 140 may include a number of components at least some of which may include one or more reverse breakdown diodes 170. A reverse breakdown diode 170 may include a diode that is subjected to a reverse bias, particularly during overvoltage events such as those encountered during an ESD event. In some implementations, when subjected to a reverse bias at a voltage typical of an ESD event (e.g. , voltages between tens and thousands of volts), the reverse breakdown diode 170 may enter a breakdown mode in which the diode enters a conductive state. The method 300 commences at 302. At 304, a cathode of a reverse breakdown diode 170 may be conductively coupled to the SCR trigger node 132 such that upon receipt of a voltage indicative of an occurrence of an ESD event, the trigger circuit 140 provides a signal at the trigger node 132 of the SCR 1 10 that transitions the SCR 1 10 from a high-impedance state to a low-impedance state.

At 306, an anode of the reverse breakdown diode 170 may be conductively coupled to a low potential structure or ground 130.

In operation, the inherent reverse breakdown diodes 170 are operated in a reverse bias condition and a small quantity of saturation current flows through the reverse biased diode to ground. Applying a high voltage (e.g. , the voltages typically seen during ESD events) to the reversed biased diode 170 causes a breakdown of the diode which allows larger quantities of current to flow from the cathode to the anode of the reverse breakdown diode(s) 170. The flow of reverse current through the reverse breakdown diode 170 may dissipate all or a portion of the received voltage to the low potential structure or ground 130. The method 300 concludes at 308.

FIG. 4 is a high-level flow diagram of an illustrative method 400 of triggering an silicon controlled rectifier (SCR) 110 using a number of reverse breakdown diodes 170 conductively coupled to the gate or trigger node 132 of the SCR 1 10, in accordance with one or more embodiments disclosed herein. In embodiments, the SCR 1 10 may be coupled between an integrated circuit pad 102 and a low potential structure or ground 130 such that during an ESD event, the SCR 1 10 triggers and latches to provide a low impedance pathway to ground for the damaging voltages generated during an ESD event. The method 400 commences at 402.

At 404, an anode of the SCR 1 10 is conductively coupled to an IC pad 102.

At 406, a cathode of the SCR 1 10 is conductively coupled to a low potential structure or ground 130. The method 400 concludes at 408.

FIG. 5 is a high-level flow diagram of an illustrative method 500 of protecting an I/O pad 102 from the dangerous voltages associated with an ESD event using at least one reverse breakdown diode, in accordance with one or more embodiments described herein. A number of grounded gate N-type metal oxide semiconductor (ggNMOS) devices 150 may be used to provide a trigger circuit 140 for a silicon controlled rectifier (SCR) 1 10. The SCR 1 10 generally presents a forward-blocking, high-impedance, pathway that can be triggered and latched-up to provide a forward-conducting, low-impedance, pathway for voltages such as those encountered during ESD events. A trigger circuit 140 may be conductively coupled to a trigger node 132 on the SCR 110 and may cause a transition of the SCR 110 from the forward-blocking, high- impedance, state to the forward-conducting, low-impedance, state responsive to receipt of a voltage indicative of an occurrence of an ESD event. In various embodiments, the trigger circuit 140 may include a number of semiconductor devices, such as a number of N-type metal oxide semiconductor (NMOS) devices masked and layered on a P-type well 180 distributed on a substrate. At times, the NMOS devices may include one or more masked and layered ggNMOS devices 150. Similar to an NMOS device, each of the ggNMOS devices 150 includes a source 156, a drain 154, a gate 152, and a well tap 158. At times, numbers of such ggNMOS devices 150 may be grouped in geometrically symmetric or geometrically asymmetric arrays such that multiple ggNMOS devices 150 trip to provide overvoltage protection during an ESD event. Within the ggNMOS 150, a first P-N junction forms between the NMOS drain 154 and the P-type well 180, a second P-N junction forms between the NMOS source 156 and the P-type well 180. In addition, within the ggNMOS device 150, a well resistance (Rweii) 168 exists between the aforementioned P-N junctions and a well tap 158. Under normal operating conditions, these P-N junctions form, provide, or create the inherent NPN B JT device 160 in the substrate. However, an increasing emphasis on finned field effect transistors (FINFETs), has revealed that such ggNMOS devices 150 may not provide a reliable, adequate, level of overvoltage protection for FINFET devices. The method 500 commences at 502.

At 504, a cathode of a first reverse breakdown diode 170 may be conductively coupled to a silicon controlled rectifier (SCR) trigger node 132. In embodiments, the P-N junction located at the interface of the N+ doped drain 154 and the P-type well 180 that forms a ggNMOS 150 may provide the first inherent reverse breakdown diode 170. In such embodiments, the N+ doped drain 154 may provide the cathode of the first inherent reverse breakdown diode 170. In such embodiments, the cathode formed by the N+ doped drain 154 may be conductively coupled to the SCR trigger node 132.

The P-N junction located at the interface of the N+ doped source 156 and the P-type well 180 that forms the ggNMOS 150 may form a second inherent reverse breakdown diode 170. In such embodiments, the N+ doped source 156 may provide the cathode of the second inherent reverse breakdown diode 170. In such embodiments, the cathode formed by the N+ doped source 156 may be conductively coupled to the SCR trigger node 132. The method 500 concludes at 508. FIG. 6 is a high-level flow diagram of an illustrative method 600 of protecting an I/O pad 102 from the dangerous voltages associated with an ESD event using at least one reverse breakdown diode, in accordance with one or more embodiments described herein. A number of grounded gate N-type metal oxide semiconductor (ggNMOS) devices may be used to provide a trigger circuit 140 for a silicon controlled rectifier (SCR) 1 10. The SCR 1 10 generally presents a high-impedance block that can be triggered and latched-up to provide a low-impedance pathway for voltages such as those encountered during ESD events. The method 600 commences at 602.

At 604, an anode of the first inherent reverse breakdown diode 170 may be conductively coupled to a low potential structure or ground 130. In embodiments, the P-N junction located at the interface of the N+ doped drain 154 and the P-type well 180 that forms a ggNMOS 150 may form the first inherent reverse breakdown diode 170. In such embodiments, the P-type well tap 158 may provide the anode of the first inherent reverse breakdown diode 170. In such embodiments, the anode formed by the P-type well tap 158 may be conductively coupled to a low potential structure or ground 130.

At 606, the P-N junction located at the interface of the N+ doped source 156 and the P-type well 180 that forms a ggNMOS 150 may form the second inherent reverse breakdown diode 170. In such embodiments, the P-type well tap 158 may provide the anode of the second inherent reverse breakdown diode 170. In such embodiments, the anode formed by the P-type well tap 158 may be conductively coupled to a low potential structure or ground 130.

In operation, the inherent reverse breakdown diodes 170 are operated in a reverse bias condition and a small quantity of saturation current flows through the reverse biased diode to ground. Applying a high voltage (e.g. , the voltages typically seen during ESD events) to the reversed biased diode causes the diode to breakdown, allowing larger quantities of current to flow from the cathode to the anode of the reverse breakdown diode(s) 170 and dissipating the received voltage to the low potential structure or ground 130. The method 600 concludes at 608.

The following examples pertain to embodiments that employ some or all of the described ESD protection apparatuses, systems, and methods described herein. The enclosed examples should not be considered exhaustive, nor should the enclosed examples be construed to exclude other combinations of the systems, methods, and apparatuses disclosed herein and which are not specifically enumerated herein. According to example 1 there is provided an electrostatic discharge (ESD) protection system. The ESD protection system may include a silicon controlled rectifier (SCR). The SCR may include an anode that, in operation, receives a voltage from a circuit that includes an integrated circuit input/output (I/O) pad, a cathode that, in operation, discharges the voltage to a low potential structure, and a gate. The ESD protection system may also include a trigger circuit that may include at least one metal-oxide semiconductor (MOS) device. The MOS device may include a source conductively coupled to the SCR gate, a drain

conductively coupled to the SCR gate, and at least one well tap that, in operation, conductively couples to the low potential structure.

Example 2 may include elements of example 1 where a diffusion region for the trigger circuit drain and the at least one well tap occupy about the same area of a substrate that includes the trigger circuit.

Example 3 may include elements of any of examples 1 or 2 where the at least one MOS device comprises an N-type metal oxide semiconductor (NMOS) device.

Example 4 may include elements of example 3 where the NMOS device comprises a grounded-gate NMOS (ggNMOS).

Example 5 may include elements of example 4 where the NMOS comprises a plurality of stacked NMOS devices.

According to example 6, there is provided an electrostatic discharge (ESD) protection method. The ESD protection method may include conductively coupling a cathode of at least one reverse breakdown diode to a silicon controlled rectifier (SCR) trigger node and conductively coupling an anode of the at least one reverse breakdown diode to a low potential structure.

Example 7 may include elements of example 6 where conductively coupling a cathode of at least one reverse breakdown diode to a silicon controlled rectifier (SCR) trigger node may include conductively coupling the SCR trigger node to a source of a metal oxide semiconductor (MOS) and conductively coupling the SCR trigger node to a drain of the MOS.

Example 8 may include elements of example 7 where conductively coupling an anode of the at least one reverse breakdown diode to a low potential structure or ground may include conductively coupling a well tap of the MOS to a low potential structure or ground.

Example 9 may include elements of example 8 where conductively coupling the SCR trigger node to a source of a MOS may include conductively coupling the SCR gate to a source of a grounded-gate N-type, metal oxide semiconductor (ggNMOS). Conductively coupling the SCR trigger node to a drain of the MOS may include conductively coupling the SCR gate to a drain of the ggNMOS. Conductively coupling a well tap of the MOS to a low potential structure or ground comprises conductively coupling a well tap of the ggNMOS to a low potential structure or ground.

Example 10 may include elements of any of examples 6 through 9 and may additionally include conductively coupling an anode of the SCR to an integrated circuit input/output pad and conductively coupling a cathode of the SCR to the low potential structure.

Example 11 may include elements of example 6 where conductively coupling a cathode of at least one reverse breakdown diode to a silicon controlled rectifier (SCR) trigger node may include conductively coupling a cathode of each reverse breakdown diode included in at least one reverse breakdown diode pair to the SCR trigger node, wherein, for each of the at least one reverse breakdown diode pairs. Conductively coupling a cathode of at least one reverse breakdown diode to a silicon controlled rectifier (SCR) trigger node may also include conductively coupling a drain of an N-type metal oxide semiconductor (NMOS) device contained on a substrate to the SCR trigger node to form a first reverse breakdown diode in the substrate. Conductively coupling a cathode of at least one reverse breakdown diode to a silicon controlled rectifier (SCR) trigger node may also include conductively coupling a source of the NMOS device contained on the substrate to the SCR trigger node to form a second reverse breakdown diode in the substrate.

Example 12 may include elements of example 11 where conductively coupling an anode of the at least one reverse breakdown diode to a low potential structure may include conductively coupling an anode of each reverse breakdown diode included in at least one reverse breakdown diode pair to the low potential structure wherein, for each of the at least one reverse breakdown diode pairs. Conductively coupling an anode of the at least one reverse breakdown diode to a low potential structure may also include conductively coupling a well tap for the NMOS device to a low potential structure to form the first reverse breakdown diode in the substrate. Conductively coupling an anode of the at least one reverse breakdown diode to a low potential structure may additionally include conductively coupling the well tap for the NMOS device to the low potential structure to form the second reverse breakdown diode in the substrate.

Example 13 may include elements of any of examples 11 or 12 and may additionally include equalizing a substrate area occupied by the well tap of the NMOS device with a substrate area occupied by the drain of the respective NMOS. According to example 14, there is provided an electrostatic discharge (ESD) protection system. The ESD protection system may include a means for conductively coupling a cathode of at least one reverse breakdown diode to a silicon controlled rectifier (SCR) trigger node and a means for conductively coupling an anode of the at least one reverse breakdown diode to a low potential structure.

Example 15 may include elements of example 14 where means for conductively coupling a cathode of at least one reverse breakdown diode to a silicon controlled rectifier (SCR) trigger node may include a means for conductively coupling the SCR trigger node to a source of a metal oxide semiconductor (MOS) and a means for conductively coupling the SCR trigger node to a drain of the MOS.

Example 16 may include elements of example 15 where the means for conductively coupling an anode of the at least one reverse breakdown diode to a low potential structure or ground may include a means for conductively coupling a well tap of the MOS to a low potential structure or ground.

Example 17 may include elements of example 16 where the means for conductively coupling the SCR trigger node to a source of a MOS comprises a means for conductively coupling the SCR gate to a source of a grounded-gate N-type, metal oxide semiconductor (ggNMOS). The means for conductively coupling the SCR trigger node to a drain of the MOS may include a means for conductively coupling the SCR gate to a drain of the ggNMOS. The means for conductively coupling a well tap of the MOS to a low potential structure or ground may include a means for conductively coupling a well tap of the ggNMOS to a low potential structure or ground.

Example 18 may include elements of any of examples 14 through 17 and may additionally include a means for conductively coupling an anode of the SCR to an integrated circuit input/output pad and a means for conductively coupling a cathode of the SCR to the low potential structure.

Example 19 may include elements of example 14 where the means for conductively coupling a cathode of at least one reverse breakdown diode to a silicon controlled rectifier (SCR) trigger node may include a means for conductively coupling a cathode of each reverse breakdown diode included in at least one reverse breakdown diode pair to the SCR trigger node, wherein, for each of the at least one reverse breakdown diode pairs. The means for conductively coupling a cathode of at least one reverse breakdown diode to a silicon controlled rectifier (SCR) trigger node may include a means conductively coupling a drain of an N-type metal oxide semiconductor (NMOS) device contained on a substrate to the SCR trigger node to form a first reverse breakdown diode in the substrate. The means for conductively coupling a cathode of at least one reverse breakdown diode to a silicon controlled rectifier (SCR) trigger node may include a means for conductively coupling a source of the NMOS device contained on the substrate to the SCR trigger node to form a second reverse breakdown diode in the substrate.

Example 20 may include elements of example 19 where the means for conductively coupling an anode of the at least one reverse breakdown diode to a low potential structure may include a means for conductively coupling an anode of each reverse breakdown diode included in at least one reverse breakdown diode pair to the low potential structure, wherein, for each of the at least one reverse breakdown diode pairs. The means for conductively coupling an anode of the at least one reverse breakdown diode to a low potential structure may also include a means for conductively coupling a well tap of the NMOS device to a low potential structure to form the first reverse breakdown diode in the substrate. The means for conductively coupling an anode of the at least one reverse breakdown diode to a low potential structure may additionally include a means for conductively coupling the well tap for the NMOS device to the low potential structure to form the second reverse breakdown diode in the substrate.

Example 21 may include elements of any of claims 19 or 20 and may additionally include

a means for equalizing a substrate area occupied by the well tap of the NMOS device with a substrate area occupied by the drain of the respective NMOS.

According to example 22, there is provided a system for triggering a silicon controlled rectifier responsive to an occurrence of an ESD event, the system being arranged to perform the method of any of examples 6 through 13.

According to example 23, there is provided a device for triggering a silicon controlled rectifier responsive to an occurrence of an ESD event, the device being arranged to perform the method of any of examples 6 through 13.

The terms and expressions which have been employed herein are used as terms of description and not of limitation, and there is no intention, in the use of such terms and expressions, of excluding any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible within the scope of the claims. Accordingly, the claims are intended to cover all such equivalents.

Claims

WHAT IS CLAIMED:

1. An electrostatic discharge protection system, comprising:

a silicon controlled rectifier (SCR) that includes:

an anode that, in operation, receives a voltage from a circuit that includes an integrated circuit input/output (I/O) pad;

a cathode that, in operation, discharges the voltage to a low potential structure; and

a gate; and

a trigger circuit that includes:

at least one metal-oxide semiconductor (MOS) device having:

a source conductively coupled to the SCR gate;

a drain conductively coupled to the SCR gate; and at least one well tap that, in operation, conductively couples to the low potential structure.

2. The electrostatic discharge protection system of claim 1 wherein a diffusion region for the trigger circuit drain and the at least one well tap occupy about the same area of a substrate that includes the trigger circuit.

3. The electrostatic discharge protection system of any of claims 1 or 2 wherein the at least one MOS device comprises an N-type metal oxide semiconductor (NMOS) device.

4. The electrostatic discharge protection system of claim 3 wherein the NMOS device comprises a grounded-gate NMOS (ggNMOS).

5. The electrostatic discharge protection system of claim 4 wherein the NMOS comprises a plurality of stacked NMOS devices.

6. An electrostatic discharge protection method, comprising:

conductively coupling a cathode of at least one reverse breakdown diode to a silicon controlled rectifier (SCR) trigger node; and conductively coupling an anode of the at least one reverse breakdown diode to a low potential structure.

7. The electrostatic discharge protection method of claim 6 wherein conductively coupling a cathode of at least one reverse breakdown diode to a silicon controlled rectifier

(SCR) trigger node comprises:

conductively coupling the SCR trigger node to a source of a metal oxide

semiconductor (MOS); and

conductively coupling the SCR trigger node to a drain of the MOS.

8. The electrostatic discharge protection method of claim 7 wherein conductively coupling an anode of the at least one reverse breakdown diode to a low potential structure or ground comprises:

conductively coupling a well tap of the MOS to a low potential structure or ground.

9. The electrostatic discharge protection method of claim 8:

wherein conductively coupling the SCR trigger node to a source of a MOS comprises conductively coupling the SCR gate to a source of a grounded-gate N-type, metal oxide semiconductor (ggNMOS);

wherein conductively coupling the SCR trigger node to a drain of the MOS comprises conductively coupling the SCR gate to a drain of the ggNMOS; and

wherein conductively coupling a well tap of the MOS to a low potential structure or ground comprises conductively coupling a well tap of the ggNMOS to a low potential structure or ground.

10. The electrostatic discharge protection method of any of claims 6 through 9, further comprising:

conductively coupling an anode of the SCR to an integrated circuit input/output pad; and

conductively coupling a cathode of the SCR to the low potential structure.

11. The electrostatic discharge protection method of claim 6 wherein conductively coupling a cathode of at least one reverse breakdown diode to a silicon controlled rectifier (SCR) trigger node comprises: conductively coupling a cathode of each reverse breakdown diode included in at least one reverse breakdown diode pair to the SCR trigger node, wherein, for each of the at least one reverse breakdown diode pairs:

conductively coupling a drain of an N-type metal oxide semiconductor (NMOS) device contained on a substrate to the SCR trigger node to form a first reverse breakdown diode in the substrate; and

conductively coupling a source of the NMOS device contained on the substrate to the SCR trigger node to form a second reverse breakdown diode in the substrate.

12. The electrostatic discharge protection method of claim 11 wherein

conductively coupling an anode of the at least one reverse breakdown diode to a low potential structure comprises:

conductively coupling an anode of each reverse breakdown diode included in at least one reverse breakdown diode pair to the low potential structure wherein, for each of the at least one reverse breakdown diode pairs:

conductively coupling a well tap for the NMOS device to a low potential structure to form the first reverse breakdown diode in the substrate; and

conductively coupling the well tap for the NMOS device to the low potential structure to form the second reverse breakdown diode in the substrate.

13. The electrostatic discharge protection method of any of claims 11 or 12, further comprising:

equalizing a substrate area occupied by the well tap of the NMOS device with a substrate area occupied by the drain of the respective NMOS.

14. An electrostatic discharge protection system, comprising:

a means for conductively coupling a cathode of at least one reverse breakdown diode to a silicon controlled rectifier (SCR) trigger node; and

a means for conductively coupling an anode of the at least one reverse breakdown diode to a low potential structure.

15. The electrostatic discharge protection system of claim 14 wherein the means for conductively coupling a cathode of at least one reverse breakdown diode to a silicon controlled rectifier (SCR) trigger node comprises: a means for conductively coupling the SCR trigger node to a source of a metal oxide semiconductor (MOS); and

a means for conductively coupling the SCR trigger node to a drain of the MOS.

16. The electrostatic discharge protection system of claim 15 wherein the means for conductively coupling an anode of the at least one reverse breakdown diode to a low potential structure or ground comprises:

a means for conductively coupling a well tap of the MOS to a low potential structure or ground.

17. The electrostatic discharge protection system of claim 16:

wherein the means for conductively coupling the SCR trigger node to a source of a MOS comprises a means for conductively coupling the SCR gate to a source of a grounded- gate N-type, metal oxide semiconductor (ggNMOS);

wherein the means for conductively coupling the SCR trigger node to a drain of the

MOS comprises a means for conductively coupling the SCR gate to a drain of the ggNMOS; and

wherein the means for conductively coupling a well tap of the MOS to a low potential structure or ground comprises a means for conductively coupling a well tap of the ggNMOS to a low potential structure or ground.

18. The electrostatic discharge protection system of any of claims 14 through 17, further comprising:

a means for conductively coupling an anode of the SCR to an integrated circuit input/output pad; and

a means for conductively coupling a cathode of the SCR to the low potential structure.

19. The electrostatic discharge protection system of claim 14 wherein the means for conductively coupling a cathode of at least one reverse breakdown diode to a silicon controlled rectifier (SCR) trigger node comprises:

a means for conductively coupling a cathode of each reverse breakdown diode included in at least one reverse breakdown diode pair to the SCR trigger node, wherein, for each of the at least one reverse breakdown diode pairs: a means conductively coupling a drain of an N-type metal oxide

semiconductor (NMOS) device contained on a substrate to the SCR trigger node to form a first reverse breakdown diode in the substrate; and

a means for conductively coupling a source of the NMOS device contained on the substrate to the SCR trigger node to form a second reverse breakdown diode in the substrate.

20. The electrostatic discharge protection system of claim 19 wherein the means for conductively coupling an anode of the at least one reverse breakdown diode to a low potential structure comprises:

a means for conductively coupling an anode of each reverse breakdown diode included in at least one reverse breakdown diode pair to the low potential structure, wherein, for each of the at least one reverse breakdown diode pairs:

a means for conductively coupling a well tap of the NMOS device to a low potential structure to form the first reverse breakdown diode in the substrate; and

a means for conductively coupling the well tap for the NMOS device to the low potential structure to form the second reverse breakdown diode in the substrate.

21. The electrostatic discharge protection system of any of claims 19 or 20, further comprising:

22. A system for triggering a silicon controlled rectifier responsive to an occurrence of an ESD event, the system being arranged to perform the method of any of claims 6 through 13.

23. A device for triggering a silicon controlled rectifier responsive to an occurrence of an ESD event, the device being arranged to perform the method of any of claims 6 through 13.