WO2017047329A1

WO2017047329A1 - Ultrasonic probe and ultrasonic diagnosing device

Info

Publication number: WO2017047329A1
Application number: PCT/JP2016/074372
Authority: WO
Inventors: 梶山　新也; 樹生中川
Original assignee: 株式会社日立製作所
Priority date: 2015-09-15
Filing date: 2016-08-22
Publication date: 2017-03-23
Also published as: JPWO2017047329A1; JP6423543B2

Abstract

Provided is a small area delay phasing circuit. An ultrasonic probe comprises a plurality of circuit units, an adder circuit to add the output from the plurality of circuit units, and an input terminal to input shared signals to the plurality of circuit units. With this ultrasonic probe, each circuit unit comprises a receiving circuit and transmitting circuit that are connected to an ultrasonic transducer, and a first delay circuit. When a signal is received in the ultrasonic transducer, the receiving circuit receives a signal from the ultrasonic transducer, the first delay circuit delays the signal from the receiving circuit, the signal delayed by the first delay circuit is added by the adder circuit, and the signal added by the adder circuit is delayed by a second delay circuit. When a signal is transmitted in the ultrasonic transducer, a signal from the input terminal is delayed by the second delay circuit, the signal delayed by the second delay circuit is split and input to the plurality of circuit units, the signal delayed by the second delay circuit is delayed by the first delay circuit in each of the plurality of circuit units, and the signals delayed by the first delay circuit are input to the transmitting circuit.

Description

Ultrasonic probe and ultrasonic diagnostic apparatus

The present invention is mounted on an ultrasonic probe that is a component of an ultrasonic diagnostic apparatus, and transmits signals to array transducers arranged repeatedly one-dimensionally or two-dimensionally. The present invention relates to a technique for delaying a received signal.

The ultrasonic diagnostic apparatus is a highly safe medical diagnostic apparatus that is non-invasive to the human body and has a smaller apparatus scale than other medical image diagnostic apparatuses such as an X-ray diagnostic apparatus and an MRI (Magnetic Resonance Imaging) apparatus. In addition, since it is a device that can display in real time the state of movement of the test object, such as the pulsation of the heart or the movement of the fetus, by simply operating the ultrasound probe from the body surface, Plays an important role.

In the ultrasonic diagnostic apparatus, an ultrasonic wave is transmitted into a subject by supplying a high-voltage drive signal to each of a plurality of transducers built in the ultrasonic probe. A reflected ultrasonic wave generated by the difference in acoustic impedance of the living tissue in the subject is received by each of the plurality of vibration elements, and an image is generated based on the reflected wave received by the ultrasonic probe.

The transmitter circuit that supplies high-voltage drive signals to each transducer built in the ultrasound probe is composed of high-voltage devices so that it can generate high-voltage signals of tens to hundreds of Vpeak to peak. Is done. Usually, a high-voltage MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) uses a device with a structure that relaxes the electric field strength between the drain and the gate, such as LDMOS (Laterally Diffused MOS), and ensures a drift region between the drain and gate. Requires a very large area. For this reason, when a transmission circuit is realized as an integrated circuit (IC: Integrated Circuit) on silicon, a large area is required.

Furthermore, it is necessary to delay the transmission signal and the reception signal for each transducer and perform the focusing operation during transmission and reception. For this purpose, a delay circuit is required in the transmission / reception circuit connected to each vibrator. Since an analog delay circuit is usually realized using a capacitor, there is a problem that the circuit area increases. In particular, in order to increase the maximum delay amount determined by the focus and beam scanning angle, it is necessary to increase the number of capacitors, and the circuit area of the analog delay circuit is determined by the maximum delay amount determined by system requirements. Even when a digital signal is delayed, a shift register and a FIFO (First-In First-Out) memory are required, and a large number of flip-flops are required, which requires a large area.

Recently, an ultrasonic diagnostic apparatus capable of obtaining a three-dimensional stereoscopic image has been developed, and inspection efficiency can be improved by obtaining a tomographic image by specifying an arbitrary cross section from the three-dimensional stereoscopic image. For three-dimensional imaging, it is necessary to change the transducers in the ultrasonic probe from a conventional one-dimensional array to a two-dimensional array, that is, a 2D array, and the number of transducers is a conventional ultrasonic probe. Increases by the square of. In this case, since it is impossible to increase the number of cables connecting the ultrasonic probe and the main unit by the square, the received signal with the number reduced by phasing addition in the ultrasonic probe is reduced. It must be transferred to the main unit via a cable. In order to realize such phasing addition in the ultrasonic probe, the function of transmission / reception and phasing addition is realized as a beamformer IC, and a transmission / reception circuit is arranged for each transducer in the IC. It is necessary to be electrically connected to the vibrator on a one-to-one basis.

In this case, the transducers and the transmission / reception circuits connected to the transducers need to be arranged at the same pitch in an array, and the transducers and ICs are stacked and mounted on the tip of the ultrasonic probe. The pitch of the transducers arranged in the array is usually determined by the restriction that the influence of the grating lobe does not occur within the scanning angle of the transmission beam. That is, the diffraction of the ultrasonic wave produces an unwanted beam in a direction different from the desired main lobe, but this angle is determined by the ultrasonic frequency and the transducer pitch. When the angle is determined, the upper limit of the transducer pitch for preventing the grating lobe from appearing within the scanning angle is determined. Therefore, it is necessary to accommodate the transmission / reception circuit area per transducer at the same pitch as the target transducer pitch.

It is an important issue in circuit design to fit a transmission circuit using the high voltage device, an analog delay circuit using a large number of capacitors, or a digital delay circuit using a large number of flip-flops into a target circuit area.

As this solution, a method of dividing the delay circuit into two or more stages and performing hierarchical phasing within the IC can be considered. In other words, the delay circuit is divided into two or more stages, and during reception, delay addition within the array is performed with a group of multiple transducers, and this output is extracted to the outside of the array together with the output of the group of other multiple transducers. This is a phasing method in which delay addition is performed. As a result, when the desired maximum delay is T, for example, the maximum delay of the first delay circuit in the array is T / 2, and the maximum delay of the delay circuit outside the array is T / 2. The area of the delay circuit in the array is ½. Although this method requires a delay circuit outside the array, the area of the in-array transmission / reception circuit can be reduced.

As an example of such hierarchical phasing, Non-Patent Document 1 proposes a 2D array IC shown in FIG. Note that FIG. 13 is shown in FIG. This is a comparative example in which 5 is redrawn from the viewpoint of the inventor.

The comparative example shown in FIG. 13 relates to a receiving IC for a CMUT (Capacitive Micro-machined Ultrasonic Transducers) 2D array using hybrid phasing combining analog phasing and digital phasing.

In the example of FIG. 13, a configuration is shown in which the vibration from the Focal point is received and processed by the CMUT vibrator 130. As the first-stage phasing, the analog delay circuit 131 delays the received analog signal from the CMUT vibrator 130 and adds it by the analog adder 132. Thereafter, the first-stage phasing output is converted into a digital signal by an analog / digital converter ADC (Analog to Digital Converter) 133, delayed by the FIFO 134 memory, and added by the digital adder 135.

With this configuration, the delay is performed in two stages of an analog delay circuit and a FIFO which is a digital delay circuit, and the maximum delay amount of the analog delay circuit is obtained by giving a part of the delay to the FIFO while maintaining a desired maximum delay amount. Can be relaxed. That is, the area of the analog delay circuit can be reduced.

However, for the purpose of transmitting and receiving ultrasonic waves, a delay operation is required not only for reception but also for transmission. Since the configuration of FIG. 13 is only a receiving circuit, a transmission operation cannot be realized.

If a transmission circuit is added to the configuration of FIG. 13, a beam forming circuit for transmission is required separately from reception. Even if it is considered that the delay circuit is shared between transmission and reception as much as possible, in the case of transmission, it is not shown in addition to the ADC, considering that the signal flow is in the direction from right to left in FIG. A DAC (Digital to Analog Converter) is required. That is, it is necessary to add a DAC only for the transmission operation, and there is a problem that the entire circuit area increases.

From such a point, it is necessary to perform hierarchical phasing so as to reduce the increase in circuit area while sharing the delay circuit for transmission and reception while supporting both transmission and reception operations. Such a problem is particularly important in an ultrasonic probe that requires the transmission / reception circuits per transducer to be accommodated at the same pitch as the target transducer pitch.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

One aspect of the present invention for solving the above problems includes a plurality of circuit units, an addition circuit that adds outputs from the plurality of circuit units, and an input terminal that inputs a common signal to the plurality of circuit units. It is an ultrasonic probe. In this ultrasonic probe, each circuit unit includes a reception circuit and a transmission circuit connected to the ultrasonic transducer, and a first delay circuit. When the signal is received by the ultrasonic transducer, the signal received from the ultrasonic transducer is received by the receiving circuit, the signal from the receiving circuit is delayed by the first delay circuit, and the signal delayed by the first delay circuit. Are added by the adder circuit, and the signal added by the adder circuit is delayed by the second delay circuit. At the time of signal transmission by the ultrasonic transducer, the signal from the input terminal is delayed by the second delay circuit, and the signal delayed by the second delay circuit is branched and input to a plurality of circuit units. The signal delayed by the delay circuit is delayed by the first delay circuit in each of a plurality of circuit units, and the signal delayed by the first delay circuit is input to the transmission circuit.

As a specific circuit arrangement suitable for application to the present invention, a plurality of circuit units are arranged in a grid pattern to form an array region, and the second delay circuit is arranged outside the array region. The second delay circuit can also be configured in an array.

Another aspect of the present invention provides a plurality of first delay circuits connected to a plurality of ultrasonic transducers on a one-to-one basis, an adder circuit that adds outputs of the plurality of first delay circuits, and an adder circuit And a second delay circuit connected to the first delay circuit, the received delay signal from the ultrasonic transducer is delayed by the first delay circuit and the second delay circuit, and the transmission signal to the ultrasonic transducer is The ultrasonic probe is delayed by one delay circuit and a second delay circuit.

Another aspect of the present invention is an ultrasonic diagnostic apparatus including an ultrasonic probe and an apparatus main body. Here, the ultrasonic probe includes a plurality of circuit units, a first addition circuit that adds outputs from the plurality of circuit units, and an input terminal that inputs a common signal to the plurality of circuit units. . Each circuit unit includes a reception circuit and a transmission circuit connected to the ultrasonic transducer, and a first delay circuit. When the signal is received by the ultrasonic transducer, the signal received from the ultrasonic transducer is received by the receiving circuit, the signal from the receiving circuit is delayed by the first delay circuit, and the signal delayed by the first delay circuit. Are added by the first adder circuit, and the signal added by the first adder circuit is delayed by the second delay circuit. At the time of signal transmission by the ultrasonic transducer, the signal from the input terminal is delayed by the second delay circuit, and the signal delayed by the second delay circuit is branched and input to a plurality of circuit units. In each circuit unit, the signal delayed by the second delay circuit is delayed by the first delay circuit, and the signal delayed by the first delay circuit is input to the transmission circuit. In addition, when receiving a signal at the ultrasonic transducer, the apparatus main body uses the signal delayed by the second delay circuit as a detection signal, forms an imaging signal based on the detection signal, and generates a signal at the ultrasonic transducer. During transmission, a transmission signal is supplied to the input terminal.

To illustrate a more specific configuration of the present invention, a plurality of circuit units are arranged in a lattice pattern to form an array region, and the second delay circuit is arranged outside the array region. The first delay circuit and the second delay circuit are analog delay circuits, and each of the analog delay circuits includes a plurality of capacitors that hold an input signal, and a plurality of writes that control write timing of the plurality of capacitors. The delay time is controlled by a signal and a plurality of readout signals for controlling the output timings of the plurality of capacitors. More specifically, the write signal and read supply lines for the first delay circuit in the circuit unit are arranged in a grid pattern, and the write signal and the read signal for controlling the timing of the first delay circuit are Are controlled independently of the write signal and read signal that control the timing of the delay circuit.

The outline of other aspects of the present application will be briefly described as follows.

In an IC in which transmission / reception circuits connected to ultrasonic transducers in a one-to-one manner are arranged in an array, analog delay circuits are connected in multiple stages, the first-stage delay circuits are arranged in the transmission / reception circuits in the array, and the others These delay circuits are arranged outside the array to reduce the area of the transmission / reception circuit per transducer. Furthermore, the delay circuit is shared between the transmission operation and the reception operation, and beam forming and phasing operations are realized with a minimum circuit configuration and circuit area that do not require an analog / digital converter and a digital / analog converter.

Furthermore, by passing either an analog signal or a digital signal through the analog delay circuit, a transmission delay operation can be realized regardless of whether the transmission circuit is a linear amplifier or a pulser.

Hierarchical phasing that reduces the increase in circuit area while sharing the delay circuit for transmission and reception is possible while supporting both transmission and reception operations. Problems, configurations, and effects other than those described above will be clarified by the following description of embodiments.

It is the block diagram which showed the principle of the reception operation | movement in this invention. It is the block diagram which showed the principle of the transmission operation | movement in this invention. It is the block diagram which showed the structure of the Example for implementing this invention. FIG. 4 is a block diagram showing an extracted circuit that operates only during the reception operation of the configuration of FIG. 3 for explaining the reception operation of the embodiment of FIG. 3; FIG. 4 is a block diagram showing an extracted circuit that operates only during the transmission operation of the configuration of FIG. 3 for explaining the transmission operation of the embodiment of FIG. 3; It is the circuit diagram which showed the implementation example of the analog delay circuit by an analog ring memory structure. FIG. 7 is a timing chart illustrating the operation of the analog delay circuit in FIG. 6. It is the top view which showed the example of the layout which has physically arrange | positioned the Example circuit for implementing this invention shown in FIG. FIG. 9 is a plan view in which an analog delay circuit write / read control circuit and control signal wiring are added to the layout of FIG. 8; 1 is a diagram showing an ultrasonic probe having a two-dimensional array transducer for three-dimensional imaging and a system configuration to which the present invention is applied as a system embodiment 1. FIG. It is a block diagram at the time of employ | adopting a linear amplifier for a transmission circuit. FIG. 5 is a diagram showing an ultrasonic probe having a two-dimensional array transducer for three-dimensional imaging and a system configuration as a second embodiment of the system to which the present invention is applied. It is a block diagram at the time of employ | adopting a pulsar in a transmission circuit. It is the figure which showed the structure of the transmission / reception circuit connected to 1 vibrator | oscillator. FIG. It is a block diagram of the comparative example which redrawn 5 from the viewpoint of the inventor.

Embodiments will be described in detail with reference to the drawings. However, the present invention is not construed as being limited to the description of the embodiments below. Those skilled in the art will readily understand that the specific configuration can be changed without departing from the spirit or the spirit of the present invention.

In the structure of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and redundant description may be omitted.

In this specification and the like, notations such as “first”, “second”, and “third” are attached to identify the constituent elements, and do not necessarily limit the number or order. In addition, a number for identifying a component is used for each context, and a number used in one context does not necessarily indicate the same configuration in another context. Further, it does not preclude that a component identified by a certain number also functions as a component identified by another number.

The position, size, shape, range, etc. of each component shown in the drawings and the like may not represent the actual position, size, shape, range, etc. in order to facilitate understanding of the invention. For this reason, the present invention is not necessarily limited to the position, size, shape, range, and the like disclosed in the drawings and the like.

In this specification, a component expressed in the singular shall include the plural unless specifically indicated otherwise.

In the following, delay circuits are connected in multiple stages, and the delay circuit is shared for transmission and reception operations. At the time of reception, phasing is performed inside the array and then phasing outside the array, and two or more hierarchical phasing is performed. An embodiment will be described in which transmission signals to a plurality of transducers are collectively delayed outside the array, and then beam forming is further delayed for each transducer within the array.

FIG. 1 shows the principle of the receiving operation in the present invention. In the figure, 10 is not particularly limited, but is an ultrasonic vibrator realized by PUT (lead zirconate titanate) or CMUT made of silicon material, which converts electrical signals into sound during transmission, and in receiving operation. For example, a transducer that converts sound from a Focal point into an electrical signal.

The reception signal converted into an electric signal in the vibrator 10 is delayed through the analog delay circuit (DLY0) 11, and the phases of the reception signals from the plurality of vibrators are aligned and added by the adder circuit 12. This is further delayed by the analog delay circuit (DLY1) 13 at the second stage to align the phases and added by the adder circuit 14.

In such two-stage phasing, the maximum delay is the sum of the maximum delay amount of DLY0 and the maximum delay amount of DLY1. Therefore, if only DLY0 is arranged in the array and DLY1 is arranged outside the array, the area of the analog delay circuit in the array can be reduced while maintaining the maximum delay amount necessary for the system. Further, the delay amount for each transducer 10 can be set by changing the delay amount of DLY0.

FIG. 2 shows the principle of the transmission operation in the present invention. Contrary to the reception operation of FIG. 1, the signal flow is from right to left in the figure. The transmission signal input to the IC is delayed by the analog delay circuit (DLY1) 13. Furthermore, an independent delay is given to each vibrator 10 by the analog delay circuit (DLY0) 11 as the delay of the second stage. The maximum delay difference between the transducers 10 is the sum of the maximum delay amount of DLY0 and the maximum delay amount of DLY1. The sound from each transducer 10 can be concentrated at, for example, Focal point by controlling the delay amount.

FIG. 3 shows the configuration of an embodiment for carrying out the present invention. The configuration for sharing the analog delay circuits DLY0 and DLY1 in the reception operation of FIG. 1 also for the transmission operation of FIG. 2 is shown in FIG. Here, an ultrasonic probe used in an ultrasonic diagnostic apparatus will be described as an example.

31 is a transmission circuit, and specifically, a linear amplifier that linearly amplifies an input transmission waveform or a pulser that outputs three values of a positive voltage, a negative voltage, and a GND voltage from a digital signal input is assumed. Reference numeral 32 denotes a receiving circuit, specifically, a low noise amplifier LNA (Low Noise Amplifier). The transmission circuit 31 drives the vibrator 10 during transmission and irradiates the subject with ultrasonic waves. The receiving circuit 32 receives a signal from the vibrator 10 at the time of reception.

In order to share the analog delay circuit (DLY0) 11 for transmission and reception, a multiplexer 33 is arranged so that the signal path can be switched between transmission and reception. Reference numeral 12 denotes an adder circuit that operates during reception. Reference numeral 36 denotes a signal path switching multiplexer for sharing the second-stage analog delay circuit (DLY1) 13 for transmission and reception. Reference numeral 14 denotes an adder circuit for second-stage phasing that operates during reception. In addition, although it is set as 2 steps | paragraphs of delay addition phasing as an Example, it is not limited to this. Although three or more stages of phasing are possible, since the control becomes complicated, two stages of phasing in the IC are practical in practice.

The reception output RxOUT transmits a reception signal from the ultrasonic probe to an ultrasonic diagnostic apparatus main body (not shown). The transmission input TxIN transmits a transmission signal from the ultrasonic diagnostic apparatus main body to the ultrasonic probe.

FIG. 4 is a diagram showing a configuration in which a circuit that operates only during the reception operation of the configuration of FIG. 3 is extracted for explaining the operation of the embodiment of FIG. An electric signal from the vibrator 10 is amplified by the receiving circuit 32. The multiplexer 33 selects the reception path, and the reception signal is delayed by the analog delay circuit (DLY0) 11. The delayed received signals having the same phase are added by the adder circuit 12 and then delayed by the second-stage analog delay circuit (DLY1) 13 through the multiplexer 36 that has selected the receiving path, so that the phases are adjusted. The signals are added by the adder circuit 14 and output as a reception output from RxOUT to the main body side of the ultrasonic diagnostic apparatus.

FIG. 5 shows the configuration extracted from the circuit that operates only during the transmission operation of the configuration of FIG. 3, as in FIG. The analog transmission signal input from the transmission input TxIN passes through the multiplexer 36 whose transmission path is selected, and is delayed by the analog delay circuit (DLY0) 11. The delayed transmission signal passes through the multiplexer 33 whose transmission path is selected, is delayed for each transducer independently by the second-stage analog delay circuit (DLY0) 11, and is transmitted by the transmission circuit 31 to the transducer 10. Is driven.

FIG. 6 is an implementation example of the analog delay circuit DLY0 or DLY1 shown in FIGS. With such an analog ring memory configuration, it is possible to delay the analog signal with clock cycle resolution by sampling / holding in synchronization with the clock.

The input analog voltage Vin is written and held in the capacitor Cs by turning on the write side switch controlled by φ * w. Thereafter, the Read side switch controlled by φ * r is turned on and output after a certain period of time. The time from writing Write to reading Read is a delay time. Here, * is 0 and a natural number. In the case of FIG. 6, a plurality of capacitor Cs and switch pairs having numbers from 0 to N sequentially sample and hold.

The maximum amount of delay is determined by clock cycle x number of capacitors Cs parallel N. Although there is no particular limitation, it is desirable to provide an output buffer BUF in order to drive the wiring load connected to the output, the input capacity of the transmission circuit that is the next stage at the time of transmission, and the addition circuit that is the next stage at the time of reception.

FIG. 7 shows a timing chart for explaining the operation of FIG. An N-phase signal having a clock cycle × N cycle as shown in the figure from the reference clock is generated for each of Write and Read. The write control signal φ * w is set to high level to turn on the write side switch, and the input analog voltage is written and held in the capacitor. After a predetermined clock cycle, the read control signal φ * r is set to the high level to turn on the read side switch and obtain an output. The number of clock cycles from writing to reading is the delay time. In the example of FIG. 7, the delay is 3 clock cycles.

∙ Control signals with suffixes 0 to N circulate in both Write and Read, and after φNw becomes high level, φ0w rises to high level. Therefore, since the analog voltage cannot be held in a clock cycle longer than N cycles, the maximum delay amount is determined by the parallel number N of switches and capacitors in FIG. That is, if an attempt is made to increase the maximum delay amount, the number of in-circuit switches and capacitors increases, resulting in an increase in the area of the delay circuit in the transmission / reception circuit of one transducer. For this purpose, the delay circuit is arranged outside the array while realizing a desired maximum delay amount by dividing the delay into two or more stages by hierarchical beam forming and phasing of two or more stages shown in FIGS. It is effective to reduce the vibrator pitch by cutting out a part of.

FIG. 8 shows an example of a layout in which the embodiment circuit for configuring the ultrasonic probe shown in FIG. 3 is physically arranged. FIG. 8 shows a circuit arrangement of a phasing unit called a subarray. For example, the circuit of FIG. 8 constitutes one IC or a part thereof. Here, as an example, a configuration is shown in which 64 transducers are delayed and added by 16 transducers in the array during reception, and further delayed and added by 4 groups outside the array and output to RxOUT.

In the example of FIG. 8, 64 transmission / reception circuits 80 are arranged in an 8 × 8 array in the subarray 100. One of the transmission / reception circuits 80 is extracted and shown in a circle 800 indicated by a dotted line.

Analog delay circuit (DLY0) 11 is arranged in transmission / reception circuit 80 connected to one oscillator (not shown). The outputs of the 16 transducers are added and wired to the outside of the array by one wiring 89. The outputs of the four wires 89 phased by 16 transducers are respectively delayed and added by analog delay circuits (DLY1) 13a, 3b, 13c, and 13d outside the array. The phasing output thus delayed and added in two steps is output from the IC as a reception output RxOUT by the cable buffer BUF indicated by 86, and transmitted to the main body side of the ultrasonic diagnostic apparatus via the cable.

In FIG. 8, 13a. a3b. 13c. An off-array analog delay circuit (DLY1) other than 13d is shown, which will be described. Since a plurality of, for example, 128 subarrays are arranged in the IC, if the subarray consisting of the 64 transducers shown in FIG. 8 is arranged at the end of the array, in fact, Although not shown on the left and right, subarrays are arranged.

The phasing output wiring from the 16 transducers in the upper subarray (not shown) is routed on the array from the top to the bottom of the figure, and delay addition is performed to bundle four wires outside the array. For this reason, if eight subarrays are arranged from end to end at the top and bottom of the entire array, 4 × 8 32 analog delay circuits must be arranged outside the array. A layout is required in which these 32 analog delay circuits outside the array are accommodated in the horizontal width of the sub-array as shown in FIG. However, there is no need for a transmission circuit and a reception circuit connected to one transducer outside the array, and there may be a small circuit such as an analog delay circuit (DLY1), an addition circuit, and other multiplexers. A simple layout is easily realizable.

FIG. 9 is a diagram in which the analog delay circuit write / read control circuit and control signal wiring are added to the layout of FIG. The write control circuit shown in 92 performs writing to the capacitors in the analog delay circuit (DLY0) 11 in the array, and the read control circuit shown in 93 reads from the capacitors in the analog delay circuit (DLY0) 11 in the array. Similarly, the write control circuit 94 performs writing to the capacitor in the off-array analog delay circuit (DLY1) 13, and the read control circuit 95 performs reading from the capacitor in the off-array analog delay circuit (DLY1) 13.

Suppose that the subarray shown in FIG. 9 is located at the bottom right of the array. The plurality of write control lines 96 are controlled independently for each row, and the plurality of read control lines 97 are controlled independently for each column. Since the time from writing to reading is a delay time, by performing independent writing and reading control for each row and column, an independent delay is applied to each transducer of the unit indicated by 80. Can do. In addition, independence of delay control can be ensured not only in the subarray but also in the control line extending across the subarray. In other words, the write / read

control lines

96 and 97 with arrows shown in FIG. 9 can independently control the delay of all the transducers even if they are wired across the sub-array from end to end of the array. Can do.

With the circuit arrangement as described above, a delay delay circuit with a small area can be provided. In particular, it is possible to provide a delay phasing circuit capable of reducing the transmission / reception circuit area per transducer in the 2D array transducer. Thereby, it is possible to reduce the pitch of the transducers repeatedly arranged in an array and to obtain a good ultrasonic beam characteristic in which the influence of the grating lobe is suppressed.

The Write Control circuit 92 and the Read Control circuit 93 in FIG. 9 control the delay amount of the in-array analog delay circuit (DLY0) 11 as the first-stage delay control. The write control circuit 94 and the read control circuit 95 control the delay amount of the off-array analog delay circuit (DLY1) 13 as the second-stage delay control by the plurality of write control lines 98 and the plurality of read control lines 99.

The delay given to the first stage is calculated from the delay profile of the subarray, and the delay given to the second stage is calculated and controlled by the respective

write control lines

96 and 98 and read

control lines

97 and 99. When the analog ring memory as shown in FIGS. 6 and 7 is used for the delay circuit, the reference clock frequency must naturally be the same in the first stage and the second stage. However, for example, φ0w shown in the timing chart of FIG. 7 does not need to be at a high level at the same timing in the first-stage analog delay circuit and the second-stage analog delay circuit. It is sufficient that the control signal circulates as an N-phase signal in both the first stage and the second stage, and there is no problem even if the start and end of the circulation are shifted. Only the number of clock cycles between writing and reading, that is, the amount of delay, becomes a problem.

Considering such a degree of freedom of control, for example, when wiring cannot be laid out over all capacitors due to layout factors on silicon, capacitive coupling to one of N capacitors. It is conceivable that periodic spurious noise is generated at a clock frequency / N frequency due to noise. The control signals of the first and second stages are controlled so that the spurious noise generated in the first stage analog delay circuit and the spurious noise generated in the second stage analog delay circuit overlap and the noise voltage does not double. The timing can be adjusted by relatively shifting in units of clocks, which is an effective means for reducing spurious. Thus, it is desirable to be able to adjust the phase relationship of these control signals so that periodic noise due to wiring coupling does not overlap in the same phase in the in-array delay circuit and the out-of-array delay circuit.

FIG. 10 shows an embodiment of an ultrasonic probe 1000 having a two-dimensional array transducer for three-dimensional imaging and a system configuration to which the present invention is applied. In the ultrasonic probe 1000, a transmission / reception circuit 80 is arranged for each transducer 10, and the reception output is an analog delay circuit (DLY 0) in the array in the transmission / reception circuit 80, an adder circuit 12, an analog delay circuit outside the array ( DLY 1) 13 and the adder circuit 14 adjust the phase in two stages and send it to the AFE (analog front end) 107 of the main unit. The sub-array 100 is a grouping unit of transducer channels to be added.

In FIG. 10, the transmission circuit in the transmission / reception circuit 80 is assumed to be a linear amplifier. That is, an analog transmission waveform is transmitted from the main unit to the main unit by a digital-analog converter DAC denoted by reference numeral 106, amplified in two steps by a linear amplifier, and the vibrator 10 is voltage-driven. All signal paths for transmission and reception are analog.

Transmission amplitude and reception gain settings are transmitted as digital data from the processor 108 of the main unit 1001 to the IC control logic circuit 109 in the ultrasonic probe, and the IC control logic circuit 109 is built in the IC in the ultrasonic probe. Set the parameters of each circuit.

FIG. 11 shows an embodiment in which the transmission circuit in the transmission / reception circuit 80 for driving each transducer 10 in the ultrasonic probe is a pulser in the system configuration of FIG. In this case, unlike FIG. 10, the transmission data is transmitted as digital data from the main body apparatus 1001 to the ultrasonic probe 1000, so that the DAC 106 of FIG. 10 is not necessary. The transmission waveform data is transmitted from the processor 117 of the main body apparatus 1001 to the IC control logic circuit 118 in the ultrasonic probe 1000 and stored in the waveform memory 119. Thereafter, the digital data is delayed in two stages by the analog delay circuit outside the array (DLY1) 13 and the analog delay circuit (DLY0) in the transmission / reception circuit 80, and the transmission pulser in the transmission / reception circuit 80 is corrected according to the digital data. A ternary voltage of a voltage, a negative voltage, and a GND voltage is output.

Here, it will be explained that when an analog delay circuit is used, there is an advantage in that not only an analog transmission waveform but also digital transmission data can be delayed. Shift registers and FIFOs can delay digital data, but not analog waveforms. If an analog waveform is digitally delayed, it is converted to digital by an ADC, then delayed using a shift register or FIFO, and returned to an analog waveform by a DAC.

Since the analog delay circuit can delay the analog waveform, the digital data can be delayed by passing the waveform of the digital data of 0 through the analog delay circuit as it is. In the case of a pulser that outputs ternary values of a positive voltage, a negative voltage, and a GND voltage, it is possible to assign the ternary value to 2 bits and assign 1 bit to each of the two analog delay circuits to delay them in parallel. As described above, by using the analog delay circuit, it is possible to realize beam forming that can correspond to any transmission circuit system of a linear amplifier that can realize an arbitrary transmission waveform and a pulser that is excellent in terms of low power consumption.

FIG. 12 shows a configuration example in the transmission / reception circuit 80 connected to one vibrator 10. The transmission / reception circuit 80 per transducer is composed of a high-voltage MOS, a linear amplifier or pulsar transmission circuit 31 that generates a high-voltage signal and drives the transducer, and a reception-system circuit that handles a low-voltage signal during transmission. A transmission / reception separation switch 123 for separating from a signal, a low-voltage reception low-noise amplifier LNA 32, a first-stage analog delay circuit (DLY0) 11 for delaying a transmission signal, performing beamforming, and delaying a reception signal Is included. The reception signals delayed by the analog delay circuit 125 are added by the adder circuit 12 and transmitted to the second-stage off-array analog delay circuit (DLY1) outside the array inside the IC.

In the embodiments of the present invention described above, in particular, beam forming, beam scanning, and reception signals from each transducer are delayed independently for each transducer by delaying a transmission signal independently for each ultrasonic transducer. A technique has been described in which delay-added phasing for focusing is realized with a small-area circuit, and the pitch of the transducer array can be reduced. According to this embodiment, analog delay circuits necessary for both transmission beamforming and reception phasing are cascaded in a plurality of stages, and only the first-stage delay circuit is arranged in the transmission / reception circuit per transducer for transmission. The area of the transducer array can be reduced, and the pitch of the transducer array can be reduced without sacrificing the maximum delay amount.

This makes it possible to reduce the influence of the grating lobe due to diffraction and to obtain good ultrasonic beam characteristics within the scanning angle.

Furthermore, by passing a transmission analog signal or a transmission digital signal through the analog delay circuit, it is possible to realize a delay of the transmission signal regardless of whether the transmission circuit is a linear amplifier or a pulsar, and to ensure flexibility in circuit design. It becomes possible.

In addition, the above embodiment is effective as a technique for realizing a desired ultrasonic beam characteristic with a limited circuit area.

The present invention is not limited to the above-described embodiment, and includes various modifications. For example, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. Further, it is possible to add, delete, and replace the configurations of other embodiments with respect to a part of the configurations of the embodiments.

It can be mounted on an IC in an ultrasonic probe connected to an ultrasonic diagnostic apparatus.

DLY0, DLY1 Analog delay circuit Tx Transmission circuit Rx Reception circuit TxIN Transmission input RxOUT Reception output VIN Voltage input VOUT Voltage output Cs Analog ring memory internal voltage holding capacitor BUF Buffer φ * w Analog ring memory write control signal φ * r Analog ring memory Read control signal CLK Reference clock EL Oscillator DAC Digital to Analog Converter
Digital / Analog Converter AFE Analog Front End IC Integrated Circuit Integrated Circuit T / R-SW Transmission / Reception Separation Switch LNA Low Noise Amplifier Low Noise Amplifier ADC Analog to Digital Converter
Analog / digital converter FIFO First-In First-Out First-in first-out memory

Claims

Multiple circuit units;
An adder circuit for adding outputs from the plurality of circuit units;
An input terminal for inputting a common signal to the plurality of circuit units;
Have
Each of the circuit units is
A receiving circuit and a transmitting circuit connected to the ultrasonic transducer, and a first delay circuit;
When receiving signals with the ultrasonic transducer,
The receiving circuit receives a signal from the ultrasonic transducer,
The first delay circuit delays the signal from the receiving circuit;
The signal delayed by the first delay circuit is added by the adder circuit,
A signal added by the adder circuit is delayed by a second delay circuit;
When transmitting a signal with the ultrasonic transducer,
A signal from the input terminal is delayed by the second delay circuit;
Branching the signal delayed by the second delay circuit and inputting it to the plurality of circuit units;
The signal delayed by the second delay circuit is delayed by the first delay circuit in each of the plurality of circuit units,
Inputting the signal delayed by the first delay circuit to the transmission circuit;
Ultrasonic probe.
The plurality of circuit units are arranged in a lattice form to form an array region,
The second delay circuit is disposed outside the array region;
The ultrasonic probe according to claim 1.
N × m (where n and m are natural numbers) including the plurality of circuit units,
M each of the adder circuit and the second delay circuit;
The n delay units share one adder circuit and the second delay circuit in units of n circuits,
m second delay circuits are arranged in a grid pattern;
The ultrasonic probe according to claim 2.
The first delay circuit and the second delay circuit are analog delay circuits;
The analog delay circuit is:
It has a plurality of capacitors to hold the input signal,
The delay time is controlled by a plurality of write signals for controlling the write timings of the plurality of capacitors and a plurality of read signals for controlling the output timings of the plurality of capacitors.
The ultrasonic probe according to claim 3.
The write signal supply line and the read signal supply line for the first delay circuit in the circuit unit are arranged in a grid pattern,
The write signal supply line and the read signal supply line for the second delay circuit are arranged in a grid pattern,
The write signal supply line for the first delay circuit and the write signal supply line for the second delay circuit are configured independently,
The read signal supply line for the first delay circuit and the read signal supply line for the second delay circuit are configured independently.
The ultrasonic probe according to claim 4.
A plurality of first delay circuits connected to the plurality of ultrasonic transducers on a one-to-one basis;
An adder circuit for adding the outputs of the plurality of first delay circuits;
A second delay circuit connected to the adder circuit;
Have
The received signal from the ultrasonic transducer is delayed by the first delay circuit and the second delay circuit,
An ultrasonic probe that delays a transmission signal to the ultrasonic transducer by the first delay circuit and the second delay circuit.
The first and second delay circuits are analog delay circuits;
The ultrasonic probe according to claim 6, wherein a delayed analog transmission signal is output to a transmission linear amplifier circuit connected to the single ultrasonic transducer.
The first and second delay circuits are analog delay circuits;
The ultrasonic probe according to claim 6, wherein a delayed digital signal is output to a transmission pulser circuit connected to the single ultrasonic transducer.
The first delay circuit is disposed in a transmission / reception circuit connected to the plurality of ultrasonic transducers on a one-to-one basis,
The plurality of transmission / reception circuits constitute a one-dimensional or two-dimensional array arranged repeatedly,
The ultrasonic probe according to claim 6, wherein the second delay circuit is arranged outside the one-dimensional or two-dimensional array.
10. The ultrasonic probe according to claim 9, wherein during transmission, the transmission signal is delayed by the second delay circuit, and then the transmission signal is further delayed by the first delay circuit in each of the transmission / reception circuits.
10. The ultrasonic wave according to claim 9, wherein at the time of reception, the received signal is delayed by the first delay circuit in each of the transmission / reception circuits, added by the adder circuit, and then further delayed by the second delay circuit. 11. Transducer.
The control signal of the first delay circuit is supplied from outside the array,
The control signal of the second delay circuit is supplied from outside the array independently of the control signal of the first delay circuit,
The ultrasonic probe according to claim 9, wherein a phase relationship between these control signals is adjustable.
An ultrasonic diagnostic apparatus comprising an ultrasonic probe and an apparatus main body,
The ultrasonic probe is
Multiple circuit units;
A first addition circuit for adding outputs from the plurality of circuit units;
An input terminal for inputting a common signal to the plurality of circuit units;
Have
Each of the circuit units is
A receiving circuit and a transmitting circuit connected to the ultrasonic transducer, and a first delay circuit;
When receiving signals with the ultrasonic transducer,
The receiving circuit receives a signal from the ultrasonic transducer,
The first delay circuit delays the signal from the receiving circuit;
The signal delayed by the first delay circuit is added by the first adder circuit,
A signal added by the first adder circuit is delayed by a second delay circuit;
When transmitting a signal with the ultrasonic transducer,
A signal from the input terminal is delayed by the second delay circuit;
Branching the signal delayed by the second delay circuit and inputting it to the plurality of circuit units;
In each of the plurality of circuit units, the signal delayed by the second delay circuit is delayed by the first delay circuit,
Inputting the signal delayed by the first delay circuit to the transmission circuit;
Configuration,
The device body is
When receiving signals with the ultrasonic transducer,
A signal delayed by the second delay circuit is used as a detection signal, and an imaging signal is formed based on the detection signal.
When transmitting a signal with the ultrasonic transducer,
Supplying a transmission signal to the input terminal;
Ultrasound diagnostic device.
The plurality of circuit units are arranged in a lattice form to form an array region,
The second delay circuit is disposed outside the array region;
The first delay circuit and the second delay circuit are analog delay circuits;
Each of the analog delay circuits is
It has a plurality of capacitors to hold the input signal,
The delay time is controlled by a plurality of write signals for controlling the write timing of the plurality of capacitors and a plurality of read signals for controlling the output timing of the plurality of capacitors.
The write signal and the read supply line for the first delay circuit in the circuit unit are arranged in a grid pattern,
The write signal and read signal that control the timing of the first delay circuit are controlled independently of the write signal and read signal that control the timing of the second delay circuit,
The ultrasonic diagnostic apparatus according to claim 13.
A plurality of the second delay circuits;
The apparatus main body is
When receiving signals with the ultrasonic transducer,
A signal delayed by a plurality of the second delay circuits is added to form a detection signal, and an imaging signal is formed based on the detection signal,
When transmitting a signal with the ultrasonic transducer,
A transmission signal supplied to the input terminal is supplied in parallel to the plurality of second delay circuits.
The ultrasonic diagnostic apparatus according to claim 14.