WO2017039045A1 - Semiconductor light-emitting device - Google Patents

Semiconductor light-emitting device Download PDF

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Publication number
WO2017039045A1
WO2017039045A1 PCT/KR2015/009404 KR2015009404W WO2017039045A1 WO 2017039045 A1 WO2017039045 A1 WO 2017039045A1 KR 2015009404 W KR2015009404 W KR 2015009404W WO 2017039045 A1 WO2017039045 A1 WO 2017039045A1
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layer
type
quantum well
type semiconductor
barrier layer
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French (fr)
Korean (ko)
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안도열
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주식회사 페타룩스
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure

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  • the present invention relates to a light emitting device, and more particularly to a semiconductor light emitting device.
  • Semiconductor light emitting devices such as light emitting diodes are environmentally friendly, capable of low power driving, and can be implemented in a small size. Due to these advantages, since semiconductor light emitting devices have been developed, such semiconductor light emitting devices have been widely used in various fields. In particular, since the development of the III-V nitride-based quantum well structure-based semiconductor light emitting device, it is possible to implement white light, and has been gradually expanding the range of application to not only LCD TV backlight but also general lighting. .
  • group II-V / I-VII semiconductors can use ZnO substrates that have higher luminous efficiency than nitride semiconductors, are cheaper than sapphire, and have large area substrates, but are still used for p-doping to form devices. This situation is not solved.
  • I-VII compound semiconductor light emitting devices have been developed. Since the I-VII compound semiconductor light emitting device has a lattice constant similar to that of silicon, it can be grown on an inexpensive silicon substrate and a large-sized silicon wafer with a diameter of 30 cm can be used as the substrate, thereby significantly reducing manufacturing costs. . In addition, the luminous efficiency is known to be relatively superior to the nitride semiconductor.
  • FIG. 1 is a diagram schematically showing a band structure of a conventional I-VII compound semiconductor light emitting device.
  • the electron blocking layer prevents electrons passing through the quantum well from moving to the p-type region to improve luminous efficiency.
  • the electron blocking layer blocks electrons moving along the path a to block the movement of the p-type semiconductor layer, but holes are injected from the p-type semiconductor layer along the path b. It acts as a potential barrier Vb with respect to. Therefore, as the hole density of the quantum well layer is reduced, the luminous efficiency acts as a cause. Moreover, the heavy effective mass of the hole and the internal field caused by piezo and spontaneous polarization also contribute to the poor hole injection efficiency.
  • An object of the present invention is to provide a semiconductor light emitting device that can improve luminous efficiency.
  • Semiconductor light emitting devices for solving this problem include an n-type semiconductor layer, a quantum well layer, a barrier layer and a p-type semiconductor layer.
  • the n-type semiconductor layer includes an I-VII compound semiconductor.
  • the quantum well layer is formed on the n-type semiconductor layer, and includes an I-VII compound semiconductor.
  • the barrier layer is formed over the quantum well layer and includes an I-VII compound semiconductor.
  • the p-type semiconductor layer is formed on the barrier layer and includes an I-VII compound semiconductor. At this time, at least one p-type local doping layer is formed on the barrier layer.
  • the p-type local doping layer may be formed adjacent to the quantum well layer.
  • the n-type semiconductor layer, the quantum well layer, the barrier layer and the p-type semiconductor layer are CuFCl, CuBrF, CuFI, CuClBr, CuClI, CuBrI, AgFCl, AgFBr, AgFI, AgClBr, AgClI, AgBrI, AuFCl, AuFBr, AuFI, AuClBr, AuClI, AuBrI, CuFClBr, CuFClI, CuFBrI, CuIBrCl, AgFClBr, AgFClI, AgFBrI, AgClBrI, AuFClBr, AuFClI, AuFBrI, or AuClBrI, which may contain at least one.
  • the semiconductor light emitting device may further include one or more electron blocking layers formed between the barrier layer and the p-type semiconductor layer.
  • the p-type local doping layer formed on the barrier layer is preferably spaced apart from the electron blocking layer by more than 10nm.
  • At least one p-type local doping layer may be formed on the electron blocking layer.
  • the electron blocking layer is CuFCl, CuBrF, CuFI, CuClBr, CuClI, CuBrI, AgFCl, AgFBr, AgFI, AgClBr, AgClI, AgBrI, AuFCl, AuFBr, AuFI, AuClBr, AuClI, AuBrI, CuFClBr, CuBrI, IBIB It may include at least one of, AgFClBr, AgFClI, AgFBrI, AgClBrI, AuFClBr, AuFClI, AuFBrI, or AuClBrI.
  • a semiconductor light emitting device includes a substrate, an n-type semiconductor layer, a quantum well layer, a barrier layer, an electron blocking layer, and a p-type semiconductor layer.
  • the n-type semiconductor layer is formed on the substrate and includes an I-VII compound semiconductor.
  • the quantum well layer is formed on the n-type semiconductor layer, and includes an I-VII compound semiconductor.
  • the barrier layer is formed on the quantum well layer and includes an I-VII compound semiconductor.
  • the electron blocking layer is formed on the barrier layer and includes an I-VII compound semiconductor.
  • the p-type semiconductor layer is formed on the electron blocking layer and includes an I-VII compound semiconductor. In this case, at least one p-type local doping layer is formed on the electron blocking layer.
  • the n-type semiconductor layer, the quantum well layer, the barrier layer, and the p-type semiconductor layer may be CuFCl, CuBrF, CuFI, CuClBr, CuClI, CuBrI, AgFCl, AgFBr, AgFI, AgClBr, AgClI, AgBrI, AuFCl, AuFBr, AuFI, AuClBr, AuClI, AuBrI, CuFClBr, CuFClI, CuFBrI, CuIBrCl, AgFClBr, AgFClI, AgFBrI, AgClBrI, AuFClBr, AuFClI, AuFBrI, or AuClBrI, which may contain at least one.
  • one or more p-type local doped layers may be formed on the barrier layer.
  • the p-type local doping layer formed on the barrier layer is preferably formed adjacent to the quantum well layer.
  • the p-type local doping layer formed on the barrier layer is preferably spaced apart from the electron blocking layer by more than 10nm.
  • the luminous efficiency can be improved by reducing the internal electric field of the active layer due to the spontaneous polarization caused by the piezo effect.
  • the p-type local doping layer on the electron blocking layer, it is possible to effectively inject holes while providing an effective blocking effect on electrons.
  • the energy level of the holes formed therein increases the tunneling probability of the holes injected from the p-type electrode, thereby increasing the internal quantum efficiency, thereby improving luminous efficiency.
  • the luminous efficiency may be further improved.
  • the distance between the electron blocking layer is maximized so that electrons and holes are spaced apart from the barrier layer as much as possible, thereby effectively increasing the Auger recombination probability. Can be reduced.
  • FIG. 1 is a diagram schematically showing a band structure of a conventional semiconductor light emitting device.
  • FIG. 2 is a diagram schematically showing a band structure of a semiconductor light emitting device according to an exemplary embodiment of the present invention.
  • FIG. 3 is a diagram schematically showing a band structure of a semiconductor light emitting device according to another exemplary embodiment of the present invention.
  • FIG. 4 is a diagram schematically showing a band structure of a semiconductor light emitting device according to another exemplary embodiment of the present invention.
  • first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.
  • the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.
  • the term “formed on” or “formed on” a film (or layer) means that in addition to being directly formed to be in contact, another film or other layer may be formed therebetween, “Formed directly” on a layer means that no other layer is interposed therebetween.
  • FIG. 2 is a diagram schematically showing a band structure of a semiconductor light emitting device according to an exemplary embodiment of the present invention.
  • a semiconductor light emitting device 100 may include an n-type semiconductor layer 110, a quantum well layer 120, a barrier layer 130, and a p-type semiconductor layer. And 150.
  • the semiconductor light emitting device 100 may further include the electron blocking layer 140 illustrated in FIG. 1.
  • the n-type semiconductor layer 110, the quantum well layer 120, the barrier layer 130, the p-type semiconductor layer 150, and the electron blocking layer 140 include an I-VII compound semiconductor. do.
  • the n-type semiconductor layer 110, the quantum well layer 120, the barrier layer 130, the p-type semiconductor layer 150, and the electron blocking layer 140 are CuFCl and CuBrF, respectively.
  • the band gap of the quantum well layer 120 is selected to be the smallest, and the band of the n-type semiconductor layer 110, the barrier layer 130, and the p-type semiconductor layer 150 is selected.
  • the gap may be formed by selecting a material larger than the quantum well layer 120.
  • the n-type semiconductor layer 110 may add n-type impurities (eg, zinc (Zn), magnesium (Mg), or the like), and the p-type semiconductor layer 150 may be p-type. It can be formed by adding impurities (eg, oxygen (O), sulfur (S), selenium (Se), or the like).
  • the n-type semiconductor layer 110 is formed on a substrate (not shown), molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), atomic layer epitaxy (ALE), and / Or else similar.
  • the substrate may be a silicon (Si) substrate.
  • the lattice constant is similar to that of the copper blend I-VII compound semiconductor, thereby enabling a good thin film formation.
  • the n-type semiconductor layer 110 may be formed on the (111) surface of the silicon substrate.
  • Relatively inexpensive silicon substrates may also be used compared to more expensive conventional substrate materials such as sapphire, since their lattice constants are close to those of the I-V compound semiconductors, although they have different crystal structures.
  • silicon is known to have a diamond structure, while CuCl has a diamond structure.
  • the (111) face of the silicon substrate may be used to fabricate the semiconductor light emitting device 100 as it may be suitable for the crystal structure of CuCl, which may be stacked on the substrate.
  • the substrate may be used with sapphire, bulk gallium nitride, or the like.
  • the quantum well layer 120 may be formed through the n-, through molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), atomic layer epitaxy (ALE), and / or the like.
  • MBE molecular beam epitaxy
  • MOCVD metal organic chemical vapor deposition
  • HVPE hydride vapor phase epitaxy
  • ALE atomic layer epitaxy
  • the semiconductor layer 110 may be formed on the semiconductor semiconductor layer 110.
  • the barrier layer 130 may be formed through the quantum well layer through molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), atomic layer epitaxy (ALE), and / or the like. 120 may be formed on top.
  • MBE molecular beam epitaxy
  • MOCVD metal organic chemical vapor deposition
  • HVPE hydride vapor phase epitaxy
  • ALE atomic layer epitaxy
  • 120 may be formed on top.
  • the p-type semiconductor layer 150 may be formed through molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), atomic layer epitaxy (ALE), and / or the like. It may be formed on the barrier layer 130.
  • MBE molecular beam epitaxy
  • MOCVD metal organic chemical vapor deposition
  • HVPE hydride vapor phase epitaxy
  • ALE atomic layer epitaxy
  • the quantum well layer 120 including the I-V compound semiconductor may have a relatively large exciton binding energy, for example, an exciton binding energy at least twice as large as those of group III nitride. This can improve quantum efficiency.
  • I-VIII compound semiconductors with large exciton binding energies may be suitable for strong optical transitions, for example, which are desirable in light emitting devices that emit light in the blue region of the visible spectrum.
  • the exciton binding energy is a measure of the interaction of holes and electrons, with opposite charges, and may be used to predict the strength of the hole-electron recombination process.
  • CuBr is known to have an exciton binding energy of about 108 meV, which is higher than the exciton binding energy of ZnO.
  • the I-VIII compound semiconductor based light emitting devices have greater optical gain than conventional wide bandgap semiconductors such as group III nitride or ZnO based light emitting devices.
  • the p-type local doping layer 131 is a thin film single crystal having an atomic unit thickness to include the p-type impurities described above.
  • the p-type local doping layer 131 may be formed adjacent to the quantum well layer 120.
  • the barrier layer 130 is formed adjacent to the quantum well layer 120, the barrier height of the well wall 120 is increased to transfer electrons from the quantum well layer 120 to the barrier layer 130.
  • the p-type local doping layer 131 may increase the internal quantum efficiency by reducing the internal electric field in the quantum well layer 120 due to the piezo effect and spontaneous polarization.
  • FIG. 3 is a diagram schematically showing a band structure of a semiconductor light emitting device according to another exemplary embodiment of the present invention.
  • the overlapping part of the description of the embodiment with reference to FIG. 2 is omitted.
  • a semiconductor light emitting device 100 may include an n-type semiconductor layer 110, a quantum well layer 120, a barrier layer 130, and an electron blocking layer 140. ) And the p-type semiconductor layer 150.
  • the n-type semiconductor layer 110 may be formed on a substrate (not shown).
  • the quantum well layer 120 is formed on the n-type semiconductor layer 110.
  • the barrier layer 130 is formed on the quantum well layer 120.
  • the electron blocking layer 140 is formed on the barrier layer 130.
  • the p-type semiconductor layer 150 is formed on the electron blocking layer 140.
  • At least one p-type local doping layer 141 is formed on the electron blocking layer 140.
  • the P-type local doping layer 141 is provided with an effective blocking effect on electrons, and enables effective transmission of holes. That is, the energy level of the holes formed in the p-type local doping layer 141 increases the tunneling probability of the holes injected from the p-type electrode, thereby increasing the internal quantum efficiency.
  • FIG. 4 is a diagram schematically showing a band structure of a semiconductor light emitting device according to another exemplary embodiment of the present invention.
  • the semiconductor light emitting device shown in FIG. 4 additionally forms the p-type local doping layer 131 shown in FIG. 2 in the semiconductor light emitting device shown in FIG.
  • the p-type local doping layer 131 is formed on the barrier layer 130 and the p-type local doping layer 141 is formed on the electron blocking layer 140 as described above, not only the foregoing effects, but also the A synergistic effect can be expected.
  • the foregoing descriptions and repeated descriptions are omitted.
  • a semiconductor light emitting device 100 may include an n-type semiconductor layer 110, a quantum well layer 120, a barrier layer 130, and an electron blocking layer 140. ) And the p-type semiconductor layer 150. At least one p-type local doping layer 131 is formed on the barrier layer 130. The p-type local doping layer 131 may be formed adjacent to the quantum well layer 120. In addition, the p-type local doping layer 131 formed on the barrier layer 130 may be spaced apart from the electron blocking layer 140 by 10 nm or more. In addition, at least one p-type local doping layer 141 is formed on the electron blocking layer 140.
  • Equation 1 The potential formed by local doping is given by Equation 1 below. [D. Ahn, Phys. Rev. 48, 7981 (1993).
  • P S is the surface charge density of the local doped layer.
  • the energy level of the hole can be obtained from Schrödinger's equation as shown in Equation 2 below.
  • FIG. 1 The structure that can separate the maximum value of the electron and hole distribution in order to reduce the Auger recombination is shown in FIG.
  • the p-type local doping layer 131 formed on the barrier layer 130 serves to cancel the internal electric field, the p-type local doping layer 131 is close to the quantum well layer 120 (just after the last barrier layer), but the electron blocking layer 140 Place at a distance (10 nm or more). Due to the electron blocking layer 140, the electrons in the p-type semiconductor layer 150 may have a maximum density immediately before the electron blocking layer 140. On the other hand, due to the p-type local doping layer 131 formed on the barrier layer 130, the maximum hole distribution is due to the p-type local doping layer 131 and the electron blocking layer formed immediately after the last barrier of the quantum well layer 120. It is expected to be formed in the p-type local doping layer 141 formed at 140 to effectively reduce the Auger recombination probability.

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Abstract

A semiconductor light-emitting device capable of improving light-emitting efficiency is disclosed. The semiconductor light-emitting device comprises an n-type semiconductor layer, a quantum well layer, a barrier layer, and a p-type semiconductor layer. The n-type semiconductor layer comprises an I-VII compound semiconductor. The quantum well layer is formed on the n-type semiconductor layer and comprises the I-VII compound semiconductor. The barrier layer is formed on the quantum well layer and comprises the I-VII compound semiconductor. The p-type semiconductor layer is formed on the barrier layer and comprises the I-VII compound semiconductor, wherein one or more p-type local doping layers are formed at the barrier layer.

Description

반도체 발광 디바이스Semiconductor light emitting device
본 발명은 발광 디바이스에 관한 것으로, 보다 상세히 반도체 발광 디바이스에 관한 것이다.The present invention relates to a light emitting device, and more particularly to a semiconductor light emitting device.
발광 다이오드 등의 반도체 발광 소자는 환경 친화적이고, 저전력 구동이 가능하며, 또한 작은 사이즈로 구현 가능하다. 이러한 장점들로 인해서, 반도체 발광 소자가 개발된 이후, 이러한 반도체 발광 소자는 여러 분야에서 널리 사용되고 있다. 특히, III-V족 질화물계 양자우물 구조기반 반도체 발광 소자가 개발된 이후, 백색광의 구현이 가능하게 되어, LCD TV의 백라이트는 물론이고, 일반 조명에 이르기 까지 그 활용범위를 점차 확대해 나아가고 있다.Semiconductor light emitting devices such as light emitting diodes are environmentally friendly, capable of low power driving, and can be implemented in a small size. Due to these advantages, since semiconductor light emitting devices have been developed, such semiconductor light emitting devices have been widely used in various fields. In particular, since the development of the III-V nitride-based quantum well structure-based semiconductor light emitting device, it is possible to implement white light, and has been gradually expanding the range of application to not only LCD TV backlight but also general lighting. .
한편, III-V족 질화물계 양자우물 구조기반 반도체 발광 소자가 개발되었으나, 질화물 반도체 성장을 위해서 사파이어 기판 사용되고 있으나, 매우 고가인 문제가 있다. 또한, II-V족/I-VII족 반도체는 질화물 반도체에 비해 발광효율이 높고 사파이어어 비해 가격이 저렴하고 대면적 기판이 가능한 ZnO 기판을 사용할 수 있지만 아직 소자 형성을 위한 p-도핑(doping)이 해결되지 않고 있는 실정이다.Meanwhile, although a III-V nitride-based quantum well structure-based semiconductor light emitting device has been developed, a sapphire substrate is used for nitride semiconductor growth, but there is a problem that it is very expensive. In addition, group II-V / I-VII semiconductors can use ZnO substrates that have higher luminous efficiency than nitride semiconductors, are cheaper than sapphire, and have large area substrates, but are still used for p-doping to form devices. This situation is not solved.
이에, I-VII 화합물 반도체 발광 디바이스가 개발되어지고 있다. 상기 I-VII 화합물 반도체 발광 디바이스는 격자상수가 실리콘과 비슷하여, 저렴한 실리콘 기판에 성장이 가능할 뿐만 아니라, 지름 30cm의 대면적의 실리콘 웨이퍼를 기판으로 적용할 수 있어, 제조비용이 획기적으로 저렴하다. 또한, 발광효율이 질화물 반도체에 비해 상대적으로 우수한 것으로 알려져 있다.Accordingly, I-VII compound semiconductor light emitting devices have been developed. Since the I-VII compound semiconductor light emitting device has a lattice constant similar to that of silicon, it can be grown on an inexpensive silicon substrate and a large-sized silicon wafer with a diameter of 30 cm can be used as the substrate, thereby significantly reducing manufacturing costs. . In addition, the luminous efficiency is known to be relatively superior to the nitride semiconductor.
도 1은 종래 I-VII 화합물 반도체 발광 디바이스의 밴드 구조를 개략적으로 도시한 다이어그램이다.1 is a diagram schematically showing a band structure of a conventional I-VII compound semiconductor light emitting device.
도 1을 참조하면, 전자 차단층은 양자 우물을 통과한 전자가 p-형 영역으로 이동하는 것을 차단하여 발광 효율을 향상시킨다.Referring to FIG. 1, the electron blocking layer prevents electrons passing through the quantum well from moving to the p-type region to improve luminous efficiency.
통상적인 전자 차단층의 구조이다. 도 1에서 볼 수 있는 것처럼 전자 차단층은 경로 a를 따라서 이동하는 전자를 블로킹하여 p-형의 반도체층으로 이동하는 것을 차단하지만, 경로 b를 따라서 p-형 반도체층로부터 주입되는 정공(hole)에 대해서 포텐셜 배리어(Vb)로 작용하게 된다. 따라서, 양자 우물층의 정공밀도를 감소시킴에 따라 발광효율이 낮아지는 원인으로 작용한다. 더욱이, 정공의 유효질량이 무거운 것과 피에조 및 자발분극에 의한 내부장도 정공의 주입 효율을 나쁘게 하는 요인이 된다. It is a structure of a conventional electron blocking layer. As can be seen in FIG. 1, the electron blocking layer blocks electrons moving along the path a to block the movement of the p-type semiconductor layer, but holes are injected from the p-type semiconductor layer along the path b. It acts as a potential barrier Vb with respect to. Therefore, as the hole density of the quantum well layer is reduced, the luminous efficiency acts as a cause. Moreover, the heavy effective mass of the hole and the internal field caused by piezo and spontaneous polarization also contribute to the poor hole injection efficiency.
본 발명이 해결하고자 하는 과제는, 발광 효율을 향상시킬 수 있는 반도체 발광 디바이스를 제공하는 것이다.An object of the present invention is to provide a semiconductor light emitting device that can improve luminous efficiency.
이러한 과제를 해결하기 위한 본 발명의 예시적인 실시예들에 의한 반도체 발광 디바이스들은, n-형 반도체층, 양자 우물층, 배리어층 및 p-형 반도체층을 포함한다. n-형 반도체층은 I-VII 화합물 반도체를 포함한다. 상기 양자 우물층은 상기 n-형 반도체층 상부에 형성되고, I-VII 화합물 반도체를 포함한다. 상기 배리어층은 양자 우물층 상부에 형성되고, I-VII 화합물 반도체를 포함한다. 상기 p-형 반도체층은 상기 배리어층 상부에 형성되고, I-VII 화합물 반도체를 포함한다. 이때, 상기 배리어층에는, 하나 이상의 p-형 국소 도핑층이 형성된다.Semiconductor light emitting devices according to exemplary embodiments of the present invention for solving this problem include an n-type semiconductor layer, a quantum well layer, a barrier layer and a p-type semiconductor layer. The n-type semiconductor layer includes an I-VII compound semiconductor. The quantum well layer is formed on the n-type semiconductor layer, and includes an I-VII compound semiconductor. The barrier layer is formed over the quantum well layer and includes an I-VII compound semiconductor. The p-type semiconductor layer is formed on the barrier layer and includes an I-VII compound semiconductor. At this time, at least one p-type local doping layer is formed on the barrier layer.
바람직하게, 상기 p-형 국소 도핑층은 상기 양자 우물층에 인접하도록 형성될 수 있다.Preferably, the p-type local doping layer may be formed adjacent to the quantum well layer.
이때, 상기 n-형 반도체층, 상기 양자 우물층, 상기 배리어층 및 상기 p-형 반도체층은 각각 CuFCl, CuBrF, CuFI, CuClBr, CuClI, CuBrI, AgFCl, AgFBr, AgFI, AgClBr, AgClI, AgBrI, AuFCl, AuFBr, AuFI, AuClBr, AuClI, AuBrI, CuFClBr, CuFClI, CuFBrI, CuIBrCl, AgFClBr, AgFClI, AgFBrI, AgClBrI, AuFClBr, AuFClI, AuFBrI, or AuClBrI 중, 적어도 어느 하나를 포함할 수 있다.In this case, the n-type semiconductor layer, the quantum well layer, the barrier layer and the p-type semiconductor layer are CuFCl, CuBrF, CuFI, CuClBr, CuClI, CuBrI, AgFCl, AgFBr, AgFI, AgClBr, AgClI, AgBrI, AuFCl, AuFBr, AuFI, AuClBr, AuClI, AuBrI, CuFClBr, CuFClI, CuFBrI, CuIBrCl, AgFClBr, AgFClI, AgFBrI, AgClBrI, AuFClBr, AuFClI, AuFBrI, or AuClBrI, which may contain at least one.
한편, 이러한 반도체 발광 디바이스는 상기 배리어층과 상기 p-형 반도체층 사이에 형성된 하나 이상의 전자 차단층을 더 포함할 수 있다.Meanwhile, the semiconductor light emitting device may further include one or more electron blocking layers formed between the barrier layer and the p-type semiconductor layer.
이때, 상기 배리어층에 형성되는 상기 p-형 국소 도핑층은 상기 전자 차단층과 10nm이상 이격시키는 것이 바람직하다.In this case, the p-type local doping layer formed on the barrier layer is preferably spaced apart from the electron blocking layer by more than 10nm.
또한, 상기 전자 차단층에는, 하나 이상의 p-형 국소 도핑층이 형성될 수 있다.In addition, at least one p-type local doping layer may be formed on the electron blocking layer.
또한, 상기 전자 차단층은 CuFCl, CuBrF, CuFI, CuClBr, CuClI, CuBrI, AgFCl, AgFBr, AgFI, AgClBr, AgClI, AgBrI, AuFCl, AuFBr, AuFI, AuClBr, AuClI, AuBrI, CuFClBr, CuFClI, CuFBrI, CuIBrCl, AgFClBr, AgFClI, AgFBrI, AgClBrI, AuFClBr, AuFClI, AuFBrI, or AuClBrI 중, 적어도 어느 하나를 포함할 수 있다.In addition, the electron blocking layer is CuFCl, CuBrF, CuFI, CuClBr, CuClI, CuBrI, AgFCl, AgFBr, AgFI, AgClBr, AgClI, AgBrI, AuFCl, AuFBr, AuFI, AuClBr, AuClI, AuBrI, CuFClBr, CuBrI, IBIB It may include at least one of, AgFClBr, AgFClI, AgFBrI, AgClBrI, AuFClBr, AuFClI, AuFBrI, or AuClBrI.
본 발명의 예시적인 다른 실시예에 의한 반도체 발광 디바이스는, 기판, n-형반도체층, 양자 우물층, 배리어층, 전자 차단층 및 p-형 반도체층을 포함한다. 상기 n-형 반도체층은 상기 기판 상에 형성되고, I-VII 화합물 반도체를 포함한다. 상기 양자 우물층은 상기 n-형 반도체층 상부에 형성되고, I-VII 화합물 반도체를 포함한다. 상기 배리어층은 상기 양자 우물층 상부에 형성되고, I-VII 화합물 반도체를 포함한다. 상기 전자 차단층은, 상기 배리어층 상부에 형성되고, I-VII 화합물 반도체를 포함한다. 상기 p-형 반도체층은 상기 전자 차단층 상부에 형성되고, I-VII 화합물 반도체를 포함한다. 이때, 상기 전자 차단층에는, 하나 이상의 p-형 국소 도핑층이 형성된다.A semiconductor light emitting device according to another exemplary embodiment of the present invention includes a substrate, an n-type semiconductor layer, a quantum well layer, a barrier layer, an electron blocking layer, and a p-type semiconductor layer. The n-type semiconductor layer is formed on the substrate and includes an I-VII compound semiconductor. The quantum well layer is formed on the n-type semiconductor layer, and includes an I-VII compound semiconductor. The barrier layer is formed on the quantum well layer and includes an I-VII compound semiconductor. The electron blocking layer is formed on the barrier layer and includes an I-VII compound semiconductor. The p-type semiconductor layer is formed on the electron blocking layer and includes an I-VII compound semiconductor. In this case, at least one p-type local doping layer is formed on the electron blocking layer.
예컨대, 상기n-형 반도체층, 상기 양자 우물층, 상기 배리어층 및 상기 p-형 반도체층은 각각 CuFCl, CuBrF, CuFI, CuClBr, CuClI, CuBrI, AgFCl, AgFBr, AgFI, AgClBr, AgClI, AgBrI, AuFCl, AuFBr, AuFI, AuClBr, AuClI, AuBrI, CuFClBr, CuFClI, CuFBrI, CuIBrCl, AgFClBr, AgFClI, AgFBrI, AgClBrI, AuFClBr, AuFClI, AuFBrI, or AuClBrI 중, 적어도 어느 하나를 포함할 수 있다.For example, the n-type semiconductor layer, the quantum well layer, the barrier layer, and the p-type semiconductor layer may be CuFCl, CuBrF, CuFI, CuClBr, CuClI, CuBrI, AgFCl, AgFBr, AgFI, AgClBr, AgClI, AgBrI, AuFCl, AuFBr, AuFI, AuClBr, AuClI, AuBrI, CuFClBr, CuFClI, CuFBrI, CuIBrCl, AgFClBr, AgFClI, AgFBrI, AgClBrI, AuFClBr, AuFClI, AuFBrI, or AuClBrI, which may contain at least one.
또한, 상기 배리어층에는, 하나 이상의 p-형 국소 도핑층이 형성될 수 있다.In addition, one or more p-type local doped layers may be formed on the barrier layer.
이 경우, 상기 배리어층에 형성된 상기 p-형 국소 도핑층은 상기 양자 우물층에 인접하게 형성되는 것이 바람직하다.In this case, the p-type local doping layer formed on the barrier layer is preferably formed adjacent to the quantum well layer.
또한, 상기 배리어층에 형성되는 상기 p-형 국소 도핑층은 상기 전자 차단층과 10nm이상 이격되는 것이 바람직하다.In addition, the p-type local doping layer formed on the barrier layer is preferably spaced apart from the electron blocking layer by more than 10nm.
본 발명에 의한 반도체 발광 디바이스와 같이, 배리어 층에 p-형 국소 도핑층을 형성하는 경우, 피에조 효과에 의한 자발 분극으로 인한 활성층의 내부전계를 감소시킴으로써 발광 효율을 향상시킬 수 있다.When the p-type local doping layer is formed in the barrier layer, as in the semiconductor light emitting device according to the present invention, the luminous efficiency can be improved by reducing the internal electric field of the active layer due to the spontaneous polarization caused by the piezo effect.
또한, 상기 전자 차단층에 상기 p-형 국소 도핑층을 형성함으로써, 전자에 대해서 효과적인 블로킹 효과를 주면서 정공(hole)에 대해서는 효율적인 주입이 가능하다. 상기 p-형 국소 도핑층은 그 내부에 형성된 정공의 에너지 준위가 p-형 전극에서 주입된 정공의 터널링 확률을 높여 줌으로써 내부 양자효율을 증가시켜 발광효율이 향상된다.In addition, by forming the p-type local doping layer on the electron blocking layer, it is possible to effectively inject holes while providing an effective blocking effect on electrons. In the p-type local doping layer, the energy level of the holes formed therein increases the tunneling probability of the holes injected from the p-type electrode, thereby increasing the internal quantum efficiency, thereby improving luminous efficiency.
또한,이렇게 형성된 전자 차단층에 p-형 국소 도핑층을 더 형성하는 경우, 발광효율을 보다 향상시킬 수 있다.In addition, when the p-type local doping layer is further formed on the thus formed electron blocking layer, the luminous efficiency may be further improved.
또한, 배리어층의 p-형 국소 도핑층을 상기 활성층에 인접하게 형성하는 경우, 전자 차단층과의 거리가 최대가 됨으로써 전자와 정공이 배리어층에서 최대한 이격되게 되어 오거(Auger) 재결합 확률을 효율적으로 감소시킬 수 있다. In addition, when the p-type local doping layer of the barrier layer is formed adjacent to the active layer, the distance between the electron blocking layer is maximized so that electrons and holes are spaced apart from the barrier layer as much as possible, thereby effectively increasing the Auger recombination probability. Can be reduced.
도 1은 종래 반도체 발광 디바이스의 밴드 구조를 개략적으로 도시한 다이어그램이다.1 is a diagram schematically showing a band structure of a conventional semiconductor light emitting device.
도 2는 본 발명의 예시적인 일 실시예에 의한 반도체 발광 디바이스의 밴드 구조를 개략적으로 도시한 다이어그램이다.2 is a diagram schematically showing a band structure of a semiconductor light emitting device according to an exemplary embodiment of the present invention.
도 3은 본 발명의 예시적인 다른 실시예에 의한 반도체 발광 디바이스의 밴드 구조를 개략적으로 도시한 다이어그램이다.3 is a diagram schematically showing a band structure of a semiconductor light emitting device according to another exemplary embodiment of the present invention.
도 4는 본 발명의 예시적인 또 다른 실시예에 의한 반도체 발광 디바이스의 밴드 구조를 개략적으로 도시한 다이어그램이다.4 is a diagram schematically showing a band structure of a semiconductor light emitting device according to another exemplary embodiment of the present invention.
본 발명은 다양한 변경을 가할 수 있고 여러 가지 형태를 가질 수 있는 바, 특정 실시예들을 도면에 예시하고 본문에 상세하게 설명하고자 한다. 그러나, 이는 본 발명을 특정한 개시 형태에 대해 한정하려는 것이 아니며, 본 발명의 사상 및 기술 범위에 포함되는 모든 변경, 균등물 내지 대체물을 포함하는 것으로 이해되어야 한다.As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.
제1, 제2 등의 용어는 다양한 구성 요소들을 설명하는데 사용될 수 있지만, 상기 구성 요소들은 상기 용어들에 의해 한정되어서는 안된다. 상기 용어들은 하나의 구성 요소를 다른 구성 요소로부터 구별하는 목적으로만 사용된다. 예를 들어, 본 발명의 권리 범위를 벗어나지 않으면서 제1 구성 요소는 제2 구성 요소로 명명될 수 있고, 유사하게 제2 구성 요소도 제1 구성 요소로 명명될 수 있다. Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.
본 출원에서 사용한 용어는 단지 특정한 실시예들을 설명하기 위해 사용된 것으로, 본 발명을 한정하려는 의도가 아니다. 단수의 표현은 문맥상 명백하게 다르게 뜻하지 않는 한, 복수의 표현을 포함한다. 본 출원에서, "포함하다" 또는 "가지다" 등의 용어는 명세서에 기재된 특징, 숫자, 단계, 동작, 구성 요소, 부분품 또는 이들을 조합한 것이 존재함을 지정하려는 것이지, 하나 또는 그 이상의 다른 특징들이나 숫자, 단계, 동작, 구성 요소, 부분품 또는 이들을 조합한 것들의 존재 또는 부가 가능성을 미리 배제하지 않는 것으로 이해되어야 한다.The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "having" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof described in the specification, and that one or more other features It should be understood that it does not exclude in advance the possibility of the presence or addition of numbers, steps, actions, components, parts or combinations thereof.
본 발명에서 막(또는 층) "위에 형성된다", "상에 형성된다"는 의미는 접촉되도록 직접 형성되는 것 이외에, 그 사이에 다른 막 또는 다른 층이 형성될 수도 있음을 의미하여, 막 또는 층 위에 "직접 형성된다"는 의미는 그 사이에 다른 층이 개재되지 못함을 의미한다.In the present invention, the term "formed on" or "formed on" a film (or layer) means that in addition to being directly formed to be in contact, another film or other layer may be formed therebetween, "Formed directly" on a layer means that no other layer is interposed therebetween.
다르게 정의되지 않는 한, 기술적이거나 과학적인 용어를 포함해서 여기서 사용되는 모든 용어들은 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에 의해 일반적으로 이해되는 것과 동일한 의미를 갖는다.Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art.
일반적으로 사용되는 사전에 정의되어 있는 것과 같은 용어들은 관련 기술의 문맥상 가지는 의미와 일치하는 의미를 갖는 것으로 해석되어야 하며, 본 출원에서 명백하게 정의하지 않는 한, 이상적이거나 과도하게 형식적인 의미로 해석되지 않는다.Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art, and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.
이하, 첨부한 도면들을 참조하여, 본 발명의 바람직한 실시예들을 보다 상세하게 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 발명의 예시적인 일 실시예에 의한 반도체 발광 디바이스의 밴드 구조를 개략적으로 도시한 다이어그램이다.2 is a diagram schematically showing a band structure of a semiconductor light emitting device according to an exemplary embodiment of the present invention.
도 2를 참조하면, 본 발명의 예시적인 일 실시예에 의한 반도체 발광 디바이스(100)는 n-형 반도체층(110), 양자 우물층(120), 배리어층(130) 및 p-형 반도체층(150)을 포함한다. 도시되지는 않았으나, 상기 반도체 발광 디바이스(100)는 도 1에서 도시된 전자 차단층(140)을 더 포함할 수도 있다. 상기 n-형 반도체층(110), 상기 양자 우물층(120), 상기 배리어층(130), 상기 p-형 반도체층(150) 및 상기 전자 차단층(140)은 I-VII 화합물 반도체를 포함한다. 보다 상세히, 상기 n-형 반도체층(110), 상기 양자 우물층(120), 상기 배리어층(130), 상기 p-형 반도체층(150) 및 상기 전자 차단층(140)은 각각 CuFCl, CuBrF, CuFI, CuClBr, CuClI, CuBrI, AgFCl, AgFBr, AgFI, AgClBr, AgClI, AgBrI, AuFCl, AuFBr, AuFI, AuClBr, AuClI, AuBrI, CuFClBr, CuFClI, CuFBrI, CuIBrCl, AgFClBr, AgFClI, AgFBrI, AgClBrI, AuFClBr, AuFClI, AuFBrI, or AuClBrI 중, 적어도 어느 하나를 포함할 수 있다.2, a semiconductor light emitting device 100 according to an exemplary embodiment of the present invention may include an n-type semiconductor layer 110, a quantum well layer 120, a barrier layer 130, and a p-type semiconductor layer. And 150. Although not shown, the semiconductor light emitting device 100 may further include the electron blocking layer 140 illustrated in FIG. 1. The n-type semiconductor layer 110, the quantum well layer 120, the barrier layer 130, the p-type semiconductor layer 150, and the electron blocking layer 140 include an I-VII compound semiconductor. do. In more detail, the n-type semiconductor layer 110, the quantum well layer 120, the barrier layer 130, the p-type semiconductor layer 150, and the electron blocking layer 140 are CuFCl and CuBrF, respectively. , CuFI, CuClBr, CuClI, CuBrI, AgFCl, AgFBr, AgFI, AgClBr, AgClI, AgBrI, AuFCl, AuFBr, AuFI, AuClBr, AuClI, AuBrI, CuFClBr, CuFClI, CuFBrI, CuIBrCl, AgFCrB AgICI At least one of AuFClI, AuFBrI, or AuClBrI may be included.
이러한 물질들 중에서, 상기 양자 우물층(120)의 밴드 갭이 가장 작도록 선택하고, 상기 n-형 반도체층(110), 상기 배리어층(130) 및 상기 p-형 반도체층(150)의 밴드 갭이 상기 상기 양자 우물층(120)보다 큰 물질을 선택하여 형성될 수 있다. 또한 상기 n-형 반도체층(110)은 n-형 불순물 (예컨대, 아연 (Zn), 마그네슘 (Mg), 또는 그밖에 유사한 것)을 첨가하고, 상기 p-형 반도체층(150)은 p-형 불순물(예컨대, 산소 (O), 황 (S), 셀레늄 (Se), 또는 그밖에 유사한 것)을 첨가하여 형성될 수 있다.Among these materials, the band gap of the quantum well layer 120 is selected to be the smallest, and the band of the n-type semiconductor layer 110, the barrier layer 130, and the p-type semiconductor layer 150 is selected. The gap may be formed by selecting a material larger than the quantum well layer 120. In addition, the n-type semiconductor layer 110 may add n-type impurities (eg, zinc (Zn), magnesium (Mg), or the like), and the p-type semiconductor layer 150 may be p-type. It can be formed by adding impurities (eg, oxygen (O), sulfur (S), selenium (Se), or the like).
상기 n-형 반도체층(110)은 기판(도시안됨) 위에, MBE (molecular beam epitaxy), MOCVD (metal organic chemical vapor deposition), HVPE (hydride vapor phase epitaxy), ALE (atomic layer epitaxy), 및/또는 그밖에 유사한 것을 통해 형성될 수 있다. 예컨대, 상기 기판은 실리콘(Si) 기판이 사용될 수 있다. 실리콘 기판의 아래의 표 1에서 도시된 것과 같이 격자상수가 구리블렌드 I-VII 화합물 반도체와 유사하여 양질의 박막형성이 가능하다. 보다 바람직하게, n-형 반도체층(110)은 실리콘 기판의 (111) 면 위에 형성될 수 있다.The n-type semiconductor layer 110 is formed on a substrate (not shown), molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), atomic layer epitaxy (ALE), and / Or else similar. For example, the substrate may be a silicon (Si) substrate. As shown in Table 1 below of the silicon substrate, the lattice constant is similar to that of the copper blend I-VII compound semiconductor, thereby enabling a good thin film formation. More preferably, the n-type semiconductor layer 110 may be formed on the (111) surface of the silicon substrate.
격자상수(옹스트롬)Lattice Constant (Angstrom) 밴드갭 에너지 (eV)Bandgap energy (eV)
SiSi 5.435.43 1.1 (indirect)1.1 (indirect)
CuClCuCl 5.425.42 3.3993.399
CuBrCuBr 5.685.68 2.912.91
CuICuI 6.056.05 2.952.95
사파이어와 같은 더 값비싼 종래 기판 재료와 비교하여 상대적으로 저렴한 실리콘 기판 사용될 수도 있는데, 이는 그의 격자 상수가, 상이한 결정 구조를 가지긴 했지만 Ⅰ- Ⅶ 화합물 반도체의 격자 상수에 가깝기 때문이다. 예를 들면, 실리콘이 다이아몬드 구조를 갖는 것으로 알려져 있는 한편, CuCl은 다이아몬드 구조를 갖는다. 특히, 실리콘 기판의 (111) 면은, 기판 상에 스택 (stack) 될 수도 있는, CuCl의 결정 구조에 적합할 수도 있으므로 반도체 발광 디바이스(100)를 제조하는데 사용될 수도 있다. 다른 실시형태들에서, 기판은 사파이어, 벌크 갈륨 질화물 (bulk gallium nitride), 또는 그밖에 유사한 것이 사용되어질 수도 있다. Relatively inexpensive silicon substrates may also be used compared to more expensive conventional substrate materials such as sapphire, since their lattice constants are close to those of the I-V compound semiconductors, although they have different crystal structures. For example, silicon is known to have a diamond structure, while CuCl has a diamond structure. In particular, the (111) face of the silicon substrate may be used to fabricate the semiconductor light emitting device 100 as it may be suitable for the crystal structure of CuCl, which may be stacked on the substrate. In other embodiments, the substrate may be used with sapphire, bulk gallium nitride, or the like.
상기 양자 우물층(120)은, MBE (molecular beam epitaxy), MOCVD (metal organic chemical vapor deposition), HVPE (hydride vapor phase epitaxy), ALE (atomic layer epitaxy), 및/또는 그밖에 유사한 것을 통해 상기 n-형 반도체층(110) 상부에 형성될 수 있다.The quantum well layer 120 may be formed through the n-, through molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), atomic layer epitaxy (ALE), and / or the like. The semiconductor layer 110 may be formed on the semiconductor semiconductor layer 110.
상기 배리어층(130)은, MBE (molecular beam epitaxy), MOCVD (metal organic chemical vapor deposition), HVPE (hydride vapor phase epitaxy), ALE (atomic layer epitaxy), 및/또는 그밖에 유사한 것을 통해 상기 양자 우물층(120) 상부에 형성될 수 있다.The barrier layer 130 may be formed through the quantum well layer through molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), atomic layer epitaxy (ALE), and / or the like. 120 may be formed on top.
상기 p-형 반도체층(150)은, MBE (molecular beam epitaxy), MOCVD (metal organic chemical vapor deposition), HVPE (hydride vapor phase epitaxy), ALE (atomic layer epitaxy), 및/또는 그밖에 유사한 것을 통해 상기 배리어층(130) 상부에 형성될 수 있다.The p-type semiconductor layer 150 may be formed through molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), atomic layer epitaxy (ALE), and / or the like. It may be formed on the barrier layer 130.
Ⅰ- Ⅶ 화합물 반도체를 포함하는 양자 우물층(120)은 상대적으로 큰 여기자 결합 에너지 (exciton binding energy), 예를 들면, Ⅲ 족 질화물의 것들에 비해 적어도 2배 더 큰 여기자 결합 에너지를 가질 수 있는데 이로 인해서 양자 효율을 향상시킬 수 있다. 특히, 큰 여기자 결합 에너지를 갖는 Ⅰ- Ⅶ 화합물 반도체들은 예를 들면, 가시 스펙트럼의 청색 영역의 광을 방출하는 발광 디바이스들에서 바람직한 강한 광 천이 (optical transition) 에 적합할 수도 있다. 여기자 결합 에너지는, 반대 전하를 갖는, 정공과 전자들의 상호작용의 척도이고, 정공-전자 재결합 프로세스의 강도를 예측하기 위해 사용될 수도 있다. 예를 들면, CuBr은 약 108meV의 여기자 결합 에너지를 갖는 것으로 알려져 있는데, 이는 ZnO의 여기자 결합 에너지 보다 더 높다. 결과적으로, Ⅰ- Ⅶ 화합물 반도체 기반 발광 디바이스들은 Ⅲ 족 질화물 또는 ZnO 기반 발광 디바이스들과 같은 종래 넓은 밴드갭 반도체들보다 더 큰 광 이득을 갖는다.The quantum well layer 120 including the I-V compound semiconductor may have a relatively large exciton binding energy, for example, an exciton binding energy at least twice as large as those of group III nitride. This can improve quantum efficiency. In particular, I-VIII compound semiconductors with large exciton binding energies may be suitable for strong optical transitions, for example, which are desirable in light emitting devices that emit light in the blue region of the visible spectrum. The exciton binding energy is a measure of the interaction of holes and electrons, with opposite charges, and may be used to predict the strength of the hole-electron recombination process. For example, CuBr is known to have an exciton binding energy of about 108 meV, which is higher than the exciton binding energy of ZnO. As a result, the I-VIII compound semiconductor based light emitting devices have greater optical gain than conventional wide bandgap semiconductors such as group III nitride or ZnO based light emitting devices.
한편, 상기 배리어층(130)에는, 하나 이상의 p-형 국소 도핑층(131)이 형성된다. 이러한 p-형 국소 도핑층(131)은 앞서 설명된 p-형 불순물을 포함하도록 원자단위 두께로 단결정 시킨 박막이다.Meanwhile, at least one p-type local doping layer 131 is formed on the barrier layer 130. The p-type local doping layer 131 is a thin film single crystal having an atomic unit thickness to include the p-type impurities described above.
상기 p-형 국소 도핑층(131)은 상기 양자 우물층(120)에 인접하게 형성될 수 있다. 상기 배리어층(130)이 양자 우물층(120)에 인접하게 형성되는 경우, 양장 우물층(120)의 장벽 높이를 증가시켜, 전자가 양자 우물층(120)으로 부터 배리어층(130)으로 전이되는 확률을 감소시킬 수 있으며, 또한 p-형 국소 도핑층(131)은 피에조 효과와 자발분극으로 인한 양자 우물층(120)에서의 내부 전계를 감소시킴으로써 내부 양자효율을 증가시킬 수 있다.The p-type local doping layer 131 may be formed adjacent to the quantum well layer 120. When the barrier layer 130 is formed adjacent to the quantum well layer 120, the barrier height of the well wall 120 is increased to transfer electrons from the quantum well layer 120 to the barrier layer 130. In addition, the p-type local doping layer 131 may increase the internal quantum efficiency by reducing the internal electric field in the quantum well layer 120 due to the piezo effect and spontaneous polarization.
도 3은 본 발명의 예시적인 다른 실시예에 의한 반도체 발광 디바이스의 밴드 구조를 개략적으로 도시한 다이어그램이다. 도 3에서의 설명은 앞서, 도 2를 참조한 실시예에 대한 설명에서 중복되는 부분은 생략한다.3 is a diagram schematically showing a band structure of a semiconductor light emitting device according to another exemplary embodiment of the present invention. In the description of FIG. 3, the overlapping part of the description of the embodiment with reference to FIG. 2 is omitted.
도 3을 참조하면, 본 발명의 예시적인 다른 실시예에 의한 반도체 발광 디바이스(100)는 n-형 반도체층(110), 양자 우물층(120), 배리어층(130), 전자 차단층(140) 및 p-형 반도체층(150)을 포함한다.Referring to FIG. 3, a semiconductor light emitting device 100 according to another exemplary embodiment of the present invention may include an n-type semiconductor layer 110, a quantum well layer 120, a barrier layer 130, and an electron blocking layer 140. ) And the p-type semiconductor layer 150.
상기 n-형 반도체층(110)은 기판(도시안됨) 위에 형성될 수 있다.The n-type semiconductor layer 110 may be formed on a substrate (not shown).
상기 양자 우물층(120)은, 상기 n-형 반도체층(110) 상부에 형성된다. 상기 배리어층(130)은 상기 양자 우물층(120) 상부에 형성된다.The quantum well layer 120 is formed on the n-type semiconductor layer 110. The barrier layer 130 is formed on the quantum well layer 120.
상기 전자 차단층(140)은 상기 배리어층(130) 상부에 형성된다. 상기 p-형 반도체층(150)은 상기 전자 차단층(140) 상부에 형성된다.The electron blocking layer 140 is formed on the barrier layer 130. The p-type semiconductor layer 150 is formed on the electron blocking layer 140.
한편, 상기 전자 차단층(140)에는 하나 이상의 p-형 국소 도핑층(141)이 형성된다. 이와 같이, 전자 차단층(141)에 p-형 국소 도핑층(141)을 형성하는 경우, 전자에 대한 효과적인 블로킹 효과를 주면서, 정공에 대해서는 효과적인 투과를 가능하게 한다. 즉, p-형 국소 도핑층(141) 내에 형성된 정공의 에너지 준위가 p-형 전극에서 주입된 정공의 터널링 확률을 높여 주게 되어 내부 양자 효율을 증가시킬 수 있다.Meanwhile, at least one p-type local doping layer 141 is formed on the electron blocking layer 140. As described above, when the p-type local doping layer 141 is formed on the electron blocking layer 141, the P-type local doping layer 141 is provided with an effective blocking effect on electrons, and enables effective transmission of holes. That is, the energy level of the holes formed in the p-type local doping layer 141 increases the tunneling probability of the holes injected from the p-type electrode, thereby increasing the internal quantum efficiency.
도 4는 본 발명의 예시적인 또 다른 실시예에 의한 반도체 발광 디바이스의 밴드 구조를 개략적으로 도시한 다이어그램이다. 도 4에서 도시된 반도체 발광 디바이스는 도 3에서 도시된 반도체 발광 디바이스에 도 2에서 도시된 p-형 국소 도핑층(131)을 추가적으로 형성하였다. 그러나, 이와 같이 배리어층(130)에 p-형 국소 도핑층(131)을 형성하고, 전자 차단층(140)에 p-형 국소 도핑층(141)을 형성하면, 앞선 효과들 뿐 아니라, 보다 상승적인 효과를 기대할 수 있다. 앞선 설명들과 반복되는 설명은 생략한다.4 is a diagram schematically showing a band structure of a semiconductor light emitting device according to another exemplary embodiment of the present invention. The semiconductor light emitting device shown in FIG. 4 additionally forms the p-type local doping layer 131 shown in FIG. 2 in the semiconductor light emitting device shown in FIG. However, if the p-type local doping layer 131 is formed on the barrier layer 130 and the p-type local doping layer 141 is formed on the electron blocking layer 140 as described above, not only the foregoing effects, but also the A synergistic effect can be expected. The foregoing descriptions and repeated descriptions are omitted.
도 4를 참조하면, 본 발명의 예시적인 다른 실시예에 의한 반도체 발광 디바이스(100)는 n-형 반도체층(110), 양자 우물층(120), 배리어층(130), 전자 차단층(140) 및 p-형 반도체층(150)을 포함한다. 상기 배리어층(130)에는, 하나 이상의 p-형 국소 도핑층(131)이 형성된다. 상기 p-형 국소 도핑층(131)은 상기 양자 우물층(120)에 인접하게 형성될 수 있다. 또한, 상기 배리어층(130)에 형성되 상기 p-형 국소 도핑층(131)은 상기 전자 차단층(140)과 10nm이상 이격될 수 있다. 또한, 상기 전자 차단층(140)에는, 하나 이상의 p-형 국소 도핑층(141)이 형성된다.4, a semiconductor light emitting device 100 according to another exemplary embodiment of the present invention may include an n-type semiconductor layer 110, a quantum well layer 120, a barrier layer 130, and an electron blocking layer 140. ) And the p-type semiconductor layer 150. At least one p-type local doping layer 131 is formed on the barrier layer 130. The p-type local doping layer 131 may be formed adjacent to the quantum well layer 120. In addition, the p-type local doping layer 131 formed on the barrier layer 130 may be spaced apart from the electron blocking layer 140 by 10 nm or more. In addition, at least one p-type local doping layer 141 is formed on the electron blocking layer 140.
국소 도핑에 의해 형성된 포텐셜을 다음의 수학식 1과 같이 주어진다. [D. Ahn, Phys. Rev. 48, 7981 (1993)]. The potential formed by local doping is given by Equation 1 below. [D. Ahn, Phys. Rev. 48, 7981 (1993).
Figure PCTKR2015009404-appb-M000001
Figure PCTKR2015009404-appb-M000001
여기서 PS는 국소 도핑층의 표면 전하 밀도이다. Hole의 에너지 준위는 다음의 수학식 2와 같은 슈뢰딩거 방정식에서 구하면 된다. Where P S is the surface charge density of the local doped layer. The energy level of the hole can be obtained from Schrödinger's equation as shown in Equation 2 below.
Figure PCTKR2015009404-appb-M000002
Figure PCTKR2015009404-appb-M000002
여기서
Figure PCTKR2015009404-appb-I000001
이다.
here
Figure PCTKR2015009404-appb-I000001
to be.
오거(Auger) 재결합의 감소를 위해 전자와 hole 분포의 최대값을 분리 시킬 수 있는 구조는 도 4와 같다. The structure that can separate the maximum value of the electron and hole distribution in order to reduce the Auger recombination is shown in FIG.
배리어층(130)에 형성된 p-형 국소 도핑층(131)은 내부전계를 상쇄시키는 역할을 수행하기 때문에 양자 우물층(120)에는 가깝게 (마지막 배리어 층 바로 다음) 하지만 전자 차단층(140)에서는 거리를 두고 위치 시킨다 (10nm 이상). 전자 차단층(140) 때문에 p형 반도체층(150) 영역에서 전자는 전자 차단층(140) 바로 직전이 최대 밀도가 형성될 것이다. 반면 배리어층(130)에 형성된 p-형 국소 도핑층(131)으로 인해 정공 분포의 최대는 양자 우물층(120)의 마지막 배리어 바로 다음에 형성된 p-형 국소 도핑층(131)과 전자 차단층(140)에 형성된 p-형 국소 도핑층(141)에서 형성될 것으로 예상되어 오거(Auger) 재결합 확률을 효과적으로 감소시킬 수 있다. Since the p-type local doping layer 131 formed on the barrier layer 130 serves to cancel the internal electric field, the p-type local doping layer 131 is close to the quantum well layer 120 (just after the last barrier layer), but the electron blocking layer 140 Place at a distance (10 nm or more). Due to the electron blocking layer 140, the electrons in the p-type semiconductor layer 150 may have a maximum density immediately before the electron blocking layer 140. On the other hand, due to the p-type local doping layer 131 formed on the barrier layer 130, the maximum hole distribution is due to the p-type local doping layer 131 and the electron blocking layer formed immediately after the last barrier of the quantum well layer 120. It is expected to be formed in the p-type local doping layer 141 formed at 140 to effectively reduce the Auger recombination probability.
앞서 설명한 본 발명의 상세한 설명에서는 본 발명의 바람직한 실시예들을 참조하여 설명하였지만, 해당 기술분야의 숙련된 당업자 또는 해당 기술분야에 통상의 지식을 갖는 자라면 후술될 특허청구범위에 기재된 본 발명의 사상 및 기술 영역으로부터 벗어나지 않는 범위 내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다.In the detailed description of the present invention described above with reference to the preferred embodiments of the present invention, those skilled in the art or those skilled in the art having ordinary skill in the art will be described in the claims to be described later It will be understood that various modifications and variations can be made in the present invention without departing from the scope of the present invention.

Claims (12)

  1. I-VII 화합물 반도체를 포함하는 n-형 반도체층;An n-type semiconductor layer comprising an I-VII compound semiconductor;
    상기 n-형 반도체층 상부에 형성되고, I-VII 화합물 반도체를 포함하는 양자 우물층;A quantum well layer formed on the n-type semiconductor layer and including an I-VII compound semiconductor;
    상기 양자 우물층 상부에 형성되고, I-VII 화합물 반도체를 포함하는 배리어층; 및A barrier layer formed on the quantum well layer and including an I-VII compound semiconductor; And
    상기 배리어층 상부에 형성되고, I-VII 화합물 반도체를 포함하는 p-형 반도체층을 포함하고,A p-type semiconductor layer formed on the barrier layer and including an I-VII compound semiconductor,
    상기 배리어층에는, 하나 이상의 p-형 국소 도핑층이 형성된 것을 특징으로 하는 반도체 발광 디바이스.At least one p-type local doped layer is formed in the barrier layer.
  2. 제1항에 있어서,The method of claim 1,
    상기 p-형 국소 도핑층은 상기 양자 우물층에 인접하도록 형성된 것을 특징으로 하는 반도체 발광 디바이스.And the p-type local doped layer is formed adjacent to the quantum well layer.
  3. 제1항에 있어서,The method of claim 1,
    상기 n-형 반도체층, 상기 양자 우물층, 상기 배리어층 및 상기 p-형 반도체층은 각각 CuFCl, CuBrF, CuFI, CuClBr, CuClI, CuBrI, AgFCl, AgFBr, AgFI, AgClBr, AgClI, AgBrI, AuFCl, AuFBr, AuFI, AuClBr, AuClI, AuBrI, CuFClBr, CuFClI, CuFBrI, CuIBrCl, AgFClBr, AgFClI, AgFBrI, AgClBrI, AuFClBr, AuFClI, AuFBrI, or AuClBrI 중, 적어도 어느 하나를 포함하는 것을 특징으로 하는 반도체 발광 디바이스.The n-type semiconductor layer, the quantum well layer, the barrier layer and the p-type semiconductor layer are CuFCl, CuBrF, CuFI, CuClBr, CuClI, CuBrI, AgFCl, AgFBr, AgFI, AgClBr, AgClI, AgBrI, AuFCl, A device comprising at least one semiconductor light emitting device comprising at least one of AuFBr, AuFI, AuClBr, AuClI, AuBrI, CuFClBr, CuFClI, CuFBrI, CuIBrCl, AgFClBr, AgFClI, AgFBrI, AgClBrI, AuFClBr, AuFClI, AuFBrI, or AuClBrI.
  4. 제1항에 있어서,The method of claim 1,
    상기 배리어층과 상기 p-형 반도체층 사이에 형성된 하나 이상의 전자 차단층을 더 포함하는 것을 특징으로 하는 반도체 발광 디바이스.And at least one electron blocking layer formed between the barrier layer and the p-type semiconductor layer.
  5. 제4항에 있어서,The method of claim 4, wherein
    상기 배리어층에 형성되는 상기 p-형 국소 도핑층은 상기 전자 차단층과 10nm이상 이격된 것을 특징으로 하는 반도체 발광 디바이스.And the p-type local doped layer formed on the barrier layer is spaced apart from the electron blocking layer by 10 nm or more.
  6. 제4항에 있어서,The method of claim 4, wherein
    상기 전자 차단층에는, 하나 이상의 p-형 국소 도핑층이 형성된 것을 특징으로 하는 반도체 발광 디바이스.At least one p-type local doped layer is formed in the electron blocking layer.
  7. 제4항에 있어서,The method of claim 4, wherein
    상기 전자 차단층은 CuFCl, CuBrF, CuFI, CuClBr, CuClI, CuBrI, AgFCl, AgFBr, AgFI, AgClBr, AgClI, AgBrI, AuFCl, AuFBr, AuFI, AuClBr, AuClI, AuBrI, CuFClBr, CuFClI, CuFBrI, CuIBrCl, AgFClBr, AgFClI, AgFBrI, AgClBrI, AuFClBr, AuFClI, AuFBrI, or AuClBrI 중, 적어도 어느 하나를 포함하는 것을 특징으로 하는 반도체 발광 디바이스.The electron blocking layer is CuFCl, CuBrF, CuFI, CuClBr, CuClI, CuBrI, AgFCl, AgFBr, AgFI, AgClBr, AgClI, AgBrI, AuFCl, AuFBr, AuFI, AuClBr, AuClI, AuBrI, CuFClBr, CuBrIFC, CuBBI And at least one of AgFClI, AgFBrI, AgClBrI, AuFClBr, AuFClI, AuFBrI, or AuClBrI.
  8. 기판;Board;
    상기 기판 상에 형성되고, I-VII 화합물 반도체를 포함하는 n-형 반도체층;An n-type semiconductor layer formed on the substrate and comprising an I-VII compound semiconductor;
    상기 n-형 반도체층 상부에 형성되고, I-VII 화합물 반도체를 포함하는 양자 우물층;A quantum well layer formed on the n-type semiconductor layer and including an I-VII compound semiconductor;
    상기 양자 우물층 상부에 형성되고, I-VII 화합물 반도체를 포함하는 배리어층;A barrier layer formed on the quantum well layer and including an I-VII compound semiconductor;
    상기 배리어층 상부에 형성되고, I-VII 화합물 반도체를 포함하는 하나 이상의 전자 차단층; 및At least one electron blocking layer formed on the barrier layer and including an I-VII compound semiconductor; And
    상기 전자 차단층 상부에 형성되고, I-VII 화합물 반도체를 포함하는 p-형 반도체층을 포함하고,A p-type semiconductor layer formed on the electron blocking layer and including an I-VII compound semiconductor,
    상기 전자 차단층에는, 하나 이상의 p-형 국소 도핑층이 형성된 것을 특징으로 하는 반도체 발광 디바이스.At least one p-type local doped layer is formed in the electron blocking layer.
  9. 제8항에 있어서,The method of claim 8,
    상기n-형 반도체층, 상기 양자 우물층, 상기 배리어층 및 상기 p-형 반도체층은 각각 CuFCl, CuBrF, CuFI, CuClBr, CuClI, CuBrI, AgFCl, AgFBr, AgFI, AgClBr, AgClI, AgBrI, AuFCl, AuFBr, AuFI, AuClBr, AuClI, AuBrI, CuFClBr, CuFClI, CuFBrI, CuIBrCl, AgFClBr, AgFClI, AgFBrI, AgClBrI, AuFClBr, AuFClI, AuFBrI, or AuClBrI 중, 적어도 어느 하나를 포함하는 것을 특징으로 하는 반도체 발광 디바이스.The n-type semiconductor layer, the quantum well layer, the barrier layer and the p-type semiconductor layer are CuFCl, CuBrF, CuFI, CuClBr, CuClI, CuBrI, AgFCl, AgFBr, AgFI, AgClBr, AgClI, AgBrI, AuFCl, A device comprising at least one semiconductor light emitting device comprising at least one of AuFBr, AuFI, AuClBr, AuClI, AuBrI, CuFClBr, CuFClI, CuFBrI, CuIBrCl, AgFClBr, AgFClI, AgFBrI, AgClBrI, AuFClBr, AuFClI, AuFBrI, or AuClBrI.
  10. 제8항에 있어서,The method of claim 8,
    상기 배리어층에는, 하나 이상의 p-형 국소 도핑층이 형성된 것을 특징으로 하는 반도체 발광 디바이스.At least one p-type local doped layer is formed in the barrier layer.
  11. 제10항에 있어서,The method of claim 10,
    상기 배리어층에 형성된 상기 p-형 국소 도핑층은 상기 양자 우물층에 인접하게 형성된 것을 특징으로 하는 반도체 발광 디바이스.And the p-type local doped layer formed in the barrier layer is formed adjacent to the quantum well layer.
  12. 제10항에 있어서,The method of claim 10,
    상기 배리어층에 형성되는 상기 p-형 국소 도핑층은 상기 전자 차단층과 10nm이상 이격된 것을 특징으로 하는 반도체 발광 디바이스.And the p-type local doped layer formed on the barrier layer is spaced apart from the electron blocking layer by 10 nm or more.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111063753A (en) * 2019-10-31 2020-04-24 厦门大学 AlGaN-based deep ultraviolet LED epitaxial structure of Mg-doped quantum well and preparation method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120057646A (en) * 2009-11-18 2012-06-05 서울시립대학교 산학협력단 Copper blend i-vii compound semiconductor light-emitting devices
JP2013168680A (en) * 2013-05-28 2013-08-29 Toshiba Corp Semiconductor light-emitting element and method of manufacturing the same
KR20140003124A (en) * 2012-06-29 2014-01-09 인텔렉추얼디스커버리 주식회사 Semiconductor light generating device
KR20140003125A (en) * 2012-06-29 2014-01-09 인텔렉추얼디스커버리 주식회사 Semiconductor light generating device
KR20150010146A (en) * 2013-07-18 2015-01-28 엘지이노텍 주식회사 Light emitting device and lighting system

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120057646A (en) * 2009-11-18 2012-06-05 서울시립대학교 산학협력단 Copper blend i-vii compound semiconductor light-emitting devices
KR20140003124A (en) * 2012-06-29 2014-01-09 인텔렉추얼디스커버리 주식회사 Semiconductor light generating device
KR20140003125A (en) * 2012-06-29 2014-01-09 인텔렉추얼디스커버리 주식회사 Semiconductor light generating device
JP2013168680A (en) * 2013-05-28 2013-08-29 Toshiba Corp Semiconductor light-emitting element and method of manufacturing the same
KR20150010146A (en) * 2013-07-18 2015-01-28 엘지이노텍 주식회사 Light emitting device and lighting system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111063753A (en) * 2019-10-31 2020-04-24 厦门大学 AlGaN-based deep ultraviolet LED epitaxial structure of Mg-doped quantum well and preparation method thereof

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