WO2017030054A1 - Memory device - Google Patents

Abstract

The present invention makes it possible to easily realize the extension of a network function at low cost and with low power consumption on the occasion of network functions virtualization (NFV) or network commoditization. A poco-watcher 11 configured from a single chip has a functional configuration including a route control unit 31, a band control unit 32, a traffic monitoring unit 33, a buffer unit 34, and an access control unit 35 so that at least route control, band control, traffic monitoring, buffering, and access control among network functions can be exhibited.

Description

Memory equipment

The present invention relates to a memory device.

Conventionally, personal computers (hereinafter abbreviated as “PC” as appropriate) and servers are IT devices that are manufactured and sold by limited manufacturers. However, in recent years, components used inside the equipment, such as processors and memories, have become general-purpose, so that it has been transformed into IT equipment that anyone can assemble.
In addition, PCs and servers are generally adopting an open platform that allows anyone to become a developer or a technical proposer by commoditizing OS and application software.
A system in which the configuration of the internal specifications is visualized even if the housing of the apparatus is different, such as a system such as a current PC or server, is called “White Box” or the like.

Conventionally, network devices such as routers and switches (see, for example, Patent Documents 1 to 3) have also been special IT equipment markets that are dominated by only a limited number of manufacturers. However, the term NFV (Network Functions Virtualization) has recently appeared. As shown, the recent trends are the same as those of PCs and servers.
For example, low-cost enterprise models are becoming increasingly popular as open platforms that anyone can manufacture due to the commoditization of processors and memory.

JP 2013-38536 A JP 2012-27998 A Japanese Patent No. 4934825

However, when making NFV and network commoditized, it is necessary to expand network functions, for example, route control with search.
In this case, as shown in FIG. 15, a plurality of expensive components with high power consumption such as a special memory are required.

FIG. 15 is a block diagram illustrating a configuration example of a conventional information processing system for realizing a network function.
For example, the conventional information processing system shown in FIG. 15 is mounted on a substrate built in a server or a PC.
The conventional information processing system includes a network processor 12, a CPU 13, a plurality of (four in the example of FIG. 15) communication devices 14a to 14d, a TCAM 501, an SRAM 502, and a DRAM 503.
In the conventional information processing system, when the function of the network processor 12 is expanded, various memories are required. For example, the TCAM 501 is used for realizing the path control and traffic monitoring, the SRAM 502 is used for the path control, bandwidth control, and traffic monitoring, and the DRAM 503 capable of a large capacity is used as a buffer.
These TCAM 501, SRAM 502, and DRAM 503 are expensive components that consume a large amount of power.

The present invention has been made in view of such a situation, and an object of the present invention is to make it possible to easily extend network functions at low cost and with low power consumption when commoditizing NFV and networks.

A memory device of one embodiment of the present invention includes:
A memory device composed of a single chip,
Among network functions, at least routing control, bandwidth control, traffic monitoring, buffer, and access control function.
It is a memory device.

Here, the memory device
A search unit that includes a first memory unit, and executes a search operation for referring to an input search key for data stored in the first memory unit;
A statistical information processing unit having a second memory unit that associates an address of the first memory unit with each search key hit in the search unit and stores statistical information of the address;
An arithmetic unit that updates the statistical information every time it is hit by the search unit;
Can be provided.

The search unit has a function of changing a bit width of a search key;
be able to.

The search unit has a function of outputting a determination signal indicating whether writing of information is successful or unsuccessful,
be able to.

The search unit selectively executes the access control of a white list method and the access control of a black list method.
be able to.

In an information processing system including individual devices that constitute a network and a network controller that controls the individual devices, the memory device is provided by being connected to each individual device,
The memory device is
A function of monitoring the traffic of connected ones of the individual devices to acquire data and transmitting it to the network controller;
When the network controller analyzes the data of the individual device and generates and transmits control information to the individual device, the network controller receives the control information, and based on the control information, receives the control information of the individual device. The ability to control what is connected,
Can be provided.

The memory device is
A memory section;
A network function unit for exerting the network function;
A selector unit that switches between a first route between the memory unit and the network function unit and a second route of the memory unit;
Can be provided.

The selector unit is realized by at least one of a metal mask and an address key.
Can be.

The network function unit is configured by a comparator group for a test mode for the memory unit.
Can be.

According to the present invention, network functions can be easily expanded with low cost and low power consumption when commoditizing NFV and networks.

It is a block diagram which shows the structural example of the information processing system which concerns on one Embodiment of this invention. It is a block diagram which shows the example of a structure of the information processing system which concerns on one Embodiment of this invention, Comprising: The example different from the example of FIG. FIG. 3 is a functional block diagram for realizing a network function among the functions of the pocowatcher of the information processing system of FIG. 1 or FIG. 2. FIG. 3 is a functional block diagram for realizing a mining function among the functions of the pocowatcher of the information processing system of FIG. 1 or FIG. 2. Of the hardware configuration of the pocowatcher of the information processing system in FIG. 1 or FIG. 2, the hardware configuration that operates when the path control unit or traffic monitoring unit in FIG. 3 or the clustering unit or ranking unit in FIG. 4 functions. It is a figure which shows an example. Of the hardware configuration of the pocowatcher of the information processing system in FIG. 1 or FIG. 2, the hardware configuration that operates when the path control unit or traffic monitoring unit in FIG. 3 or the clustering unit or ranking unit in FIG. 4 functions. FIG. 6 is a diagram illustrating an example different from FIG. 5. FIG. 7 shows an enlarged view of a memory cell array, a sense amplifier & selector, and a calculation unit in the pocowatcher in the example of FIG. 6. It is a schematic diagram for demonstrating the router function which combined each function of the path | route control part and buffer part of FIG. FIG. 7 is a diagram illustrating an example of a hardware configuration of a search engine of the pocowatcher in the information processing system of FIG. 1 or 2, and illustrates an example different from FIGS. 5 and 6. FIG. 10 is a diagram illustrating an example of a hardware configuration of a search engine of the pocowatcher in the information processing system of FIG. 1 or 2, and is a diagram illustrating an example different from FIGS. It is an information processing system concerning one embodiment of the present invention, and is a figure showing an example of composition of an information processing system using two search engines. It is a figure which shows the operation example of the information processing system of FIG. FIG. 3 is a block diagram illustrating an example of a configuration of an information processing system according to an embodiment of the present invention, which is different from the examples of FIGS. 1 and 2. FIG. 14 is a block diagram illustrating an example of a configuration of an information processing system according to an embodiment of the present invention, which is different from the examples of FIGS. 1, 2, and 13. It is a block diagram which shows the structural example of the conventional information processing system for implement | achieving a network function. It is a block diagram which shows another structural example of the pocowatcher of the information processing system of FIG. 1 or FIG. It is a figure which shows the state of the connection of the pocowatcher of FIG. It is a comparison figure of the structural example of the conventional information processing system for implement | achieving a network function, and the structural example of the information processing system containing the pocowatcher of FIG.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram illustrating a configuration example of an information processing system according to an embodiment of the present invention.
For example, the information processing system shown in FIG. 1 is mounted on a substrate built in a server or a PC.
The information processing system includes a pocowatcher 11 as an embodiment of an electronic apparatus to which the present invention is applied, a network processor 12, a CPU 13, and a plurality (four in the example of FIG. 1) of communication devices 14a to 14d. It has.

When expanding the function of the network processor 12, conventionally, various memories are required as described above. For example, in the conventional example of FIG. 15 described above, the TCAM 501 is used for realizing the path control and traffic monitoring, the SRAM 502 is used for the path control, bandwidth control, and traffic monitoring, and the DRAM 503 capable of a large capacity as a buffer is provided. It was used.
On the other hand, in the information processing system according to the present embodiment, the pocowatcher 11 is configured by a single chip capable of a DRAM process, and therefore can cope with a large-capacity buffer. For this reason, as shown in FIG. 1, the function of the network processor 12 can be expanded only by connecting the pocowatcher 11 to the network processor 12.

The configuration of the information processing system is not particularly limited to the configuration of FIG. 1 as long as the network processor 12 and the pocowatcher 11 can communicate with each other.

FIG. 2 is a block diagram showing an example of the configuration of the information processing system according to the embodiment of the present invention, which is an example different from the example of FIG.
In the information processing system of the example of FIG. 2A, communication devices 14a to 14d are connected to the pocowatcher 11 as a difference from the example of FIG.
In the information processing system of the example of FIG. 2B, a communication device 14e connected to a router or the like (not shown) is connected to the poco watcher 11 as a difference from the example of FIG.
2A and 2B is merely an example, and for example, although not shown, two pocowatchers 11 are prepared, the communication device 14e and the network processor 12, and the network processor. The pocowatcher 11 may be inserted simultaneously between the communication device 12 and the communication devices 14a to 14d.

FIG. 3 is a functional block diagram for realizing a network function among the functions of the pocowatcher 11.
As shown in FIG. 3, in the pocowatcher 11, a path control unit 31, a bandwidth control unit 32, a traffic monitoring unit 33, a buffer unit 34, an access control unit 35, and a main control unit 36 function. .

The route control unit 31 realizes the same function as the route control realized by the conventional TCAM and HS SRAM.
The bandwidth control unit 32 realizes the same function as the bandwidth control realized by the conventional HS SRAM and LLDRAM.
The traffic monitoring unit 33 realizes the same function as the traffic monitoring realized by the conventional TCAM, HS SRAM counter, and ALU.
The buffer unit 34 has a function equivalent to that of a conventional DRAM and realizes a buffer.
The access control unit 35 realizes the same function as the access control that has been realized conventionally.
The main control unit 36 performs overall control of the pocowatcher 11 including the path control unit 31 to the access control unit 35.

FIG. 4 is a functional block diagram for realizing the mining function among the functions of the pocowatcher 11.
As shown in FIG. 4, in the pocowatcher 11, a clustering unit 37, a ranking unit 38, and a mining unit 39 function in addition to the main control unit 36 described above.

The clustering unit 37 realizes a function equivalent to the clustering control that has been conventionally realized.
The ranking unit 38 realizes a function equivalent to the ranking control that has been conventionally realized.
The mining unit 39 realizes the same function as the mining that has been realized conventionally.

FIG. 5 shows an example of a hardware configuration that operates when the path control unit 31 or the traffic monitoring unit 33 in FIG. 3 or the clustering unit 37 or the ranking unit 38 in FIG. 4 functions among the hardware configurations of the pocowatcher 11. Is shown.
6 illustrates an example of a hardware configuration that operates when the path control unit 31 or the traffic monitoring unit 33 in FIG. 3 or the clustering unit 37 or the ranking unit 38 in FIG. 4 functions among the hardware configurations of the pocowatcher 11. However, an example different from the example of FIG. 5 is shown.
In order to clearly distinguish the example of FIG. 5 from the example of FIG. 6, hereinafter, the pocowatcher 11 of the example of FIG. 5 is particularly referred to as “pocowatcher 11a”, and the pocowatcher 11 of the example of FIG. This is called “Pocowatcher 11b”.

5 includes a search unit 51a, a statistical information processing unit 52a, and a calculation unit 53a.

The search unit 51 a is a so-called search engine, and includes a hash generator 61, a memory unit 62, and a comparator 63.
Here, the search is an operation of referring to a desired search key (data string to be searched) with respect to data stored in a storage device such as a memory (memory unit 62 in the example of FIG. 5). Say.
A case where a search key is found in the memory unit 62 is defined as a hit (Search hit), and a case where the search key cannot be found is defined as a miss (Search miss).
After the search hit, an action (or rule) is output from the memory unit 62.
Specifically, for example, it is assumed that the search key 55_23_75_A4_53_10_89_bd is stored in the memory unit 62 and PortB (the output destination is set to the communication device 14b) is defined as an action when a hit occurs. In this case, when the search key 55_23_75_A4_53_10_89_bd is input to the search unit 51a, the search key is searched from the memory unit 62 and hits, so Port B is output as an action.

Such a search operation is necessary when executing various applications that cause the path control unit 31 or the traffic monitoring unit 33 in FIG. 3 or the clustering unit 37 or the ranking unit 38 in FIG. 4 to function.
In a conventional hardware configuration with a normal memory (a configuration with only the memory unit 62 in FIG. 5), the search operation (instruction) cannot be executed. Therefore, conventionally, when searching for a network IP address or the like, a search operation is performed using a special memory called TCAM 501 (FIG. 14). The TCAM 501 is provided with an address comparator on the memory cell side, and performs a search operation by performing a process of comparing the data stored in the memory cell with the search key in all the memory cells.
The problem in the search using the TCAM 501 is that the power consumption is extremely large because all memory cells are accessed in parallel.

Therefore, in the present embodiment, a search unit 51a capable of executing a search operation is provided in the single chip called the pocowatcher 11 so that the search operation can be executed without providing a special memory such as the TCAM 501.

Here, in the search unit 51a, the memory unit 62 has the same hardware configuration as that of a normal memory. That is, the memory unit 62 includes a memory cell array 621, a decoder 622, and a sense amplifier & selector 623.
The decoder 622 restores the encoded data (input address). Here, the decoder 622 develops a binary signal. For example, if there are N bits, the decoder 622 expands them to 2N. Then, the decoder 622 selects the position of the memory cell array 621 based on the developed value, writes data to the selected position, or reads data from the selected position.
The sense amplifier & selector 623 includes a sense amplifier that amplifies data read from the memory cell array 621 and a selector that selects data read from the memory cell array 621 according to an address signal.
In this manner, the memory unit 62 alone has all the operations (commands) for writing and reading, and does not have a search operation (command).
Therefore, when the search operation is realized by using a normal memory (memory unit 62) as in the case of the pocowatcher 11 of the present embodiment, it is necessary to handle the input search key as an address.
By defining the memory address as search key data, the memory data as an action, and inputting the search data as an address, the action data can be obtained from the memory. However, according to this method, when the bit width used as the search key is long, there is a problem that the memory capacity becomes enormous. For example, in the case of a 64-bit search key, the total memory capacity is 2 ^ 64 (≈16 × 10 ^ 18), which is much larger than the memory capacity that can be realized in the semiconductor technology at the time of filing this application.

Therefore, the search unit 51a of the present embodiment further includes a hash generator 61 in addition to the memory unit 62.
The hash generator 61 reduces the bit length of the input search key using a hash function. For example, the hash generator 61 compresses an input having a search key 64-bit length into an output having a 16-bit width.
As described above, the search unit 51a of the present embodiment reduces the searchable bit length by the internal hash generator 61, and enables the search operation while taking into consideration the limitation and limit of the mounting capacity of the memory unit 62. It is.

However, since the search key is compressed, there is a problem that it cannot be distinguished even though the addresses are different. In order to solve this problem, the search unit 51 a of the present embodiment further includes a comparator 63 in addition to the hash generator 61 and the memory unit 62.
The comparator 63 reads the search key written in addition to the action result at the time of reading from the memory cell array 621 via the sense amplifier & selector 623, compares the read search key with the input search key, and finally Judge hit / miss.
For further details of the search unit 51a, refer to Patent Document 3.

Here, in the pocowatcher 11 of FIG. 5, not only the search unit 51a but also a statistical information processing unit 52a and a calculation unit 53a are further provided.
This is because if only the search unit 51a is used, there is a problem that the search table that varies depending on the application is less flexible.
For example, when an IP address in a network device such as a router is used as a search table, IPv4 requires a capacity for storing data of about several million entries. In the case of IPv6, the search key is up to 64b, but since the number of entries is large, a large search table is required. Further, in recent ICN (Information Centric Network) and CCN / DCN (Content Centric Network / Data Centric Network), a path is controlled by a character string, so a search key that handles a long bit length is required.
As described above, various devices that function the route control unit 31 or the traffic monitoring unit 33 in FIG. 3 or the clustering unit 37 or the ranking unit 38 in FIG. Or a problem that waste occurs.
In order to solve such a problem, the pocowatcher 11 of FIG. 5 is further provided with not only the search unit 51a but also a statistical information processing unit 52a and a calculation unit 53a.

For example, consider the forwarding of routers among search engine applications. This forwarding is realized by route control by the route control unit 31 of FIG.
In the forwarding, it is necessary to determine a port number for outputting a packet from a destination address or the like described in the packet header.
Here, consider a case where a technique is adopted in which the output port number is uniquely determined when the destination is determined. For example, when determining the port number, a table describing the relationship between the destination address and the output port is used. In such a case, traffic congestion occurs due to an increase in selection of the same destination or the same output port.
Since the traffic cannot be bypassed by such a uniquely determined method, a method of accumulating the data amount of each flow and determining the output port in consideration of the data amount is adopted in the forwarding. According to this method, if there are many hits for a specific flow, the output port is biased and the traffic is congested. To avoid this congestion, the number of times each flow was hit and the amount of traffic that flowed It is necessary to process to count. That is, a process for accumulating statistics and building an efficient network is required.

In order to realize such processing with a single chip, the pocowatcher 11 in FIG. 5 is further provided with not only the search unit 51a but also a statistical information processing unit 52a and a calculation unit 53a.

The statistical information processing unit 52a includes a memory unit 71 in order to accumulate statistical information necessary for the above-described processing.
The memory unit 71 has the same hardware configuration as a normal memory. That is, the memory unit 71 includes a memory cell array 711, a decoder 712, and a sense amplifier & selector 713. As described above, since the memory unit 71 for storing statistical information is not a special memory cell but a normal memory cell, the configuration of FIG. 5 can be realized by a single chip called the pocowatcher 11.
The memory unit 71 stores information corresponding to the flow hit in the search unit 51a (search engine) in order to store statistical information. That is, the memory unit 71 associates an address with each search key hit and accumulates statistical information at the address.

The calculation unit 53a inputs the hit / miss determination result by the comparator 63, and if it is a hit, reads the unique address corresponding to the search key of the hit, and accesses the memory unit 71 according to the read address. Read statistical information.
The adder 81 of the arithmetic unit 53 updates the data by adding the statistical information read in this way, and writes it back to the same address in the memory unit 71. Thus, the adder 81 is a device that adds data to the read data. The adder 81 adds only when there is a hit in the search unit 51a. The adder 81 adds 1 when the statistical information is the number of packets. When the statistical information is the packet size, the adder 81 describes the read data in the packet header. Add packet size.
Here, it is necessary to compare the data read from the memory unit 71 and the search key for hit / miss determination. For this reason, the operation of the adder 81 is controlled by the hit signal of the comparator 63 of the search unit 51a.

Statistic information is accumulated in the memory unit 71 by such a series of operations.

Similar to the pocowatcher 11a in the example of FIG. 5, the pocowatcher 11b in the example of FIG. 6 includes a search unit 51b, a statistical information processing unit 52b, and a calculation unit 53b.
In the example of FIG. 6, the memory unit 62 of the search unit 51b and the memory unit 91 of the statistical information processing unit 52b are integrally formed. Thus, by writing the statistical information data to the same row as the action of the search memory cell array 621 in the statistical information memory cell array 911, a function equivalent to the example of FIG. Path control) can be realized.
As a specific operation, the hash generator 61 inputs data (search key) such as a destination inputted from the outside to the hash function to reduce the number of bits. The degenerated data is used as an address of the memory (memory unit 62 and memory unit 91). If the search result action is input to the memory data, the search operation can be realized. When an action is read from the memory cell array 621 on the search unit 51b side, the statistical data described in the same row is read from the memory cell array 911 on the statistical information processing unit 52b side. If the search result is a hit, the calculation unit 53 updates the read statistical information and writes it back to the same row in the memory cell array 911 on the statistical information processing unit 52b side.
On the other hand, when the statistical information is read, a search key is input, and among the statistical information stored in the memory cell array 911, the statistical information stored at the address corresponding to the search key is read.

FIG. 7 shows an enlarged view of the memory cell array 911, the sense amplifier & selector 912, and the calculation unit 53b in the pocowatcher 11b in the example of FIG.
As shown in FIG. 7, each memory cell (memory cell composed of a word line and two bit lines) constituting the memory cell array 911 is connected to two sense amplifiers, a selector, and an adder 81. Yes.
Therefore, although not shown, the adder 81 can be inserted into the memory unit 91. In this case, the time from reading to writing back can be shortened.

FIG. 8 is a schematic diagram for explaining a router function combining the functions of the path control unit 31 and the buffer unit 34 of FIG.
As described above, the path control unit 31 can be realized by the configuration of the example of FIG. 5 or the example of FIG. 6 of the poco watcher 11 as described above.
Input data (such as a packet) for setting the route to the route control unit 31 is input to the input buffer 34IN of the buffer unit 34.
On the other hand, the data (packets and the like) routed by the route control unit 31 is an output buffer connected to the routed output port among a plurality of output ports (output ports # 1 to # 4 in the example of FIG. 8). 34OUT (in the example of FIG. 8, one of the four output buffers 34OUT) is input.
Here, as shown in FIG. 8, the output buffer 34OUT employs a queue configuration to output data with high priority first. That is, by dividing the output buffer 34OUT into FIFOs having the number of queues, it is possible to control the FIFO queues input according to the priority. The FIFO can be configured with standard memory.

As described above, the poco watcher 11 is configured so that the search engine (the search unit 51a in FIG. 5 and the search unit 51b in FIG. 6) includes the standard memory (the memory unit 62 in FIG. 5 and FIG. 6), and , A memory for storing statistical information (the memory unit 71 in FIG. 5 and the memory unit 91 in FIG. 6 are also configured by a standard memory.
As a result, the network functions required in the data plane of the router or network switch, that is, path control, bandwidth control, traffic control, buffer, and access control can be realized by the one-chip pocowatcher 11 (FIG. 3). reference).

Specifically, the route control can be realized mainly by the configuration (search engine or the like) shown in FIG. 5 or 6 as described above. That is, in the route control, the destination address of the input packet is input to the search units 51a and 51b, and the packet is output to a specific output buffer 340UIT (see FIG. 8) according to the action output from the search units 51a and 51b. The

As described above, the bandwidth control can be realized by the FIFO queue of the output buffer 34OUT in FIG. That is, the amount of data to be output is limited by the FIFO provided in the output buffer 34OUT. If the amount of data input from the input buffer 34IN is larger, the data is stored in the FIFO of the output buffer 34OUT.

Traffic monitoring can be realized by analyzing statistical information stored in the memory unit 71 of FIG. 5 or the memory unit 91 of FIG. That is, traffic monitoring is performed by reading data stored in the memory unit 71 of the statistical information processing unit 52a and the memory unit 91 of the statistical information processing unit 52b and checking each data value. For example, it is checked from the read data that there is a lot of specific data or the specific data suddenly increases. Note that the operation subject of the check is, for example, the CPU 13 in FIG.

The buffer can be realized by a FIFO or the like as described above (see FIG. 8). That is, the buffer temporarily stores data until the route of the input packet is determined. Similar to the bandwidth control, data is accumulated in the FIFO until output.

Access control (filtering) can be realized by a search engine. Details of the access control will be described later with reference to FIG.

In summary, the information processing system according to the present embodiment can easily expand the network function by simply connecting the pocowatcher 11 configured with one chip to the network processor 12.

Specifically, conventionally, a packet input from the outside is input from a predetermined communication device (for example, the communication device 14a in FIG. 14), and the destination is determined by the network processor 12 functioning as a switch chip. The communication device (for example, the communication device 14b in FIG. 14) or the same communication device (for example, the communication device 14a in FIG. 14).
In order to expand network functions such as path control, bandwidth control, access control, traffic monitoring, and buffers, special memories (TCAM 501 and SRAM 502) are required in addition to the DRAM 503 in FIG.

On the other hand, in the information processing system according to the present embodiment, the pocowatcher 11 that realizes network functions such as path control, bandwidth control, access control, traffic monitoring, and buffer in one chip is simply connected to the network processor 12. Network functions can be easily expanded.

For example, when the information processing system takes the configuration example of FIG. 2A, the poco watcher 11 is inserted between the communication device 14 a and the network processor 12.
In this case, the constituent parts of the example of FIG. 5 or FIG. 6 of the pocowatcher 11 accumulate the statistical information of the packet, and output the statistical information in response to a request from the CPU 13. The CPU 13 determines whether or not the flow is biased based on the statistical information. The determination result is fed back to the network processor 12 functioning as a switch chip. The network processor 12 controls selection of a port to which a packet is output based on the feedback above. In this way, path control is realized by the pocowatcher 11.
In this case, the pocowatcher 11 can also be used as a buffer for temporarily storing externally input packets. The pocowatcher 11 can also be used as a buffer when outputting a packet. In this way, band control for limiting the amount of output data is realized by the pocowatcher 11.

For example, when the information processing system takes the configuration example of FIG. 1, the pocowatcher 11 is arranged on the network processor 12 side, so that the performance of the network processor 12 can be supplemented.
As a result, the expansion of the buffer function, the expansion of statistical information, the expansion of path control, and the like can be realized as the expansion of the network function of the network processor 12. Here, the expansion of the statistical information means, for example, increasing the function that can only hold the statistical information for each input port for each flow. Such expansion of statistical information increases the number of types of statistics, thus enabling fine control.

Further, for example, the information processing system can take the configuration example of FIG. 2B as an application for monitoring only packets input from the WAN, which is an external network (not shown), or output to the WAN side. .

Although one embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment, and modifications, improvements, and the like within a scope that can achieve the object of the present invention are included in the present invention. is there.

For example, search engines are used for a variety of applications. Specifically, the search engine can be applied to pattern authentication such as face authentication. When applied in this way, the bit width of the input search key depends on the application.
Therefore, by adopting a method of increasing the bit width of the search key, it becomes possible to deal with all applications, which seems advantageous at first glance. However, with this method, the time for inputting the search key becomes redundant, which eventually causes a problem of deteriorating system performance.
Further, in the device, a memory capacity for comparison with the search key is required, and extra resources are consumed. In the case of the same memory capacity, there is a problem that the number of entries is reduced.

In the search engine of the above-described embodiment, that is, the search unit 51a in the example of FIG. 5 and the search unit 51b in the example of FIG. 6, it is difficult to solve these problems.
Therefore, in order to solve these problems, it is preferable to employ a search engine whose configuration can be switched by a mode register. This doubles the number of search key bits instead of halving the number of entries. By switching the configuration according to the application, a single device (Pocowatcher 11) can provide an optimal configuration for various applications.

A search engine capable of switching such a configuration is shown in FIG.
That is, FIG. 9 shows a hardware configuration example of the search engine of the poco watcher 11 and shows an example different from those shown in FIGS.

As shown in FIG. 9, the search unit 51 c includes an address conversion circuit 91, a main search unit 92 </ b> A, a main search unit 92 </ b> B, and a selection circuit 93.
Here, since each of the main search unit 92A and the main search unit 92B has basically the same function and configuration as the search unit 51a in the example of FIG. 5, detailed description thereof will be omitted.

In the example of FIG. 9, the search engine is divided into two parts, a main search unit 92A and a main search unit 92B.
The mode set (mode register signal) is input to the address conversion circuit 91 and the selection circuit 93. That is, the input address is switched by the mode conversion in the address conversion circuit 91, and the search result is switched by the mode set in the selection circuit 93.

For example, in the example of FIG. 9, when the number of entries is doubled, the address conversion circuit 91 performs the same search for the two divided search engines, that is, the main search unit 92A and the main search unit 92B. Enter the key.
Of the actions output from the main search unit 92A and the main search unit 92B, the action result in which the hit signal is active is selected and output as a search result by the selection circuit 93.
Further, when a miss signal is output from each of the main search unit 92A and the main search unit 92B, the selection circuit 93 outputs a miss.

For example, in the example of FIG. 9, when the bit width of the search key is doubled, the address conversion circuit 91 divides the input search key into the first half bit and the second half bit, and the first half bit is divided. While making it input into the main search part 92A, the latter half bit is input into the main search part 92B.
When the hit signal is active from each of the main search unit 92A and the main search unit 92B, the selection circuit 93 outputs an action result as a hit.
When a miss signal is output from at least one of the main search unit 92A and the main search unit 92B, the selection circuit 93 outputs a miss.

In the example of FIG. 9, the search engine is divided into two, but the number of search engines is not particularly limited to this, and may be divided into four, for example. In the case of four divisions, the number of entries can be switched between 1, 2 and 4 times.

Here, access control (filtering) by the search engine will be described.
Filtering is roughly divided into a black list method and a white list method.
The black list method is a method that excludes search key information including a known bit string described in the black list and outputs other information.
The white list method is a method for outputting search key information described in the white list.
Here, in the black list method, it is assumed that a bit string whose upper 3 bits are “000” in the 4-bit search key is described in the black list. In this case, it is necessary to exclude search results having both search keys “0001” and “0000”.
In this case, “0001” and “0000” may be input to the search engine twice as search keys and the search results may be output respectively. However, by adding a mask function to the search key, the lower 1 bit is masked. By inputting “000 *” as a search key once, both “0001” and “0000” search results can be output. In this manner, by adding a mask function to the search key, the processing time and processing load of the search engine can be reduced when the black list method is adopted.

There are also applications that output top candidates. For example, it is an application that searches for directions to a museum and outputs a plurality of candidates as search results.
Even when a plurality of candidates are output as search results, a mask function may be added to the search key.

FIG. 10 is a hardware configuration example of the search engine of the poco watcher 11 and shows an example different from that of FIGS. 5, 6, and 9.
As shown in FIG. 10, the search unit 51d includes a main search unit 101A, a main search unit 101B, and a selection circuit 102.
Here, since each of the main search unit 101A and the main search unit 101B has basically the same function and configuration as the search unit 51a in the example of FIG. 5, detailed description thereof will be omitted.
When the search key is masked, the number of bits of the input search key is reduced. However, since it is necessary to have a configuration capable of outputting a plurality of search result actions, the configuration shown in FIG. 10 is adopted.
Here, when the mask signal is activated, the selection circuit 102 outputs a result from the search engine corresponding to the search table corresponding to the mask.

As described above with reference to FIGS. 9 and 10, by dividing the internal search engine, changing the search key to be input, and changing the determination of the search result, the optimal device (Poco) It is possible to provide a watcher 11).

As described above, as a method corresponding to various applications, a method of changing specifications by switching the function of a search engine with a mode set or the like is suitable, but the method is not limited to this method.
For example, as another method, a method using a plurality of LSIs (Pocowatcher 11) on which one search engine is mounted may be employed.

FIG. 11 is an information processing system according to an embodiment of the present invention, and shows a configuration example of an information processing system using two search engines.
In the example of FIG. 11, each of the search engines 111A and 111B is connected to the search engine controller 110 of the network processor 12.
With such a configuration, the capacity of the search table, that is, the number of entries can be doubled.
When searching, a search key is simultaneously input to each of the two search engines 111A and 111B. Then, the search engine controller 110 confirms the search results output from each of the two search engines 111A and 111B, and uses the hit one of the two search engines 111A and 111B.
By operating in this way, the search table can be enlarged.

When a large-capacity search table is constructed, different tables are written to the search engines 111A and 111B. Therefore, the search engines 111A and 111B do not hit at the same time.
In the case of building a large-capacity table, as shown in FIG. 12, first, writing is performed to the first search engine 111A.
If this writing is successful, writing is not performed to the second search engine 111B.
On the other hand, if writing to the first search engine 111A is unsuccessful, writing to the second search engine 111B is performed.

In order to expand the search table by using such a plurality of search engines (two search engines 111A and 111B in the examples of FIGS. 11 and 12), is the write completed and “successful”? Alternatively, it can be realized by outputting the result of “unsuccessful” from each search engine (two search engines 111A and 111B in the examples of FIGS. 11 and 12).

Note that the search engine controller 110 can also determine whether writing has succeeded.
However, since the same functions as those of the search engines 111A and 111B are provided in the search engine controller 110, resources are often insufficient. It's also a wasteful resource, so it's not a wise method.
Conversely, the search table can be easily expanded by using the write completion signal.
In the above example, the example in which the search table is doubled has been shown. However, the present invention is not particularly limited to this. If the number of search engines (LSIs) is increased, the search table is proportionally increased. Can be easily expanded.

By the way, in the above-described embodiment, the poco watcher 11 is mounted together with a CPU and a network controller on a substrate in a server or a PC (one housing), but the mounting form is not particularly limited to this.
For example, as shown in FIGS. 13 and 14, the pocowatcher 11 may be configured as one device (one housing) and connected to another device (one housing).
FIG. 13 is a block diagram illustrating an example of the configuration of the information processing system according to the embodiment of the present invention, which is different from the examples of FIGS. 1 and 2.
In the information processing system in the example of FIG. 13A, the pocowatcher 11 is connected between the L2 switch 203 connected to the router 202 and the plurality of PCs 204a to 204d. The network controller 201 is connected to each of the router 202, the L2 switch 203, and the pocowatcher 11.
In the information processing system in the example of FIG. 13B, the pocowatcher 11 is connected between the router 202 and each of the two L2 switches 203A and 203B. The network controller 201 is connected to the router 202 and the poco watcher 11. A plurality of PCs 204a to 204c are connected to the L2 switch 203A. A plurality of PCs 204d to 204f different from these are connected to the L2 switch 203B.

FIG. 14 is a block diagram illustrating an example of a configuration of an information processing system according to an embodiment of the present invention, which is different from the examples of FIGS. 1, 2, and 13.
In the information processing system of the example of FIG. 14, there are a router 301, enterprise routers 302-1 and 302-2, and consumer routers 303-1 to 303-3 as devices constituting the network N.
The network controller 401 in the example of FIG. 14 is a device that provides an overview of information about the entire network N. That is, the information processing system in the example of FIG. 14 implements SDN (Software Defined Network).
In order to realize the SDN, the network controller 401 needs to acquire the status of each device that configures the network N, and control each device based on the obtained information.
For this reason, conventionally, although not shown, since the network controller 401 and the devices constituting the network N directly communicate with each other, it is very difficult to realize SNS due to the following factors. Met.
The first factor is that each device is provided by a separate manufacturer. Furthermore, some devices support SDN and some do not.
The second factor is that the router will be simplified more and more due to future technological trends, for example, by NFV (Network Function-Virtualization) FV.
Therefore, in the information processing system of the example of FIG. 14, the poco watchers 11-1 to 11-5 are connected to individual devices constituting the network N, and the network controller 401 and the poco watchers 11-1 to 11-5 are connected. (Hereinafter, these are collectively referred to as “Pocowatcher 11”).
The pocowatcher 11 monitors traffic (data collection) and executes various controls. That is, the pocowatcher 11 transmits traffic data to the network controller 401, and conversely receives control data from the network controller 401.
As described above, the pocowatcher 11 monitors the traffic of the connected devices among the individual devices, acquires the data and transmits the data to the network controller 401, and the network controller 401 analyzes the data of the individual devices to individually When the control information is generated and transmitted to the device, the control information is received, and the connected device is controlled based on the control information.

In other words, the memory device to which the present invention is applied only needs to have the following configuration, and can take various embodiments including the above-described embodiment.
That is, the memory device to which the present invention is applied is
A memory device composed of a single chip (for example, the pocowatcher 11 in FIGS. 1 and 2),
Among network functions, at least path control, bandwidth control, traffic monitoring, buffer, and access control function (for example, having the functional configuration of FIG. 3)
Any memory device may be used.
By adopting a memory device having such a configuration, network functions can be easily expanded with low cost and low power consumption when commoditizing NFV and networks.

Here, the memory device
A search unit having a first memory unit (for example, the memory unit 62 in FIGS. 5 and 6) and performing a search operation for referring to the input search key for the data stored in the first memory unit. For example, the search units 51a and 51b) in FIG. 5 and FIG.
A second memory unit (for example, the memory unit 71 of FIG. 5 or the memory unit 91 of FIG. 6) that stores the statistical information of the address by associating the address of the first memory unit with each search key hit in the search unit. A statistical information processing unit (for example, the statistical information processing units 52a and 52b in FIGS. 5 and 6),
An arithmetic unit (e.g., arithmetic units 53a and 53b in FIGS. 5 and 6) that updates the statistical information every time it is hit by the search unit;
Can be provided.

In addition, the search unit (for example, the search unit 51c in FIG. 9) can have a function of changing the bit width of the search key.

Further, the search unit (for example, the search engines 111A and 111B in FIG. 11) can have a function of outputting a determination signal indicating whether information writing is successful or unsuccessful.

Also, the search unit (for example, the search unit 51d in FIG. 10) can selectively execute the access control of the white list method and the access control of the black list method.

Further, individual devices constituting the network (for example, the router 301, enterprise routers 302-1 and 302-2, and consumer routers 303-1 to 303-3 constituting the network N in FIG. 14), and the individual devices In the information processing system including a network controller (for example, the network controller 401 in FIG. 14) for controlling the devices, the memory devices are provided to be connected to each of the individual devices,
The memory device (for example, the poco watchers 11-1 to 11-5 in FIG. 14)
A function of monitoring the traffic of connected ones of the individual devices to acquire data and transmitting it to the network controller;
When the network controller analyzes the data of the individual device and generates and transmits control information to the individual device, the network controller receives the control information, and based on the control information, receives the control information of the individual device. The ability to control what is connected,
Is provided.

By the way, the pocowatcher 11 can be embodied as a network-specific DDR DRAM as described above, but as shown in FIG. 16, it is embodied as a general-purpose DDR DRAM with a network function selectively attached thereto. be able to.
Here, the general-purpose DRAM means a DRAM standardized by JEDEC.

The pocowatcher 11c of FIG. 16 is formed in a DDR DRAM, and has a configuration that can be used by selectively switching between a network and a general-purpose PC.
The hash generator 61 is provided outside the DDR DRAM, but other network units 601 such as the memory units 62 and 81, the comparator 68, and the adder 82 are formed in the DDR DRAM.
Here, the network function unit 601 has the functional configuration shown in FIG.
The DDR DRAM is provided with a selector 602. That is, when the selector 602 is switched to the upper route in FIG. 16, that is, the network function unit 601 side such as the memory units 62 and 81, the comparator 68, and the adder 82, it functions as a network DDR DRAM. On the other hand, when the selector 602 is switched to the upper route in FIG. 16, that is, the route directly from the memory units 62 and 81 to the selector 602, it functions as a general-purpose DDR DRAM.
As a mounting method of the selector 602, it is preferable to use at least one of a metal mask and an address key.

FIG. 17 is a diagram showing a connection state of the poco watcher 11c (functioning as a network DDR DRAM) in FIG.
As shown in FIG. 17, a poco watcher 11c (functioning as a network DDR DRAM) can be connected to a controller 701 as an IP of an FPGA or ASIC.
As a result, a function capable of parallel comparison like TCAM can be realized. Here, as shown in the lower diagram on the right side of FIG. 17, the general-purpose DRAM is originally provided with a comparator group 712 for use in the test mode in addition to the memory unit 711. This comparator group 712 can be used for the network function unit 601 in FIG. 16 as it is.

18 is a comparison diagram of a configuration example of a conventional information processing system for realizing a network function and a configuration example of an information processing system including the pocowatcher 11c (functioning as a network DDR DRAM) in FIG. .

FIG. 18A shows a configuration example of a conventional information processing system for realizing a network function.
As described above with reference to FIG. 15, in the conventional information processing system for realizing the network function, a plurality of TCAMs, RLDRAMs, QDR / DDR SRAMs are connected to NP, ASIC, FPGA, and the like. The network function is realized.
A plurality of TCAMs, RLDRAMs, and QDR / DDR SRAMs are expensive components with high power consumption. These components are expected to remain expensive because the market size is small and the price will not drop (no scale merit).
Furthermore, there is a demerit that separate interfaces from NP, ASIC, FPGA, etc. to these components are also required.

FIG. 17B shows a configuration example of an information processing system including the pocowatcher 11c (functioning as a network DDR DRAM) of FIG. 16 to which the present invention is applied.
All of the network functions (FIG. 3) are inserted in the poco watcher 11c. The pocowatcher 11c is formed on a general-purpose DDT2 (3,4) DRAM. That is, the selector 602 (FIG. 16) is realized by at least one of the metal mask (wiring layer) and the address key (mode register), and the DDT2 DRAM is switched between the general-purpose PC and the network.
Here, since the comparator group 712 is provided in advance in the DDT2 DRAM for use in the test mode (FIG. 17), it is necessary to provide a new component by diverting it as the network function unit 601. Absent.
As a result, it is possible to reduce the price of the memory for the network and realize an information processing system at a low cost and with low power consumption by the price premium of the general-purpose DDR.
Furthermore, since the network functions are integrated into the pocowatcher 11c, as shown in FIG. 18, there may be an interface between the pocowatcher 11c and a controller 701 as an IP such as NP, ASIC, or FPGA. In other words, the interface can be put together.

11, 11a, 11b, 11c: Pocowatcher, 12 ... Network processor, 31 ... Path control unit, 32 ... Band control unit, 33 ... Traffic monitoring unit, 34 ... Buffer unit 35 ... Access control unit 36 ... Main control unit 37 ... Clustering unit 38 ... Ranking unit 39 ... Minning unit 51a, 51b, 51c, 51d ... Search unit 52a, 52b ... statistical information processing unit, 53a, 53b ... calculation unit, 62 ... memory unit, 71 ... memory unit, 81 ... adder, 91 ... memory unit, 92A , 92B, 101A, 101B ... main search unit, 111A, 111B ... search engine, 601 ... network function unit, 602 ... selector, 712 ... comparator group

Claims (9)

1. A memory device composed of a single chip,
   Among network functions, at least routing control, bandwidth control, traffic monitoring, buffer, and access control function.
   Memory equipment.
2. A search unit that includes a first memory unit, and executes a search operation for referring to an input search key for data stored in the first memory unit;
   A statistical information processing unit having a second memory unit that associates an address of the first memory unit with each search key hit in the search unit and stores statistical information of the address;
   An arithmetic unit that updates the statistical information every time it is hit by the search unit;
   The memory device according to claim 1.
3. The search unit has a function of changing a bit width of a search key;
   The memory device according to claim 2.
4. The search unit has a function of outputting a determination signal indicating whether writing of information is successful or unsuccessful,
   The memory device according to claim 2.
5. The search unit selectively executes the access control of a white list method and the access control of a black list method.
   The memory device according to claim 2.
6. In an information processing system including individual devices that constitute a network and a network controller that controls the individual devices, the memory device is provided by being connected to each individual device,
   The memory device is
   A function of monitoring the traffic of connected ones of the individual devices to acquire data and transmitting it to the network controller;
   When the network controller analyzes the data of the individual device and generates and transmits control information to the individual device, the network controller receives the control information, and based on the control information, receives the control information of the individual device. The ability to control what is connected,
   The memory device according to claim 1.
7. A memory section;
   A network function unit for exerting the network function;
   A selector unit that switches between a first route between the memory unit and the network function unit and a second route of the memory unit;
   The memory device according to claim 1, further comprising:
8. The selector unit is realized by at least one of a metal mask and an address key.
   The memory device according to claim 7.
9. The network function unit is configured by a comparator group for a test mode for the memory unit.
   The memory device according to claim 7 or 8.

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