WO2017027028A1 - Gestion de liaison serdes - Google Patents

Gestion de liaison serdes Download PDF

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Publication number
WO2017027028A1
WO2017027028A1 PCT/US2015/044849 US2015044849W WO2017027028A1 WO 2017027028 A1 WO2017027028 A1 WO 2017027028A1 US 2015044849 W US2015044849 W US 2015044849W WO 2017027028 A1 WO2017027028 A1 WO 2017027028A1
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WO
WIPO (PCT)
Prior art keywords
superflit
memory
transactions
crc
serdes
Prior art date
Application number
PCT/US2015/044849
Other languages
English (en)
Inventor
Ryan Akkerman
Gregg B. Lesartre
James Donald Regan
Original Assignee
Hewlett Packard Enterprise Development Lp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Enterprise Development Lp filed Critical Hewlett Packard Enterprise Development Lp
Priority to PCT/US2015/044849 priority Critical patent/WO2017027028A1/fr
Publication of WO2017027028A1 publication Critical patent/WO2017027028A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum

Definitions

  • Fig. 1 is an example media device for serializer-deserializer (SERDES) link management
  • Fig. 2 is an example memory cluster for SERDES link management
  • FIG. 3 is a process flow diagram of a method for SERDES link
  • FIG. 4 is a process flow diagram of a method for SERDES link
  • the media controller transmits the data across serializer-deserializer (SERDES) links, which are high-speed communication links between a computer processing chip and a system, such as a memory cluster.
  • SERDES serializer-deserializer
  • the SERDES link takes a parallel input signal, and sends one bit at a time over a differential pair, to a receiver at the other end. At the other end, the bits are turned back into a parallel signal.
  • SERDES links are typically used because they are a more power efficient, and wire- count efficient, way to transfer data between components in a computer system. Further, SERDES links provide a useful communication mechanism for accessing a large number of memory components efficiently from a memory controller, both directly and forwarded from memory component to memory component.
  • SERDES links however, have a non-zero transmission failure rate. As such, in order to use these links for a memory system, transmission errors are detected and corrected.
  • CRC cyclical redundancy checking
  • CRC is performed in parallel with forwarding transactions to memory. If there is a CRC error, the transactions are canceled, and retransmitted. In this way, read and write transactions can be performed without a store and forward penalty. While these techniques may incur a larger latency when CRC errors occur, the frequency with which the errors occur present a long-term gain in terms of computational efficiency.
  • Fig. 1 is an example media device 100 for SERDES link management.
  • the media device 100 may be a random access memory device that includes a media controller chip 1 02, and memory components 104.
  • the media controller chip 102 includes a media controller 106 and a SERDES link controller 108-1 .
  • the media controller 106 may be a memory controller that receives read and write transactions from a computer processor (not shown).
  • the media controller 106 transmits the transactions to memory component 104-1 via the SERDES link controller 108-1 across SERDES links 1 1 0.
  • the memory components 104-1 , 104-2 include link controllers 108-2 - 108-5 and interfaces to memory 1 1 2-1 , 1 12-2.
  • the interfaces 1 12-1 , 1 12-2 are each associated with a pool of memory being read from, or written to. Actual reads and writes are forwarded to the interface to memory 1 1 2-1 , 1 12-2 to perform the transaction.
  • the SERDES link controller 108-1 receives transactions from the media controller 106, and combines them into a superflit.
  • a superflit is a set of bits, or flits, of a specific size.
  • a flit is a group of bits.
  • the number of bits in a flit is a ratio of the frequency of the SERDES bit rate to the internal core frequency. For example, if the frequency of the SERDES bit rate is 2.66 Gigahertz (Ghz) and the internal core frequency is 0.0833 Ghz, a flit would be 32 bits.
  • a superflit is 288 bits, or 9 flits. In such an example, 256 bits of the superflit are payload, which may be used for multiple transactions. The other 32 bits of the superflit are reserved for a CRC code used to validate the transmission.
  • the SERDES link controller 108-1 serializes and transmits the superflit to a SERDES link controller 108-2 at the other end of link 1 10.
  • the controller 108-2 turns the transmission back into a parallel signal.
  • the first received flit of a transaction contains the address of the transaction, and the transaction type. Thus, if the address of one of the transactions in the superflit matches the address of the memory component 104-1 , the transaction is forwarded to an interface to memory 1 12-1 . It may take several flits to constitute an entire transaction, but the link controller 108-2 does not wait until the entire transaction is received to start forwarding. Rather, the link controller 108-2 automatically forwards flits of data as they arrive at the link controller 108-2. The link controller 108-2 knows, based on the transaction type in the first flit, how many subsequent flits are to be forwarded. TABLE 1 shows the number of flits in each transaction type in an example of the claimed subject matter: TABLE 1
  • the interface to memory 1 1 2-1 places the transaction in a write buffer (not shown) until the CRC is complete.
  • Write transactions are placed in the write buffer to avoid writing potentially bad data to memory. Accordingly, the write transactions are held in the write buffer until a good transmission is confirmed by the CRC. No buffer is used for read transactions because read transactions do not overwrite existing data.
  • the received flits are also automatically forwarded to the link controller 108-3 for transmission to memory component 104-2.
  • the link controller 108-3 combines each forwarded flit into a superflit, and transmits the superflit to link controller 108-4.
  • Link controller 108-4 performs similar techniques to those described for link controller 108-2.
  • the flits for the transaction to be performed on memory component 104-2 are automatically forwarded to the interface to memory 1 12-2. All flits are automatically forwarded to link controller 108-5, which ignores the flits as link controller 108-5 is the last link controller and has no further memory components 104 to forward to.
  • the link controllers 108 also send responses back to the media controller 106.
  • a link controller 1 08-4 generates a superflit with a read response from the interface to memory 1 12-2.
  • the read response includes the data read from memory.
  • Write responses include an indicator whether the write was performed successfully.
  • the superflit is padded with blank flits if the read response does not take up the full complement of bits in the superflit, and there is not another read or write response available to pack into the superflit.
  • the link controller 108-4 also computes the CRC code, and incorporates the CRC code into the superflit. The link controller 108-4 then transmits the superflit to link controller 108-3.
  • the link controller 108-3 automatically forwards the received flits to link controller 108-2 while performing CRC on the received superflit. If there are no transactions in the interface to memory 1 1 2-1 to add to the superflit, the superflit is forwarded to the link controller 108-1 unchanged. However, if there are transactions in the interface to memory 1 1 2-1 to add to the superflit, the link controller 108-2 buffers the
  • the link controller 108-2 may remove blank flits from the received superflit to make room for the transactions of the interface to memory 1 12-1 . If there is not enough room in the superflit for the transactions of the interface to memory 1 12-1 , the link controller 108-2 may continue the transactions in a new superflit. The link controller 108-2 then transmits the superflit to the link controller 108-1 .
  • read and write transactions are forwarded on to the interface to memory 1 1 2 or the next SERDES link hop, flit-by-flit immediately, instead of waiting for the complete transaction to accumulate.
  • a hop is going over the SERDES link 1 10 to the next memory component 104.
  • the transaction is always forwarded to the next hop since it is slightly faster to not have to decode it first. In this way, all transactions go all the way down the chain of memory components 1 04, but are only consumed at one hop.
  • CRC is performed on the data transmitted from the link controller 108-1 to link controller 108-2.
  • CRC codes are built, and compared to a CRC code stored in the superflit. If the CRC is good, the link controller 108-1 sends a good CRC signal to the interface to memory 1 12-1 . If the current transaction is a write transaction, the transaction is moved from the buffer to actual memory. If the CRC is not good, the link controller 108-2 signals a panic mode to the interface to memory 1 12-1 , the memory component 104-2, and the media controller 106. Additionally, a packet declaring the panic mode is spread along the SERDES links 1 10 so that all the memory components 104, and the media controller 1 06 are informed.
  • the read or write response includes a panic indicator.
  • the media device 100 clears all outstanding transactions in the memory components 104. Additionally, the interfaces to memory 1 1 2 drop all outstanding transactions. Further, the media controller 106 waits until all memory components 104 are done panicking, and then re-transmits the transaction.
  • CRC generation happens in the transmit portion of the link controller 108.
  • CRC checking happens in the receive portion of the link controller 1 08. Specifically, Read and Write transactions go outbound from the media controller towards the end of the chain and are checked in the even 108 blocks, e.g., link controllers 108-2, 108-4. Further, read responses and write responses come from memory towards the media controller and are checked in the odd 108 blocks. Thus, when a superflit, with the response transactions, is transmitted back to the link controller 108-1 from link controller 108-2, the CRC checking is performed on that transmission in link controller 108-1 .
  • Figure 1 is described with respect to the execution of a single transaction.
  • examples of the claimed subject matter are capable of executing multiple transactions at a time, described with reference to Fig. 2.
  • Fig. 2 is an example memory cluster 200 for SERDES link management.
  • the memory cluster 200 includes a media controller chip 202, memory components 204, a SERDES interface 208, and SERDES links 210.
  • each memory component 204 includes two SERDES interfaces (not shown), which perform CRC, and forward the superflits through the memory components 204.
  • the media controller 206 receives requests from a host (not shown), to perform read or write transactions to the memory components 204.
  • the media controller 206 forwards transactions so the SERDES interface 208, which may group transactions into superflits and transmit them to the memory components 204.
  • the media controller 206 includes a scheduler 214 and a transaction buffer 216.
  • the scheduler 214 determines the sequence of execution for the transactions.
  • the transaction buffer 21 6 is used by the media controller 206, which writes transactions to the transaction buffer 216 before transmission to the memory components. If there is an error in a given transmission, the media controller 206 panics, dropping all transactions active in the memory components 204, and retransmitting the transactions from the transaction buffer 216. In this way, dedicated retry buffers at the SERDES interface 208 can be avoided.
  • the SERDES interface 208 may communicate with 4 chained ranks 21 2 of SERDES control blocks through 9 SERDES links 210 for a 4x9 array of memory components 204.
  • Each chained rank 212 is considered a hop.
  • a link controller in the SERDES interface 208 communicates with the first chained rank, which talks to the second chained rank, etc.
  • the SERDES control blocks are responsible for converting slower parallel data into high speed serial bits.
  • the chained ranks are additional SERDES hops behind the first set of memory components 204.
  • the media controller 206 transmits multiple transactions in a superflit of data to the memory components 204 through the SERDES interface 208.
  • a superflit is a predetermined number of bits, encompassing multiple flits.
  • a superflit is 288 bits, 256 bits of payload plus 32 bits for CRC.
  • transmitting in superflits with CRC helps keep the bandwidth overhead of the CRC low while still having a large enough CRC to give good error protection.
  • the memory device 200 includes multiple SERDES links 21 0 going to different memory components 204. Each 288 bit superflit is entirely transmitted across one SERDES link 210. Thus, each of the 9 SERDES links will have its own 288 bit superflit.
  • each 64 byte cacheline gets 8 bytes from each of 8 links 21 0.
  • Overhead such as error correcting code, is provided on the 9th link 210.
  • all links 210 are panicked in order to allow the media controller 206 to be able to keep them all synchronized.
  • a 64 byte write is transmitted as 8 bytes (64 bits) across each of 8 SERDES links 210.
  • Each of these 8 byte chunks are part of the 256 bits of payload in 8 separate superflits, each on a separate SERDES link.
  • Fig. 3 is a process flow diagram of a method 300 for serializer-deserializer (SERDES) link management.
  • the method 300 is performed by a media controller, and begins at block 302, where the media controller receives transactions from a computer processor.
  • the media controller stores the received transactions in a transaction buffer.
  • the media controller combines the received transactions into a superflit of predetermined size. Additionally, the media controller uses a specific portion of the superflit for the CRC code.
  • a CRC code may be up to 32 bits, depending on the desired redundancy.
  • the superflit for a 256-bit payload may be 288 bits.
  • the media controller transmits the superflit to the memory components over SERDES links.
  • the link controller at the media controller chip e.g., link controller 108-1 , performs the transmission.
  • a response to the transmission is received.
  • the response may include the data read from a READ transaction, or an indicator that a WRITE transaction was performed. Additionally, the response may indicate a panic mode.
  • the media controller re-transmits all transactions that were in flight when the panic was received.
  • the media controller then returns to block 302.
  • the order of these steps may be modified. For instance, media controller 206 may receive additional new transactions even as a CRC error is processed, and retransmission of cleared transactions may be mixed with transactions that were not in flight when the CRC panic error was encountered.
  • Fig. 4 is a process flow diagram of a method 400 for SERDES link management.
  • the method 400 is performed by the link controller, and begins at block 402 where the link controller receives a flit of data over a SERDES link.
  • the flit is forwarded to the next SERDES hop.
  • the link controller determines if the memory address of the associated transaction matches the address of the memory component. If so, at block 408, the flit is forwarded to the interface to memory.
  • the link controller performs CRC on the superflit.
  • the transaction is released for execution. If the transaction is a WRITE transaction, the transaction is released to modify memory. If the CRC is not good, at block 41 8, the link controller signals a panic mode to the interface to memory, all connected memory components, and the media controller. The link controller returns to block 402.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

L'invention concerne un dispositif de mémoire qui comprend un dispositif de commande de liaison de sérialiseur-désérialiseur (SERDES) recevant une flit de données associées à une transaction par l'intermédiaire d'une liaison SERDES. Le dispositif de commande de liaison SERDES transfère la flit de données vers un saut SERDES suivant avant d'achever un contrôle de redondance cyclique (CRC) sur une superflit. La superflit comprend la flit de données. Le dispositif de commande de liaison SERDES transfère la flit de données vers une interface de mémoire avant d'achever le CRC, si une adresse de mémoire de la transaction correspond à une adresse de mémoire associée au dispositif de commande de liaison SERDES. De plus, la liaison SERDES transfère un résultat du CRC vers l'interface de mémoire.
PCT/US2015/044849 2015-08-12 2015-08-12 Gestion de liaison serdes WO2017027028A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/US2015/044849 WO2017027028A1 (fr) 2015-08-12 2015-08-12 Gestion de liaison serdes

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Application Number Priority Date Filing Date Title
PCT/US2015/044849 WO2017027028A1 (fr) 2015-08-12 2015-08-12 Gestion de liaison serdes

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080168323A1 (en) * 2007-01-09 2008-07-10 Scott Douglas Clark Pipelined Cyclic Redundancy Check for High Bandwith Interfaces
US20100185919A1 (en) * 2009-01-21 2010-07-22 Cisco Systems, Inc. Enhanced Error Detection in Multilink Serdes Channels
US7801121B1 (en) * 2006-04-20 2010-09-21 Altera Corporation Serial communications systems with cyclic redundancy checking
US20110191647A1 (en) * 2010-02-01 2011-08-04 Miller Michael J Communication interface and protocol
WO2014158130A1 (fr) * 2013-03-25 2014-10-02 Hewlett-Packard Development Company, L.P. Dispositif de mémoire ayant une logique de correction d'erreur

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7801121B1 (en) * 2006-04-20 2010-09-21 Altera Corporation Serial communications systems with cyclic redundancy checking
US20080168323A1 (en) * 2007-01-09 2008-07-10 Scott Douglas Clark Pipelined Cyclic Redundancy Check for High Bandwith Interfaces
US20100185919A1 (en) * 2009-01-21 2010-07-22 Cisco Systems, Inc. Enhanced Error Detection in Multilink Serdes Channels
US20110191647A1 (en) * 2010-02-01 2011-08-04 Miller Michael J Communication interface and protocol
WO2014158130A1 (fr) * 2013-03-25 2014-10-02 Hewlett-Packard Development Company, L.P. Dispositif de mémoire ayant une logique de correction d'erreur

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