WO2017022117A1

WO2017022117A1 - Control device, control program, and control method

Info

Publication number: WO2017022117A1
Application number: PCT/JP2015/072333
Authority: WO
Inventors: 啓至森戸
Original assignee: 富士通株式会社
Priority date: 2015-08-06
Filing date: 2015-08-06
Publication date: 2017-02-09

Abstract

Provided is a control device (11) which an information processing device (100) comprises, said information processing device (100) further comprising: a first unit (1), further comprising a first memory (15) and a first processing device (14) which includes a plurality of first cores (141); and a second unit (1) which is added as an expansion after the first unit (1) and further comprises a second memory (15) and a second processing device (14) which includes a plurality of second cores (141). The control device (11) comprises: an input unit (111) into which information is inputted which relates to a usage state of the first and second processing devices (14) in association with the adding-on of resources in the information processing device (100); and a setting unit (112) which sets to active the second memory (15) and a portion of the second cores (141) among the plurality of second cores (141) in addition to the first unit (1) which is set to active, if the second unit (1) is added on and a first usage state is inputted to the input unit (111) as the usage state.

Description

Control device, control program, and control method

The present invention relates to a control device, a control program, and a control method.

A server device capable of mounting a plurality of system boards on which a plurality of central processing units (CPUs) are mounted is known. When a system is constructed with such a server device, the user determines the number of system boards, CPU, and memory capacity installed in the server device according to the middleware or software to be used, the required processing capacity, the required memory capacity, etc. decide. The number of CPUs operating in the system, the number of processor cores (cores), the memory capacity, etc. are directly recognized by the Operating System (OS), so the number of CPUs, cores, memory capacity, etc. that are physically installed Are equivalent to each other.

Also known are middleware and software (hereinafter sometimes simply referred to as “core billing software”) whose license fee is determined by the number of CPUs and the number of cores operated on the server device. When using core billing software in a server device equipped with a plurality of system boards (CPUs), the server configuration may be set so that the license fee can be reduced.

JP 2014-127059 A JP 2002-236527 A JP-A-8-221375

Here, when core billing software and non-core billing software are used in one server device, the number of cores operated on the added CPU may be maximized in order to improve processing performance. In this way, when the number of operating cores is maximized, the license fee increases when the core billing software is used.
Therefore, it is conceivable to set the number of cores to be operated by starting up a setup menu of Basic Input / Output System (BIOS).

However, in this case, at the timing of starting and ending use of the core billing software, it is necessary to repeat the complicated operation of starting the BIOS setup menu and restarting the server device after setting the number of cores to be operated. There is a problem of not becoming.
In one aspect, an object of the present invention is to improve processing performance while maintaining operation costs in a server device operating in a core billing software environment.

Therefore, the control device includes a first unit including a first memory and a first processing device having a plurality of first cores, and a second processing device having a second memory and a plurality of second cores. A control unit provided in an information processing apparatus having a second unit added after the first unit, wherein the first and second processing apparatuses are associated with an increase in resources in the information processing apparatus. The input unit to which information on the usage pattern is input and the second unit are added, and the first usage pattern is input to the input unit as the usage pattern. In addition to the first unit, the second memory and a setting unit that effectively sets some of the second cores among the plurality of second cores.

According to the disclosed control device, it is possible to improve the processing performance while maintaining the operation cost in the server device operating in the core billing software environment.

It is a figure which shows typically the function structure of the information processing system as an example of embodiment. It is a figure which shows typically the functional structure of Baseboard <> Management> Controller (BMC) as an example of embodiment. It is a figure which illustrates CPU structure in the case of using core accounting software in the server apparatus as an example of embodiment. It is a figure which illustrates the server structure management table in BMC as an example of embodiment. It is a figure which illustrates the CPU configuration setting table in BMC as an example of embodiment. It is a figure which illustrates the user setting screen in the management terminal as an example of embodiment. It is a figure explaining the CPU structure change process in the server apparatus as an example of an embodiment. It is a flowchart explaining the effective core determination process in the server apparatus as an example of an embodiment. It is a flowchart explaining the BIOS setting change process in the server apparatus as an example of an embodiment.

Hereinafter, an embodiment relating to a control device, a control program, and a control method will be described with reference to the drawings. However, the embodiment described below is merely an example, and there is no intention to exclude application of various modifications and techniques not explicitly described in the embodiment. That is, the present embodiment can be implemented with various modifications without departing from the spirit of the present embodiment.

Each figure is not intended to include only the components shown in the figure, and may include other functions.
Hereinafter, in the drawings, the same reference numerals indicate the same parts, and the description thereof is omitted.

[A] Example of Embodiment [A-1] System Configuration FIG. 1 is a diagram schematically illustrating a functional configuration of an information processing system as an example of an embodiment.
As shown in FIG. 1, the information processing system 1000 includes a plurality (two in the illustrated example) of system boards 1 (# 0, # 1) and a management terminal 2.

Hereinafter, when it is necessary to specify one of a plurality of system boards, it is expressed as “system board # 0” or “system board # 1”, but when referring to any system board, it is expressed as “system board 1”. .
The system boards # 0 and # 1 and the management terminal 2 are connected to be communicable with each other via, for example, a Local Area Network cable.

The management terminal 2 is a device that includes a CPU (not shown), a read-only memory (ROM), a random access memory (RAM), and a hard disk drive (HDD). The user performs installation / maintenance work of the server apparatus 100 via the management terminal 2. As will be described later with reference to FIG. 6, the management terminal 2 displays a user setting screen for the user to input an instruction for changing the usage pattern of the server device 100 on the display. In addition, the management terminal 2 instructs the BMC 11 described later provided in the system board 1 to change the operation setting of the CPU 14.

System boards # 0 and # 1 function as a server apparatus 100 as shown in FIG. The server apparatus 100 is an example of an information processing apparatus, and is a computer having a server function. In addition to the system board 1, the server device 100 includes various functional configurations such as a magnetic disk device such as an HDD, an input / output (I / O) device, a fan device, and a power supply unit (PSU). However, these are not shown for simplicity.

In the example illustrated in FIG. 1, the system board # 0 is a standard system board (hereinafter, may be referred to as “standard system board 1”, “standard system board # 0”, or the like) provided when the server apparatus 100 is installed. is there. The system board # 1 is an expansion system board (hereinafter, may be referred to as “extension system board 1”, “extension system board # 1”, etc.) provided for improving the processing performance of the server device.

The system board 1 includes a BMC 11, a BIOS 12, a setting information storage unit 13, one or more CPUs 14, and one or more memories 15. The system board 1 includes one or a plurality of units (two sets in the example shown in FIG. 1) including a CPU 14 and one or a plurality of memories that are communicably connected to each other via a bus line.
The memory 15 is a storage device including a ROM and a RAM. Various programs are written in the ROM of the memory 15. The software program on the memory 15 is appropriately read by the CPU 14 and executed. The RAM of the memory 15 is used as a primary recording memory or a working memory.

The CPU 14 is an example of a processing device that performs various controls and calculations, and implements various functions by executing an OS and programs stored in the memory 15. The CPU 14 in the example of the present embodiment is a multi-core processor, and includes 12 cores 141 in the example illustrated in FIG.
In FIG. 1, for simplicity, only one of the 12 cores included in the CPU 14 is shown as a reference, and the other cores are not shown. Further, the number of cores 141 included in each CPU 14 can be variously changed.

The operation of each core 141 is set to be valid or invalid by the BMC 11 as described later with reference to FIG.
The setting information storage unit 13 stores setting information related to validity / invalidity of the core 141, as will be described later with reference to FIGS.
The BIOS 12 is a firmware program for performing input / output at the lowest level with the hardware provided in the system board 1, and is activated in response to power-on of the system board 1. The BIOS 12 switches between valid / invalid of each core 141 included in the CPU 14 by reading the setting information written in the setting information storage unit 13 via the BMC 11.

FIG. 2 is a diagram schematically illustrating a functional configuration of the BMC as an example of the embodiment.
The BMC 11 is an example of a control device, and includes a CPU 110, a nonvolatile memory 120, and a memory 130 as shown in FIG.
The memory 130 is a storage device including a ROM and a RAM. Various programs are written in the ROM of the memory 130. The software program on the memory 130 is appropriately read by the CPU 110 and executed. The RAM of the memory 130 is used as a primary recording memory or a working memory.

The non-volatile memory 120 is a memory that retains stored contents even when power is not supplied, and stores server configuration management information 121 and CPU configuration setting information 122. The server configuration management information 121 will be described later with reference to FIG. 4, and the CPU configuration setting information 122 will be described later with reference to FIG.
The CPU 110 is an example of a computer and controls the entire system board 1. The CPU 110 may be a multiprocessor. Further, the device for controlling the entire system board 1 is not limited to the CPU 110. For example, a micro processing unit (MPU), a digital signal processor (DSP), an application specific integrated circuit (ASIC), or a programmable logic device. Any one of (PLD) and Field Programmable Gate Array (FPGA) may be used. In addition, the device for controlling the entire system board 1 may be a combination of two or more elements of CPU, MPU, DSP, ASIC, PLD, and FPGA.

The CPU 110 functions as an input unit 111 and a setting unit 112 as shown in FIG.
A program (control program) for realizing the functions as the input unit 111 and the setting unit 112 is, for example, a flexible disk, a CD (CD-ROM, CD-R, CD-RW, etc.), a DVD (DVD-DVD-). (ROM, DVD-RAM, DVD-R, DVD + R, DVD-RW, DVD + RW, HD DVD, etc.), Blu-ray disc, magnetic disc, optical disc, magneto-optical disc, etc. Is done. Then, the computer reads the program from the recording medium via a reading device (not shown), transfers the program to the internal recording device or the external recording device, and uses it. Alternatively, the program may be recorded in a storage device (recording medium) such as a magnetic disk, an optical disk, or a magneto-optical disk, and provided to the computer from the storage device via a communication path.

When realizing the functions as the input unit 111 and the setting unit 112, a program stored in an internal storage device (memory 130 in this embodiment) is executed by a microprocessor of the computer (CPU 110 in this embodiment). At this time, the computer may read and execute the program recorded on the recording medium.
The input unit 111 receives an input from the user via the management terminal 2. Specifically, the input unit 111 receives information regarding the usage pattern of the CPU 14 associated with the addition of the system board 1 in the server device 100 from the management terminal 2.

Here, the information on the usage pattern of the CPU 14 is information indicating that the memory 15 of the added system board 1 is enabled, and that the CPU 14 is enabled in addition to the memory 15 of the added system board 1. Information. Hereinafter, information indicating that the memory 15 of the added system board 1 is enabled is referred to as “memory addition instruction”, and information indicating that the CPU 14 is enabled in addition to the memory 15 of the added system board 1. There is a case of “CPU + memory expansion instruction”.

The memory expansion instruction is issued, for example, when using middleware or software whose license fee is affected by the number of cores operated on the server device (hereinafter sometimes simply referred to as “core billing software”). The CPU + memory expansion instruction is issued when, for example, software other than the core billing software whose license fee is not affected by the number of cores operated on the server device is used.

The usage pattern of the server device 100 that uses the core billing software is an example of a first usage pattern that is one of the usage patterns of the server device 100. Moreover, the usage pattern of the server apparatus 100 that uses software other than the core billing software is one of the usage patterns of the server apparatus 100, and is an example of a second usage pattern that is different from the first usage pattern.

FIG. 3 is a diagram illustrating a CPU configuration when core accounting software is used in a server device as an example of an embodiment.
In FIG. 3, a core 141 indicated by “x” indicates a core set to be invalid, and a core 141 not indicated by “x” indicates a core that is set valid.
The setting unit 112 sets each core 14 included in the CPU 14 to be valid or invalid according to an input to the input unit 111.

In the initial state after the system board # 1 is added to the server apparatus 100, the memory 15 and the core 141 of the CPU 14 included in the standard system board # 0 are all set to be valid. Further, all the memory 15 provided in the additional system board # 1 and the core 141 of the CPU 14 are all set to invalid.
When the system board # 1 is added to the server apparatus 100 and a CPU addition instruction is input to the input unit 111, the setting unit 112, as shown in FIG. In addition, all the memories 15 included in the system board # 1 are set to be valid. In addition, the setting unit 112 effectively sets some cores 141 among the plurality of cores 141 provided in the CPU 14 of the system board # 1. Specifically, the setting unit 112 sets some of the cores 141 out of the plurality of cores 141 included in the CPU 14 of the system board # 0 to be invalid, and out of the plurality of cores included in the CPU 14 of the system board # 1. Some cores 141 are set to be valid. As a result, the setting unit 112 makes the total number of cores 141 of the system boards # 0 and # 1 that are effectively set constant before and after the addition of the system board # 1.

The memory 15 provided in the system board 1 becomes usable when at least one core 141 among the plurality of cores 141 provided in the connected CPU 14 is set to be valid. Therefore, the setting unit 112 is effective so that the number of CPUs 14 in which at least one core 141 is effectively set becomes the maximum number so that the memory 15 mounted on the server device 100 can be used to the maximum extent. The core 141 to be set to is distributed to each CPU 14.

In the example illustrated in FIG. 3, the setting unit 112 sets one core 141 to invalid among the plurality of cores 141 included in the CPUs # 0 and # 1 of the system board # 0. The setting unit 112 sets all the memories 15 included in the added system board # 1 to be valid, and one core 141 among the plurality of cores 141 included in the CPUs # 0 and # 1 of the system board # 1. Set each to valid. That is, in the example illustrated in FIG. 3, the setting unit 112 sets the total number of cores 141 that are set to be effective to 24, which is the same as the total number of cores 141 that are set to be effective before the addition of the system board # 1. To do.

When the system board # 1 is added to the server device 100 and the CPU + memory addition instruction is input to the input unit 111, the setting unit 112 sets the system board # 1 to be valid as shown in FIG. To do. Specifically, the setting unit 112 sets all of the memory 15 and the core 141 of the CPU 14 included in the system board # 1 to be enabled in addition to the system board # 0 that is set to be enabled.

When the memory expansion instruction is input to the input unit 111 during the operation in the state illustrated in FIG. 1 based on the CPU + memory expansion instruction after the system board # 1 is expanded, the setting unit 112 is illustrated in FIG. As shown, the number of cores 141 to be effectively set is reduced. Specifically, the setting unit 112 sets some of the cores 141 out of the plurality of cores 141 included in the CPU 14 of the system board # 0. In addition, the setting unit 112 sets some cores 141 out of the plurality of cores 141 included in the CPU 14 of the system board # 1. As a result, the setting unit 112 calculates the total number of the plurality of cores 141 included in the CPUs 14 of the system boards # 0 and # 1 that are effectively set as the number of cores 141 included in the CPUs # 0 and # 1 of the system board # 0. The number is the same (24 in the example shown in FIG. 3).

The setting unit 112 is shown in FIG. 1 when a CPU + memory addition instruction is input to the input unit 111 during operation in the state shown in FIG. 3 based on the memory addition instruction after the addition of the system board # 1. As described above, the number of cores 141 to be effectively set is increased. Specifically, the setting unit 112 sets the invalid core 141 among the plurality of cores 141 included in the CPU 14 of the system board # 0 to be valid. In addition, the setting unit 112 sets the invalid core 141 among the plurality of cores 141 included in the CPU 14 of the system board # 1 to be valid.

FIG. 4 is a diagram illustrating a server configuration management table in the BMC as an example of the embodiment.
The server configuration management table shown in FIG. 4 represents the server configuration management information 121 stored in the nonvolatile memory 120 of the BMC 11 shown in FIG. 2 in a table format.
Hereinafter, in the figure, both the server configuration management information and the server configuration management table may be represented by the same reference numeral “121”.

Further, hereinafter, the CPU 14 and the core 141 provided in the system board 1 (system board # 1 in the example shown in FIGS. 1 and 3) added to the server apparatus 100 are referred to as “addition CPU 14” and “addition core 141”, respectively. May be written. Further, the CPU 14 and the core 141 included in the system board 1 (system board # 0 in the example shown in FIGS. 1 and 3) mounted on the server apparatus 100 before the added system board 1 is referred to as “standard CPU 14”. And “standard core 141” in some cases.

The server configuration management information 121 is information indicating how to handle the additional CPU 14 for each application of the server device 100. In the server information management information 121, the usage of the server device 100 and the validity / invalidity of the additional CPU are associated with each other.
For example, “memory expansion operation” and “CPU + memory expansion operation” are registered in the usage column of the server configuration management information 121 illustrated in FIG. 4. Then, “invalidating” the expansion CPU 14 is associated with “memory expansion operation”, and “validating” the expansion CPU 14 is associated with “CPU + memory expansion operation”.

The setting unit 112 reads the server configuration management information 121 stored in the nonvolatile memory 120 when information on the usage pattern of the CPU 14 is input to the input unit 111.
Specifically, when a memory expansion instruction is input to the input unit 111, the setting unit 112 sets the expansion CPU 14 corresponding to the usage “memory expansion operation” of the server apparatus 100 in the server configuration management information 121. read out. Then, the setting unit 112 determines (selects) that some cores 141 included in the CPU 14 of the added system board 1 are “invalid”.

The setting unit 112 corresponds to the usage “CPU + memory expansion operation” of the server apparatus 100 in the server configuration management information 121 of the server configuration management information 121 when a CPU + memory expansion instruction is input to the input unit 111. Read the setting of the expansion CPU 14. Then, the setting unit 112 determines (selects) that all the cores 141 included in the CPU 14 of the added system board 1 are “valid”.

FIG. 5 is a diagram illustrating a CPU configuration setting table in the BMC as an example of the embodiment.
The CPU configuration setting table shown in FIG. 5 represents the CPU configuration setting information 122 stored in the nonvolatile memory 120 of the BMC 11 shown in FIG. 2 in a table format.
Hereinafter, in the figure, both the CPU configuration setting information and the CPU configuration setting table may be represented by the same reference numeral “122”.

In the CPU configuration setting information 122, the validity / invalidity of the additional CPU 14, the validity / invalidity of the additional core 141, and the validity / invalidity of the standard core 141 are associated with each other.
“Valid” and “invalid” registered in the column of the additional CPU 14 of the CPU configuration setting information 122 shown in FIG. 5 are “valid” registered in the column of the additional CPU 14 of the server configuration management information 121 described with reference to FIG. "And" Invalid "respectively.

In the CPU configuration management information 122, the “invalid” row of the additional CPU 14 is associated with the setting of the additional core 141 as “1 core valid” and the setting of the standard core 141 as “1 core invalid”. It is done. Also, the “valid” row of the expansion CPU 14 is associated with setting the expansion core 141 to “all cores valid” and setting the standard core 141 to “all cores valid”.

The setting unit 112 reads the CPU configuration setting information 122 stored in the nonvolatile memory 120 based on the reference result of the server configuration management information 121 described with reference to FIG.
Specifically, when the setting unit 112 selects “invalid” of the additional CPU 14 in the server configuration management information 121, the setting core 112 corresponds to the additional core 141 corresponding to “invalid” of the additional CPU 14 in the CPU configuration setting information 122. The setting of the standard core 141 is read. Then, the setting unit 112 determines to set the additional core 141 to “1 core valid”, and determines to set the standard core 141 to “1 core invalid”. As described above, the setting unit 112 sets the number of the additional cores 141 to be enabled effectively and the number of the standard cores 141 to be disabled to be the same, so that the total number of the cores 141 that are effectively set in the entire server device 100 is set. To be constant.

Further, when the setting unit 112 selects “valid” for the additional CPU 14 in the server configuration management information 121, the setting core 112 and the standard core 141 corresponding to “invalid” for the additional CPU 14 in the CPU configuration setting information 122. Read the setting. Then, the setting unit 112 determines to set the additional core 141 to “all cores valid” and determines to set the standard core 141 to “all cores valid”.

The setting unit 112 stores information regarding the settings of the additional core 141 and the standard core 141 determined based on the CPU configuration setting information 122 in the setting information storage unit 13 illustrated in FIGS. 1 and 3 as setting information.
Here, the functions as the input unit 111 and the setting unit 112 of the CPU 110 included in the BMC 11 may be included in each of the system boards # 0 and # 1. In this case, the setting unit 112 of each system board # 0, # 1 creates setting information indicating the setting of validity / invalidity of each core 141 of the CPU 14 provided in the same system board 1, and stores the setting information. Stored in the unit 13. As a result, the BIOS 12 of each system board # 0, # 1 refers to the setting information stored in the setting information storage unit 13 to enable / disable each core 141 of the CPU 14 provided in the same system board 1. Can be switched.

Further, the functions as the input unit 111 and the setting unit 112 of the CPU 110 provided in the BMC 11 may be provided only in the standard system board # 0. In this case, the setting information stored in the setting information storage unit 13 of the standard system board # 0 is transferred to the setting information storage unit 13 of the standard system board # 1 by communication (not shown) between the system boards # 0 and # 1. Store. As a result, the BIOS 12 of each system board # 0, # 1 refers to the setting information stored in the setting information storage unit 13 to enable / disable each core 141 of the CPU 14 provided in the same system board 1. Can be switched.

FIG. 6 is a diagram illustrating a user setting screen in the management terminal as an example of the embodiment.
The user setting screen 21 shown in FIG. 6 is displayed on the display of the management terminal 2 shown in FIGS. The user setting screen 21 is displayed by, for example, a Web User Interface (Web UI) set from the web screen. The user setting screen 21 includes a memory expansion radio button 211, a CPU + memory expansion radio button 212, an OK button 213, and a cancel button 214.

The user selects the memory expansion radio button 211 or the CPU + memory expansion radio button 212 and clicks the OK button. FIG. 6 shows an example in which the CPU + memory expansion radio button 212 is selected.
As a result, the management terminal 2 transmits to the BMC 11 of the system board 1 information related to the usage pattern of the CPU 14 accompanying the addition of the system board 1 in the server device 100. Specifically, the management terminal 2 transmits a memory expansion instruction to the BMC 11 when the memory expansion radio button 211 is selected, and CPU + memory to the BMC 11 when the CPU + memory expansion radio button 212 is selected. Send expansion instructions.

When the user clicks the cancel button 214, the user setting screen 21 is not displayed.
In addition, the input from the user by the management terminal 2 may not be based on the user setting screen 21, but may be based on, for example, a command line interface (CLI) set by a command by logging in through telnet or the like. .

[A-2] Operation The effective core determination process in the server apparatus as an example of the embodiment configured as described above will be described according to the flowchart (steps S1 to S7) shown in FIG. 8 with reference to FIG.
FIG. 7 is a diagram illustrating a CPU configuration change process in the server device as an example of the embodiment.

Of the processes indicated by reference signs A1 to A6 in FIG. 7, the processes indicated by reference signs A4 to A6 will be described together with the BIOS setting change process described later with reference to FIG.
The user uses the user setting screen 21 of the management terminal 2 to input information (usage selection setting) regarding the usage pattern of the CPU 14 associated with the addition of the system board 1 in the server device 100 to the BMC 11 (reference numeral in FIG. A1). As the usage selection setting, a memory expansion instruction or a CPU + memory expansion instruction is input.

The input unit 111 (not shown in FIG. 7) of the BMC 11 acquires the application selection setting based on the input from the management terminal 2 (step S1 in FIG. 8).
The setting unit 112 (not shown in FIG. 7) of the BMC 11 refers to the server configuration management information 121 based on the usage selection setting acquired by the input unit 111 (step S2 in FIG. 8). Specifically, when the input unit 111 acquires a memory expansion instruction, the setting unit 112 sets the expansion CPU 14 corresponding to “memory expansion operation” that is the use of the server device 100 in the server configuration management information 121. Read some "invalid". In addition, when the input unit 111 acquires a CPU + memory expansion instruction, the setting unit 112 is a setting of the expansion CPU 14 corresponding to “CPU + memory expansion operation” which is the use of the server device 100 in the server configuration management information 121. Read “valid”.

The setting unit 112 refers to the CPU configuration setting information 122 based on the setting of the additional CPU 14 in the referenced server configuration management information 121 (step S3 in FIG. 8). Specifically, when the setting unit 112 reads “invalid” as the setting of the additional CPU 14 in the server configuration management information 121, the setting unit 112 increases when the setting of the additional CPU 14 is “invalid” in the CPU configuration setting information 122. The settings of the core 141 and the standard core 141 are read out. That is, the setting unit 112 reads “1 core valid” as the setting of the additional core 141 and reads “1 core invalid” as the setting of the standard core 141. When the setting unit 112 reads “valid” as the setting of the additional CPU 14 in the server configuration management information 121, the setting unit 112 and the additional core 141 when the setting of the additional CPU 14 is “valid” in the CPU configuration setting information 122. The setting of the standard core 141 is read. That is, the setting unit 112 reads “all core valid” as the setting of the additional core 141, and reads “all core valid” as the setting of the standard core 141.

The setting unit 112 acquires setting information by reading setting information regarding validity / invalidity of each core 141 from the setting information storage unit 13 (reference A2 in FIG. 7 and step S4 in FIG. 8).
The setting unit 112 changes the setting for enabling / disabling the additional core 141 in the setting information based on the setting of the additional core 141 in the CPU configuration setting information 122 referred to (step S5 in FIG. 8).

The setting unit 112 changes the valid / invalid setting of the standard core 141 in the setting information based on the setting of the standard core 141 in the referred CPU configuration setting information 122 (step S6 in FIG. 8).
The setting unit 112 saves the setting information by writing the setting information in which the valid / invalid setting of the additional core 141 and the standard core 141 is changed to the setting information storage unit 13 (reference A3 in FIG. 7 and step in FIG. 8). S7). Then, the process ends.

Next, the BIOS setting change processing in the server device as an example of the embodiment will be described according to the flowchart (steps S11 to S16) shown in FIG. 9 with reference to FIG.
The user gives an instruction to power on the server device 100 via the management terminal 2 (reference A4 in FIG. 7).

The BIOS 12 acquires the setting information stored in the setting information storage unit 13 in response to a power-on instruction (step S11 in FIG. 9). Specifically, the BIOS 12 requests the BMC 11 to notify the setting information (reference A5 in FIG. 7 and reference B1 in FIG. 9). The BMC 11 reads the setting information from the setting information storage unit 13 (reference A2 in FIG. 7 and reference B2 in FIG. 9). The BMC 11 notifies the BIOS 12 of the read setting information (reference A6 in FIG. 7 and reference B3 in FIG. 9).

The BIOS 12 acquires the valid / invalid setting of each core 141 by referring to the acquired setting information (step S12 in FIG. 9).
The BIOS 12 changes each core included in the additional CPU 14 and the standard CPU 14 to valid or invalid based on the acquired valid / invalid setting of each core 141 (step S13 in FIG. 9).

Each CPU 14 initializes the subordinate memory 15 belonging to the same unit (step S14 in FIG. 9), so that the memory 15 connected to the subordinate of each CPU 14 can be recognized from the OS.
The BIOS 12 initializes I / O of the system board 1 (step S15 in FIG. 9).
The BIOS 12 boots an OS stored in an auxiliary storage device (not shown) such as a hard disk drive (HDD) provided in the server device 100 by the boot setting function (step S16 in FIG. 9). Then, the process ends.

[A-3] Effect When the system board 1 is added and a memory expansion instruction is input to the input unit 111, the setting unit 112 sets validity / invalidity of the expansion core 141. Specifically, in addition to the standard system board 1 that is set to be valid, the setting unit 112 sets the additional memory 15 and some of the additional cores 141 among the plurality of additional cores 141 to be effective.

Thereby, in the server apparatus 100 operating in the core billing software environment, it is possible to improve the processing performance while maintaining the operation cost. That is, in a server apparatus including a plurality of CPUs 14 including a plurality of cores 141, middleware or software license fees operated on the server apparatus 100 may be determined by the number of CPUs 14 (cores 141) used. When the server apparatus 100 is operated in such an environment, the license fee can be reduced.

Further, since the user does not need to set the setup menu of the BIOS 12 in order to enable / disable each core 141, the user can also set each core 141 even when the user has no specialized knowledge. Can be easily set to be valid / invalid. Furthermore, the user does not have to repeatedly perform a complicated operation of starting up the BIOS 12 setup menu, setting it, and restarting the server device 100 at each timing of starting and ending use of the core billing software. That is, the user can easily set validity / invalidity of each core 141 in a short time.

When the system board 1 is added and a memory expansion instruction is input to the input unit 111, the setting unit 112 sets some of the standard cores 141 to be invalid and adds a plurality of expansions. Among the cores 141, some of the additional cores 141 are set to be valid. Then, the setting unit 112 makes the total number of the plurality of standard cores 141 and additional cores 141 that are effectively set constant.

Thus, the added number of CPUs 14 (cores 141) are not recognized by the OS, while the added memory 15 is recognized by the OS. That is, it is possible to reliably maintain the operation cost in the server apparatus 100 operating in the core billing software environment. In addition, when using software such as a database, the processing performance may be improved by increasing the memory capacity rather than increasing the number of CPUs 14, thereby improving the efficient processing performance. Can do.

When the system board 1 is expanded and a CPU + memory expansion instruction is input to the input unit 111, the setting unit 112 adds the expanded memory 15 and the expanded CPU 14 in addition to the standard system board 1 set to be valid. Set to valid.
Accordingly, when software other than the core billing software is used in the server apparatus 100, the added resources can be used to the maximum, and the processing performance of the server apparatus 100 can be improved.

The setting unit 112 reduces the total number of cores 141 to be effectively set when the CPU + memory expansion instruction is input to the input unit 111 during operation based on the memory expansion instruction after the system board 1 is expanded. Specifically, the setting unit 112 sets some standard cores 141 out of the plurality of standard cores 141 to be invalid, and sets some extension cores 141 out of the plurality of additional cores 141 to be invalid. Then, the setting unit 112 sets the total number of the plurality of standard cores 141 and the number of the additional cores 141 that are effectively set to be the same as the number of the plurality of standard cores 141.

Thereby, when the use of the core billing software is started during the operation of the server apparatus 100 after the addition of the system board 1, the number of cores 141 to be operated can be easily reduced, and the operation cost of the server apparatus 100 is increased. Can be reduced. On the other hand, since the number of the memories 15 to be operated is not reduced, the processing performance of the server device 100 can be ensured.

The setting unit 112 increases the total number of cores 141 to be effectively set when a memory expansion instruction is input to the input unit 111 during operation based on the CPU + memory expansion instruction after the system board 1 is expanded. Specifically, the setting unit 112 enables the standard core 141 that is disabled among the plurality of standard cores 141 and enables the standard core 141 that is disabled among the plurality of additional cores 141. Set to.

As a result, the number of cores 141 to be operated can be easily increased when the use of the core billing software is terminated during operation of the server device 100 after the addition of the system board 1, and the processing performance of the server device 100 is increased. Can be improved.
Here, when using the core billing software, if the number of cores 141 to be operated is made constant, unlike the above-described embodiment, without adding a system board (CPU) to the server device, A mode in which only memory is added is also assumed. However, the upper limit number of memories 15 that can be connected to each CPU 14 is determined by the number of memory slots provided in the system board 1, and there is a limit to increasing the memory capacity. Therefore, the processing performance can be improved more efficiently in the example of the above-described embodiment than in the aspect in which only the memory is added to the server device.

Also, in the case of using the core billing software, unlike the above-described example of the embodiment, a mode in which the capacity per memory is increased without adding a system board (CPU) to the server device is also assumed. However, for example, one 32 GB memory may be more expensive than two 16 GB memories, and if a memory with a large capacity is used, the installation cost of the server device increases. Also, it is often cheaper to increase the number of system boards (CPUs) than to increase the capacity per memory. Therefore, the installation cost of the server apparatus 100 can be reduced in the example of the above-described embodiment, compared to an aspect in which the capacity per memory mounted in the server apparatus is increased.

[B] Others The disclosed technology is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present embodiment. Each structure and each process of this embodiment can be selected as needed, or may be combined suitably.
In the exemplary embodiment described above, as illustrated in FIGS. 3 and 5, when the core billing software is used in the server device 100, the setting unit 112 has the standard system board # 1 rather than the additional system board # 1. The number of cores 141 that are effectively set at 0 is increased. That is, the setting unit 112 sets one core 141 out of the plurality of cores 141 included in each standard CPU 14 to be invalid, and sets one core 141 out of the plurality of cores 141 included in each additional CPU 14 to be effective. did.

However, the present invention is not limited to this, and the number of cores 141 that are effectively set in each of the system boards # 0 and # 1 is equal to the number of cores 141 that have been set valid before the addition of the system board # 1. As long as the number is the same, various changes can be made.
If each embodiment of the present invention is disclosed, the control device, control program, and control method of the present invention can be implemented and manufactured by those skilled in the art.

1000 Information processing system 100 Server device 1 System board 11 BMC
110 CPU
111 Input unit 112 Setting unit 120 Non-volatile memory 121 Server configuration management information 122 CPU configuration setting information 130 Memory 12 BIOS
13 Setting Information Storage Unit 14 CPU
141 Core 15 Memory 2 Management terminal 21 User setting screen 211 Memory expansion radio button 212 CPU + Memory expansion radio button 213 OK button 214 Cancel button

Claims

A first unit including a first memory and a first processing device having a plurality of first cores;
A second unit that includes a second memory and a second processing device having a plurality of second cores, and is added after the first unit;
A control device provided in an information processing apparatus having
An input unit for inputting information on usage patterns of the first and second processing devices accompanying an increase in resources in the information processing device;
When the second unit is added and the first usage pattern is input to the input unit as the usage pattern, the second memory is added in addition to the first unit that is set to be valid. And a setting unit that effectively sets some of the plurality of second cores, and
A control device comprising:
The setting unit disables some of the plurality of first cores when the second unit is added and the first usage pattern is input to the input unit. Setting, by setting a part of the plurality of second cores to be valid, the total number of the plurality of first and second cores to be effectively set is made constant,
The control device according to claim 1, wherein:
The setting unit is set to be effective when the second unit is added and a second usage pattern different from the first usage pattern is input to the input unit as the usage pattern. In addition to the first unit being configured, the second memory and the second processing device are enabled.
The control device according to claim 1 or 2, wherein
When the first usage pattern is input to the input unit during operation in the second usage pattern after the addition of the second unit, the setting unit receives the plurality of first units. The first and second plurality of the first cores and the second cores that are set to be valid by disabling some of the first cores and disabling some of the second cores of the plurality of second cores. Making the total number of cores equal to the number of the first cores;
The control device according to any one of claims 1 to 3, characterized in that:
When the second usage pattern is input to the input unit during operation in the first usage pattern after the addition of the second unit, the setting unit receives the plurality of first units. Enabling a first core that is set to invalid among cores, and setting a second core that is set to invalid among the plurality of second cores;
The control device according to any one of claims 1 to 4, characterized in that:
The first usage pattern is a usage pattern in which software affected by the total number of the first and second cores whose operating costs are effectively set is operated.
The second usage pattern is a usage pattern for operating software that is not affected by the total number of the first and second cores whose operating costs are effectively set.
The control device according to any one of claims 1 to 5, characterized in that:
A first unit including a first memory and a first processing device having a plurality of first cores;
A second unit that includes a second memory and a second processing device having a plurality of second cores, and is added after the first unit;
In a computer provided in a control device provided in an information processing apparatus having
Accepting input of information relating to usage patterns of the first and second processing devices accompanying an increase in resources in the information processing device;
When the second unit is added and the first usage pattern is input as the usage pattern, in addition to the first unit being set to be valid, the second memory, and the plurality of second memory modules Set some of the 2 cores to be valid,
A control program for executing a process.
When the second unit is added and the first usage pattern is input, a part of the plurality of first cores is set to be invalid, and the plurality of second cores By setting some of the second cores to be effective, the total number of the plurality of first and second cores to be enabled is made constant.
The control program according to claim 7, which causes the computer to execute processing.
When the second unit is added and a second usage pattern different from the first usage pattern is input as the usage pattern, in addition to the first unit being set to be effective, Enable the second memory and the second processing device;
The control program according to claim 7 or 8, characterized by causing the computer to execute processing.
When the first usage pattern is input during operation in the second usage pattern after the addition of the second unit, some of the first cores are disabled. And by setting some of the plurality of second cores to invalid, the total number of the plurality of first and second cores set to be effective is set to the number of the plurality of first cores. The same as the number,
The control program according to any one of claims 7 to 9, which causes the computer to execute processing.
When the second usage pattern is input during operation in the first usage pattern after the addition of the second unit, the first of the plurality of first cores is set to be invalid. A core is set to be enabled, and a second core that is set to be disabled among the plurality of second cores is set to be enabled,
The control program according to any one of claims 7 to 10, which causes the computer to execute processing.
The first usage pattern is a usage pattern in which software affected by the total number of the first and second cores whose operating costs are effectively set is operated.
The second usage pattern is a usage pattern for operating software that is not affected by the total number of the first and second cores whose operating costs are effectively set.
The control program according to any one of claims 7 to 11, characterized in that:
A first unit including a first memory and a first processing device having a plurality of first cores;
A second unit that includes a second memory and a second processing device having a plurality of second cores, and is added after the first unit;
A control method in a control device provided in an information processing apparatus having
Accepting input of information relating to usage patterns of the first and second processing devices accompanying an increase in resources in the information processing device;
When the second unit is added and the first usage pattern is input as the usage pattern, in addition to the first unit being set to be valid, the second memory, and the plurality of second memory modules Set some of the 2 cores to be valid,
The control method characterized by the above-mentioned.
When the second unit is added and the first usage pattern is input, a part of the plurality of first cores is set to be invalid, and the plurality of second cores By setting some of the second cores to be effective, the total number of the plurality of first and second cores to be enabled is made constant.
The control method according to claim 13, wherein:
When the second unit is added and a second usage pattern different from the first usage pattern is input as the usage pattern, in addition to the first unit being set to be effective, Enable the second memory and the second processing device;
The control method according to claim 13 or 14, characterized in that:
When the first usage pattern is input during operation in the second usage pattern after the addition of the second unit, some of the first cores are disabled. And by setting some of the plurality of second cores to invalid, the total number of the plurality of first and second cores set to be effective is set to the number of the plurality of first cores. The same as the number,
The control method according to any one of claims 13 to 15, characterized in that:
When the second usage pattern is input during operation in the first usage pattern after the addition of the second unit, the first of the plurality of first cores is set to be invalid. A core is set to be enabled, and a second core that is set to be disabled among the plurality of second cores is set to be enabled,
The control method according to any one of claims 13 to 16, wherein:
The first usage pattern is a usage pattern in which software affected by the total number of the first and second cores whose operating costs are effectively set is operated.
The second usage pattern is a usage pattern for operating software that is not affected by the total number of the first and second cores whose operating costs are effectively set.
The control method according to any one of claims 13 to 17, characterized in that: