WO2017019097A1 - Pixels d'enregistrement memristiques - Google Patents

Pixels d'enregistrement memristiques Download PDF

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Publication number
WO2017019097A1
WO2017019097A1 PCT/US2015/042958 US2015042958W WO2017019097A1 WO 2017019097 A1 WO2017019097 A1 WO 2017019097A1 US 2015042958 W US2015042958 W US 2015042958W WO 2017019097 A1 WO2017019097 A1 WO 2017019097A1
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WO
WIPO (PCT)
Prior art keywords
pixel bit
photodiode
image
recording pixel
resistive memory
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PCT/US2015/042958
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English (en)
Inventor
Brent Buchanan
Richard AULETTA
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Hewlett Packard Enterprise Development Lp
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Application filed by Hewlett Packard Enterprise Development Lp filed Critical Hewlett Packard Enterprise Development Lp
Priority to PCT/US2015/042958 priority Critical patent/WO2017019097A1/fr
Publication of WO2017019097A1 publication Critical patent/WO2017019097A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Definitions

  • Image sensor array systems are ubiquitous in many different applications and have significant power and storage requirements.
  • image sensor array systems may employ semiconductor charge- coupled devices (CCD) which require a significant amount of power for their operation.
  • CCD semiconductor charge- coupled devices
  • image sensor array systems will often employ additional storage for offloading the captured images.
  • FIG. 1 illustrates an example block diagram of an image sensor array system comprising a plurality of recording pixel bit-cells
  • FIG. 2 illustrates an example block diagram of an array of recording pixel bit-cells
  • FIG. 3 illustrates an example block diagram of a plurality of arrays of recording pixel bit-cells
  • FIG. 4 illustrates an example circuit diagram of an image sensor array system comprising a plurality of recording pixel bit-cells
  • FIG. 5 illustrates a flowchart of an example method related to the operation an image sensor array system comprising a plurality of recording pixel bit-cells.
  • Image sensor array systems are ubiquitous in many different applications and have significant power and storage requirements.
  • image sensor array systems may employ semiconductor charge- coupled devices (CCD) which require a significant amount of power for their operation.
  • CCD semiconductor charge- coupled devices
  • image sensor array systems will often employ additional storage for offloading the captured images.
  • an active-pixel sensor is an image sensor having an integrated circuit containing an array of pixel sensors, each pixel having a photodetector and an active amplifier.
  • active pixel sensors including the Complementary Metal-Oxide Semiconductor (CMOS) APS that is often used in devices such as cell phone cameras, web cameras, and digital pocket cameras.
  • CMOS APS can be used as an alternative to the charge-coupled device (CCD) image sensors.
  • image sensor array systems that employ either CCD image sensors or CMOS APS often consume a fair amount of power in the process of capturing images and the subsequent offloading of these captured images onto a storage medium, e.g., a storage memory device. Since image sensor array systems are often portable devices, reducing the power and storage requirements would enhance the overall performance of these image sensor array systems.
  • loT devices may employ a sensor system such as an image sensor array system for capturing images.
  • a mailbox may employ an image sensor array system to capture images for determining whether mail has been delivered
  • an entrance door to a home may employ an image sensor array system to capture images for determining whether a package has been left in front of the door
  • a refrigerator may employ an image sensor array system to capture images of various items stored within the refrigerator for determining whether certain items need to be reordered, and so on.
  • providing power to so many of these devices will be challenging as is the cost of providing a significant amount of memory storage within these devices to store the data captured by these loT devices.
  • the present disclosure provides a recording pixel bit- cell that enables low-power operation. Furthermore, the offloading (or broadly reading) and resetting of the recording pixel bit-cell can be performed at any rate of speed or at any later time.
  • the recording pixel bit-cell employs a resistive memory in conjunction with a photodiode and a current mirror circuit.
  • the present disclosure provides an apparatus comprising a photodiode, a resistive memory, and a current mirror circuit.
  • the current mirror circuit is coupled to the photodiode and the resistive memory, where the current mirror circuit is for restricting a resistance of the resistive memory to a resistive value corresponding to a current of the photodiode when a bias voltage is provided to the photodiode.
  • the present disclosure provides an image sensor array system comprising a controller and an array of recording pixel bit-cells, in communication with the controller.
  • Each of the recording pixel bit-cells comprises a photodiode, a resistive memory, and a current mirror circuit coupled to the photodiode and the resistive memory, the current mirror circuit for setting a resistance of the resistive memory to a value corresponding to a current that is sensed for the photodiode when a bias voltage is provided to the photodiode.
  • a method of an image sensor array system may include a processor activating at least one array having a plurality of recording pixel bit-cells for capturing an image, where each recording pixel bit-cell comprises a photodiode, a resistive memory, and a current mirror circuit, storing the image that is captured on the array, and reading image from the array.
  • a resistive memory (broadly a resistive random-access memory) can include a passive two-terminal circuit element that maintains a functional relationship between the time integral of current, and the time integral of voltage.
  • a resistive memory can include a two-terminal non-volatile memory device based on resistance switching. Examples of a resistive memory may comprise: a memristor, a transistor-less cross point memory, and a phase-change memory. As such, the resistive memory of the present disclosure is not limited by these illustrative examples. In other words, any other types of resistive memories can be used in the recording pixel bit-cell of the present disclosure.
  • FIG. 1 illustrates an example block diagram of an image sensor array system 100 comprising a plurality of recording pixel bit-cells 1 10i-1 10 n (herein also referred to individually as a recording pixel bit-cell 1 10 or collectively as recording pixel bit-cells 1 10).
  • the recording pixel bit-cell 1 10i employs a photodiode 1 12, a resistive memory 1 14, and a current mirror circuit 1 16.
  • Each of the other recording pixel bit-cells 1 10 2-n of FIG. 1 also respectively employs a photodiode, a resistive memory, and a current mirror circuit, but they are not shown in FIG. 1 to improve clarity of FIG. 1 .
  • the image sensor array system 100 comprises a controller 120.
  • Controller 120 generally comprises a processor 122 (e.g., a central processing unit (CPU)) and a memory 124, and may additionally include firmware and other electronics for communicating with and controlling the recording pixel bit-cell 1 10.
  • Memory 124 can include both volatile (i.e., RAM) and nonvolatile memory components (e.g., ROM, hard disk, optical disc, CD- ROM, magnetic tape, flash memory, etc.).
  • memory 124 may comprise non-transitory, physical, machine-readable (e.g., computer/processor-readable) media that provide for the storage of machine- readable coded program instructions, data structures, program instruction modules, and other data and/or instructions executable by the processor 122.
  • machine-readable e.g., computer/processor-readable
  • Examples of instructions stored in memory 124 include instructions associated with the operations of an array of recording pixel bit-cells 1 10.
  • the memory 124 can include programming instructions executable by the processor 122 to cause the operation of an array of recording pixel bit- cells 1 10 to perform various general and/or specific functions such as the steps, blocks, or operations of method 500, as described below with respect to FIG. 5.
  • the memory 124 may comprise a plurality of instructions 1 17a-c in accordance with method 500 of FIG. 5.
  • instructions 1 17a comprise instructions for activating an array having a plurality of recording pixel bit-cells to capture an image, where each recording pixel bit-cell comprises a photodiode, a resistive memory, and a current mirror circuit.
  • Instructions 1 17b comprise instructions for storing the image that is captured on the array.
  • Instructions 1 17c comprise instructions for reading the image from the array at a later time.
  • the controller 120 is employed to control the operations of the recording pixel bit-cells 1 10, e.g., resetting some or all of the recording pixel bit-cells 1 10, capturing an image using the some or all of the recording pixel bit- cells 1 10, and/or reading the data representing the captured image from some or all of the recording pixel bit-cells 1 10.
  • the recording pixel bit-cells 1 10 can be reset such that the resistive memory 1 14 is reset to a state that is ready to capture a resistive value.
  • the resistive memory 1 14 may initially be set to a high resistive state.
  • each of the respective photodiode 1 12 When the controller causes the recording pixel bit-cells 1 10 to capture an image, each of the respective photodiode 1 12 will cause a current to flow across the respective resistive memory 1 14 via the respective current mirror circuit 1 16. The flow of current across the respective resistive memory 1 14 will cause the resistive memory 1 14 to switch to a different resistive state, e.g., a lower resistive state.
  • the lower resistive state e.g., a recorded resistive value
  • the stored resistive value can be read from the resistive memory 1 14 under the control of the controller 120.
  • the image sensor array system 100 is able to read and reset any number of the recording pixel bit-cells 1 10 at any rate of speed or at any later time.
  • the controller 120 is able to operate any number of the recording pixel bit-cells 1 10 to capture an image (broadly a writing operation performed on the recording pixel bit-cells 1 10) and then access the captured image at a later (broadly a reading operation performed on the recording pixel bit-cells 1 10).
  • the controller 120 may cause the recording pixel bit-cells 1 10 to capture an image within the mailbox.
  • Such captured image can be offloaded or read at some later time, e.g., when polled by another device (e.g., a portable user device such as a smart phone or a centralized device deployed within the home such as a security or home monitoring system). The captured image can then be used to determine whether the mail has been delivered into the mailbox.
  • the controller 120 may cause the recording pixel bit-cells 1 10 to capture an image just outside the entrance door.
  • image can be offloaded or read at some later time, e.g., when polled by another device (e.g., a portable user device such as a smart phone or a centralized device deployed within the home such as a security or home monitoring system).
  • the captured image can then be used to determine whether an individual has entered an entrance door, whether an individual has attempted to enter the entrance door, or whether a package has been left outside of the entrance door.
  • such recorded images can be used for security or general monitoring applications.
  • the controller 120 is represented as a single module or circuit as shown in FIG. 1 .
  • the controller 120 can be implemented via a plurality of circuits as illustrated and discussed further below in FIG. 4.
  • the controller 120 can be implemented in a number of different ways having different physical structures.
  • each of the recording pixel bit-cells 1 10 employs a current mirror circuit 1 16.
  • a current mirror circuit 1 16 is designed to copy a current through one device by controlling the current in another device.
  • the current mirror circuit 1 16 is designed to copy a current passing through the photodiode 1 12 by controlling the current in the resistive memory 1 14, thereby creating a stored resistive value in the resistive memory 1 14.
  • a current mirror circuit 1 16 may apply bipolar junction transistors, which serves as a current regulator for supplying nearly constant current.
  • the current mirror circuit 1 16 can be implemented in a number of different ways having different physical structures. In one example, the current mirror circuit 1 16 is further described below in FIG. 4
  • FIG. 2 illustrates an example block diagram of an array 200 (or an array of recording pixels) having a plurality recording pixel bit-cells 1 10.
  • FIG. 2 illustrates an 8x8 array 200 of recording pixel bit-cells 1 10, e.g., having 64 recording pixel bit-cells 1 10. It should be noted that the number of recording pixel bit-cells 1 10 in the array 200 is merely illustrative and not a limitation of the present disclosure.
  • FIG. 2 illustrates the array 200 as having a grid-like structure organized into columns and rows of recording pixel bit-cells 1 10.
  • each recording pixel bit-cells 1 10 has a particular set of coordinates represented by (i, j), where i represents a row and j represents a column.
  • the controller 120 can use the coordinate values (i, j) for the respective recording pixel bit-cells 1 10.
  • the controller 120 may want to employ 50% (e.g., one- half) of the recording pixel bit-cells 1 10 to capture an image.
  • the controller 120 may activate recording pixel bit-cells 1 10 having the i values of 1 -4, thereby activating the upper four (4) rows of recording pixel bit-cells 1 10 of array 200 of FIG. 2.
  • the controller 120 may want to employ the bottom 50% (e.g., one-half) of the recording pixel bit-cells 1 10 to capture another image.
  • the controller 120 may then activate recording pixel bit-cells 1 10 having the i values of 5-8, thereby activating the lower four (4) rows of recording pixel bit- cells 1 10 of array 200 of FIG. 2.
  • the controller 120 may want to employ 25% (e.g., one-quarter) of the recording pixel bit-cells 1 10 to capture an image.
  • the controller 120 may activate recording pixel bit-cells 1 10 having the i values of 1 - 4, but limited to j values of 1 -4 thereby activating the upper left sixteen (16) recording pixel bit-cells 1 10 of array 200 of FIG. 2.
  • the controller 120 may want to employ another 25% (e.g., one-quarter) of the recording pixel bit-cells 1 10 to capture another image.
  • the controller 120 may activate recording pixel bit-cells 1 10 having the i values of 5-8, but limited to j values of 5-8, thereby activating the lower right sixteen (16) recording pixel bit-cells 1 10 of array 200 of FIG. 2. In this manner, each "quarter" of the array can be activated by the controller to perform a write operation, a read operation, or a reset operation. In fact, the selected recording pixel bit-cells 1 10 do not need to be contiguous, e.g., selecting every other recording pixel bit-cells 1 10 row wise or column wise, selecting every other second recording pixel bit-cells 1 10 row wise or column wise, and so on.
  • the array 200 can be implemented for any sizes other than 8x8, e.g., 16x16, 32x32, 64x64, 128x128, 256x256, 512x512, 1024x1024 and so on.
  • the values i and j do not need to be equal.
  • the array 200 can be rectangular in shape instead of a square shape.
  • the array does not need to be rectangular and may take any irregular shape as required for a particular implementation, e.g., circular, trapezoidal, triangular and so on.
  • the image sensor array system 100 of the present disclosure is able to take an image of any sizes to conserve power usage. For example, if the controller 120 determines that power is limited, the controller 120 can decide that 25% of the recording pixel bit-cells 1 10 will be used to capture the next captured image. This flexibility in determining the number of recording pixel bit-cells 1 10 to use for capturing images allows the controller 120 to adjust captured image quality based on available power. For example, if the power source for the image sensor array system 100 is based on solar energy, then during the day light hours, the image sensor array system 100 can operate at full resolution, e.g., using the entire array 200 of recording pixel bit-cells 1 10. However, during the low light hours in the evening, the image sensor array system 100 can operate at partial resolution, e.g., using a subset of the entire array 200 of recording pixel bit-cells 1 10.
  • FIG. 3 illustrates an example block diagram 300 of a plurality of arrays 200i -n of recording pixel bit-cells (herein also referred to individually as an array of recording pixel bit-cell 200 or collectively as a plurality of arrays of recording pixel bit-cell 200).
  • the image sensor array system 100 may employ a plurality of arrays of recording pixel bit-cell 200.
  • the use of a plurality of arrays of recording pixel bit-cell 200 allows each array 200 to be selected for capturing an image. Once the image is captured, the captured image can be persistently stored in one of the selected array 200 until a reset operation is performed on the selected array 200.
  • the use of a plurality of arrays of recording pixel bit-cell 200 provides a cost effective method of storing captured images until they are needed in a read operation.
  • an image comparison operation may need to be performed for two successive captured images.
  • the controller 120 can perform a read operation on two different arrays 200 for the same pixel location of (i, j).
  • the controller can read the value from recording pixel bit-cells 1 10(i,i) of array 200i and the value from recording pixel bit-cells 1 10 ( i , i ) of array 200 2 and then perform a comparison operation.
  • each of the arrays 200 stores the captured image while retaining "context" information in terms of the relative location or position of each pixel value. This context information allows an image comparison operation (or broadly a pixel comparison operation) to be performed with ease.
  • an image convolution operation may need to be performed.
  • the controller 120 may need to perform a read operation on a convolution kernel of recording pixel bit-cells 1 10, e.g., a 2x2 kernel.
  • the controller 120 may read the stored values from recording pixel bit-cells 1 10(i,i), 1 10(i,2), 1 0(2, i), and 1 10(2,2)-
  • the controller 120 may then read the stored values from recording pixel bit-cells 1 10(i,2), 1 10(1 ,3), 1 10(2,2), and 1 10(2,3) and so on.
  • the convolution kernel may need to be applied across the entire array of stored values.
  • the stored values are accessed and read repeatedly, where each set of the four pixel values can be used in a convolution operation.
  • the convolution kernel can be any size, e.g., 4x4, 8x8, 16x16 and so on.
  • the use of the present array 200 provides a low cost method where pixel values are not offloaded onto yet another memory storage device, but instead are repeatedly read from the same array 200. Not having another memory storage device lowers the overall cost of the image sensor array system 100. Additionally, retaining the context information of the pixel values further enhances various operations such as image comparison operation and image convolution operation.
  • FIG. 4 illustrates an example circuit diagram of an example image sensor array system 400 comprising a plurality of recording pixel bit-cells 1 10.
  • FIG. 4 illustrates a single recording pixel bit-cell 1 10 for clarity purposes.
  • the image sensor array system 400 comprises a plurality of recording pixel bit-cells 1 10 that are not shown.
  • FIG. 4 illustrates a portion of a controller 120 implemented as circuits (e.g., the portion of FIG. 4 that is external to the recording pixel bit-cell 1 10) that provide the ability: 1 ) to set (or write) a resistive value to a resistive memory, e.g., a memristor 1 14 as shown in FIG. 4, 2) to read a resistive value from the memristor 1 14, and 3) to reset a resistive value in the memristor 1 14.
  • a resistive memory e.g., a memristor 1 14 as shown in FIG. 4, 2
  • a resistive value from the memristor 1 14, and 3 to
  • the memristor 1 14 is in a "reset state" (e.g., a state where the resistive value does not reflect data of a captured image).
  • a "reset state” e.g., a state where the resistive value does not reflect data of a captured image.
  • the V wri te signal line 410 is set low.
  • the Vwrite signal line 410 is set high (e.g., when a bias voltage is provided to the photodiode), a resistive value is set into the memristor 1 14.
  • the Vwrite signal line 410 is pulsed high for a sufficient amount of time (e.g., an amount of time to allow transistor 414 to be in saturation to conduct the same amount of current as transistor 412) so that a resistive value is set in the memristor 1 14.
  • a sufficient amount of time e.g., an amount of time to allow transistor 414 to be in saturation to conduct the same amount of current as transistor 412
  • the voltage provides both the bias voltage for the photodiode 1 12 and the write field for the memristor 1 14.
  • the pair of transistors 412 and 414 in the current mirror circuit 1 16 restricts the resistance of the memristor 1 14 to a value that corresponds to a photodiode current, e.g., nse 416 (e.g., a sensed current).
  • nse 416 e.g., a sensed current
  • the light is correlated with the current of the photodiode, i.e., a high intensity light will correlate to a higher current value and a low intensity light will correlate to a lower current value.
  • This sensed current 416 is also "mirrored" by transistor 414. In doing so, the sensed current 416 causes the memristor 1 14 to switch to a resistance (broadly a resistive value) that is commensurate with the sensed current 416.
  • the resistive value is persistently stored in the memristor 1 14 until the memristor 1 14 is reset.
  • the recording pixel bit-cell 1 10 of FIG. 4 is needed to capture another image, then the recording pixel bit-cell 1 10 will need to be reset first before the recording pixel bit-cell 1 10 is ready to capture another image.
  • the memristor 1 14 is in a written state with a stored resistive value and the V wr ite signal line 410 is set back to low, and the reset signal line 420 is set high and the read signal line 430 is set high.
  • the reset signal line 420 is set low and the reset-read signal line 440 is pulsed so that the voltage V reS et is provided to the recording pixel bit-cell 1 10.
  • the voltage V reS et is provided to the memristor 1 14 which causes the memristor 1 14 to take on a resistive value that is commensurate with the rest state. More specifically, when the reset-read signal line 440 is high, both transistors 422 and 424 are turned on, thereby allowing the voltage V reS et to be provided to the memristor 1 14 since the voltage of V wri te will be equal to V ss . Again, the duration of the reset-read signal line 440 being set high is sufficiently long to set the resistive value in the memristor 1 14 to the reset state.
  • the stored resistive value of the recording pixel bit-cell 1 10 of FIG. 4 can be read out at any time and at any rate.
  • the memristor 1 14 is in a written state (e.g., having a stored resistive value) and the Vwrite signal line 410 is set to low, the reset signal line 420 is set high and the read signal line 430 is set high.
  • the read signal line 430 is set low (turning on transistors 432, 434 and 436), thereby allowing a current to flow through the memristor 1 14 when the reset-read signal line 440 is set high.
  • the voltage of the V re ad line 450 is connected to the memristor 1 14.
  • the actual read voltage connected to the memristor 1 14 is reduced by the voltage drops across four transistors, i.e., transistors 434, 432, 422 and 424.
  • the effect is that the current flowing through the memristor 1 14 will be mirrored and compared to a bias current source 455, I bias- If the current flowing through the memristor 1 14 is larger than I bias, then the V ou t line 460 will go high. However, if the current flowing through the memristor 1 14 is smaller than l b ias, then the V ou t line 460 will go low.
  • the V ou t line 460 is the line in which the resistive value of the memristor 1 14 will be caused to be read out.
  • FIG. 5 illustrates a flowchart of an example method 500 related to the operation of an image sensor array system 100 comprising a plurality of recording pixel bit-cells 1 10 of the present disclosure.
  • the method 500 may be performed, for example, by the controller of the image sensor array system 100 of FIG. 1 .
  • the method 500 will now be described in terms of an example where blocks of the method are performed by a processor, such as processor 122 in performing various operations of the image sensor array system 100 in FIG. 1 .
  • a processor such as processor 122 in performing various operations of the image sensor array system 100 in FIG. 1 .
  • processor may also include multiple processors, a plurality of circuits, or hardware logic units, e.g., an application specific integrated circuit (ASIC), a programmable logic device (PLD), such as a field programmable gate array (FPGA), and so forth.
  • ASIC application specific integrated circuit
  • PLD programmable logic device
  • FPGA field programmable gate array
  • the method 500 begins in block 505.
  • the processor activates an array having a plurality of recording pixel bit-cells to capture an image, where each recording pixel bit-cell comprises a photodiode, a resistive memory, and a current mirror circuit.
  • the processor activates at least a subset of the array 200 having a plurality recording pixel bit-cells 1 10.
  • the entire array 200 can be activated to capture an image or a subset of the plurality recording pixel bit-cells 1 10 can be activated to capture the image.
  • the determination as to how many recording pixel bit-cells 1 10 to be used can be based on the available amount of power.
  • the processor stores the image that is captured on the array.
  • the captured image does not need to be offloaded immediately from the array 200 onto another memory storage device.
  • the captured image can be read at any rate and at any later time.
  • the operation of storing the image that is captured on the array comprises storing the resistive values in the resistive memories representative of the captured image or a portion of the captured image.
  • the processor reads the image that is captured on the array.
  • the captured image can be read from the array 200.
  • the captured image can be read at any rate and at any later time to support various operations, e.g., an image comparison operation or an image convolution operation.
  • the operation of reading the image that is captured on the array comprises reading the resistive values in the resistive memories representative of the captured image or a portion of the captured image.
  • blocks 510-530 are described in the context of capturing, storing and the subsequent reading of a single captured image using the array 200. If additional images are to be captured, then the array 200 can be reset and blocks 510-530 are repeated to capture another image and so on.
  • the method 500 ends in block 595.
  • At least one of the blocks, functions, or operations of the method 500 described above may include storing, displaying, and/or outputting.
  • any data, records, fields, and/or intermediate results discussed in the method can be stored, displayed, and/or outputted to another device depending on the particular application.
  • blocks, functions, or operations in FIG. 5 that recite a determining operation, or involve a decision do not necessarily imply that both branches of the determining operation are practiced. In other words, one of the branches of the determining operation can be deemed as optional.
  • the present disclosure can be implemented by machine readable instructions and/or in a combination of machine readable instructions and hardware, e.g., using application specific integrated circuits (ASIC), a programmable logic array (PLA), including a field-programmable gate array (FPGA), a plurality of circuits, or a state machine deployed on a hardware device, a computer or any other hardware equivalents, e.g., computer readable instructions pertaining to the method(s) discussed above can be used to configure a hardware processor to perform the blocks, functions and/or operations of the above disclosed method(s).
  • ASIC application specific integrated circuits
  • PDA programmable logic array
  • FPGA field-programmable gate array

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Abstract

L'invention, selon un exemple, concerne un système de réseau de capteurs d'image. Le système de réseau de capteurs d'image comprend un organe de commande et un réseau de cellules binaires de pixels d'enregistrement, en communication avec l'organe de commande. Chacune des cellules binaires de pixels d'enregistrement comprend une photodiode, une mémoire résistive et un circuit à miroir de courant couplé à la photodiode et à la mémoire résistive, le circuit à miroir de courant servant à régler une résistance de la mémoire résistive à une valeur correspondant à un courant qui est détecté aux bornes de la photodiode lorsqu'une tension de polarisation est appliquée à la photodiode.
PCT/US2015/042958 2015-07-30 2015-07-30 Pixels d'enregistrement memristiques WO2017019097A1 (fr)

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