WO2017019008A1 - Prédiction de danger pour un groupe d'instructions d'accès mémoire utilisant un tampon associé à une prédiction de branchement - Google Patents

Prédiction de danger pour un groupe d'instructions d'accès mémoire utilisant un tampon associé à une prédiction de branchement Download PDF

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Publication number
WO2017019008A1
WO2017019008A1 PCT/US2015/042199 US2015042199W WO2017019008A1 WO 2017019008 A1 WO2017019008 A1 WO 2017019008A1 US 2015042199 W US2015042199 W US 2015042199W WO 2017019008 A1 WO2017019008 A1 WO 2017019008A1
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Prior art keywords
hazard
instruction
memory access
prediction
instructions
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PCT/US2015/042199
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English (en)
Inventor
Matthew Ashcraft
Richard Thaik
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Applied Micro Circuits Corporation
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Priority to PCT/US2015/042199 priority Critical patent/WO2017019008A1/fr
Publication of WO2017019008A1 publication Critical patent/WO2017019008A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1021—Hit rate improvement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6024—History based prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6028—Prefetching based on hints or prefetch instructions

Definitions

  • This disclosure relates to hazard prediction for a group of memory access instructions using a buffer associated with branch prediction.
  • processor systems can implement an instruction pipeline to increase throughput of processor instructions (e.g., load instructions and store instructions).
  • an instruction pipeline can be divided into multiple stages (e.g., fetch instruction, decode instruction, execute instruction, write-back instruction, etc.) to allow processing of multiple processor instructions in parallel.
  • a processor can implement out-of-order execution to execute processor instructions based on availability (e.g., availability of processor instructions) rather than an original program order for the processor instructions.
  • each processor instruction e.g., load instruction and/or store instruction
  • the processor instructions e.g., load instructions and/or stores instructions
  • a processor can avoid being in an idle state while data is retrieved for a next processor instruction (e.g., a processor can process a next processor instruction as soon as data operands associated with the next processor instruction are available).
  • out-of-order execution can lead to memory order violations (e.g., reordering issues), incorrect data, etc.
  • out-of-order execution can lead to an instruction pipeline hazard (e.g., a read after write (RAW) hazard, a write after read (WAR) hazard, a write after write (WAW) hazard, etc.).
  • a memory order violation e.g., an instruction pipeline hazard
  • the violating processor instruction e.g., load instruction or store instruction
  • each subsequent processor instruction are re-executed (e.g., the data structure employed for out- of-order execution is erased and/or reformatted).
  • a system comprises a fetch component and an execution component.
  • the fetch component is configured for storing a hazard prediction entry associated with a group of memory access instructions in a buffer associated with branch prediction.
  • the execution component is configured for executing a memory access instruction associated with the group of memory access instructions as a function of the prediction entry.
  • the hazard prediction entry is configured for predicting whether a group of memory access instructions is associated with an instruction pipeline hazard.
  • a method comprises storing a prediction entry, for predicting whether a group of memory access instructions is associated with an instruction pipeline hazard, in a buffer associated with branch prediction. Furthermore, the method comprises executing a memory access instruction associated with the group of memory access instructions as a function of the prediction entry.
  • a system in yet another embodiment, includes means for storing a hazard prediction entry, for predicting whether a group of memory access instructions is associated with an instruction pipeline hazard, in a buffer associated with branch prediction.
  • the system also includes means for executing a memory access instruction associated with the group of memory access instructions as a function of the hazard prediction entry.
  • FIG. 1 is a block diagram illustrating an example of a processor system.
  • FIG. 2 is a block diagram illustrating an example of a fetch component in a processor system.
  • FIG. 3 is a block diagram illustrating an example of a prediction component in a processor system.
  • FIG. 4 is a block diagram illustrating an example of a branch target buffer.
  • FIG. 5 is a block diagram illustrating an example of an execution component in a processor system.
  • FIG. 6 is a block diagram illustrating an example of a shared memory system.
  • FIG. 7 is a block diagram illustrating an example of a
  • FIG. 8 illustrates a flow diagram of an example of a method for implementing prediction associated with memory hazards in connection with branch prediction.
  • FIG. 9 illustrates a flow diagram of an example of a method for predicting a hazard associated with load/store execution.
  • FIG. 10 illustrates a flow diagram of an example of a method for employing a branch target buffer (BTB) for hazard prediction.
  • BTB branch target buffer
  • FIG. 11 illustrates a flow diagram of an example of a method for implementing a BTB and an instruction cache to facilitate hazard prediction.
  • FIG. 12 illustrates a flow diagram of an example of a method for facilitating hazard prediction for one or more memory access instructions.
  • FIG. 13 illustrates a block diagram of an example electronic computing environment.
  • FIG. 14 illustrates a block diagram of an example data
  • hazard predictions e.g., instruction pipeline hazard predictions, memory ordering pipeline hazards, predictions for ordering violation, predictions for load/store ordering violations, predictions for memory order violations, etc.
  • hazard predictions for processor instructions can be stored in a branch prediction pipeline rather than a cache or a separate data structure in a load/store pipeline (e.g., an execution pipeline).
  • hazard predictions for processor instructions can be stored in a branch target buffer (BTB).
  • hazard predictions for processor instructions can be tagged as aggressive or conservative and/or stored in the branch prediction pipeline (e.g., the BTB) as an aggressive value or a conservative value.
  • the BTB can be associated with more processor instructions than an instruction cache implemented in the branch prediction pipeline.
  • a history e.g., an execution history and/or an memory hazard history
  • instruction pipeline hazards and/or memory ordering pipeline hazards e.g., a read after read (RAR) hazard, a read after write (RAW) hazard, a write after read (WAR) hazard, a write after write (WAW) hazard, etc.
  • hazard prediction cost e.g., data structure size for hazard predictions
  • complexity e.g., difficulty
  • FIG. 1 is a block diagram illustrating an example of a processor system for facilitating hazard prediction (e.g., management and/or generation of hazard predictions) in accordance with various aspects described herein.
  • hazard prediction e.g., management and/or generation of hazard predictions
  • System 100 includes fetch component 102 and execution component 104.
  • fetch component 102 can be implemented as a front end component.
  • fetch component 102 can be implemented as an instruction cache and fetch (ICF) component.
  • execution component 104 can be implemented as a back end component.
  • execution component 104 can be implemented as at least one load-store (LSU).
  • Fetch component 102 can include a buffer 106.
  • buffer 106 can be associated with branch prediction and hazard prediction (e.g., buffer 106 can be configured for storing information associated with branch prediction and hazard prediction).
  • buffer 106 can be employed to predict a next processor instruction fetch (e.g., branch prediction) and to predict whether a processor instruction (e.g., a memory access instruction, a load instruction, a store instruction, etc.) is associated with an instruction pipeline hazard and/or a memory ordering pipeline hazard (e.g., hazard prediction).
  • a processor instruction e.g., a memory access instruction, a load instruction, a store instruction, etc.
  • buffer 106 can be implemented as a cache memory.
  • buffer 106 can be a BTB.
  • System 100 can be implemented in a processor system.
  • system 100 can be implemented in a multiprocessor system and/or a shared memory system.
  • system 100 can be implemented in a memory management apparatus.
  • a processor e.g., a central processing unit (CPU)
  • CPU central processing unit
  • system 100 can be implemented to facilitate an instruction cycle (e.g., a fetch-and-execute cycle) of a CPU.
  • System 100 can be configured to execute processor instructions (e.g., load instructions, store instructions and/or other types of memory access instructions) out-of-order (e.g., system 100 can implement out-of-order
  • processor instructions e.g., load instructions, store instructions and/or other types of memory access instructions
  • out-of-order e.g., system 100 can implement out-of-order
  • system 100 can be configured to predict memory order violations (e.g., memory ordering pipeline hazards) and/or instruction pipeline hazards based on hazard prediction entries stored in buffer 106 (e.g., a buffer associated with branch prediction).
  • a load instruction can be a processor instruction to read data from memory.
  • a store instruction can be a processor instruction to update data (e.g., write data) to memory.
  • Fetch component 102 can receive one or more processor instructions (e.g., PROCESSOR INSTRUCTION(S) shown in FIG. 1).
  • fetch component 102 can receive one or more memory access instructions.
  • fetch component 102 can receive a load instruction (e.g., a load operation), a store instruction (e.g., a store operation) and/or another type of memory access instruction (e.g., another type of memory access operation).
  • the one or more processor instructions can be received from memory (e.g., main memory).
  • fetch component 102 can implement at least an instruction cache component (e.g., a Level-1 cache component) and/or an instruction fetch component in addition to the buffer 106.
  • the fetch component 102 can implement a fetch cycle for the memory access instruction (e.g., load instruction, store instruction, another type of memory access instruction, etc.). For example, the fetch component 102 can fetch load/store instructions.
  • the execution component 104 can implement an execute cycle (e.g., out-of-order execution) for the memory access instruction (e.g., load instruction, store instruction, another type of memory access instruction, etc.).
  • Fetch component 102 can facilitate prediction to predict whether the memory access instruction (e.g., load instruction, store instruction, another type of memory access instruction, etc.) is associated with (e.g., will be associated with) a memory hazard (e.g., an instruction pipeline hazard, a memory ordering pipeline hazard, a load/store ordering violation, etc.).
  • a memory hazard e.g., an instruction pipeline hazard, a memory ordering pipeline hazard, a load/store ordering violation, etc.
  • an instruction pipeline hazard and/or a memory ordering pipeline hazard can be a data hazard (e.g., a RAR hazard, a RAW hazard, a WAR hazard, a WAW hazard, etc.).
  • Fetch component 102 can utilize a hazard prediction entry to predict whether a group of instructions (e.g., a group of memory access instructions) is associated with a memory hazard (e.g., an instruction pipeline hazard, a memory ordering pipeline hazard, a load/store ordering violation, etc.).
  • fetch component 102 can utilize a first hazard prediction entry to predict whether a first group of instructions is associated with an instruction pipeline hazard and/or a memory ordering pipeline hazard, a second hazard prediction entry to predict whether a second group of instructions is associated with an instruction pipeline hazard and/or a memory ordering pipeline hazard, etc.
  • a group of instructions can include, but is not limited to, one or more groups of load instructions, one or more groups of store instructions and/or one or more groups of other memory access instructions.
  • fetch component 102 can utilize (e.g., store) one or more hazard prediction entries.
  • the one or more hazard prediction entries can be stored in buffer 106 (e.g., a buffer associated with branch prediction).
  • buffer 106 can be configured as a BTB.
  • the BTB can be a branch target cache.
  • the BTB can be configured to store a predicted address for a next instruction after a branch (e.g., after initiation of a different instruction sequence).
  • the BTB can be configured to predict a next instruction address before a particular instruction is decoded.
  • a column of the BTB can include a set of instruction addresses (e.g., addresses of one or more branches).
  • another column of the BTB can include a set of predictions for a next program counter after a branch.
  • yet another column of the BTB can include prediction state information (e.g., prediction state bits). Therefore, the BTB can be configured to identify a branch and/or predict a target of a branch instruction.
  • the BTB can also be configured to store a hazard prediction for an instruction (e.g., a group of instructions). As such, a branch prediction entry and a hazard prediction entry for each group of instructions (e.g., each group of memory access instructions) can be stored in a BTB.
  • a BTB entry can be associated with branch prediction (e.g., one or more branch predictors) and hazard prediction (e.g., one or more hazard prediction entries) to predict whether a group of instructions is associated with an instruction pipeline hazard and/or a memory ordering pipeline hazard.
  • branch prediction e.g., one or more branch predictors
  • hazard prediction e.g., one or more hazard prediction entries
  • buffer 106 e.g. the BTB
  • buffer 106 can store more instructions than an instruction cache associated with (e.g., included in) fetch component 102.
  • Execution component 104 can execute an instruction associated with the group of instructions (e.g., the first group of instructions, the second group of instructions, etc.) as a function of the hazard prediction entry. In one example, execution component 104 can execute each memory access
  • execution component 104 can execute another type of memory access instruction in a group of instructions as a function of a hazard prediction entry associated with each instruction (e.g., the group of instructions).
  • the group of instructions e.g., the first group of instructions, the second group of instructions, etc.
  • execution component 104 can receive and/or execute instruction(s) received from an instruction cache.
  • execution component 104 can implement out-of-order execution to execute the instruction(s).
  • execution component 104 can be associated with a queue buffer (e.g., a load buffer) to store the group of instructions and/or execute the group of instructions out-of-order.
  • a queue buffer e.g., a load buffer
  • the hazard prediction entries stored in buffer 106 can be updated as a function of instruction dependencies an instruction pipeline hazard and/or a memory ordering pipeline hazard.
  • a particular hazard prediction entry stored in buffer 106 can be updated based at least on dependency (e.g., data dependency) between a load instruction associated with the particular hazard prediction entry and one or more store instructions associated with the load instruction (e.g., a particular hazard prediction entry stored in buffer 106 can be updated based on speculative execution of a load instruction).
  • a particular hazard prediction entry stored in buffer 106 can be updated based on whether a memory access instruction (e.g., a load instruction, a store instruction, another type of memory access instruction, etc.) associated with the particular hazard prediction is associated with an instruction pipeline hazard and/or a memory ordering pipeline hazard.
  • a hazard prediction entry for a group of memory access instructions e.g., group of load instructions, group of store instructions, etc.
  • Buffer 106 can facilitate prediction to speculate whether one or more instructions are associated with an instruction pipeline hazard and/or a memory ordering pipeline hazard.
  • Each hazard prediction value stored in buffer 106 can be associated with likelihood of an instruction pipeline hazard and/or a memory ordering pipeline hazard for a group of instructions (e.g., a group of memory access instructions).
  • a particular hazard prediction value can correspond to a higher likelihood of an instruction pipeline hazard and/or a memory ordering pipeline hazard.
  • a hazard prediction value can be determined based on likelihood of an instruction pipeline hazard and/or a memory ordering pipeline hazard.
  • each hazard prediction entry stored in buffer 106 can be assigned a hazard prediction value (e.g., a bit value).
  • a hazard prediction value e.g., a bit value
  • an aggressive value e.g., a first bit value
  • a conservative value e.g., a second bit value
  • each hazard prediction entry stored in buffer 106 can be assigned a single bit value.
  • an aggressive value can be a bit value equal to "1 " (or a bit value equal to "0") and a conservative value can be a bit value equal to "0" (or a bit value equal to "1 ").
  • a hazard prediction entry can include a greater number of bit values (e.g., two bits, three bits, etc.).
  • Each of the hazard prediction entries in buffer 106 can be initially assigned an aggressive value (e.g., a first bit value).
  • memory access instructions e.g., a group of memory access instructions
  • the hazard prediction entries in buffer 106 can be updated based on execution of memory access instruction(s) associated with the hazard prediction entries.
  • a conservative value (e.g., a second bit value) can be assigned to a hazard prediction entry in response to a determination that a memory access instruction (e.g., a memory access instruction in a group of memory access instructions associated with the hazard prediction entry) is associated with an instruction pipeline hazard and/or a memory ordering pipeline hazard.
  • a conservative value (e.g., a second bit value) can be assigned to a hazard prediction entry in response to a determination that a memory access instruction (e.g., a load instruction) is additionally executed speculatively (e.g., executed before one or more store instructions associated with the load instruction).
  • memory access instructions associated with an updated hazard prediction entry can be marked as conservative (e.g., assigned a conservative value) in response to the updating of the hazard prediction entry in buffer 106 (e.g., the BTB).
  • execution component 104 can execute a memory access instruction by employing in-order execution in response to a prediction that the memory access instruction is associated with a memory hazard (e.g., an instruction pipeline hazard and/or a memory ordering pipeline hazard).
  • execution component 104 can execute a memory access instruction by employing out-of-order execution in response to a prediction that the memory access instruction is not associated with a memory hazard (e.g., an instruction pipeline hazard and/or a memory ordering pipeline hazard).
  • a memory hazard e.g., an instruction pipeline hazard and/or a memory ordering pipeline hazard
  • execution component 104 can notify fetch component 102 via a signal that a memory access instruction is associated with an instruction pipeline hazard and/or a memory ordering pipeline hazard in response to a determination that the memory access instruction has executed out-of-order.
  • execution component 104 can generate a signal (e.g., an abort signal) in response to a determination that a memory access instruction is executed speculatively and/or that the memory access instruction is associated with an instruction pipeline hazard and/or a memory ordering pipeline hazard.
  • hazard prediction entries can be updated as a function of a signal generated by execution component 104 (e.g., an abort signal).
  • the signal (e.g., the abort signal) can comprise a branch checkpoint associated with the instruction pipeline hazard and/or the memory ordering pipeline hazard. Additionally, the signal (e.g., the abort signal) can indicate that the instruction pipeline hazard and/or a memory ordering pipeline hazard occurred because the memory access instruction executed speculatively (e.g., the memory access instruction executed out-of-order, a load instruction should have waited for all previous store instructions associated with the load instruction to execute, etc.).
  • Fetch component 102 can communicate directly with execution component 104.
  • fetch component 102 and/or execution component 104 can be coupled to a memory subsystem (MSS) 108.
  • the MSS 108 can include one or more memory components (e.g., one or more cache memories, one or more components associated with virtual memory, etc.) and/or one or more controllers. However, MSS 108 can include additional components.
  • MSS 108 can be associated with a Level-1 cache, a Level-2 cache and/or main memory.
  • FIG. 2 is a block diagram illustrating an example of a system in accordance with various aspects described herein.
  • System 200 can include fetch component 102 and execution component 104.
  • fetch component 102 can directly communicate with execution component 104.
  • fetch component 102 and/or execution component 104 can be coupled to the MSS 108.
  • Fetch component 102 can include a branch target buffer (BTB) 202 and an instruction cache 204.
  • BTB 202 can correspond to buffer 106.
  • the BTB 202 can be implemented as a cache memory (e.g., a branch target cache).
  • the BTB 202 can be associated with branch prediction and hazard prediction.
  • BTB 202 can facilitate branch prediction and memory hazard prediction (e.g., instruction pipeline hazard prediction, memory ordering pipeline hazard prediction, etc.).
  • the BTB 202 can store one or more hazard predictions (e.g., one or more hazard prediction values) associated with instruction pipeline hazard(s) and/or memory ordering pipeline hazard(s).
  • BTB 202 can generate and/or store a hazard prediction value (e.g., an instruction pipeline hazard prediction value, a memory ordering pipeline hazard value) for one or more memory access instructions.
  • BTB 202 can implement a hash table to store the one or more hazard prediction values.
  • the BTB 202 can provide a hazard prediction to speculate whether a memory access instruction will have an instruction pipeline hazard and/or a memory ordering pipeline hazard when executed.
  • Execution component 104 can perform load/store ordering (e.g., execute memory access instructions) based at least in part on instruction pipeline hazard predictions and/or memory ordering pipeline hazard predictions (e.g., the one or more hazard prediction values) stored in BTB 202.
  • a BTB entry of BTB 202 can be associated with one or more memory access instructions (e.g., a BTB entry of BTB 202 can be associated with multiple memory access instructions).
  • the BTB 202 can include a plurality of fields.
  • each BTB entry in BTB 202 can include at least a branch prediction field and a hazard prediction field.
  • each hazard prediction field of BTB 202 can be initialized with an aggressive value (e.g., a value to permit memory access instructions, load instructions, store instructions, etc. to execute immediately).
  • an aggressive value e.g., a value to permit memory access instructions, load instructions, store instructions, etc. to execute immediately.
  • each memory access instruction associated with a particular hazard prediction field can execute speculatively.
  • a hazard prediction field of BTB 202 can be updated as a function of execution of one or more memory access instructions associated with the hazard prediction field, an instruction pipeline hazard associated with the one or more memory access instructions and/or a memory ordering pipeline hazard associated with the one or more memory access instructions.
  • a hazard prediction field of BTB 202 can be updated with a conservative value (e.g., a value to not permit memory access instructions to execute immediately).
  • each memory access instruction e.g., a group of memory access instructions
  • each memory access instruction associated with a particular hazard prediction field can execute after waiting for associated store instruction to execute.
  • an instruction e.g., a group of memory access instructions
  • aggressive value can be a first bit value (e.g., a single bit value) and a
  • BTB 202 can store information associated with execution of one or more memory access instructions, instruction pipeline hazards associated with the one or more memory access instructions and/or memory ordering pipeline hazards associated with the one or more memory access instructions.
  • BTB 202 can facilitate branch prediction in addition to the hazard prediction.
  • BTB 202 can be implemented to predict a next fetch in an instruction pipeline.
  • BTB 202 can store one or more branch prediction values.
  • BTB 202 can store one or more branch predictions associated with a path of a branch (e.g., information regarding whether a next sequence of data will be taken) and/or information utilized by a branch.
  • a branch prediction pipeline associated with BTB 202 can facilitate hazard prediction (e.g., prediction of instruction pipeline hazards, prediction of memory ordering pipeline hazards, etc.) and/or branch prediction.
  • Instruction cache 204 can store one or more memory access instructions.
  • instruction cache 204 can store the group of memory access instructions (e.g., the first group of memory access instructions, the second group of memory access instructions, etc.) associated with BTB 202.
  • BTB 202 can be configured to store more predictions (e.g., hazard predictions) than memory access instructions stored in instruction cache 204.
  • BTB 202 can maintain (e.g., store) a history of memory access instructions (e.g., a history of hazard predictions for memory access instructions) currently stored in instruction cache 204 and/or other memory access instructions not stored in instruction cache 204 (e.g., previously stored in instruction cache 204, stored in another cache, etc.).
  • the one or more memory access instructions stored in instruction cache 204 can be transmitted to execution component 104 for execution.
  • FIG. 3 is a block diagram illustrating an example of a system in accordance with various aspects described herein.
  • System 300 can include fetch component 102 and execution component 104.
  • Fetch component 102 can include BTB 202 and/or the instruction cache 204.
  • BTB 202 can correspond to buffer 106.
  • Fetch component 102 and/or execution component 104 can be associated with a prediction component 302.
  • the prediction component 302 can be implemented separate from fetch component 102 and execution component 104.
  • the fetch component 102 can include prediction component 302.
  • execution component 104 can include prediction component 302.
  • Prediction component 302 can manage (e.g., initialize and/or update) BTB 202.
  • prediction component 302 can manage hazard prediction entries for memory access instructions.
  • Prediction component 302 can initially assign an aggressive value to each of the one or more hazard prediction entries in BTB 202.
  • memory access instruction(s) associated with the one or more hazard prediction entries in BTB 202 can execute immediately (e.g., speculatively) without waiting for previous store instructions to execute when assigned an aggressive value.
  • prediction component 302 can facilitate dynamic learning and/or updating of hazard prediction entries.
  • prediction component 302 can monitor fetch component 102 and/or execution component 104.
  • prediction component 302 can monitor fetch component 102 and/or execution component 104 to determine whether an instruction pipeline hazard, a memory ordering pipeline hazard and/or a dependency issue exists.
  • Prediction component 302 can determine which memory access instruction is associated with an instruction pipeline hazard, a memory ordering pipeline hazard and/or a dependency issue.
  • prediction component 302 can determine which hazard prediction entry stored in BTB 202 is associated with the memory access instruction associated with the instruction pipeline hazard, a memory ordering pipeline hazard and/or a dependency issue (e.g., prediction component 302 can determine which hazard prediction entry stored in BTB 202 to update based on the instruction pipeline hazard, the memory ordering pipeline hazard and/or the dependency issue).
  • Prediction component 302 can assign a conservative value to a hazard prediction entry for a particular memory access instruction of the one or more memory access instructions in response to a determination that an instruction pipeline hazard and/or a memory ordering pipeline hazard has occurred.
  • prediction component 302 can assign a conservative value to a hazard prediction entry for a particular memory access instruction of the one or more memory access instructions in response to a determination that a particular load instruction is executed speculatively (e.g., before a store instruction associated with the particular load instruction) and that an instruction pipeline hazard and/or a memory ordering pipeline hazard has occurred.
  • prediction component 302 can tag memory access instructions with a hazard prediction value (e.g., associate and/or assign a hazard prediction value to one or more memory access instructions). For example, in response to a hazard prediction entry in BTB 202 being initialized and/or updated, prediction component 302 can associate a hazard prediction value (e.g., an aggressive value or a conservative value) with memory access instruction(s) associated with the hazard prediction entry. Therefore, prediction component 302 can tag memory access instruction(s) stored in instruction cache 204 as a function of the hazard prediction entries stored in BTB 202.
  • a hazard prediction value e.g., an aggressive value or a conservative value
  • execution component 104 can notify fetch component 102 via a signal that a memory access instruction is associated with an instruction pipeline hazard in response to a determination that the memory access instruction has executed out-of-order. For example, execution
  • component 104 can generate an abort signal in response to a determination that a load instruction is executed speculatively before a store instruction associated with the load instruction and/or that the load instruction is associated with an instruction pipeline hazard and/or a memory ordering pipeline hazard.
  • the abort signal can include a branch checkpoint associated with a memory access instruction.
  • prediction component 302 can receive an abort signal (e.g., a signal that indicates that a memory access instruction is associated with an instruction pipeline hazard and/or a memory ordering pipeline hazard) generated by execution component 104.
  • hazard prediction entries of BTB 202 can be updated in response to the abort signal generated by execution component 104.
  • FIG. 4 is a block diagram illustrating an example of a BTB in accordance with various aspects described herein.
  • BTB 400 can include BTB entries 402a-n, branch prediction entries 404a-n and hazard prediction entries (e.g., instruction pipeline hazard prediction entries, memory ordering pipeline hazard prediction entries, dependence prediction entries, etc.) 406a-n.
  • BTB 202 and/or buffer 106 can implement BTB 400.
  • BTB entry 402a can be associated with a first group of instructions (e.g., a first group of memory access instructions), BTB entry 402 be can be associated with a second group of instructions (e.g., a second group of memory access instructions), etc.
  • BTB entry 402a can be associated with one or more instructions (e.g., one or more instructions stored in instruction cache 204), BTB entry 402b can be associated with one or more other instructions (e.g., one or more other instructions stored in instruction cache 204), etc. Additionally, BTB entry 402a can be associated with one or more different instructions (e.g., one or more different instructions not stored in instruction cache 204), BTB entry 402b can be associated with one or more other different instructions (e.g., one or more other different instructions not stored in instruction cache 204), etc.
  • a group of instructions e.g., the first group of instructions, the second group of instructions, etc.
  • a group of instructions (e.g., the first group of instructions, the second group of instructions, etc.) can additionally or alternatively include one or more groups of store instructions.
  • a group of instructions (e.g., the first group of instructions, the second group of instructions, etc.) can additionally or alternatively include one or more groups of different memory access instructions.
  • Branch prediction entry 404a can facilitate branch prediction for BTB entry 402a (e.g., the first group of instructions associated with BTB entry 402a), branch prediction entry 404b can facilitate branch prediction for BTB entry 402b (e.g., the second group of instructions associated with BTB entry 402b), etc.
  • Hazard prediction entry 406a can facilitate instruction pipeline hazard prediction, memory ordering pipeline hazard prediction and/or data dependency prediction for BTB entry 402a (e.g., the first group of instructions associated with BTB entry 402a), hazard prediction entry 406b can facilitate instruction pipeline hazard prediction, memory ordering pipeline hazard prediction and/or
  • Hazard prediction entries 406a-n can be initialized with an aggressive value (e.g., via prediction component 302).
  • prediction component 302 can assign an aggressive value to instructions associated with hazard prediction entries 406a-n in response to the hazard prediction entries 406a-n being initialized.
  • hazard prediction entries 406a-n can be updated as a function of execution of one or more instructions associated with hazard prediction entries 406a-n, a memory ordering pipeline hazard associated with hazard prediction entries 406a-n and/or an instruction pipeline hazard associated with hazard prediction entries 406a-n.
  • hazard prediction entries 406a-n can be updated with a conservative value as a function of execution of one or more instructions associated with hazard prediction entries 406a-n, an occurrence of a memory ordering pipeline hazard when executing the one or more instructions associated with hazard prediction entries 406a-n and/or an occurrence of an instruction pipeline hazard when executing the one or more instructions associated with hazard prediction entries 406a-n.
  • prediction component 302 can assign a conservative value to one or more instructions associated with a particular hazard prediction entry 406a-n in response to particular hazard prediction entry 406a-n being updated.
  • hazard prediction entries 406a-n can be updated as a function of an abort signal (e.g., an abort signal indicating that an instruction pipeline hazard and/or a memory ordering pipeline hazard has occurred).
  • hazard prediction entry 406a is updated in response to a determination that an instruction associated with BTB entry 402a is associated with a memory ordering pipeline hazard and/or an instruction pipeline hazard.
  • the instruction associated with BTB entry 402 can be assigned a new value (e.g., a value updated in hazard prediction entry 406a).
  • FIG. 5 is a block diagram illustrating an example of a system in accordance with various aspects described herein.
  • System 500 can include fetch component 102 and execution component 104.
  • Fetch component 102 can include BTB 202 and/or instruction cache 204.
  • BTB 202 can correspond to buffer 106.
  • Fetch component 102 and/or execution component 104 can be associated with the prediction component 302.
  • Execution component 104 can be associated with a queue buffer 502.
  • execution component 104 can include queue buffer 502.
  • queue buffer 502 can be implemented separate from execution component 104.
  • queue buffer 502 can be implemented as load queue (or a load/store queue).
  • queue buffer 502 can be implemented as a store forwarding buffer.
  • Queue buffer 502 can facilitate out-of-order execution of memory access instructions (e.g., load instructions stored in instruction cache 204, store instructions stored in instruction cache 204, etc.).
  • memory access instructions e.g., load instructions
  • the memory access instructions (e.g., load instructions) allocated to queue buffer 502 can be executed out-of-order.
  • the memory access instructions (e.g., load instructions) allocated to queue buffer 502 can be received from instruction cache 204.
  • the memory access instructions (e.g., load instructions) can be allocated to queue buffer 502 and/or executed from queue buffer 502 as a function of the hazard prediction values.
  • ordering between load instructions and store instructions can be performed based at least in part on hazard prediction (e.g., hazard prediction values stored in BTB 202).
  • hazard prediction entries of BTB 202 e.g., buffer 106
  • FIG. 6 is a block diagram illustrating an example of a system in accordance with various aspects described herein.
  • System 600 can include a processor 602, a cache memory 604, a cache controller 606 and a main memory 608.
  • Processor 602 can correspond to system 100, system 200, system 300 or system 500.
  • processor 602 can include the fetch component 102, execution component 104, buffer 106 (e.g., BTB 202), MSS 108, instruction cache 204, prediction component 302 and/or queue buffer 502.
  • cache memory 604, cache controller 606 and/or main memory 608 can be implemented in MSS 108.
  • cache memory 604 can be implemented as a primary cache (e.g., a Level-1 cache). In another example, the cache memory 604 can be implemented as a secondary cache (e.g., a Level-2 cache).
  • cache memory 604 can be implemented as a different type of cache memory.
  • cache memory 604 can include one or more levels of cache.
  • Cache controller 606 can manage cache memory 604 so that cache memory 604 includes a most recent copy of data that matches data in the main memory 608 (e.g., system memory 608).
  • main memory 608 e.g., system memory 608
  • cache controller 606 can manage cache memory 604 so that cache memory 604 includes a most recent copy of processor instructions that match processor instructions in main memory 608 (e.g., system memory 608).
  • Main memory 608 can be main memory of a multiprocessor system (e.g., memory that one or more processors can read and write to).
  • Main memory 608 can store one or more memory access instructions (e.g., one or more load instructions, one or more store instructions and/or one or more other memory access instructions).
  • fetch component 102 can receive memory access instruction(s) (e.g., load instruction(s), a store
  • main memory 608 main memory 608.
  • FIG. 7 is a block diagram illustrating an example of a system in accordance with various aspects described herein.
  • system 700 can be implemented as a shared-memory multiprocessor system.
  • System 700 can include one or more processing components 702a- n and main memory 608.
  • System 700 can also include one or more processor 602a-n, one or more cache memories 604a-n and one or more cache controllers 606a-n.
  • Each of the one or more processing components 702a-n can include a processor (e.g., processor 602 shown in FIG. 6), a cache memory (e.g., cache memory 604 shown in FIG. 6) and/or a cache controller (e.g., cache controller 606 shown in FIG. 6).
  • processing component 702a can include processor 602a, cache memory 604a and cache controller 606a
  • processing component 702b can include processor 602b, cache memory 604b and cache controller 606b, etc.
  • a cache controller (e.g. a cache controller 606a-n) can be implemented separate from a processor (e.g., a processor 602a- n).
  • a processor e.g., a processor 602a-n
  • a cache controller e.g., a cache controller 606a-n
  • the one or more processors 602a-n can be implemented as processor cores (e.g., processor cores in a multi-core processor).
  • a copy of data stored in main memory 608 can be stored in each of cache memories 604a-n.
  • a copy of processor instructions stored in main memory 608 can be stored in each of cache memories 604a-n. Therefore, when data is updated in main memory 608, the copies of the data stored in each of cache memories 604a-n can also be updated.
  • one or more cache controllers 606a-n can manage cache memories 604a-n so that a most recent copy of data (e.g., processor instructions) is stored in each of cache memories 604a-n (e.g., a copy of data that matches data in main memory 608 is stored in each of cache memories 604a-n). Therefore, cache coherency while executing processor instructions out-of-order can be achieved.
  • a cache controller, a processor and/or a cache memory in each processing component 702a-n can be coupled via a bus (e.g., a bus 710 and/or a bus coupled to bus 710).
  • a bus e.g., a bus 710 and/or a bus coupled to bus 710.
  • only a cache controller in each processing component 702a-n can be coupled to bus 7 0, where the cache controller can additionally be coupled to a processor and a cache memory.
  • component 702a-n can isolate a processor and/or a cache memory from bus 710.
  • Methods that may be implemented in accordance with the described subject matter are described in the flow charts of FIGs. 8-12. While for purposes of simplicity of explanation, the methods are shown and described as a series of blocks, the claimed subject matter is not limited by the order of the blocks, as some blocks may occur in different orders and/or concurrently with other blocks from what is depicted and described herein.
  • FIG. 8 is a flow diagram of an example of a method for
  • Method 800 can begin at block 802, where a prediction entry, for predicting whether a group of memory access instructions associated with the memory access instruction is associated with an instruction pipeline hazard and/or a memory ordering pipeline hazard, is stored (e.g., by fetch component 102) in a buffer associated with branch prediction (e.g., buffer 106).
  • a hazard prediction entry to facilitate predicting whether a group of memory access instructions associated with the memory access instruction is associated with an instruction pipeline hazard and/or a memory ordering pipeline hazard, is stored in a BTB associated with branch prediction.
  • the memory access instruction associated with the group of memory access instructions is executed (e.g., by an execution component 104).
  • memory access instruction can be stored in an instruction cache (e.g., instruction cache 204).
  • the memory access instruction can be transmitted from the instruction cache to an execution component (e.g., execution component 104) to be executed (e.g., executed out- of-order).
  • Memory access instruction can be stored in a queue buffer (e.g., queue buffer 502) included in the execution component before being executed (e.g., to facilitate out-of-order execution of the memory access instruction).
  • the prediction entry for the group of memory access instructions is updated (e.g., by prediction component 302) as a function of the execution of the memory access instruction, the instruction pipeline hazard associated with the memory access instruction and/or the memory ordering pipeline hazard associated with the memory access instruction. For example, in response to a determination that a memory access instruction executed speculatively and/or that the memory access instruction is associated with an instruction pipeline hazard and/or a memory ordering pipeline hazard, a prediction entry in the BTB for the group of instructions that includes the memory access instruction is updated.
  • the memory access instruction can be updated in response to an abort signal (e.g., an abort signal being generated that indicates that an instruction pipeline hazard and/or a memory ordering pipeline hazard has occurred).
  • FIG. 9 is a flow diagram of another example of a method for predicting a hazard associated with load/store execution.
  • Method 900 can begin at block 902, branch target buffer (BTB) is configured (e.g., by fetch component 102 and/or a prediction component 302) for branch prediction and hazard prediction.
  • BTB 400 can be partitioned to store a branch prediction entry and a hazard prediction entry for each BTB entry 402a-n (e.g., each group of memory access instructions).
  • each hazard prediction entry in the BTB is initialized (e.g., by prediction component 302) with an aggressive value (e.g., a value to execute memory access instruction(s) immediately).
  • an aggressive value e.g., a value to execute memory access instruction(s) immediately.
  • hazard prediction entries 406a-n can be initialized with an aggressive value (e.g., a value to permit one or more memory access instructions associated with a particular hazard prediction entry 406a-n to execute immediately).
  • one or more memory access instructions associated with each hazard prediction entry are tagged (e.g., by a prediction component 302) with the aggressive value. For example, a first group of memory access instructions associated with hazard prediction entry 406a is tagged with an aggressive value, a second group of memory access instructions associated with hazard prediction entry 406b is tagged with an aggressive value, etc.
  • a hazard prediction entry in the BTB is updated (e.g., by prediction component 302) with a conservative value (e.g., a value to wait to execute memory access instruction(s) until other memory access instructions are executed) in response to at least a determination the memory access instruction is associated with a memory hazard.
  • a conservative value e.g., a value to wait to execute memory access instruction(s) until other memory access instructions are executed
  • a memory access instruction e.g., a load instruction
  • a particular hazard prediction entry 406a-n e.g., hazard prediction entry 406a
  • the particular hazard prediction entry 406a-n e.g., hazard prediction entry 406a
  • a conservative value e.g., a value to wait to execute one or more memory access instructions associated with a particular hazard prediction entry 406a-n until previous memory access instructions associated with the one or more memory access instructions are executed.
  • each memory access instruction e.g., group of memory access
  • hazard prediction entry 406a-n e.g., hazard prediction entry 406a
  • one or more memory access instructions associated with the hazard prediction entry are tagged (e.g., by prediction component 302) with the conservative value.
  • each memory access instruction e.g., the group of memory access instructions
  • the particular hazard prediction entry 406a-n e.g., hazard prediction entry 406a
  • FIG. 10 is a flow diagram of an example of a method for employing a BTB for hazard prediction.
  • Method 000 can begin at block 1002, where a memory access instruction is received (e.g., by fetch component 102).
  • a memory access instruction e.g., a processor instruction
  • the memory access instruction can be received from main memory (e.g., main memory 608).
  • a prediction value is generated (e.g., by a prediction component 302) to predict whether a memory access instruction and/or a group of memory access instructions associated with the memory access instruction is associated with a memory hazard.
  • a prediction value is generated (e.g., by a prediction component 302) to predict whether a memory access instruction and/or a group of memory access instructions associated with the memory access instruction is associated with a memory hazard.
  • an aggressive value or a conservative value can be generated to predict whether a memory access instruction and/or a group of memory access instructions associated with the memory access instruction is associated with an instruction pipeline hazard and/or a memory ordering pipeline hazard.
  • a branch target buffer is updated (e.g., by prediction component 302) based on the prediction value that predicts whether the memory access instruction and/or the group of memory access instructions is associated with a memory hazard.
  • prediction value can be stored in a BTB entry (e.g., a BTB entry associated with a group of memory access instructions).
  • a prediction for more than one memory access instruction can be updated based on the prediction value that predicts whether the memory access instruction is associated with an instruction pipeline hazard and/or a memory ordering pipeline hazard.
  • the prediction value can be initially set as an aggressive value.
  • the prediction value can be updated as a conservative value based on the prediction value that predicts whether the memory access instruction is associated with an instruction pipeline hazard and/or a memory ordering pipeline hazard.
  • the memory access instruction is executed based on the prediction value. For example, if the prediction value is set as an aggressive value, the memory access instruction can be executed immediately. In another example, if a prediction value is a conservative value, a load instruction can wait to be executed until previous store instruction(s) associated with the load instruction are executed.
  • FIG. 11 is a flow diagram of an example of a method for
  • Method 1100 can begin at block 1102, where one or more memory access instructions are stored in an instruction cache (e.g., via a fetch component 102). For example, one or more memory access instructions can be stored in instruction cache 204 included in fetch component 102.
  • a hazard prediction value for each of the one or more memory access instructions and/or one or more other memory access instructions are stored in a buffer associated with branch prediction (e.g., via a fetch component 102).
  • a hazard prediction value for each of the one or more memory access instructions stored in instruction cache 204 and/or one or more other memory access instructions not stored in instruction cache 204 can be stored in BTB 202.
  • BTB 202 can include more memory access instructions than memory access instructions stored in instruction cache 204. Therefore, a history of memory access instructions and/or BTB entries can be generated.
  • the one or more memory access instructions stored in the instruction cache are executed (e.g., via an execution component) based on a respective hazard prediction value.
  • the one or more memory access instructions stored in instruction cache 204 can be transmitted to execution component 104.
  • the one or more memory access instructions can be stored in queue buffer 502 prior to being executed (e.g., the one or more memory access instructions can be executed out of order).
  • the hazard prediction values for each of the one or more memory access instructions are updated (e.g., via a prediction component 302) based on the execution of the one or more memory access instructions.
  • prediction component 302 can monitor execution of the one or more memory access instructions to determine whether an instruction pipeline hazard and/or a memory ordering pipeline hazard has occurred.
  • a hazard prediction entry for a memory access instruction associated with the instruction pipeline hazard and/or the memory ordering pipeline hazard can be updated.
  • FIG. 12 is a flow diagram of an example of a method for facilitating hazard prediction for one or more memory access instructions.
  • Method 1200 can begin at block 1202, where one or more hazard prediction values stored in a branch target buffer (BTB) are initialized (e.g., by a prediction component 302). For example, one or more hazard prediction values stored in BTB 202 can be initialized with an aggressive value.
  • BTB branch target buffer
  • each of the one or more hazard prediction values are monitored (e.g., by prediction component 302). For example, it can be determined whether an instruction pipeline hazard and/or a memory ordering pipeline hazard is associated with the one or more memory access instructions.
  • one or more hazard prediction values are updated (e.g., by prediction component 302) as a function of monitoring of the execution of the one or more memory access instructions.
  • a particular hazard prediction value can be updated (e.g., with a conservative value) in response to at least a determination that a particular memory access instruction is associated with an instruction pipeline hazard and/or a memory ordering pipeline hazard.
  • a particular hazard prediction value can be updated (e.g., with a conservative value) in response to a determination that an abort signal associated with the particular hazard prediction value (e.g., an abort signal indicating that an instruction pipeline hazard and/or a memory ordering pipeline hazard has occurred) has been generated.
  • an abort signal associated with the particular hazard prediction value e.g., an abort signal indicating that an instruction pipeline hazard and/or a memory ordering pipeline hazard has occurred
  • the techniques described herein can be applied to any device and/or network where prediction of memory hazards (e.g., instruction pipeline hazards, memory ordering pipeline hazards, etc.) is desirable. It is to be understood that handheld, portable and other computing devices and computing objects of all kinds are contemplated for use in connection with the various embodiments, i.e., anywhere that a device may wish to predict memory hazards (e.g., instruction pipeline hazards, memory ordering pipeline hazards, etc.).
  • the general purpose remote computer described below in FIG. 13 is but one example, and the disclosed subject matter can be implemented with any client having network/bus interoperability and interaction.
  • FIG. 13 illustrates an example of a suitable computing system environment 1300 in which aspects of the disclosed subject matter can be implemented, the computing system environment 1300 is only one example of a suitable computing environment for a device and is not intended to limit the scope of use or functionality of the disclosed subject matter.
  • FIG. 13 is an exemplary device for implementing the disclosed subject matter includes a general-purpose computing device in the form of a computer 1310.
  • Components of computer 1310 may include a processing unit 1320, a system memory 1330, and a system bus 1321 that couples various system components including the system memory to processing unit 1320.
  • System bus 1321 may be any of several types of bus structures including a memory bus or memory controller, a peripheral bus, and a local bus using any of a variety of bus architectures.
  • Computer 1310 typically includes a variety of computer readable media.
  • System memory 1330 may include computer storage media in the form of volatile and/or nonvolatile memory such as read only memory (ROM) and/or random access memory (RAM).
  • ROM read only memory
  • RAM random access memory
  • BIOS basic input/output system
  • Computer 1310 may also include other removable/non-removable,
  • a user can enter commands and information into the computer 1310 through input devices such as a keyboard and pointing device, commonly referred to as a mouse, trackball, or touch pad.
  • input devices such as a keyboard and pointing device, commonly referred to as a mouse, trackball, or touch pad.
  • Computer 1310 can operate in a networked or distributed environment using logical connections to one or more other remote computer(s), such as remote computer 1370, which can in turn have media capabilities different from device 1310.
  • FIG. 14 provides a schematic diagram of an exemplary networked or distributed computing environment.
  • the distributed computing environment comprises computing objects 1410, 1412, etc. and computing objects or devices 1420, 1422, 1424, 1426, 1428, etc., which may include programs, methods, data stores, programmable logic, etc., as represented by applications 1430, 1432, 1434, 1436, 1438 and data store(s) 1440.
  • Data store(s) 1440 can include one or more cache memories, one or more registers, or other similar data stores disclosed herein.
  • Each computing object 1410, 1412, etc. and computing objects or devices 1420, 1422, 1424, 1426, 1428, etc. can communicate with one or more other computing objects 1410, 1412, etc. and computing objects or devices 1420, 1422, 1424, 1426, 1428, etc. by way of the communications network 1442, either directly or indirectly.

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Abstract

L'invention concerne un système de composant d'extraction et de composant d'exécution et un procédé, le composant d'extraction étant conçu pour mémoriser une prédiction de danger associée à un groupe d'instructions d'accès mémoire dans un tampon associé avec une prédiction de branchement. Le composant d'exécution est conçu pour l'exécution d'une instruction d'accès mémoire associée avec le groupe d'instructions d'accès mémoire en fonction de l'entrée de prédiction de danger.
PCT/US2015/042199 2015-07-27 2015-07-27 Prédiction de danger pour un groupe d'instructions d'accès mémoire utilisant un tampon associé à une prédiction de branchement WO2017019008A1 (fr)

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WO2011076602A1 (fr) * 2009-12-22 2011-06-30 International Business Machines Corporation Prévision et évitement des risques de comparaison de stockage d'opérande dans des microprocesseurs en panne
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US5666506A (en) * 1994-10-24 1997-09-09 International Business Machines Corporation Apparatus to dynamically control the out-of-order execution of load/store instructions in a processor capable of dispatchng, issuing and executing multiple instructions in a single processor cycle
US20020138713A1 (en) * 2001-03-22 2002-09-26 International Business Machines Corporation Method and apparatus for using past history to avoid flush conditions in a microprocessor
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WO2011076602A1 (fr) * 2009-12-22 2011-06-30 International Business Machines Corporation Prévision et évitement des risques de comparaison de stockage d'opérande dans des microprocesseurs en panne
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