WO2017018216A1 - Solid-state imaging device, method for manufacturing same, and electronic device - Google Patents

Solid-state imaging device, method for manufacturing same, and electronic device Download PDF

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Publication number
WO2017018216A1
WO2017018216A1 PCT/JP2016/070651 JP2016070651W WO2017018216A1 WO 2017018216 A1 WO2017018216 A1 WO 2017018216A1 JP 2016070651 W JP2016070651 W JP 2016070651W WO 2017018216 A1 WO2017018216 A1 WO 2017018216A1
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Prior art keywords
guard ring
solid
state imaging
imaging device
insulating film
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PCT/JP2016/070651
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French (fr)
Japanese (ja)
Inventor
明 古川
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ソニーセミコンダクタソリューションズ株式会社
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Publication of WO2017018216A1 publication Critical patent/WO2017018216A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures

Definitions

  • the present technology relates to a solid-state imaging device, a manufacturing method thereof, and an electronic device, and more particularly, to a solid-state imaging device, a manufacturing method thereof, and an electronic device that can reduce a manufacturing process.
  • Solid-state imaging devices such as CMOS (Complementary Metal Oxide Semiconductor) image sensors have become widespread.
  • Some solid-state imaging devices of this type have a structure in which a signal charge from a photoelectric conversion element is transferred by a through electrode provided between a front surface and a back surface of a semiconductor substrate (see, for example, Patent Document 1). .
  • the present technology has been made in view of such a situation, and makes it possible to reduce the manufacturing process of a solid-state imaging device having a through electrode.
  • a solid-state imaging device includes a semiconductor substrate, a photoelectric conversion element that passes through the semiconductor substrate, receives incident light, and converts the incident light into a signal charge, and the signal charge that holds the signal charge.
  • an insulating film formed around the through electrode portion that penetrates the semiconductor substrate and connects the photoelectric conversion element and the signal charge holding portion is embedded.
  • a groove-shaped embedded portion for forming the insulating film for forming the guard ring portion and a groove-shaped embedded portion for forming the guard ring portion are simultaneously formed.
  • a manufacturing method includes a through electrode that connects a photoelectric conversion element that passes through a semiconductor substrate, receives incident light, and converts the incident light into a signal charge, and a signal charge holding unit that holds the signal charge.
  • a first step of forming a portion, a groove-shaped embedded portion for embedding an insulating film formed around the through electrode portion, and an insulating film for forming a guard ring portion in the semiconductor substrate And a second step of simultaneously forming the groove-shaped embedded portion.
  • a through-electrode portion that penetrates the semiconductor substrate and connects the photoelectric conversion element and the signal charge holding portion is formed, and is formed around the through-electrode portion in the semiconductor substrate.
  • a trench-shaped buried portion for embedding the insulating film and a groove-shaped buried portion for embedding the insulating film forming the guard ring portion are simultaneously formed.
  • An electronic apparatus includes a semiconductor substrate, a photoelectric conversion element that passes through the semiconductor substrate, receives incident light, and converts the incident light into signal charge, and the signal charge holding that holds the signal charge.
  • the portion and the groove-like buried portion for embedding the insulating film forming the guard ring portion include a solid-state imaging device that is formed at the same time.
  • a groove-shaped embedded portion for embedding the film and a groove-shaped embedded portion for embedding the insulating film forming the guard ring portion are formed simultaneously.
  • the manufacturing process can be reduced.
  • FIG. 1 is a diagram illustrating a top view of a solid-state imaging device 10 to which the present technology is applied.
  • the solid-state imaging device 10 includes a pixel unit 100 in which a plurality of pixels are two-dimensionally arranged in a matrix, and a peripheral circuit unit (not shown) that performs pixel driving, A / D (Analog / Digital) conversion, and the like.
  • the solid-state imaging device 10 is a back-illuminated type, and is a vertical-spectral-type solid in which R (red), G (green), and B (blue) photoelectric conversion regions are stacked in the vertical direction of the same pixel.
  • An imaging device is a back-illuminated type, and is a vertical-spectral-type solid in which R (red), G (green), and B (blue) photoelectric conversion regions are stacked in the vertical direction of the same pixel.
  • the pad units 101-1 to 101-12 are arranged so as to surround the pixel unit 100.
  • the pad portions 101-1 to 101-12 are respectively formed with openings for exposing the bonding pads.
  • the solid-state imaging device 10 has a structure in which a photoelectric conversion layer, a silicon substrate, and a wiring layer are stacked.
  • a photoelectric conversion element that receives incident light and converts it into signal charges;
  • a through electrode portion that connects the signal charge holding portion that holds the signal charge is formed.
  • the silicon substrate as a guard ring for preventing chipping, around the first guard ring portion 151 along the outer periphery of the solid-state imaging device 10 (the outer periphery of the chip) and the pads 101-1 to 101-12.
  • the second guard ring portions 152-1 to 152-12 are arranged along the respective lines.
  • Chipping means that silicon (Si) is scratched due to silicon debris or damage when silicon (Si) is processed in processes such as dry etching or dicing, and this is propagated.
  • guard rings such as the first guard ring portion 151 and the second guard ring portions 152-1 to 152-12 are arranged.
  • the photoelectric conversion layer formed on the upper side (wafer back side) of the silicon substrate is provided along the outer periphery (chip outer periphery) of the solid-state imaging device 10 as a guard ring for the purpose of protecting the pixel portion 100 against moisture and the like.
  • a third guard ring portion 153A and third guard ring portions 153B-1 to 153B-12 along the periphery of the pad portions 101-1 to 101-12 are respectively arranged.
  • the third guard ring portion 153A disposed along the outer periphery of the solid-state imaging device 10 blocks, for example, moisture and gas that have entered from the lateral direction of the end surface (end surface of the chip) of the solid-state imaging device 10, and the pixel portion 100 characteristic deterioration can be suppressed. Further, the third guard ring portions 153B-1 to 153B-12 arranged along the periphery of the pad portions 101-1 to 101-12 allow moisture to enter from the lateral direction such as the side surface of the opening on the bonding pad. Further, it is possible to shut off the gas and suppress the characteristic deterioration of the pixel portion 100.
  • the first guard ring portion 151 and the third guard ring portion 153 ⁇ / b> A are formed in a layered manner with the silicon substrate and the photoelectric conversion layer, thereby obtaining the solid-state imaging device. It is possible to prevent chipping of the outer periphery 10 and to block moisture entering from the lateral direction of the end face. Further, the second guard ring portions 152-1 to 152-12 and the third guard ring portions 153B-1 to 153B-12 are formed in a layered manner by the silicon substrate and the photoelectric conversion layer, whereby the pad portion 101 is formed. It is possible to prevent chipping around -1 to 101-12 and to block moisture entering from the lateral direction such as the side surface of the opening.
  • the solid-state imaging device 10 is configured as described above.
  • the pad portions 101-1 to 101-12 are referred to as the pad portion 101 when it is not necessary to distinguish them.
  • the second guard ring portions 152-1 to 152-12 are referred to as the second guard ring portions 152 when it is not necessary to particularly distinguish them.
  • the third guard ring portions 153B-1 to 153B-12 they are referred to as third guard ring portions 153B, and the third guard ring portions 153A and the third guard ring portions 153B are referred to as the third guard ring portions 153B.
  • the third guard ring portion 153 is referred to.
  • FIG. 2 is a cross-sectional view of a solid-state imaging device 10A having a structure in which the through electrode portion is doped with impurities in silicon.
  • FIG. 2 represents a cross section taken along the line AA ′ in the top view of FIG. 2 shows a scribe line unit 102 corresponding to a scribe line provided between chips on a wafer when the solid-state imaging device 10A is manufactured, and other chips adjacent to the solid-state imaging device 10A. (Solid-state imaging device 10A) is also illustrated. These relationships are the same in other sectional views described later.
  • the solid-state imaging device 10 ⁇ / b> A has a so-called vertical spectroscopic structure in which, for example, one photoelectric conversion element and two photodiodes (PD) are stacked in the thickness direction of the silicon substrate 12. . Further, the solid-state imaging device 10A has a structure in which the photoelectric conversion layer 11, the silicon substrate 12, and the wiring layer 13 are stacked.
  • an insulating film 111 is formed on the photoelectric conversion layer 11.
  • an upper electrode 112 that is a transparent electrode
  • a photoelectric conversion film 113 that receives incident light and converts it into signal charges
  • lower electrodes 114-1 to 114-3 that are transparent electrodes are laminated. Is protected.
  • through electrodes 122-1 to 122-3 are formed in the silicon 121 between the wafer rear surface side and the wafer front surface side.
  • the through electrode portions 122-1 to 122-3 are made of the same semiconductor as the silicon substrate 12, that is, silicon (Si), and doped (implanted) with, for example, N-type or P-type impurities.
  • the through electrode portion 122-1 is made of silicon (Si) doped with impurities, and connects the lower electrode 114-1 of the photoelectric conversion film 113 and a signal charge holding portion (not shown). That is, the through electrode portion 122-1 serves as a transmission path for signal charges (electrons) generated in the photoelectric conversion element. Further, a through electrode insulating portion 123-1 is formed in a donut shape around the through electrode portion 122-1.
  • the material of the through electrode insulating portion 123-1 is not particularly limited, but for example, an insulating film such as a silicon oxide film (SiO 2 ), a silicon nitride film (SiN), or a silicon oxynitride film (SiON) is used. it can.
  • the upper end of the through electrode portion 122-1 is connected to the lower electrode 114-1 of the photoelectric conversion film 113 through, for example, the upper contact 115-1. Further, the lower end of the through electrode portion 122-1 is connected to the connection portion 131-1, and is also connected to a signal charge holding portion (not shown) connected to the connection portion 131-1.
  • the signal charge holding unit is a floating diffusion (FD) formed in the silicon 121, and converts the signal charge from the through electrode unit 122-1 into an electric signal.
  • the through electrode part 122-2 is made of silicon (Si) doped with impurities, and a donut-like through electrode insulating part 123-2 is formed around the through electrode part 122-2. .
  • the through-electrode portion 122-2 connects the lower electrode 114-2 of the photoelectric conversion film 113 and a signal charge holding portion (not shown) connected to the connection portion 131-2.
  • the through electrode portion 122-3 is made of silicon (Si) doped with impurities, like the through electrode portions 122-1 and 122-2, and a donut-shaped through electrode insulating portion 123-3 is formed around the through electrode portion 122-3. Is formed.
  • the through-electrode portion 122-3 connects the lower electrode 114-3 of the photoelectric conversion film 113 and a signal charge holding portion (not shown) connected to the connection portion 131-3.
  • the through electrode portions 122-1 to 122-3 are referred to as the through electrode portions 122 when it is not necessary to distinguish them. Further, when it is not necessary to distinguish the through electrode insulating portions 123-1 to 123-3, they are referred to as through electrode insulating portions 123.
  • the pad portion 101-1 is formed with an opening for exposing the connection portion 132 as a bonding pad.
  • a second guard ring portion 152-1 is formed on the silicon substrate 12 around the pad portion 101-1 (opening thereof) as a guard ring for preventing chipping.
  • the material of the second guard ring portion 152-1 is not particularly limited, but for example, an insulating film such as a silicon oxide film (SiO 2 ) can be used.
  • a third guard ring portion 153B-1 is formed around the pad portion 101-1 (opening thereof) and as a guard ring for protecting the pixel portion 100 in the photoelectric conversion layer 11. .
  • the third guard ring portion 153B-1 is composed of a metal film or an insulating film.
  • the material of the third guard ring portion 153B-1 for example, aluminum (Al), tungsten (W), titanium (Ti), molybdenum (Mo), tantalum (Ta), copper (Cu)
  • an alloy film thereof, a film in which silicon (Si) or oxygen (O) is contained in these metal films, or the like can be used. That is, a material that does not transmit moisture and oxygen is used as the material of the third guard ring portion 153B-1.
  • a first guard ring portion 151 is formed on the silicon substrate 12 as a guard ring for preventing chipping on the scribe line portion 102 side, that is, the outer periphery of the solid-state imaging device 10A (the outer periphery of the chip). Yes.
  • the material of the first guard ring portion 151 is not particularly limited. For example, an insulating film such as a silicon oxide film (SiO 2 ) can be used.
  • a third guard ring portion 153 ⁇ / b> A is formed in the photoelectric conversion layer 11 as a guard ring for protecting the pixel portion 100.
  • the material of the third guard ring portion 153A is not particularly limited, but as with the third guard ring portion 153B-1, for example, an insulating film such as a metal film such as aluminum (Al) or a silicon oxide film (SiO 2 ). A membrane can be used.
  • the structure of the solid-state imaging device 10A as the first embodiment has been described above.
  • the signal charge generated in the photoelectric conversion element is transferred to the signal charge holding unit by the through electrode unit 122 formed in the silicon substrate 12.
  • the third guard ring 151 and the second guard ring 152 formed on the silicon substrate 12 prevent chipping and are formed on the photoelectric conversion layer 11.
  • the guard ring portions 153A and 153B suppress the characteristic deterioration of the pixel portion 100.
  • FIG. 2 shows a cross section taken along the line AA ′ in the top view of FIG. 1.
  • a partial cross section of the pixel portion 100 and a peripheral portion of the pad portion 101-1 In the above description, a part of the cross section and a part of the outer periphery of the solid-state imaging device 10A (peripheral part of the scribe line part 102) have been described.
  • the cross sections of other regions such as the peripheral portion have the same structure as the corresponding portions in the cross section of FIG.
  • FIG. 3 is a cross-sectional view of a solid-state imaging device 10B having a structure in which a through electrode portion embeds a conductive material.
  • the structure of the solid-state imaging device 10B of FIG. 3 is different from the structure of the solid-state imaging device 10A of FIG. 2 in that the silicon substrate 12 has through electrode portions 125-1 to 125-1 instead of the through electrode portions 122-1 to 122-3.
  • the other structure is the same as the solid-state imaging device 10A of FIG. 2 except that 125-3 is formed.
  • the silicon 121 between the wafer back surface and the wafer front surface is provided with a through electrode portion 125- made of a conductive material such as a metal as a through electrode portion for connecting the photoelectric conversion element and the signal charge holding portion. 1 to 125-3 are formed.
  • the through electrode portion 125-1 is made of a conductive material such as metal, and connects the lower electrode 114-1 of the photoelectric conversion film 113 and a signal charge holding portion (not shown).
  • a through electrode insulating portion 123-1 is formed in a donut shape around the through electrode portion 125-1.
  • an insulating film such as a silicon oxide film (SiO 2 ) can be used.
  • the through electrode portion 125-2 is made of a conductive material such as a metal like the through electrode portion 125-1 and around the through electrode insulating portion 123 made of an insulating film such as a silicon oxide film (SiO 2 ). -2 is formed in a donut shape.
  • the through electrode portion 125-2 connects the lower electrode 114-2 of the photoelectric conversion film 113 and a signal charge holding portion (not shown).
  • the through-electrode portion 125-3 is made of a conductive material such as a metal, like the through-electrode portions 125-1 and 125-2, and is surrounded by an insulating film such as a silicon oxide film (SiO 2 ).
  • the electrode insulating portion 123-3 is formed in a donut shape.
  • the through electrode portion 125-3 connects the lower electrode 114-3 of the photoelectric conversion film 113 and a signal charge holding portion (not shown).
  • the through electrode portions 125-1 to 125-3 are referred to as the through electrode portions 125 when it is not necessary to particularly distinguish them.
  • the silicon substrate 12 has a guard ring for preventing chipping around the pad portion 101-1 (opening thereof).
  • a second guard ring portion 152-1 is formed, and a third guard ring portion 153B-1 is formed in the photoelectric conversion layer 11 as a guard ring for protecting the pixel portion 100.
  • the outer periphery of the solid-state imaging device 10 (on the scribe line unit 102 side) is provided on the silicon substrate 12 for preventing chipping.
  • a first guard ring portion 151 is formed as a guard ring
  • a third guard ring portion 153 A is formed in the photoelectric conversion layer 11 as a guard ring for protecting the pixel portion 100.
  • the structure of the solid-state imaging device 10B as the second embodiment has been described above.
  • the signal charge generated by the photoelectric conversion element is transferred to the signal charge holding unit by the through electrode unit 125 formed in the silicon substrate 12.
  • the third guard ring 151 and the second guard ring 152 formed on the silicon substrate 12 prevent chipping and are formed on the photoelectric conversion layer 11.
  • the guard ring portions 153A and 153B suppress the characteristic deterioration of the pixel portion 100.
  • FIG. 4 is a cross-sectional view of a solid-state imaging device 10C having a structure in which an insulating film used for element isolation is formed at the bottom of the embedded portion.
  • the structure of the solid-state imaging device 10C in FIG. 4 has a first guard ring portion 151 and a second guard formed on the silicon substrate 12 as compared to the solid-state imaging device 10A in FIG. 2 and the solid-state imaging device 10B in FIG.
  • An insulating film 128 and an insulating film 129 (129-1) used for element isolation are formed on the bottom of the ring portion 152 (152-1).
  • an insulating film 128 is formed at the bottom of the embedded portion in which the insulating film used as the first guard ring portion 151 is embedded.
  • an insulating film 129 (129-1) is formed at the bottom of the buried portion where the insulating film used as the second guard ring portion 152 (152-1) is buried.
  • the insulating film 128 and the insulating film 129 (129-1) used for element isolation are formed at the bottoms of the first guard ring portion 151 and the second guard ring portion 152 (152-1).
  • the insulating film 128 and the insulating film 129 (129-1) can be used as a stopper at the time of processing.
  • the manufacturing process of the solid-state imaging device 10A as the first embodiment of the first to third embodiments described above will be described as a representative.
  • the silicon penetration process for forming the through electrode insulating part 123, the first guard ring part 151, and the second guard ring part 152 on the silicon substrate 12 is performed on the wafer surface side. Or since it may be performed from the wafer back surface side, these are demonstrated as another manufacturing process.
  • FIG. 5 is a flowchart for explaining the flow of the manufacturing process of the solid-state imaging device 10 ⁇ / b> A in the case of performing silicon penetration processing from the wafer surface side.
  • 6 to 8 schematically show the manufacturing process of FIG. 5, and the detailed contents of each process in the flowchart of FIG. 5 will be described with reference to these drawings as appropriate.
  • the cross-sectional views of FIGS. 6 to 8 correspond to the cross section AA ′ in the top view of FIG.
  • step S101 an impurity ion implantation step is performed.
  • impurity ions are implanted from the opening portion of the photoresist 161 provided on the silicon 121 on the wafer surface side of the silicon substrate 12.
  • Through electrode portions 122-1 to 122-3 are formed in the portions where the impurity ions are implanted. Note that after the implantation of impurity ions, the photoresist 161 is peeled off from the silicon 121.
  • step S102 a silicon through process / insulating film embedding process is performed.
  • this silicon penetration processing / insulating film embedding step as shown in FIG. 6B, first, through processing of silicon 121 into which impurity ions are implanted is performed from the wafer surface side of the silicon substrate 12, each through electrode portion.
  • a donut-shaped opening (groove-shaped embedded portion) for embedding an insulating film for the through-electrode insulating portion 123 is formed around the periphery of 122.
  • an opening (groove-like embedded portion) for embedding the insulating film for the first guard ring portion 151 is formed in the peripheral portion of the scribe line portion 102 by this penetration processing, and the second guard ring portion 152 is formed.
  • An opening (groove-shaped buried portion) for embedding the insulating film for (152-1) is formed in the peripheral portion of the pad portion 101 (101-1).
  • the openings (groove-like embedded portions) for embedding the insulating film for the second guard ring portion 152 (152-1) are simultaneously formed by the penetration processing of the silicon 121. They are formed to have the same width or the opening width of the opening for embedding the insulating film of the first guard ring portion 151 and the second guard ring portion 152 (152-1).
  • the width of each opening formed by the penetration processing of the silicon 121 By aligning the width of each opening formed by the penetration processing of the silicon 121 to the same width, it is possible to form a buried portion in which the insulating film is embedded with the same pattern. 123, the step of forming the first guard ring portion 151 and the second guard ring portion 152 (152-1) can be easily performed.
  • the width of the opening for embedding the insulating film of the first guard ring portion 151 and the second guard ring portion 152 is the width of the opening for embedding the insulating film for the through electrode insulating portion 123. This is because the peripheral portion of the pixel portion 100 has a large layout restriction. On the other hand, the peripheral portion of the pad portion 101 and the scribe line portion 102 is closer to the layout portion than the peripheral portion of the pixel portion 100. There are no restrictions. Therefore, in order to embed the insulating films of the first guard ring portion 151 disposed in the peripheral portion of the scribe line portion 102 and the second guard ring portion 152 (152-1) disposed in the peripheral portion of the pad portion 101. Even if the width of the opening is increased, there is almost no possibility of being restricted by the layout.
  • the width of the opening for embedding the insulating film of the first guard ring portion 151 and the second guard ring portion 152 (the width of the groove of the groove-shaped embedded portion).
  • the width of the opening for embedding the insulating film of the first guard ring portion 151 and the second guard ring portion 152 (the width of the groove of the groove-shaped embedded portion).
  • An opening (groove-shaped buried portion) for embedding the insulating film for the portion 151 is formed at the same time.
  • the through electrode insulating part 123 is formed in a donut shape around each through electrode part 122 in the pixel unit 100, and the second guard is formed around the pad part 101.
  • a ring portion 152 (152-1) is formed, and a first guard ring portion 151 is formed around the scribe line portion 102.
  • the insulating film embedded in the opening (groove-shaped embedded portion) for embedding the insulating film for the first guard ring portion 151 is the first guard for preventing chipping in the dicing process (S108) described later.
  • the insulating film that functions as the ring portion 151 and is embedded in the opening (groove-shaped embedded portion) for embedding the insulating film for the second guard ring portion 152 (152-1) is a pad portion opening step (to be described later) It functions as the second guard ring portion 152 (152-1) for preventing chipping in the dry etching process in S107).
  • step S103 a wiring layer forming step is performed.
  • the wiring layer 13 is formed on the wafer surface side of the silicon substrate 12 as shown in FIG.
  • step S104 a wafer front / back reversing process is performed.
  • step S105 a photoelectric conversion element / insulating film forming step is performed.
  • the lower electrodes 114-1 to 114-3, the photoelectric conversion film 113, and the upper electrode 112 are formed on the wafer rear surface side of the silicon substrate 12.
  • a photoelectric conversion element is formed by laminating in this order.
  • An insulating film 111 is formed on the region of the pixel portion 100 including the photoelectric conversion element and the peripheral region around the pixel portion 100 (region including the peripheral portion of the pad portion 101 and the scribe line portion 102).
  • step S106 a third guard ring forming step is performed.
  • the pixel is formed on the region of the pixel portion 100 and its peripheral region (the region including the peripheral portion of the pad portion 101 and the scribe line portion 102).
  • a wall-shaped third guard ring part 153B (153B-1) made of a metal film or an insulating film is formed around the pad part 101, and a metal part is formed around the scribe line part 102.
  • a wall-like third guard ring portion 153A made of a film or an insulating film is formed.
  • the third guard ring portions 153A and 153B (153B-1) are formed on the photoelectric conversion layer 11 on the upper side (wafer back side) of the silicon substrate 12, but the third guard ring portions 153A and 153B (153B) are formed. It is desirable to connect the bottom of (-1) (the bottom of a metal film, an insulating film, etc.) to the silicon substrate 12. This is because by adopting such a structure, it is possible to reliably block the entry of moisture and the like.
  • the third guard ring portion 153B (153B-1) in the peripheral portion of the pad portion 101, for example, moisture entering from the lateral direction such as the side surface of the opening on the connection portion 132, etc.
  • the third guard ring portion 153A in the peripheral portion of the scribe line portion 102, for example, moisture that has entered from the lateral direction of the end face of the solid-state imaging device 10 can be blocked. As a result, deterioration of the characteristics of the pixel unit 100 can be suppressed.
  • step S107 a pad opening process is performed.
  • step S108 a dicing process is performed.
  • the silicon substrate 12 and the like are cut into a rectangular shape by a dicing blade (not shown), and the solid-state imaging device 10 is cut out (separated).
  • the first guard ring portion 151 is formed on the silicon substrate 12 in the process of step S102, for example, chipping such as scratches caused by silicon dust or damage is prevented. .
  • step S108 when the process of step S108 is completed, a package sorting process or the like is performed on the plurality of solid-state imaging devices 10 cut out by the dicing process.
  • the silicon substrate 12 is provided with the through-electrode insulating part 123 around the through-electrode part 122, the first guard ring part 151, and the second Since the guard ring part 152 can be formed at the same time, it is possible to reduce the manufacturing process at the time of manufacturing the solid-state imaging device 10A having the silicon substrate on which the through electrode part and the guard ring part are formed.
  • the digging steps can be performed at the same time. Can be reduced.
  • FIG. 9 is a flowchart for explaining the flow of the manufacturing process of the solid-state imaging device 10 ⁇ / b> A in the case of performing silicon penetration processing from the back side of the wafer.
  • 9 to 13 schematically show the manufacturing process of FIG. 9, and the detailed contents of each process in the flowchart of FIG. 9 will be described with reference to those drawings as appropriate.
  • the cross-sectional views of FIGS. 10 to 12 correspond to the cross section AA ′ in the top view of FIG.
  • step S201 an impurity ion implantation process is performed.
  • impurity ions are implanted from the opening portion of the photoresist 161 provided on the silicon 121 on the wafer surface side of the silicon substrate 12.
  • Through electrode portions 122-1 to 122-3 are formed in the portions where the impurity ions are implanted. Note that after the implantation of impurity ions, the photoresist 161 is peeled off from the silicon 121.
  • step S202 a wiring layer forming process is performed.
  • the wiring layer 13 is formed on the wafer surface side of the silicon substrate 12 as shown in FIG.
  • step S203 a wafer front / back reversing process is performed.
  • step S204 a silicon penetration process, a fixed charge film formation process, and an insulating film embedding process are performed.
  • this through silicon processing / fixed charge film formation / insulating film embedding step first, through the silicon 121 into which impurity ions are implanted is performed from the back side of the silicon substrate 12, as shown in FIG. 11A.
  • a donut-shaped (groove-shaped) opening for the through-electrode insulating portion 123 is formed around each through-electrode portion 122.
  • a groove-shaped opening for forming the first guard ring portion 151 is formed in the peripheral portion of the scribe line portion 102 by this penetration processing, thereby forming the second guard ring portion 152 (152-1).
  • a groove-shaped opening is formed in the peripheral portion of the pad portion 101.
  • an opening (groove-shaped buried portion) for embedding an insulating film for the through electrode insulating portion 123 formed in the pixel portion 100 and the periphery of the pad portion 101 are formed.
  • An insulating film for embedding the insulating film for the second guard ring portion 152 (152-1) (groove-shaped embedding portion) and an insulation for the first guard ring portion 151 formed around the scribe line portion 102 Openings (groove-shaped buried portions) for embedding the film are formed at the same time.
  • the through electrode insulating part 123 is formed in a donut shape around each through electrode part 122 in the pixel unit 100, and the second guard is formed around the pad part 101.
  • a ring portion 152 (152-1) is formed, and a first guard ring portion 151 is formed around the scribe line portion 102, respectively.
  • the insulating film embedded in the opening (groove-shaped embedded portion) for embedding the insulating film for the first guard ring portion 151 is the first guard for preventing chipping in the dicing process (S208) described later.
  • the insulating film that functions as the ring portion 151 and is embedded in the opening (groove-shaped embedded portion) for embedding the insulating film for the second guard ring portion 152 (152-1) is a pad portion opening step (to be described later) It functions as the second guard ring portion 152 (152-1) for preventing chipping in the dry etching process in S207).
  • FIG. 13 shows the silicon penetration processing, fixed charge film formation, and insulating film embedding step (S204) in more detail. That is, FIG. 13A shows a through silicon processing step, FIG. 13B shows a fixed charge film forming step, and FIG. 13C shows an insulating film embedding step, and these steps are sequentially performed.
  • the through electrode insulating portion 123, the first guard ring portion 151, and the second guard ring portion 152 (152-1) are formed on the silicon substrate 12 in the same process and simultaneously. .
  • a negative fixed charge film can be used for the purpose of preventing so-called whiteout.
  • the pixel unit 100 side is used for that purpose.
  • a negative fixed charge film is generally formed.
  • the fixed charge film 171 is also formed in the region including the.
  • step S205 a photoelectric conversion element / insulating film forming step is performed.
  • the lower electrodes 114-1 to 114-3, the photoelectric conversion film 113, and the upper electrode 112 are formed on the wafer rear surface side of the silicon substrate 12.
  • a photoelectric conversion element is formed by laminating in this order.
  • an insulating film 111 is formed on the region of the pixel portion 100 including the photoelectric conversion element and its peripheral region (region including the peripheral portion of the pad portion 101 and the scribe line portion 102).
  • step S206 a third guard ring forming step is performed.
  • the pixel is formed on the region of the pixel portion 100 and its peripheral region (the region including the peripheral portion of the pad portion 101 and the scribe line portion 102).
  • a wall-shaped third guard ring portion 153B (153B-1) made of a metal film or the like is formed around the pad portion 101, and a metal film or the like is formed around the scribe line portion 102.
  • a wall-like third guard ring portion 153A is formed.
  • the third guard ring portions 153A and 153B (153B-1) are formed on the photoelectric conversion layer 11 on the upper side (wafer back side) of the silicon substrate 12, but the third guard ring portions 153A and 153B (153B) are formed. It is desirable to connect the bottom of (-1) (the bottom of the metal film or the like) to the silicon substrate 12. This is because by adopting such a structure, it is possible to reliably block the entry of moisture and the like.
  • the third guard ring portion 153B (153B-1) in the peripheral portion of the pad portion 101, for example, moisture entering from the lateral direction such as the side surface of the opening on the connection portion 132, etc.
  • the third guard ring portion 153A in the peripheral portion of the scribe line portion 102, for example, moisture that has entered from the lateral direction of the end face of the solid-state imaging device 10 can be blocked. As a result, deterioration of the characteristics of the pixel unit 100 can be suppressed.
  • step S207 a pad opening process is performed.
  • this pad portion opening step as shown in FIG. 12A, dry etching is performed to form the pad portion 101.
  • the second guard ring portion 152 (152-1) is formed on the silicon substrate 12 in the process of step S204, for example, scratches may occur due to silicon dust or damage. Chipping is prevented.
  • step S208 a dicing process is performed.
  • the silicon substrate 12 and the like are cut into a rectangular shape by a dicing blade (not shown), and the solid-state imaging device 10 is cut out (separated).
  • the first guard ring portion 151 is formed on the silicon substrate 12 in the process of step S204, for example, chipping such as scratches caused by silicon dust or damage is prevented. .
  • the flow of the manufacturing process of the solid-state imaging device 10A in the case of performing silicon penetration processing from the wafer back side has been described.
  • the through silicon processing / fixed charge film forming / insulating film embedding process of step S204 the through electrode insulating portion 123 around the through electrode portion 122 and the first guard ring portion are formed on the silicon substrate 12.
  • 151 and the second guard ring portion 152 can be formed at the same time, and therefore the manufacturing process at the time of manufacturing the solid-state imaging device 10A having the silicon substrate on which the through electrode portion and the guard ring portion are formed can be reduced. it can.
  • FIG. 14 is a diagram illustrating another arrangement example of the third guard ring portion 153.
  • FIG. 14 is a top view of the solid-state imaging device 10.
  • the solid-state imaging device 10 includes a third guard ring portion 153A disposed along the outer periphery thereof, and a third guard ring portion 153B- along the periphery of the pad portions 101-1 to 101-12.
  • a third guard ring portion 153C is disposed along the periphery of the pixel portion 100.
  • the third guard ring portion 153C is made of a material that does not transmit moisture and oxygen, such as a metal film or an insulating film, like the third guard ring portions 153A and 153B. Further, it is desirable that the bottom portion (the bottom portion of the metal film or the like) of the third guard ring portion 153C is connected to the silicon substrate 12 in order to reliably block the entry of moisture or the like.
  • the third guard ring portion 153C blocks moisture and gas that have entered from the lateral direction, such as the end surface of the solid-state imaging device 10 (end surface of the chip) and the side surface of the opening on the bonding pad, and the characteristics of the pixel unit 100 Deterioration can be suppressed.
  • the third guard ring portion 153A, the third guard ring portions 153B-1 to 153B-12, as the third guard ring portion 153 for the purpose of protecting the pixel portion 100 such as moisture proofing And, the case where the third guard ring part 153C is arranged is illustrated, but the third guard ring part 153 is not necessarily arranged, and among these third guard ring parts 153, At least one third guard ring portion 153 may be arranged.
  • the above-described arrangement example of the third guard ring portion 153 is an example.
  • the third guard ring portion 153B arranged along the periphery of the pad portions 101-1 to 101-12 is provided with a plurality of pieces.
  • Various arrangement forms such as providing the pad part 101 so as to extend over the pad part 101 or providing the third guard ring part 153C arranged along the periphery of the pixel part 100 can be adopted. .
  • FIG. 15 is a diagram illustrating a configuration example of an electronic apparatus 300 having a solid-state imaging device to which the present technology is applied.
  • an electronic device such as an imaging device such as a digital still camera or a video camera, or a mobile terminal device such as a smartphone or a tablet-type terminal.
  • the electronic device 300 includes a solid-state imaging device 301, a DSP circuit 302, a frame memory 303, a display unit 304, a recording unit 305, an operation unit 306, and a power supply unit 307.
  • the DSP circuit 302, the frame memory 303, the display unit 304, the recording unit 305, the operation unit 306, and the power supply unit 307 are connected to each other via a bus line 308.
  • the solid-state imaging device 301 corresponds to the solid-state imaging device 10 of any of the first to third embodiments, and has the cross-sectional structure shown in FIG. 2, FIG. 3, or FIG. is doing.
  • the DSP circuit 302 is a camera signal processing circuit that processes a signal supplied from the solid-state imaging device 301.
  • the DSP circuit 302 outputs image data obtained by processing a signal from the solid-state imaging device 301.
  • the frame memory 303 temporarily holds the image data processed by the DSP circuit 302 in units of frames.
  • the display unit 304 includes a panel type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays a moving image or a still image captured by the solid-state imaging device 301.
  • the recording unit 305 records moving image or still image image data captured by the solid-state imaging device 301 on a recording medium such as a semiconductor memory or a hard disk.
  • the operation unit 306 outputs operation commands for various functions of the electronic device 300 in accordance with user operations.
  • the power supply unit 307 appropriately supplies various power sources serving as operation power sources for the DSP circuit 302, the frame memory 303, the display unit 304, the recording unit 305, and the operation unit 306 to these supply targets.
  • the electronic device 300 is configured as described above.
  • FIG. 16 is a diagram illustrating a usage example of the solid-state imaging device 10 as an image sensor.
  • the solid-state imaging device 10 described above can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-ray as follows. That is, as shown in FIG. 16, not only the above-mentioned field of viewing images taken for viewing, but also, for example, the field of transportation, the field of home appliances, the field of medical / healthcare, the field of security.
  • the solid-state imaging device 10 can also be used in an apparatus used in the field of beauty, the field of sports, the field of agriculture, or the like.
  • a device for taking an image for viewing eg, a digital camera, a smartphone, a mobile phone with a camera function, etc.
  • the solid-state imaging device 10 can be used in the electronic apparatus 300).
  • the solid-state imaging device 10 can be used as a device used for traffic such as a monitoring camera, a distance measuring sensor for measuring a distance between vehicles, and the like.
  • a device that is used for home appliances such as a television receiver, a refrigerator, and an air conditioner to capture a user's gesture and perform device operations according to the gesture.
  • the solid-state imaging device 10 is used in a device used for medical treatment or health care such as an endoscope or a blood vessel photographing device that receives infrared light. can do.
  • the solid-state imaging device 10 can be used in devices used for security, such as surveillance cameras for crime prevention and cameras for personal authentication.
  • the solid-state imaging device 10 can be used in a device used for beauty, such as a skin measuring device for photographing the skin and a microscope for photographing the scalp.
  • the solid-state imaging device 10 can be used in sports devices such as action cameras and wearable cameras for sports applications.
  • the solid-state imaging device 10 can be used in devices used for agriculture, such as a camera for monitoring the state of fields and crops.
  • the present technology can take the following configurations.
  • a semiconductor substrate A through-electrode portion that connects the photoelectric conversion element that passes through the semiconductor substrate and receives incident light and converts it into signal charge, and the signal charge holding portion that holds the signal charge;
  • a guard ring portion formed on the semiconductor substrate, In the semiconductor substrate, the groove-shaped embedded portion for embedding the insulating film formed around the through electrode portion and the groove-shaped embedded portion for embedding the insulating film forming the guard ring portion are simultaneously Solid-state imaging device that is formed.
  • the said guard ring part contains the 1st guard ring part formed in the outer periphery of the said solid-state imaging device, and the 2nd guard ring part formed in the circumference
  • the solid-state imaging device as described in (1). .
  • the solid-state imaging device according to (1) or (2), wherein the through electrode portion is formed by doping impurities into the semiconductor substrate.
  • the solid-state imaging device according to (1) or (2), wherein the through electrode portion is formed by embedding a conductive material in the semiconductor substrate.
  • the solid-state imaging device according to (4), wherein the conductive material is a metal.
  • the solid-state imaging device according to (1) or (2), wherein the embedded portion is formed by digging from the surface side of the semiconductor substrate.
  • the solid-state imaging device according to (1) or (2), wherein the embedded portion is formed by digging from the back side of the semiconductor substrate.
  • a fixed charge film is deposited on the embedded portion, The solid-state imaging device according to (7), wherein the insulating film is embedded on the fixed charge film. (9) The solid-state imaging device according to (7), wherein an insulating film for a stopper at the time of processing is formed on a bottom portion of a buried portion of the insulating film that forms the first card ring portion and the second guard ring portion.
  • a groove-shaped embedded portion for embedding an insulating film formed around the through electrode portion and a groove-shaped embedded portion for embedding an insulating film forming a guard ring portion are formed simultaneously.
  • a manufacturing method comprising the second step.
  • the said guard ring part contains the 1st guard ring part formed in the outer periphery of a solid-state imaging device, and the 2nd guard ring part formed in the circumference
  • the said penetration electrode part is formed by doping an impurity in the said semiconductor substrate.
  • (11) Or the manufacturing method as described in (12).
  • (14) The manufacturing method according to (11) or (12), wherein the through electrode portion is formed by embedding a conductive material in the semiconductor substrate.
  • the conductive material is a metal.
  • (16) The manufacturing method according to (11) or (12), wherein in the second step, the embedded portion is dug from the surface side of the semiconductor substrate.
  • a semiconductor substrate A through-electrode portion that connects the photoelectric conversion element that passes through the semiconductor substrate and receives incident light and converts it into signal charge, and the signal charge holding portion that holds the signal charge;
  • a guard ring portion formed on the semiconductor substrate, In the semiconductor substrate, the groove-shaped embedded portion for embedding the insulating film formed around the through electrode portion and the groove-shaped embedded portion for embedding the insulating film forming the guard ring portion are simultaneously
  • An electronic device provided with a solid-state imaging device.
  • 10, 10A, 10B, 10C solid-state imaging device 11 photoelectric conversion layer, 12 silicon substrate, 13 wiring layer, 100 pixel unit, 101 pad unit, 102 scribe line unit, 111 insulating film, 112 upper electrode, 113 photoelectric conversion film, 114, lower electrode, 121 silicon, 122, 122-1 to 122-3 through electrode part, 123, 123-1 to 123-3 through electrode insulating part, 125, 125-1 to 125-3 through electrode part, 128, 129 Insulating film, 151, first guard ring, 152, second guard ring, 153A, 153B, 153C, third guard ring, 171 fixed charge film, 300 electronic device, 301 solid-state imaging device

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Abstract

The present technology pertains to a solid-state imaging device for which manufacturing steps can be reduced, a method for manufacturing the same, and an electronic device. The solid-state imaging device is provided with: a through electrode part passing through a semiconductor substrate to connect a photoelectric conversion element which receives incident light and converts the light to signal charges, to a signal charge holding part which holds the signal charges; and a guard ring part formed on the semiconductor substrate. In the semiconductor substrate, a groove-shaped embedding section for embedding therein an insulation film to be formed around the through electrode part and a groove-shaped embedding section for embedding therein an insulation film to form the guard ring part are simultaneously formed. The present technology is applicable to CMOS image sensors, for example.

Description

固体撮像装置及びその製造方法、並びに電子機器Solid-state imaging device, manufacturing method thereof, and electronic apparatus
　本技術は、固体撮像装置及びその製造方法、並びに電子機器に関し、特に、製造工程を削減することができるようにした固体撮像装置及びその製造方法、並びに電子機器に関する。 The present technology relates to a solid-state imaging device, a manufacturing method thereof, and an electronic device, and more particularly, to a solid-state imaging device, a manufacturing method thereof, and an electronic device that can reduce a manufacturing process.
　近年、CMOS(Complementary Metal Oxide Semiconductor)イメージセンサなどの固体撮像装置が普及している。この種の固体撮像装置においては、半導体基板の表面と裏面との間に設けられた貫通電極によって、光電変換素子からの信号電荷を転送する構造を有するものがある(例えば、特許文献１参照)。 In recent years, solid-state imaging devices such as CMOS (Complementary Metal Oxide Semiconductor) image sensors have become widespread. Some solid-state imaging devices of this type have a structure in which a signal charge from a photoelectric conversion element is transferred by a through electrode provided between a front surface and a back surface of a semiconductor substrate (see, for example, Patent Document 1). .
特開２０１５－３８９３１号公報JP 2015-38931 A
　ところで、上述した貫通電極を有する固体撮像装置の製造時において、半導体基板に貫通電極を形成する工程以外で、当該半導体基板を貫通加工するための工程が必要な場合がある。その場合には、複数回の貫通加工を行う工程が存在することになるため、製造工程を削減することが求められていた。 Incidentally, when manufacturing the above-described solid-state imaging device having a through electrode, there may be a case where a process for penetrating the semiconductor substrate is required in addition to the process of forming the through electrode on the semiconductor substrate. In that case, since there is a step of performing a plurality of times of penetration processing, it has been required to reduce the number of manufacturing steps.
　本技術はこのような状況に鑑みてなされたものであり、貫通電極を有する固体撮像装置の製造工程を削減することができるようにするものである。 The present technology has been made in view of such a situation, and makes it possible to reduce the manufacturing process of a solid-state imaging device having a through electrode.
　本技術の第１の側面の固体撮像装置は、半導体基板と、前記半導体基板を貫通して、入射光を受光して信号電荷に変換する光電変換素子と、前記信号電荷を保持する前記信号電荷保持部とを接続する貫通電極部と、前記半導体基板に形成されるガードリング部とを備え、前記半導体基板において、前記貫通電極部の周囲に形成される絶縁膜を埋め込むための溝状の埋め込み部と、前記ガードリング部を形成する絶縁膜を埋め込むための溝状の埋め込み部とは、同時に形成されたものである。 A solid-state imaging device according to a first aspect of the present technology includes a semiconductor substrate, a photoelectric conversion element that passes through the semiconductor substrate, receives incident light, and converts the incident light into a signal charge, and the signal charge that holds the signal charge. A groove-shaped embedding provided in the semiconductor substrate for embedding an insulating film formed around the through-electrode portion, comprising a through-electrode portion connecting the holding portion and a guard ring portion formed on the semiconductor substrate The portion and the groove-shaped buried portion for embedding the insulating film forming the guard ring portion are formed at the same time.
　本技術の第１の側面の固体撮像装置においては、半導体基板において、当該半導体基板を貫通して光電変換素子と信号電荷保持部とを接続する貫通電極部の周囲に形成される絶縁膜を埋め込むための溝状の埋め込み部と、ガードリング部を形成する絶縁膜を埋め込むための溝状の埋め込み部とが、同時に形成されている。 In the solid-state imaging device according to the first aspect of the present technology, in the semiconductor substrate, an insulating film formed around the through electrode portion that penetrates the semiconductor substrate and connects the photoelectric conversion element and the signal charge holding portion is embedded. A groove-shaped embedded portion for forming the insulating film for forming the guard ring portion and a groove-shaped embedded portion for forming the guard ring portion are simultaneously formed.
　本技術の第２の側面の製造方法は、半導体基板を貫通して、入射光を受光して信号電荷に変換する光電変換素子と、前記信号電荷を保持する信号電荷保持部を接続する貫通電極部を形成する第１の工程と、前記半導体基板において、前記貫通電極部の周囲に形成される絶縁膜を埋め込むための溝状の埋め込み部と、ガードリング部を形成する絶縁膜を埋め込むための溝状の埋め込み部とを同時に形成する第２の工程とを含む。 A manufacturing method according to a second aspect of the present technology includes a through electrode that connects a photoelectric conversion element that passes through a semiconductor substrate, receives incident light, and converts the incident light into a signal charge, and a signal charge holding unit that holds the signal charge. A first step of forming a portion, a groove-shaped embedded portion for embedding an insulating film formed around the through electrode portion, and an insulating film for forming a guard ring portion in the semiconductor substrate And a second step of simultaneously forming the groove-shaped embedded portion.
　本技術の第２の側面の製造方法においては、半導体基板を貫通して、光電変換素子と信号電荷保持部を接続する貫通電極部が形成され、半導体基板において、貫通電極部の周囲に形成される絶縁膜を埋め込むための溝状の埋め込み部と、ガードリング部を形成する絶縁膜を埋め込むための溝状の埋め込み部とが同時に形成される。 In the manufacturing method according to the second aspect of the present technology, a through-electrode portion that penetrates the semiconductor substrate and connects the photoelectric conversion element and the signal charge holding portion is formed, and is formed around the through-electrode portion in the semiconductor substrate. A trench-shaped buried portion for embedding the insulating film and a groove-shaped buried portion for embedding the insulating film forming the guard ring portion are simultaneously formed.
　本技術の第３の側面の電子機器は、半導体基板と、前記半導体基板を貫通して、入射光を受光して信号電荷に変換する光電変換素子と、前記信号電荷を保持する前記信号電荷保持部とを接続する貫通電極部と、前記半導体基板に形成されるガードリング部とを有し、前記半導体基板において、前記貫通電極部の周囲に形成される絶縁膜を埋め込むための溝状の埋め込み部と、前記ガードリング部を形成する絶縁膜を埋め込むための溝状の埋め込み部とは、同時に形成されたものである固体撮像装置を備える。 An electronic apparatus according to a third aspect of the present technology includes a semiconductor substrate, a photoelectric conversion element that passes through the semiconductor substrate, receives incident light, and converts the incident light into signal charge, and the signal charge holding that holds the signal charge. A groove-shaped embedding for embedding an insulating film formed around the through-electrode portion in the semiconductor substrate. The portion and the groove-like buried portion for embedding the insulating film forming the guard ring portion include a solid-state imaging device that is formed at the same time.
　本技術の第３の側面の電子機器においては、固体撮像装置の半導体基板において、当該半導体基板を貫通して光電変換素子と信号電荷保持部とを接続する貫通電極部の周囲に形成される絶縁膜を埋め込むための溝状の埋め込み部と、ガードリング部を形成する絶縁膜を埋め込むための溝状の埋め込み部とが、同時に形成されている。 In the electronic device according to the third aspect of the present technology, in the semiconductor substrate of the solid-state imaging device, insulation formed around the through electrode portion that penetrates the semiconductor substrate and connects the photoelectric conversion element and the signal charge holding portion. A groove-shaped embedded portion for embedding the film and a groove-shaped embedded portion for embedding the insulating film forming the guard ring portion are formed simultaneously.
　本技術の第１の側面乃至第３の側面によれば、製造工程を削減することができる。 According to the first aspect to the third aspect of the present technology, the manufacturing process can be reduced.
　なお、ここに記載された効果は必ずしも限定されるものではなく、本開示中に記載されたいずれかの効果であってもよい。 It should be noted that the effects described here are not necessarily limited, and may be any of the effects described in the present disclosure.
本技術を適用した固体撮像装置の上面図を示す図である。It is a figure which shows the top view of the solid-state imaging device to which this technique is applied. 貫通電極部がシリコンに不純物をドーピングした構造を有する固体撮像装置の断面図を示す図である。It is a figure which shows sectional drawing of the solid-state imaging device which has a structure where the penetration electrode part doped the impurity to silicon. 貫通電極部が導電材料を埋め込んだ構造を有する固体撮像装置の断面図を示す図である。It is a figure which shows sectional drawing of the solid-state imaging device which has a structure where the penetration electrode part embedded the electrically-conductive material. 埋め込み部の底部に素子分離で使用する絶縁膜を形成した構造を有する固体撮像装置の断面図を示す図である。It is a figure which shows sectional drawing of the solid-state imaging device which has the structure which formed the insulating film used for element isolation in the bottom part of the embedding part. ウェハ表面側からシリコン貫通加工を行う場合の固体撮像装置の製造工程の流れを説明するフローチャートである。It is a flowchart explaining the flow of the manufacturing process of a solid-state imaging device in the case of performing silicon penetration processing from the wafer surface side. 不純物イオン注入工程、シリコン貫通加工・絶縁膜埋め込み工程、及び、配線層形成工程を模式的に表した図である。It is the figure which represented typically the impurity ion implantation process, the silicon penetration process, the insulating film embedding process, and the wiring layer formation process. ウェハ表裏反転工程、光電変換素子・絶縁膜成膜工程、及び、第３のガードリング形成工程を模式的に表した図である。It is the figure which represented typically the wafer front-back inversion process, the photoelectric conversion element and the insulating film film-forming process, and the 3rd guard ring formation process. パッド部開口工程、及び、ダイシング工程を模式的に表した図である。It is the figure which represented the pad part opening process and the dicing process typically. ウェハ裏面側からシリコン貫通加工を行う場合の固体撮像装置の製造工程の流れを説明するフローチャートである。It is a flowchart explaining the flow of the manufacturing process of a solid-state imaging device in the case of performing silicon penetration processing from the wafer back side. 不純物イオン注入工程、配線層形成工程、及び、ウェハ表裏反転工程を模式的に表した図である。It is the figure which represented typically the impurity ion implantation process, the wiring layer formation process, and the wafer front / back inversion process. シリコン貫通加工・固定電荷膜成膜・絶縁膜埋め込み工程、光電変換素子・絶縁膜成膜工程、及び、第３のガードリング形成工程を模式的に表した図である。It is the figure which represented typically the silicon penetration process, fixed charge film | membrane film-forming / insulating film embedding process, a photoelectric conversion element and insulating film film-forming process, and the 3rd guard ring formation process. パッド部開口工程、及び、ダイシング工程を模式的に表した図である。It is the figure which represented the pad part opening process and the dicing process typically. 固定電荷膜の成膜の工程を模式的に表した図である。It is the figure which represented typically the process of film-forming of a fixed charge film | membrane. 第３のガードリング部の他の配置例を示す図である。It is a figure which shows the other example of arrangement | positioning of a 3rd guard ring part. 電子機器の構成例を示す図である。It is a figure which shows the structural example of an electronic device. 固体撮像装置の使用例を示す図である。It is a figure which shows the usage example of a solid-state imaging device.
　以下、図面を参照しながら本技術の実施の形態について説明する。なお、説明は以下の順序で行うものとする。 Hereinafter, embodiments of the present technology will be described with reference to the drawings. The description will be made in the following order.
１．固体撮像装置の構造
（１）第１の実施の形態：貫通電極部がシリコンに不純物をドーピングした構造
（２）第２の実施の形態：貫通電極部が導電材料を埋め込んだ構造
（３）第３の実施の形態：ガードリングの埋め込み部の底部に素子分離で使用する絶縁膜を形成した構造
２．製造工程の流れ
（１）ウェハ表面側からシリコン貫通加工を行う場合の製造工程
（２）ウェハ裏面側からシリコン貫通加工を行う場合の製造工程
３．変形例
４．電子機器の構成
５．固体撮像装置の使用例 1. Structure of solid-state imaging device (1) First embodiment: structure in which through electrode portion is doped with impurities in silicon (2) Second embodiment: structure in which through electrode portion is embedded with conductive material (3) second Embodiment 3: Structure in which an insulating film used for element isolation is formed at the bottom of the buried portion of the guard ring 2. Flow of manufacturing process (1) Manufacturing process in the case of performing silicon through processing from the wafer front side (2) Manufacturing process in the case of performing silicon through processing from the back side of the wafer Modification 4 4. Configuration of electronic device Examples of using solid-state imaging devices
＜１．固体撮像装置の構造＞ <1. Structure of solid-state imaging device>
（固体撮像装置の構造）
　図１は、本技術を適用した固体撮像装置１０の上面図を示す図である。 (Structure of solid-state imaging device)
FIG. 1 is a diagram illustrating a top view of a solid-state imaging device 10 to which the present technology is applied.
　図１の固体撮像装置１０は、CMOS(Complementary Metal Oxide Semiconductor)イメージセンサやCCD(Charge Coupled Device)イメージセンサ等のイメージセンサである。固体撮像装置１０は、複数の画素が行列状に２次元配置される画素部１００と、画素の駆動やA/D(Analog/Digital)変換等を行う周辺回路部(不図示)などから構成される。また、固体撮像装置１０は、裏面照射型であって、同一画素の縦方向にＲ(赤)、Ｇ(緑)、及び、Ｂ(青)の光電変換領域を積層した縦方向分光型の固体撮像装置である。 1 is an image sensor such as a CMOS (Complementary Metal Oxide Semiconductor) image sensor or a CCD (Charge Coupled Device) image sensor. The solid-state imaging device 10 includes a pixel unit 100 in which a plurality of pixels are two-dimensionally arranged in a matrix, and a peripheral circuit unit (not shown) that performs pixel driving, A / D (Analog / Digital) conversion, and the like. The The solid-state imaging device 10 is a back-illuminated type, and is a vertical-spectral-type solid in which R (red), G (green), and B (blue) photoelectric conversion regions are stacked in the vertical direction of the same pixel. An imaging device.
　また、固体撮像装置１０においては、画素部１００を取り囲むようにして、パッド部１０１－１乃至１０１－１２が配置される。パッド部１０１－１乃至１０１－１２には、ボンディングパッドを露出させるための開口がそれぞれ形成されている。 Further, in the solid-state imaging device 10, the pad units 101-1 to 101-12 are arranged so as to surround the pixel unit 100. The pad portions 101-1 to 101-12 are respectively formed with openings for exposing the bonding pads.
　ここで、固体撮像装置１０は、光電変換層と、シリコン基板と、配線層とが積層された構造を有し、シリコン基板においては、入射光を受光して信号電荷に変換する光電変換素子と、信号電荷を保持する信号電荷保持部とを接続する貫通電極部が形成されている。また、シリコン基板においては、チッピング防止用のガードリングとして、固体撮像装置１０の外周(チップの外周)に沿った第１のガードリング部１５１と、パッド部１０１－１乃至１０１－１２の周囲に沿った第２のガードリング部１５２－１乃至１５２－１２がそれぞれ配置される。 Here, the solid-state imaging device 10 has a structure in which a photoelectric conversion layer, a silicon substrate, and a wiring layer are stacked. In the silicon substrate, a photoelectric conversion element that receives incident light and converts it into signal charges; A through electrode portion that connects the signal charge holding portion that holds the signal charge is formed. Further, in the silicon substrate, as a guard ring for preventing chipping, around the first guard ring portion 151 along the outer periphery of the solid-state imaging device 10 (the outer periphery of the chip) and the pads 101-1 to 101-12. The second guard ring portions 152-1 to 152-12 are arranged along the respective lines.
　なお、チッピングとは、ドライエッチングやダイシング等の工程でシリコン(Si)を加工する際に、シリコン屑やダメージ等により、シリコン(Si)にキズが生じたりすることをいい、これが伝搬されるのを防止するために、第１のガードリング部１５１や第２のガードリング部１５２－１乃至１５２－１２等のガードリングが配置される。 Chipping means that silicon (Si) is scratched due to silicon debris or damage when silicon (Si) is processed in processes such as dry etching or dicing, and this is propagated. In order to prevent this, guard rings such as the first guard ring portion 151 and the second guard ring portions 152-1 to 152-12 are arranged.
　また、シリコン基板の上側(ウェハ裏面側)に形成される光電変換層には、画素部１００に対する防湿等の保護を目的としたガードリングとして、固体撮像装置１０の外周(チップの外周)に沿った第３のガードリング部１５３Ａと、パッド部１０１－１乃至１０１－１２の周囲に沿った第３のガードリング部１５３Ｂ－１乃至１５３Ｂ－１２がそれぞれ配置される。 Further, the photoelectric conversion layer formed on the upper side (wafer back side) of the silicon substrate is provided along the outer periphery (chip outer periphery) of the solid-state imaging device 10 as a guard ring for the purpose of protecting the pixel portion 100 against moisture and the like. A third guard ring portion 153A and third guard ring portions 153B-1 to 153B-12 along the periphery of the pad portions 101-1 to 101-12 are respectively arranged.
　固体撮像装置１０の外周に沿って配置される第３のガードリング部１５３Ａによって、例えば、固体撮像装置１０の端面(チップの端面)の横方向から進入してきた水分やガスを遮断し、画素部１００の特性劣化を抑制することができる。また、パッド部１０１－１乃至１０１－１２の周囲に沿って配置される第３のガードリング部１５３Ｂ－１乃至１５３Ｂ－１２によって、ボンディングパッド上の開口の側面などの横方向から進入してきた水分やガスを遮断し、画素部１００の特性劣化を抑制することができる。 The third guard ring portion 153A disposed along the outer periphery of the solid-state imaging device 10 blocks, for example, moisture and gas that have entered from the lateral direction of the end surface (end surface of the chip) of the solid-state imaging device 10, and the pixel portion 100 characteristic deterioration can be suppressed. Further, the third guard ring portions 153B-1 to 153B-12 arranged along the periphery of the pad portions 101-1 to 101-12 allow moisture to enter from the lateral direction such as the side surface of the opening on the bonding pad. Further, it is possible to shut off the gas and suppress the characteristic deterioration of the pixel portion 100.
　このように、図１の固体撮像装置１０においては、シリコン基板と光電変換層で、第１のガードリング部１５１と第３のガードリング部１５３Ａとを階層状に形成することにより、固体撮像装置１０の外周のチッピングの防止と、端面の横方向から進入する水分等の遮断を実現することができる。また、シリコン基板と光電変換層で、第２のガードリング部１５２－１乃至１５２－１２と第３のガードリング部１５３Ｂ－１乃至１５３Ｂ－１２とを階層状に形成することにより、パッド部１０１－１乃至１０１－１２の周囲のチッピングの防止と、開口の側面等の横方向から進入する水分等の遮断を実現することができる。 As described above, in the solid-state imaging device 10 of FIG. 1, the first guard ring portion 151 and the third guard ring portion 153 </ b> A are formed in a layered manner with the silicon substrate and the photoelectric conversion layer, thereby obtaining the solid-state imaging device. It is possible to prevent chipping of the outer periphery 10 and to block moisture entering from the lateral direction of the end face. Further, the second guard ring portions 152-1 to 152-12 and the third guard ring portions 153B-1 to 153B-12 are formed in a layered manner by the silicon substrate and the photoelectric conversion layer, whereby the pad portion 101 is formed. It is possible to prevent chipping around -1 to 101-12 and to block moisture entering from the lateral direction such as the side surface of the opening.
　固体撮像装置１０は、以上のように構成される。 The solid-state imaging device 10 is configured as described above.
　なお、以下の説明では、パッド部１０１－１乃至１０１－１２を特に区別する必要がない場合、パッド部１０１と称する。また、第２のガードリング部１５２－１乃至１５２－１２を特に区別する必要がない場合、第２のガードリング部１５２と称する。さらに、第３のガードリング部１５３Ｂ－１乃至１５３Ｂ－１２を特に区別する必要がない場合、第３のガードリング部１５３Ｂと称し、第３のガードリング部１５３Ａと第３のガードリング部１５３Ｂを特に区別する必要がない場合、第３のガードリング部１５３と称する。 In the following description, the pad portions 101-1 to 101-12 are referred to as the pad portion 101 when it is not necessary to distinguish them. In addition, the second guard ring portions 152-1 to 152-12 are referred to as the second guard ring portions 152 when it is not necessary to particularly distinguish them. Further, when it is not necessary to particularly distinguish the third guard ring portions 153B-1 to 153B-12, they are referred to as third guard ring portions 153B, and the third guard ring portions 153A and the third guard ring portions 153B are referred to as the third guard ring portions 153B. When it is not necessary to distinguish between them, the third guard ring portion 153 is referred to.
　次に、図１の固体撮像装置１０の断面の構造について説明するが、ここでは、その断面の構造に応じて、第１の実施の形態乃至第３の実施の形態を説明する。 Next, the cross-sectional structure of the solid-state imaging device 10 of FIG. 1 will be described. Here, the first to third embodiments will be described according to the cross-sectional structure.
（１）第１の実施の形態 (1) First embodiment
（固体撮像装置の断面図）
　図２は、貫通電極部がシリコンに不純物をドーピングした構造を有する固体撮像装置１０Ａの断面図を示す図である。 (Cross sectional view of solid-state imaging device)
FIG. 2 is a cross-sectional view of a solid-state imaging device 10A having a structure in which the through electrode portion is doped with impurities in silicon.
　なお、図２の断面図は、図１の上面図におけるＡ－Ａ'の断面を表している。また、図２においては、固体撮像装置１０Ａの製造時における、ウェハ上のチップの間に設けられるスクライブラインに相当するスクライブライン部１０２が示されており、固体撮像装置１０Ａに隣接する他のチップ(固体撮像装置１０Ａ)も図示されている。これらの関係については、後述する他の断面図でも同様とされる。 Note that the cross-sectional view of FIG. 2 represents a cross section taken along the line AA ′ in the top view of FIG. 2 shows a scribe line unit 102 corresponding to a scribe line provided between chips on a wafer when the solid-state imaging device 10A is manufactured, and other chips adjacent to the solid-state imaging device 10A. (Solid-state imaging device 10A) is also illustrated. These relationships are the same in other sectional views described later.
　図２において、固体撮像装置１０Ａは、例えば、１つの光電変換素子と、２つのフォトダイオード(PD)とをシリコン基板１２の厚み方向に積層した、いわゆる縦方向分光型の構造を有している。また、固体撮像装置１０Ａは、光電変換層１１と、シリコン基板１２と、配線層１３とが積層された構造を有している。 In FIG. 2, the solid-state imaging device 10 </ b> A has a so-called vertical spectroscopic structure in which, for example, one photoelectric conversion element and two photodiodes (PD) are stacked in the thickness direction of the silicon substrate 12. . Further, the solid-state imaging device 10A has a structure in which the photoelectric conversion layer 11, the silicon substrate 12, and the wiring layer 13 are stacked.
　画素部１００において、光電変換層１１には、絶縁膜１１１が形成される。この絶縁膜１１１によって、透明な電極である上部電極１１２、入射光を受光して信号電荷に変換する光電変換膜１１３、及び、透明な電極である下部電極１１４－１乃至１１４－３が積層して構成される光電変換素子を保護している。 In the pixel unit 100, an insulating film 111 is formed on the photoelectric conversion layer 11. By this insulating film 111, an upper electrode 112 that is a transparent electrode, a photoelectric conversion film 113 that receives incident light and converts it into signal charges, and lower electrodes 114-1 to 114-3 that are transparent electrodes are laminated. Is protected.
　シリコン基板１２において、ウェハ裏面側とウェハ表面側との間のシリコン１２１には、貫通電極部１２２－１乃至１２２－３が形成されている。貫通電極部１２２－１乃至１２２－３は、シリコン基板１２と同じ半導体、すなわち、シリコン(Si)により構成され、例えばＮ型又はＰ型の不純物がドーピングされる(注入される)。 In the silicon substrate 12, through electrodes 122-1 to 122-3 are formed in the silicon 121 between the wafer rear surface side and the wafer front surface side. The through electrode portions 122-1 to 122-3 are made of the same semiconductor as the silicon substrate 12, that is, silicon (Si), and doped (implanted) with, for example, N-type or P-type impurities.
　貫通電極部１２２－１は、不純物をドーピングしたシリコン(Si)から構成され、光電変換膜１１３の下部電極１１４－１と、信号電荷保持部(不図示)とを接続している。すなわち、貫通電極部１２２－１は、光電変換素子において生じた信号電荷(電子)の伝送路となる。また、貫通電極部１２２－１の周囲には、貫通電極絶縁部１２３－１がドーナツ状に形成されている。この貫通電極絶縁部１２３－１の材料は、特に限定されないが、例えば、シリコン酸化膜(SiO2)、シリコン窒化膜(SiN)、又はシリコン酸窒化膜(SiON)などの絶縁膜を用いることができる。 The through electrode portion 122-1 is made of silicon (Si) doped with impurities, and connects the lower electrode 114-1 of the photoelectric conversion film 113 and a signal charge holding portion (not shown). That is, the through electrode portion 122-1 serves as a transmission path for signal charges (electrons) generated in the photoelectric conversion element. Further, a through electrode insulating portion 123-1 is formed in a donut shape around the through electrode portion 122-1. The material of the through electrode insulating portion 123-1 is not particularly limited, but for example, an insulating film such as a silicon oxide film (SiO 2 ), a silicon nitride film (SiN), or a silicon oxynitride film (SiON) is used. it can.
　なお、貫通電極部１２２－１の上端は、例えば、上部コンタクト１１５－１を介して光電変換膜１１３の下部電極１１４－１と接続されている。また、貫通電極部１２２－１の下端は、接続部１３１－１と接続され、接続部１３１－１に接続されている信号電荷保持部(不図示)とも接続される。この信号電荷保持部は、シリコン１２１内に形成されるフローティングディフュージョン(FD：Floating Diffusion)であって、貫通電極部１２２－１からの信号電荷を電気信号に変換する。 Note that the upper end of the through electrode portion 122-1 is connected to the lower electrode 114-1 of the photoelectric conversion film 113 through, for example, the upper contact 115-1. Further, the lower end of the through electrode portion 122-1 is connected to the connection portion 131-1, and is also connected to a signal charge holding portion (not shown) connected to the connection portion 131-1. The signal charge holding unit is a floating diffusion (FD) formed in the silicon 121, and converts the signal charge from the through electrode unit 122-1 into an electric signal.
　貫通電極部１２２－２は、貫通電極部１２２－１と同様に、不純物をドーピングしたシリコン(Si)から構成され、その周囲には、ドーナツ状の貫通電極絶縁部１２３－２が形成されている。貫通電極部１２２－２は、光電変換膜１１３の下部電極１１４－２と、接続部１３１－２に接続されている信号電荷保持部(不図示)とを接続している。 Similar to the through electrode part 122-1, the through electrode part 122-2 is made of silicon (Si) doped with impurities, and a donut-like through electrode insulating part 123-2 is formed around the through electrode part 122-2. . The through-electrode portion 122-2 connects the lower electrode 114-2 of the photoelectric conversion film 113 and a signal charge holding portion (not shown) connected to the connection portion 131-2.
　貫通電極部１２２－３は、貫通電極部１２２－１，１２２－２と同様に、不純物をドーピングしたシリコン(Si)から構成され、その周囲には、ドーナツ状の貫通電極絶縁部１２３－３が形成されている。貫通電極部１２２－３は、光電変換膜１１３の下部電極１１４－３と、接続部１３１－３に接続されている信号電荷保持部(不図示)とを接続している。 The through electrode portion 122-3 is made of silicon (Si) doped with impurities, like the through electrode portions 122-1 and 122-2, and a donut-shaped through electrode insulating portion 123-3 is formed around the through electrode portion 122-3. Is formed. The through-electrode portion 122-3 connects the lower electrode 114-3 of the photoelectric conversion film 113 and a signal charge holding portion (not shown) connected to the connection portion 131-3.
　なお、以下の説明では、貫通電極部１２２－１乃至１２２－３を特に区別する必要がない場合、貫通電極部１２２と称する。また、貫通電極絶縁部１２３－１乃至１２３－３を特に区別する必要がない場合、貫通電極絶縁部１２３と称する。 In the following description, the through electrode portions 122-1 to 122-3 are referred to as the through electrode portions 122 when it is not necessary to distinguish them. Further, when it is not necessary to distinguish the through electrode insulating portions 123-1 to 123-3, they are referred to as through electrode insulating portions 123.
　パッド部１０１－１には、ボンディングパッドとしての接続部１３２を露出させるための開口が形成される。ここで、パッド部１０１－１(の開口)の周囲であって、シリコン基板１２には、チッピング防止用のガードリングとして、第２のガードリング部１５２－１が形成されている。この第２のガードリング部１５２－１の材料は、特に限定されないが、例えば、シリコン酸化膜(SiO2)等の絶縁膜を用いることができる。 The pad portion 101-1 is formed with an opening for exposing the connection portion 132 as a bonding pad. Here, a second guard ring portion 152-1 is formed on the silicon substrate 12 around the pad portion 101-1 (opening thereof) as a guard ring for preventing chipping. The material of the second guard ring portion 152-1 is not particularly limited, but for example, an insulating film such as a silicon oxide film (SiO 2 ) can be used.
　また、パッド部１０１－１(の開口)の周囲であって、光電変換層１１には、画素部１００を保護するためのガードリングとして、第３のガードリング部１５３Ｂ－１が形成されている。この第３のガードリング部１５３Ｂ－１は、金属膜又は絶縁膜などから構成される。具体的には、第３のガードリング部１５３Ｂ－１の材料としては、例えば、アルミニウム(Al)、タングステン(W)、チタン(Ti)、モリブデン(Mo)、タンタル(Ta)、銅(Cu)、若しくはこれらの合金膜、又は、これらの金属膜にシリコン(Si)若しくは酸素(O)を含有させた膜などを用いることができる。すなわち、第３のガードリング部１５３Ｂ－１の材料としては、水分及び酸素を透過しない材料が用いられる。 A third guard ring portion 153B-1 is formed around the pad portion 101-1 (opening thereof) and as a guard ring for protecting the pixel portion 100 in the photoelectric conversion layer 11. . The third guard ring portion 153B-1 is composed of a metal film or an insulating film. Specifically, as the material of the third guard ring portion 153B-1, for example, aluminum (Al), tungsten (W), titanium (Ti), molybdenum (Mo), tantalum (Ta), copper (Cu) Alternatively, an alloy film thereof, a film in which silicon (Si) or oxygen (O) is contained in these metal films, or the like can be used. That is, a material that does not transmit moisture and oxygen is used as the material of the third guard ring portion 153B-1.
　また、スクライブライン部１０２側、すなわち、固体撮像装置１０Ａの外周(チップの外周)であって、シリコン基板１２には、チッピング防止用のガードリングとして、第１のガードリング部１５１が形成されている。この第１のガードリング部１５１の材料は、特に限定されないが、例えば、シリコン酸化膜(SiO2)等の絶縁膜を用いることができる。 A first guard ring portion 151 is formed on the silicon substrate 12 as a guard ring for preventing chipping on the scribe line portion 102 side, that is, the outer periphery of the solid-state imaging device 10A (the outer periphery of the chip). Yes. The material of the first guard ring portion 151 is not particularly limited. For example, an insulating film such as a silicon oxide film (SiO 2 ) can be used.
　また、固体撮像装置１０Ａの外周(チップの外周)であって、光電変換層１１には、画素部１００を保護するためのガードリングとして、第３のガードリング部１５３Ａが形成されている。この第３のガードリング部１５３Ａの材料は特に限定されないが、第３のガードリング部１５３Ｂ－１と同様に、例えば、アルミニウム(Al)等の金属膜又はシリコン酸化膜(SiO2)等の絶縁膜を用いることができる。 Further, on the outer periphery of the solid-state imaging device 10 </ b> A (the outer periphery of the chip), a third guard ring portion 153 </ b> A is formed in the photoelectric conversion layer 11 as a guard ring for protecting the pixel portion 100. The material of the third guard ring portion 153A is not particularly limited, but as with the third guard ring portion 153B-1, for example, an insulating film such as a metal film such as aluminum (Al) or a silicon oxide film (SiO 2 ). A membrane can be used.
　以上、第１の実施の形態としての固体撮像装置１０Ａの構造について説明した。この固体撮像装置１０Ａでは、シリコン基板１２に形成される貫通電極部１２２によって、光電変換素子において生じた信号電荷が、信号電荷保持部に転送される。また、固体撮像装置１０Ａでは、シリコン基板１２に形成される、第１のガードリング部１５１と第２のガードリング部１５２によって、チッピングが防止され、光電変換層１１に形成される、第３のガードリング部１５３Ａ，１５３Ｂによって、画素部１００の特性劣化が抑制される。 The structure of the solid-state imaging device 10A as the first embodiment has been described above. In the solid-state imaging device 10 </ b> A, the signal charge generated in the photoelectric conversion element is transferred to the signal charge holding unit by the through electrode unit 122 formed in the silicon substrate 12. In the solid-state imaging device 10 </ b> A, the third guard ring 151 and the second guard ring 152 formed on the silicon substrate 12 prevent chipping and are formed on the photoelectric conversion layer 11. The guard ring portions 153A and 153B suppress the characteristic deterioration of the pixel portion 100.
　また、詳細は後述するが、固体撮像装置１０Ａの製造時(シリコン貫通加工時)において、シリコン基板１２に形成される、貫通電極部１２２の周囲の貫通電極絶縁部１２３と、第１のガードリング部１５１と、第２のガードリング部１５２とが、同一の工程で、かつ、同時に形成されているため、それらを別々の工程で形成した場合と比べて、製造工程を削減することができる。 Although details will be described later, the through-electrode insulating portion 123 around the through-electrode portion 122 and the first guard ring formed on the silicon substrate 12 at the time of manufacturing the solid-state imaging device 10A (during silicon penetration processing). Since the part 151 and the second guard ring part 152 are formed in the same process and at the same time, the manufacturing process can be reduced as compared with the case where they are formed in separate processes.
　なお、図２の断面図は、図１の上面図におけるＡ－Ａ'の断面を示しているため、上述した説明では、画素部１００の一部の断面と、パッド部１０１－１の周辺部の一部の断面と、固体撮像装置１０Ａの外周の周辺部(スクライブライン部１０２の周辺部)の一部の断面を代表して説明したが、例えば、パッド部１０１－２乃至１０１－１２の周辺部などの他の領域の断面についても、図２の断面における対応する部分と同様の構造を有している。 2 shows a cross section taken along the line AA ′ in the top view of FIG. 1. In the above description, a partial cross section of the pixel portion 100 and a peripheral portion of the pad portion 101-1. In the above description, a part of the cross section and a part of the outer periphery of the solid-state imaging device 10A (peripheral part of the scribe line part 102) have been described. The cross sections of other regions such as the peripheral portion have the same structure as the corresponding portions in the cross section of FIG.
（２）第２の実施の形態 (2) Second embodiment
（固体撮像装置の断面図）
　図３は、貫通電極部が導電材料を埋め込んだ構造を有する固体撮像装置１０Ｂの断面図を示す図である。 (Cross sectional view of solid-state imaging device)
FIG. 3 is a cross-sectional view of a solid-state imaging device 10B having a structure in which a through electrode portion embeds a conductive material.
　図３の固体撮像装置１０Ｂの構造は、図２の固体撮像装置１０Ａの構造と比べて、シリコン基板１２に、貫通電極部１２２－１乃至１２２－３の代わりに、貫通電極部１２５－１乃至１２５－３が形成されている点が異なっているが、それ以外の構造は、図２の固体撮像装置１０Ａと同様の構造を有している。 The structure of the solid-state imaging device 10B of FIG. 3 is different from the structure of the solid-state imaging device 10A of FIG. 2 in that the silicon substrate 12 has through electrode portions 125-1 to 125-1 instead of the through electrode portions 122-1 to 122-3. The other structure is the same as the solid-state imaging device 10A of FIG. 2 except that 125-3 is formed.
　すなわち、シリコン基板１２において、ウェハ裏面とウェハ表面との間のシリコン１２１には、光電変換素子と信号電荷保持部とを接続する貫通電極部として、金属等の導電材料からなる貫通電極部１２５－１乃至１２５－３が形成されている。 That is, in the silicon substrate 12, the silicon 121 between the wafer back surface and the wafer front surface is provided with a through electrode portion 125- made of a conductive material such as a metal as a through electrode portion for connecting the photoelectric conversion element and the signal charge holding portion. 1 to 125-3 are formed.
　貫通電極部１２５－１は、金属等の導電材料から構成され、光電変換膜１１３の下部電極１１４－１と、信号電荷保持部(不図示)とを接続している。また、貫通電極部１２５－１の周囲には、貫通電極絶縁部１２３－１がドーナツ状に形成されている。この貫通電極絶縁部１２３－１の材料としては、例えば、シリコン酸化膜(SiO2)等の絶縁膜を用いることができる。 The through electrode portion 125-1 is made of a conductive material such as metal, and connects the lower electrode 114-1 of the photoelectric conversion film 113 and a signal charge holding portion (not shown). In addition, a through electrode insulating portion 123-1 is formed in a donut shape around the through electrode portion 125-1. As a material of the through electrode insulating portion 123-1, for example, an insulating film such as a silicon oxide film (SiO 2 ) can be used.
　貫通電極部１２５－２は、貫通電極部１２５－１と同様に、金属等の導電材料から構成され、その周囲には、シリコン酸化膜(SiO2)等の絶縁膜からなる貫通電極絶縁部１２３－２がドーナツ状に形成されている。貫通電極部１２５－２は、光電変換膜１１３の下部電極１１４－２と、信号電荷保持部(不図示)とを接続している。 The through electrode portion 125-2 is made of a conductive material such as a metal like the through electrode portion 125-1 and around the through electrode insulating portion 123 made of an insulating film such as a silicon oxide film (SiO 2 ). -2 is formed in a donut shape. The through electrode portion 125-2 connects the lower electrode 114-2 of the photoelectric conversion film 113 and a signal charge holding portion (not shown).
　貫通電極部１２５－３は、貫通電極部１２５－１，１２５－２と同様に、金属等の導電材料から構成され、その周囲には、シリコン酸化膜(SiO2)等の絶縁膜からなる貫通電極絶縁部１２３－３がドーナツ状に形成されている。貫通電極部１２５－３は、光電変換膜１１３の下部電極１１４－３と、信号電荷保持部(不図示)とを接続している。 The through-electrode portion 125-3 is made of a conductive material such as a metal, like the through-electrode portions 125-1 and 125-2, and is surrounded by an insulating film such as a silicon oxide film (SiO 2 ). The electrode insulating portion 123-3 is formed in a donut shape. The through electrode portion 125-3 connects the lower electrode 114-3 of the photoelectric conversion film 113 and a signal charge holding portion (not shown).
　なお、以下の説明では、貫通電極部１２５－１乃至１２５－３を特に区別する必要がない場合、貫通電極部１２５と称する。 In the following description, the through electrode portions 125-1 to 125-3 are referred to as the through electrode portions 125 when it is not necessary to particularly distinguish them.
　図３の固体撮像装置１０Ｂにおいても、図２の固体撮像装置１０Ａと同様に、パッド部１０１－１(の開口)の周囲であって、シリコン基板１２には、チッピング防止用のガードリングとして、第２のガードリング部１５２－１が形成され、光電変換層１１には、画素部１００を保護するためのガードリングとして、第３のガードリング部１５３Ｂ－１が形成されている。 Also in the solid-state imaging device 10B of FIG. 3, as with the solid-state imaging device 10A of FIG. 2, the silicon substrate 12 has a guard ring for preventing chipping around the pad portion 101-1 (opening thereof). A second guard ring portion 152-1 is formed, and a third guard ring portion 153B-1 is formed in the photoelectric conversion layer 11 as a guard ring for protecting the pixel portion 100.
　また、図３の固体撮像装置１０Ｂにおいても、図２の固体撮像装置１０Ａと同様に、固体撮像装置１０の外周(スクライブライン部１０２側)であって、シリコン基板１２には、チッピング防止用のガードリングとして、第１のガードリング部１５１が形成され、光電変換層１１には、画素部１００を保護するためのガードリングとして、第３のガードリング部１５３Ａが形成されている。 Further, in the solid-state imaging device 10B of FIG. 3 as well as the solid-state imaging device 10A of FIG. 2, the outer periphery of the solid-state imaging device 10 (on the scribe line unit 102 side) is provided on the silicon substrate 12 for preventing chipping. A first guard ring portion 151 is formed as a guard ring, and a third guard ring portion 153 A is formed in the photoelectric conversion layer 11 as a guard ring for protecting the pixel portion 100.
　以上、第２の実施の形態としての固体撮像装置１０Ｂの構造について説明した。この固体撮像装置１０Ｂでは、シリコン基板１２に形成される貫通電極部１２５によって、光電変換素子によって生じた信号電荷が、信号電荷保持部に転送される。また、固体撮像装置１０Ｂでは、シリコン基板１２に形成される、第１のガードリング部１５１と第２のガードリング部１５２によって、チッピングが防止され、光電変換層１１に形成される、第３のガードリング部１５３Ａ，１５３Ｂによって、画素部１００の特性劣化が抑制される。 The structure of the solid-state imaging device 10B as the second embodiment has been described above. In the solid-state imaging device 10B, the signal charge generated by the photoelectric conversion element is transferred to the signal charge holding unit by the through electrode unit 125 formed in the silicon substrate 12. In the solid-state imaging device 10 </ b> B, the third guard ring 151 and the second guard ring 152 formed on the silicon substrate 12 prevent chipping and are formed on the photoelectric conversion layer 11. The guard ring portions 153A and 153B suppress the characteristic deterioration of the pixel portion 100.
　また、詳細は後述するが、固体撮像装置１０Ｂの製造時(シリコン貫通加工時)において、シリコン基板１２に形成される、貫通電極部１２５の周囲の貫通電極絶縁部１２３と、第１のガードリング部１５１と、第２のガードリング部１５２とが、同一の工程で、かつ、同時に形成されているため、それらを別々の工程で形成した場合と比べて、製造工程を削減することができる。 Although details will be described later, the through-electrode insulating portion 123 around the through-electrode portion 125 and the first guard ring formed on the silicon substrate 12 at the time of manufacturing the solid-state imaging device 10B (during silicon through processing). Since the part 151 and the second guard ring part 152 are formed in the same process and at the same time, the manufacturing process can be reduced as compared with the case where they are formed in separate processes.
（３）第３の実施の形態 (3) Third embodiment
　図４は、埋め込み部の底部に素子分離で使用する絶縁膜を形成した構造を有する固体撮像装置１０Ｃの断面図を示す図である。 FIG. 4 is a cross-sectional view of a solid-state imaging device 10C having a structure in which an insulating film used for element isolation is formed at the bottom of the embedded portion.
　図４の固体撮像装置１０Ｃの構造は、図２の固体撮像装置１０Ａ及び図３の固体撮像装置１０Ｂと比べて、シリコン基板１２に形成される、第１のガードリング部１５１と第２のガードリング部１５２(１５２－１)の底部に、素子分離で使用する絶縁膜１２８と絶縁膜１２９(１２９－１)がそれぞれ形成されている。絶縁膜１２８と絶縁膜１２９(１２９－１)としては、例えば、シリコン酸化膜(SiO2)等を用いることができる。 The structure of the solid-state imaging device 10C in FIG. 4 has a first guard ring portion 151 and a second guard formed on the silicon substrate 12 as compared to the solid-state imaging device 10A in FIG. 2 and the solid-state imaging device 10B in FIG. An insulating film 128 and an insulating film 129 (129-1) used for element isolation are formed on the bottom of the ring portion 152 (152-1). As the insulating film 128 and the insulating film 129 (129-1), for example, a silicon oxide film (SiO 2 ) or the like can be used.
　具体的には、シリコン基板１２において、第１のガードリング部１５１として用いられる絶縁膜が埋め込まれる埋め込み部の底部に、絶縁膜１２８が形成されている。また、第２のガードリング部１５２(１５２－１)として用いられる絶縁膜が埋め込まれる埋め込み部の底部に、絶縁膜１２９(１２９－１)が形成されている。 Specifically, in the silicon substrate 12, an insulating film 128 is formed at the bottom of the embedded portion in which the insulating film used as the first guard ring portion 151 is embedded. In addition, an insulating film 129 (129-1) is formed at the bottom of the buried portion where the insulating film used as the second guard ring portion 152 (152-1) is buried.
　このように、第１のガードリング部１５１と第２のガードリング部１５２(１５２－１)の底部に、素子分離で使用する絶縁膜１２８と絶縁膜１２９(１２９－１)が形成されるようにすることで、この絶縁膜１２８と絶縁膜１２９(１２９－１)を、加工時のストッパとして用いることができる。 As described above, the insulating film 128 and the insulating film 129 (129-1) used for element isolation are formed at the bottoms of the first guard ring portion 151 and the second guard ring portion 152 (152-1). Thus, the insulating film 128 and the insulating film 129 (129-1) can be used as a stopper at the time of processing.
　以上、本技術を適用した固体撮像装置１０の構造について説明した。なお、本技術を適用した固体撮像装置１０は、上述した第１の実施の形態乃至第３の実施の形態で説明した各構成要素をすべて備えている必要はなく、また逆に他の構成要素を備えていてもよい。 The structure of the solid-state imaging device 10 to which the present technology is applied has been described above. Note that the solid-state imaging device 10 to which the present technology is applied does not have to include all the components described in the first to third embodiments, and conversely, other components. May be provided.
＜２．製造工程の流れ＞ <2. Flow of manufacturing process>
　次に、本技術を適用した固体撮像装置１０の製造工程の流れについて説明する。ここでは、上述した第１の実施の形態乃至第３の実施の形態のうち、第１の実施の形態としての固体撮像装置１０Ａの製造工程を代表して説明する。また、当該製造工程において、シリコン基板１２に、貫通電極絶縁部１２３、第１のガードリング部１５１、及び、第２のガードリング部１５２を形成するためのシリコン貫通加工の工程は、ウェハ表面側又はウェハ裏面側から行われる場合があるので、それらを別の製造工程として説明する。 Next, the flow of the manufacturing process of the solid-state imaging device 10 to which the present technology is applied will be described. Here, the manufacturing process of the solid-state imaging device 10A as the first embodiment of the first to third embodiments described above will be described as a representative. In the manufacturing process, the silicon penetration process for forming the through electrode insulating part 123, the first guard ring part 151, and the second guard ring part 152 on the silicon substrate 12 is performed on the wafer surface side. Or since it may be performed from the wafer back surface side, these are demonstrated as another manufacturing process.
（１）ウェハ表面側からシリコン貫通加工を行う場合の製造工程 (1) Manufacturing process when performing through-silicon processing from the wafer surface side
　図５は、ウェハ表面側からシリコン貫通加工を行う場合の固体撮像装置１０Ａの製造工程の流れを説明するフローチャートである。なお、図６乃至図８には、図５の製造工程が模式的に表されており、それらの図を適宜参照しながら、図５のフローチャートにおける各工程の詳細な内容を説明するものとする。ただし、図６乃至図８の断面図は、図１の上面図におけるＡ－Ａ'の断面に対応している。 FIG. 5 is a flowchart for explaining the flow of the manufacturing process of the solid-state imaging device 10 </ b> A in the case of performing silicon penetration processing from the wafer surface side. 6 to 8 schematically show the manufacturing process of FIG. 5, and the detailed contents of each process in the flowchart of FIG. 5 will be described with reference to these drawings as appropriate. . However, the cross-sectional views of FIGS. 6 to 8 correspond to the cross section AA ′ in the top view of FIG.
　ステップＳ１０１においては、不純物イオン注入工程が行われる。 In step S101, an impurity ion implantation step is performed.
　この不純物イオン注入工程では、図６のＡに示すように、シリコン基板１２のウェハ表面側であって、シリコン１２１上に設けられたフォトレジスト１６１の開口部分から、不純物イオンが注入されることで、その不純物イオンが注入された部分に、貫通電極部１２２－１乃至１２２－３が形成される。なお、不純物イオンの注入後、フォトレジスト１６１は、シリコン１２１上から剥がされる。 In this impurity ion implantation step, as shown in FIG. 6A, impurity ions are implanted from the opening portion of the photoresist 161 provided on the silicon 121 on the wafer surface side of the silicon substrate 12. Through electrode portions 122-1 to 122-3 are formed in the portions where the impurity ions are implanted. Note that after the implantation of impurity ions, the photoresist 161 is peeled off from the silicon 121.
　ステップＳ１０２においては、シリコン貫通加工・絶縁膜埋め込み工程が行われる。 In step S102, a silicon through process / insulating film embedding process is performed.
　このシリコン貫通加工・絶縁膜埋め込み工程では、図６のＢに示すように、まず、シリコン基板１２のウェハ表面側から、不純物イオンが注入されたシリコン１２１の貫通加工が行われ、各貫通電極部１２２の周囲に、貫通電極絶縁部１２３用の絶縁膜を埋め込むためのドーナツ状の開口(溝状の埋め込み部)が形成される。また、この貫通加工によって、第１のガードリング部１５１用の絶縁膜を埋め込むための開口(溝状の埋め込み部)が、スクライブライン部１０２の周辺部に形成され、第２のガードリング部１５２(１５２－１)用の絶縁膜を埋め込むための開口(溝状の埋め込み部)が、パッド部１０１(１０１－１)の周辺部に形成される。 In this silicon penetration processing / insulating film embedding step, as shown in FIG. 6B, first, through processing of silicon 121 into which impurity ions are implanted is performed from the wafer surface side of the silicon substrate 12, each through electrode portion. A donut-shaped opening (groove-shaped embedded portion) for embedding an insulating film for the through-electrode insulating portion 123 is formed around the periphery of 122. In addition, an opening (groove-like embedded portion) for embedding the insulating film for the first guard ring portion 151 is formed in the peripheral portion of the scribe line portion 102 by this penetration processing, and the second guard ring portion 152 is formed. An opening (groove-shaped buried portion) for embedding the insulating film for (152-1) is formed in the peripheral portion of the pad portion 101 (101-1).
　ここで、貫通電極絶縁部１２３用の絶縁膜を埋め込むための開口(溝状の埋め込み部)と、第１のガードリング部１５１用の絶縁膜を埋め込むための開口(溝状の埋め込み部)と、第２のガードリング部１５２(１５２－１)用の絶縁膜を埋め込むための開口(溝状の埋め込み部)とは、シリコン１２１の貫通加工によって同時に形成されるが、それらの開口幅は、同一の幅、又は、第１のガードリング部１５１及び第２のガードリング部１５２(１５２－１)の絶縁膜を埋め込むための開口の開口幅のほうが広くなるように形成される。 Here, an opening (groove-shaped embedded portion) for embedding the insulating film for the through electrode insulating portion 123, and an opening (groove-shaped embedded portion) for embedding the insulating film for the first guard ring portion 151, The openings (groove-like embedded portions) for embedding the insulating film for the second guard ring portion 152 (152-1) are simultaneously formed by the penetration processing of the silicon 121. They are formed to have the same width or the opening width of the opening for embedding the insulating film of the first guard ring portion 151 and the second guard ring portion 152 (152-1).
　シリコン１２１の貫通加工により形成される各開口の幅を、同一の幅に揃えることで、同じパターンで、絶縁膜が埋め込まれる埋め込み部を形成することができるため、シリコン１２１に、貫通電極絶縁部１２３、第１のガードリング部１５１、及び、第２のガードリング部１５２(１５２－１)を形成する工程を容易に行うことができる。 By aligning the width of each opening formed by the penetration processing of the silicon 121 to the same width, it is possible to form a buried portion in which the insulating film is embedded with the same pattern. 123, the step of forming the first guard ring portion 151 and the second guard ring portion 152 (152-1) can be easily performed.
　また、第１のガードリング部１５１及び第２のガードリング部１５２(１５２－１)の絶縁膜を埋め込むための開口の幅を、貫通電極絶縁部１２３用の絶縁膜を埋め込むための開口の幅よりも広くできる理由であるが、画素部１００の周辺部は、レイアウト上の制約が大きく、一方で、パッド部１０１やスクライブライン部１０２の周辺部は、画素部１００の周辺部ほど、レイアウト上の制約はない。そのため、スクライブライン部１０２の周辺部に配置される第１のガードリング部１５１と、パッド部１０１の周辺部に配置される第２のガードリング部１５２(１５２－１)の絶縁膜を埋め込むための開口の幅を広くしても、レイアウト上の制約を受ける可能性はほとんどない。 The width of the opening for embedding the insulating film of the first guard ring portion 151 and the second guard ring portion 152 (152-1) is the width of the opening for embedding the insulating film for the through electrode insulating portion 123. This is because the peripheral portion of the pixel portion 100 has a large layout restriction. On the other hand, the peripheral portion of the pad portion 101 and the scribe line portion 102 is closer to the layout portion than the peripheral portion of the pixel portion 100. There are no restrictions. Therefore, in order to embed the insulating films of the first guard ring portion 151 disposed in the peripheral portion of the scribe line portion 102 and the second guard ring portion 152 (152-1) disposed in the peripheral portion of the pad portion 101. Even if the width of the opening is increased, there is almost no possibility of being restricted by the layout.
　具体的な値を例示すれば、第１のガードリング部１５１及び第２のガードリング部１５２(１５２－１)の絶縁膜を埋め込むための開口の幅(溝状の埋め込み部の溝の幅)は、例えば、0.1μm～0.5μmの範囲内のいずれかの幅、あるいは、0.2μm～0.4μmの範囲内のいずれかの幅とすることができる。 For example, the width of the opening for embedding the insulating film of the first guard ring portion 151 and the second guard ring portion 152 (152-1) (the width of the groove of the groove-shaped embedded portion). Can be, for example, any width within the range of 0.1 μm to 0.5 μm, or any width within the range of 0.2 μm to 0.4 μm.
　このようにして、シリコン１２１の貫通加工を行うに際して、画素部１００に形成される貫通電極絶縁部１２３用の絶縁膜を埋め込むための開口(溝状の埋め込み部)と、パッド部１０１の周辺部に形成される第２のガードリング部１５２(１５２－１)用の絶縁膜を埋め込むための開口(溝状の埋め込み部)と、スクライブライン部１０２の周辺部に形成される第１のガードリング部１５１用の絶縁膜を埋め込むための開口(溝状の埋め込み部)とが、同時に形成されることになる。 In this way, when performing penetration processing of the silicon 121, an opening (groove-shaped buried portion) for embedding an insulating film for the through electrode insulating portion 123 formed in the pixel portion 100, and a peripheral portion of the pad portion 101 An opening (groove-shaped embedded portion) for embedding an insulating film for the second guard ring portion 152 (152-1) formed in the first guard ring, and a first guard ring formed in the peripheral portion of the scribe line portion 102 An opening (groove-shaped buried portion) for embedding the insulating film for the portion 151 is formed at the same time.
　そして、シリコン貫通加工・絶縁膜埋め込み工程では、図６のＢに示すように、シリコン貫通加工によって、複数の開口(溝状の埋め込み部)が同時に形成されると、それらの開口(溝状の埋め込み部)に、絶縁膜がそれぞれ埋め込まれる。 In the through silicon processing / insulating film embedding process, as shown in FIG. 6B, when a plurality of openings (groove-shaped embedded portions) are simultaneously formed by through silicon processing, these openings (groove-shaped embedded portions) are formed. Insulating films are embedded in the embedded portions).
　これにより、シリコン基板１２において、画素部１００における各貫通電極部１２２の周囲には、ドーナツ状に貫通電極絶縁部１２３がそれぞれ形成されるとともに、パッド部１０１の周辺部には、第２のガードリング部１５２(１５２－１)が形成され、スクライブライン部１０２の周辺部には、第１のガードリング部１５１が形成される。 As a result, in the silicon substrate 12, the through electrode insulating part 123 is formed in a donut shape around each through electrode part 122 in the pixel unit 100, and the second guard is formed around the pad part 101. A ring portion 152 (152-1) is formed, and a first guard ring portion 151 is formed around the scribe line portion 102.
　すなわち、第１のガードリング部１５１用の絶縁膜を埋め込むための開口(溝状の埋め込み部)に埋め込まれた絶縁膜が、後述するダイシング工程(Ｓ１０８)でのチッピング防止用の第１のガードリング部１５１として機能し、第２のガードリング部１５２(１５２－１)用の絶縁膜を埋め込むための開口(溝状の埋め込み部)に埋め込まれた絶縁膜が、後述するパッド部開口工程(Ｓ１０７)におけるドライエッチング加工でのチッピング防止用の第２のガードリング部１５２(１５２－１)として機能することになる。 That is, the insulating film embedded in the opening (groove-shaped embedded portion) for embedding the insulating film for the first guard ring portion 151 is the first guard for preventing chipping in the dicing process (S108) described later. The insulating film that functions as the ring portion 151 and is embedded in the opening (groove-shaped embedded portion) for embedding the insulating film for the second guard ring portion 152 (152-1) is a pad portion opening step (to be described later) It functions as the second guard ring portion 152 (152-1) for preventing chipping in the dry etching process in S107).
　ステップＳ１０３においては、配線層形成工程が行われる。 In step S103, a wiring layer forming step is performed.
　この配線層形成工程では、図６のＣに示すように、シリコン基板１２のウェハ表面側に、配線層１３が形成される。 In this wiring layer forming step, the wiring layer 13 is formed on the wafer surface side of the silicon substrate 12 as shown in FIG.
　ステップＳ１０４においては、ウェハ表裏反転工程が行われる。 In step S104, a wafer front / back reversing process is performed.
　このウェハ表裏反転工程では、図７のＡに示すように、シリコン基板１２のウェハ表面と裏面とが反転され、配線層１３上に、シリコン基板１２が積層された状態とされる。 In this wafer front / back reversing step, as shown in FIG. 7A, the wafer front and back surfaces of the silicon substrate 12 are reversed, and the silicon substrate 12 is laminated on the wiring layer 13.
　ステップＳ１０５においては、光電変換素子・絶縁膜成膜工程が行われる。 In step S105, a photoelectric conversion element / insulating film forming step is performed.
　この光電変換素子・絶縁膜成膜工程では、図７のＢに示すように、シリコン基板１２のウェハ裏面側に、下部電極１１４－１乃至１１４－３、光電変換膜１１３、及び、上部電極１１２が、この順に積層されることで、光電変換素子が形成される。また、この光電変換素子を含む画素部１００の領域とその周辺の周辺領域(パッド部１０１とスクライブライン部１０２の周辺部を含む領域)上には、絶縁膜１１１が形成される。 In this photoelectric conversion element / insulating film forming step, as shown in FIG. 7B, the lower electrodes 114-1 to 114-3, the photoelectric conversion film 113, and the upper electrode 112 are formed on the wafer rear surface side of the silicon substrate 12. However, a photoelectric conversion element is formed by laminating in this order. An insulating film 111 is formed on the region of the pixel portion 100 including the photoelectric conversion element and the peripheral region around the pixel portion 100 (region including the peripheral portion of the pad portion 101 and the scribe line portion 102).
　ステップＳ１０６においては、第３のガードリング形成工程が行われる。 In step S106, a third guard ring forming step is performed.
　この第３のガードリング形成工程では、図７のＣに示すように、画素部１００の領域とその周辺の周辺領域(パッド部１０１とスクライブライン部１０２の周辺部を含む領域)上に形成された絶縁膜１１１において、パッド部１０１の周辺部に、金属膜又は絶縁膜からなる壁状の第３のガードリング部１５３Ｂ(１５３Ｂ－１)が形成され、スクライブライン部１０２の周辺部に、金属膜又は絶縁膜からなる壁状の第３のガードリング部１５３Ａが形成される。 In the third guard ring forming step, as shown in FIG. 7C, the pixel is formed on the region of the pixel portion 100 and its peripheral region (the region including the peripheral portion of the pad portion 101 and the scribe line portion 102). In the insulating film 111, a wall-shaped third guard ring part 153B (153B-1) made of a metal film or an insulating film is formed around the pad part 101, and a metal part is formed around the scribe line part 102. A wall-like third guard ring portion 153A made of a film or an insulating film is formed.
　ただし、第３のガードリング部１５３Ａ，１５３Ｂ(１５３Ｂ－１)は、シリコン基板１２の上側(ウェハ裏面側)の光電変換層１１に形成されるが、第３のガードリング部１５３Ａ，１５３Ｂ(１５３Ｂ－１)の底部(金属膜や絶縁膜等の底部)を、シリコン基板１２と接続させることが望ましい。このような構造とすることで、水分等の侵入を確実に遮断することが可能となるためである。 However, the third guard ring portions 153A and 153B (153B-1) are formed on the photoelectric conversion layer 11 on the upper side (wafer back side) of the silicon substrate 12, but the third guard ring portions 153A and 153B (153B) are formed. It is desirable to connect the bottom of (-1) (the bottom of a metal film, an insulating film, etc.) to the silicon substrate 12. This is because by adopting such a structure, it is possible to reliably block the entry of moisture and the like.
　このように、パッド部１０１の周辺部に、第３のガードリング部１５３Ｂ(１５３Ｂ－１)を形成することで、例えば、接続部１３２上の開口の側面などの横方向から進入してきた水分等を遮断し、スクライブライン部１０２の周辺部に、第３のガードリング部１５３Ａを形成することで、例えば、固体撮像装置１０の端面の横方向から進入してきた水分等を遮断することができる。その結果、画素部１００の特性劣化を抑制することができる。 Thus, by forming the third guard ring portion 153B (153B-1) in the peripheral portion of the pad portion 101, for example, moisture entering from the lateral direction such as the side surface of the opening on the connection portion 132, etc. By forming the third guard ring portion 153A in the peripheral portion of the scribe line portion 102, for example, moisture that has entered from the lateral direction of the end face of the solid-state imaging device 10 can be blocked. As a result, deterioration of the characteristics of the pixel unit 100 can be suppressed.
　ステップＳ１０７においては、パッド部開口工程が行われる。 In step S107, a pad opening process is performed.
　このパッド部開口工程では、図８のＡに示すように、ドライエッチング加工が行われ、パッド部１０１が形成される。このドライエッチング加工に際しては、ステップＳ１０２の工程で、シリコン基板１２に、第２のガードリング部１５２(１５２－１)が形成されているため、例えば、シリコン屑やダメージによりキズが入ったりするなどのチッピングが防止される。 In this pad portion opening process, as shown in FIG. 8A, dry etching is performed to form the pad portion 101. In this dry etching process, since the second guard ring part 152 (152-1) is formed on the silicon substrate 12 in the process of step S102, for example, scratches may occur due to silicon dust or damage. Chipping is prevented.
　ステップＳ１０８においては、ダイシング工程が行われる。 In step S108, a dicing process is performed.
　このダイシング工程では、図８のＢに示すように、ダイシングブレード(不図示)によってシリコン基板１２等が矩形状に切断され、固体撮像装置１０が切り出される(個片化される)。このダイシング工程に際しては、ステップＳ１０２の工程で、シリコン基板１２に、第１のガードリング部１５１が形成されているため、例えば、シリコン屑やダメージによりキズが入ったりするなどのチッピングが防止される。 In this dicing step, as shown in FIG. 8B, the silicon substrate 12 and the like are cut into a rectangular shape by a dicing blade (not shown), and the solid-state imaging device 10 is cut out (separated). In the dicing process, since the first guard ring portion 151 is formed on the silicon substrate 12 in the process of step S102, for example, chipping such as scratches caused by silicon dust or damage is prevented. .
　なお、詳細な内容については省略するが、ステップＳ１０８の工程が終了すると、ダイシング工程により切り出された複数の固体撮像装置１０に対する、パッケージソート工程などが行われる。 Although detailed contents are omitted, when the process of step S108 is completed, a package sorting process or the like is performed on the plurality of solid-state imaging devices 10 cut out by the dicing process.
　以上、ウェハ表面側からシリコン貫通加工を行う場合の固体撮像装置１０Ａの製造工程の流れについて説明した。この製造工程においては、ステップＳ１０２のシリコン貫通加工・絶縁膜埋め込み工程で、シリコン基板１２に、貫通電極部１２２の周囲の貫通電極絶縁部１２３と、第１のガードリング部１５１と、第２のガードリング部１５２とを同時に形成することができるため、貫通電極部とガードリング部が形成されたシリコン基板を有する固体撮像装置１０Ａの製造時における製造工程を削減することができる。 The flow of the manufacturing process of the solid-state imaging device 10 </ b> A when performing silicon penetration processing from the wafer surface side has been described above. In this manufacturing process, in the silicon through-processing / insulating film embedding process in step S102, the silicon substrate 12 is provided with the through-electrode insulating part 123 around the through-electrode part 122, the first guard ring part 151, and the second Since the guard ring part 152 can be formed at the same time, it is possible to reduce the manufacturing process at the time of manufacturing the solid-state imaging device 10A having the silicon substrate on which the through electrode part and the guard ring part are formed.
　例えば、従来の固体撮像装置の製造方法であると、まず、シリコン基板に対して、表面側から、ガードリング部を形成するための掘り込みを行った後に、ウェハの表裏を反転させて、裏面側から、貫通電極部を形成するための掘り込みを行っていたため、２段階の工程が必要であったが、本技術では、それらの掘り込みの工程を同時に行うことができるので、製造工程を削減することができる。 For example, in the conventional method for manufacturing a solid-state imaging device, first, after performing digging for forming a guard ring portion from the front surface side to the silicon substrate, the front and back surfaces of the wafer are reversed, and the back surface Since the digging for forming the through electrode portion was performed from the side, two steps were necessary. However, in the present technology, the digging steps can be performed at the same time. Can be reduced.
（２）ウェハ裏面側からシリコン貫通加工を行う場合の製造工程 (2) Manufacturing process when performing through-silicon processing from the back side of the wafer
　図９は、ウェハ裏面側からシリコン貫通加工を行う場合の固体撮像装置１０Ａの製造工程の流れを説明するフローチャートである。なお、図１０乃至図１３には、図９の製造工程が模式的に表されており、それらの図を適宜参照しながら、図９のフローチャートにおける各工程の詳細な内容を説明するものとする。ただし、図１０乃至図１２の断面図は、図１の上面図におけるＡ－Ａ'の断面に対応している。 FIG. 9 is a flowchart for explaining the flow of the manufacturing process of the solid-state imaging device 10 </ b> A in the case of performing silicon penetration processing from the back side of the wafer. 9 to 13 schematically show the manufacturing process of FIG. 9, and the detailed contents of each process in the flowchart of FIG. 9 will be described with reference to those drawings as appropriate. . However, the cross-sectional views of FIGS. 10 to 12 correspond to the cross section AA ′ in the top view of FIG.
　ステップＳ２０１においては、不純物イオン注入工程が行われる。 In step S201, an impurity ion implantation process is performed.
　この不純物イオン注入工程では、図１０のＡに示すように、シリコン基板１２のウェハ表面側であって、シリコン１２１上に設けられたフォトレジスト１６１の開口部分から、不純物イオンが注入されることで、その不純物イオンが注入された部分に、貫通電極部１２２－１乃至１２２－３が形成される。なお、不純物イオンの注入後、フォトレジスト１６１は、シリコン１２１上から剥がされる。 In this impurity ion implantation step, as shown in FIG. 10A, impurity ions are implanted from the opening portion of the photoresist 161 provided on the silicon 121 on the wafer surface side of the silicon substrate 12. Through electrode portions 122-1 to 122-3 are formed in the portions where the impurity ions are implanted. Note that after the implantation of impurity ions, the photoresist 161 is peeled off from the silicon 121.
　ステップＳ２０２においては、配線層形成工程が行われる。 In step S202, a wiring layer forming process is performed.
　この配線層形成工程では、図１０のＢに示すように、シリコン基板１２のウェハ表面側に、配線層１３が形成される。 In this wiring layer forming step, the wiring layer 13 is formed on the wafer surface side of the silicon substrate 12 as shown in FIG.
　ステップＳ２０３においては、ウェハ表裏反転工程が行われる。 In step S203, a wafer front / back reversing process is performed.
　このウェハ表裏反転工程では、図１０のＣに示すように、シリコン基板１２のウェハ表面と裏面とが反転され、配線層１３上に、シリコン基板１２が積層された状態とされる。 In this wafer front / back reversing step, as shown in FIG. 10C, the front surface and back surface of the silicon substrate 12 are reversed, and the silicon substrate 12 is laminated on the wiring layer 13.
　ステップＳ２０４においては、シリコン貫通加工・固定電荷膜成膜・絶縁膜埋め込み工程が行われる。 In step S204, a silicon penetration process, a fixed charge film formation process, and an insulating film embedding process are performed.
　このシリコン貫通加工・固定電荷膜成膜・絶縁膜埋め込み工程では、図１１のＡに示すように、まず、シリコン基板１２の裏面側から、不純物イオンが注入されたシリコン１２１の貫通加工が行われ、各貫通電極部１２２の周囲に、貫通電極絶縁部１２３用のドーナツ状(溝状)の開口が形成される。また、この貫通加工によって、第１のガードリング部１５１を形成するための溝状の開口が、スクライブライン部１０２の周辺部に形成され、第２のガードリング部１５２(１５２－１)を形成するための溝状の開口が、パッド部１０１の周辺部に形成される。 In this through silicon processing / fixed charge film formation / insulating film embedding step, first, through the silicon 121 into which impurity ions are implanted is performed from the back side of the silicon substrate 12, as shown in FIG. 11A. A donut-shaped (groove-shaped) opening for the through-electrode insulating portion 123 is formed around each through-electrode portion 122. In addition, a groove-shaped opening for forming the first guard ring portion 151 is formed in the peripheral portion of the scribe line portion 102 by this penetration processing, thereby forming the second guard ring portion 152 (152-1). A groove-shaped opening is formed in the peripheral portion of the pad portion 101.
　すなわち、シリコン１２１の貫通加工を行うに際して、画素部１００に形成される貫通電極絶縁部１２３用の絶縁膜を埋め込むための開口(溝状の埋め込み部)と、パッド部１０１の周囲に形成される第２のガードリング部１５２(１５２－１)用の絶縁膜を埋め込むための(溝状の埋め込み部)と、スクライブライン部１０２の周辺部に形成される第１のガードリング部１５１用の絶縁膜を埋め込むための開口(溝状の埋め込み部)とが、同時に形成されることになる。 That is, when performing the penetration processing of the silicon 121, an opening (groove-shaped buried portion) for embedding an insulating film for the through electrode insulating portion 123 formed in the pixel portion 100 and the periphery of the pad portion 101 are formed. An insulating film for embedding the insulating film for the second guard ring portion 152 (152-1) (groove-shaped embedding portion) and an insulation for the first guard ring portion 151 formed around the scribe line portion 102 Openings (groove-shaped buried portions) for embedding the film are formed at the same time.
　シリコン貫通加工・固定電荷膜成膜・絶縁膜埋め込み工程では、シリコン貫通加工によって複数の開口(溝状の埋め込み部)が同時に形成されると、次に、図１１のＡに示すように、シリコン１２１の表面上に、固定電荷膜１７１が成膜され、さらに、固定電荷膜１７１が成膜された各開口(溝状の埋め込み部)には、絶縁膜がそれぞれ埋め込まれる。 In the through silicon processing / fixed charge film formation / insulating film embedding step, when a plurality of openings (groove-shaped embedded portions) are formed simultaneously by through silicon processing, silicon is then formed as shown in FIG. A fixed charge film 171 is formed on the surface of 121, and an insulating film is embedded in each opening (groove-shaped embedded portion) where the fixed charge film 171 is formed.
　これにより、シリコン基板１２において、画素部１００における各貫通電極部１２２の周囲には、ドーナツ状に貫通電極絶縁部１２３がそれぞれ形成されるとともに、パッド部１０１の周辺部には、第２のガードリング部１５２(１５２－１)が形成され、スクライブライン部１０２の周辺部には、第１のガードリング部１５１がそれぞれ形成される。 As a result, in the silicon substrate 12, the through electrode insulating part 123 is formed in a donut shape around each through electrode part 122 in the pixel unit 100, and the second guard is formed around the pad part 101. A ring portion 152 (152-1) is formed, and a first guard ring portion 151 is formed around the scribe line portion 102, respectively.
　すなわち、第１のガードリング部１５１用の絶縁膜を埋め込むための開口(溝状の埋め込み部)に埋め込まれた絶縁膜が、後述するダイシング工程(Ｓ２０８)でのチッピング防止用の第１のガードリング部１５１として機能し、第２のガードリング部１５２(１５２－１)用の絶縁膜を埋め込むための開口(溝状の埋め込み部)に埋め込まれた絶縁膜が、後述するパッド部開口工程(Ｓ２０７)におけるドライエッチング加工でのチッピング防止用の第２のガードリング部１５２(１５２－１)として機能することになる。 That is, the insulating film embedded in the opening (groove-shaped embedded portion) for embedding the insulating film for the first guard ring portion 151 is the first guard for preventing chipping in the dicing process (S208) described later. The insulating film that functions as the ring portion 151 and is embedded in the opening (groove-shaped embedded portion) for embedding the insulating film for the second guard ring portion 152 (152-1) is a pad portion opening step (to be described later) It functions as the second guard ring portion 152 (152-1) for preventing chipping in the dry etching process in S207).
　なお、図１３は、シリコン貫通加工・固定電荷膜成膜・絶縁膜埋め込み工程(Ｓ２０４)を、より詳細に表したものである。すなわち、図１３のＡがシリコン貫通加工の工程、図１３のＢが固定電荷膜成膜の工程、図１３のＣが絶縁膜埋め込みの工程を表しており、これらの工程が順に行われることで、シリコン基板１２に、貫通電極絶縁部１２３、第１のガードリング部１５１、及び、第２のガードリング部１５２(１５２－１)が、同一の工程で、かつ、同時に形成されることになる。 FIG. 13 shows the silicon penetration processing, fixed charge film formation, and insulating film embedding step (S204) in more detail. That is, FIG. 13A shows a through silicon processing step, FIG. 13B shows a fixed charge film forming step, and FIG. 13C shows an insulating film embedding step, and these steps are sequentially performed. The through electrode insulating portion 123, the first guard ring portion 151, and the second guard ring portion 152 (152-1) are formed on the silicon substrate 12 in the same process and simultaneously. .
　また、固定電荷膜１７１としては、例えば、いわゆる白飛びなどを防止する目的で、負の固定電荷膜を用いることができるが、負の固定電荷膜を用いる場合、その目的から、画素部１００側にのみ、負の固定電荷膜を成膜するのが一般的である。一方で、本技術を適用した固体撮像装置１０の製造工程では、画素部１００側の貫通電極絶縁部１２３と、パッド部１０１の周辺部の第２のガードリング部１５２(１５２－１)と、スクライブライン部１０２の周辺部の第１のガードリング部１５１とを同時に形成しているため、画素部１００の領域のほかに、その周辺の周辺領域(パッド部１０１とスクライブライン部１０２の周辺部を含む領域)にも、固定電荷膜１７１が成膜されることになる。 In addition, as the fixed charge film 171, for example, a negative fixed charge film can be used for the purpose of preventing so-called whiteout. However, when a negative fixed charge film is used, the pixel unit 100 side is used for that purpose. In general, a negative fixed charge film is generally formed. On the other hand, in the manufacturing process of the solid-state imaging device 10 to which the present technology is applied, the through electrode insulating portion 123 on the pixel portion 100 side, the second guard ring portion 152 (152-1) in the peripheral portion of the pad portion 101, Since the first guard ring portion 151 in the peripheral portion of the scribe line portion 102 is formed at the same time, in addition to the region of the pixel portion 100, the peripheral region (the peripheral portion of the pad portion 101 and the scribe line portion 102). The fixed charge film 171 is also formed in the region including the.
　ステップＳ２０５においては、光電変換素子・絶縁膜成膜工程が行われる。 In step S205, a photoelectric conversion element / insulating film forming step is performed.
　この光電変換素子・絶縁膜成膜工程では、図１１のＢに示すように、シリコン基板１２のウェハ裏面側に、下部電極１１４－１乃至１１４－３、光電変換膜１１３、及び、上部電極１１２が、この順に積層されることで、光電変換素子が形成される。また、この光電変換素子を含む画素部１００の領域とその周辺領域(パッド部１０１とスクライブライン部１０２の周辺部を含む領域)上には、絶縁膜１１１が形成される。 In this photoelectric conversion element / insulating film forming step, as shown in FIG. 11B, the lower electrodes 114-1 to 114-3, the photoelectric conversion film 113, and the upper electrode 112 are formed on the wafer rear surface side of the silicon substrate 12. However, a photoelectric conversion element is formed by laminating in this order. Further, an insulating film 111 is formed on the region of the pixel portion 100 including the photoelectric conversion element and its peripheral region (region including the peripheral portion of the pad portion 101 and the scribe line portion 102).
　ステップＳ２０６においては、第３のガードリング形成工程が行われる。 In step S206, a third guard ring forming step is performed.
　この第３のガードリング形成工程では、図１１のＣに示すように、画素部１００の領域とその周辺の周辺領域(パッド部１０１とスクライブライン部１０２の周辺部を含む領域)上に形成された絶縁膜１１１において、パッド部１０１の周辺部に、金属膜等からなる壁状の第３のガードリング部１５３Ｂ(１５３Ｂ－１)が形成され、スクライブライン部１０２の周辺部に、金属膜等からなる壁状の第３のガードリング部１５３Ａが形成される。 In the third guard ring forming step, as shown in FIG. 11C, the pixel is formed on the region of the pixel portion 100 and its peripheral region (the region including the peripheral portion of the pad portion 101 and the scribe line portion 102). In the insulating film 111, a wall-shaped third guard ring portion 153B (153B-1) made of a metal film or the like is formed around the pad portion 101, and a metal film or the like is formed around the scribe line portion 102. A wall-like third guard ring portion 153A is formed.
　ただし、第３のガードリング部１５３Ａ，１５３Ｂ(１５３Ｂ－１)は、シリコン基板１２の上側(ウェハ裏面側)の光電変換層１１に形成されるが、第３のガードリング部１５３Ａ，１５３Ｂ(１５３Ｂ－１)の底部(金属膜等の底部)を、シリコン基板１２と接続させることが望ましい。このような構造とすることで、水分等の侵入を確実に遮断することが可能となるためである。 However, the third guard ring portions 153A and 153B (153B-1) are formed on the photoelectric conversion layer 11 on the upper side (wafer back side) of the silicon substrate 12, but the third guard ring portions 153A and 153B (153B) are formed. It is desirable to connect the bottom of (-1) (the bottom of the metal film or the like) to the silicon substrate 12. This is because by adopting such a structure, it is possible to reliably block the entry of moisture and the like.
　このように、パッド部１０１の周辺部に、第３のガードリング部１５３Ｂ(１５３Ｂ－１)を形成することで、例えば、接続部１３２上の開口の側面などの横方向から進入してきた水分等を遮断し、スクライブライン部１０２の周辺部に、第３のガードリング部１５３Ａを形成することで、例えば、固体撮像装置１０の端面の横方向から進入してきた水分等を遮断することができる。その結果、画素部１００の特性劣化を抑制することができる。 Thus, by forming the third guard ring portion 153B (153B-1) in the peripheral portion of the pad portion 101, for example, moisture entering from the lateral direction such as the side surface of the opening on the connection portion 132, etc. By forming the third guard ring portion 153A in the peripheral portion of the scribe line portion 102, for example, moisture that has entered from the lateral direction of the end face of the solid-state imaging device 10 can be blocked. As a result, deterioration of the characteristics of the pixel unit 100 can be suppressed.
　ステップＳ２０７においては、パッド部開口工程が行われる。 In step S207, a pad opening process is performed.
　このパッド部開口工程では、図１２のＡに示すように、ドライエッチング加工が行われ、パッド部１０１が形成される。このドライエッチング加工に際しては、ステップＳ２０４の工程で、シリコン基板１２に、第２のガードリング部１５２(１５２－１)が形成されているため、例えば、シリコン屑やダメージによりキズが入ったりするなどのチッピングが防止される。 In this pad portion opening step, as shown in FIG. 12A, dry etching is performed to form the pad portion 101. In this dry etching process, since the second guard ring portion 152 (152-1) is formed on the silicon substrate 12 in the process of step S204, for example, scratches may occur due to silicon dust or damage. Chipping is prevented.
　ステップＳ２０８においては、ダイシング工程が行われる。 In step S208, a dicing process is performed.
　このダイシング工程では、図１２のＢに示すように、ダイシングブレード(不図示)によってシリコン基板１２等が矩形状に切断され、固体撮像装置１０が切り出される(個片化される)。このダイシング工程に際しては、ステップＳ２０４の工程で、シリコン基板１２に、第１のガードリング部１５１が形成されているため、例えば、シリコン屑やダメージによりキズが入ったりするなどのチッピングが防止される。 In this dicing process, as shown in FIG. 12B, the silicon substrate 12 and the like are cut into a rectangular shape by a dicing blade (not shown), and the solid-state imaging device 10 is cut out (separated). In the dicing process, since the first guard ring portion 151 is formed on the silicon substrate 12 in the process of step S204, for example, chipping such as scratches caused by silicon dust or damage is prevented. .
　以上、ウェハ裏面側からシリコン貫通加工を行う場合の固体撮像装置１０Ａの製造工程の流れについて説明した。この製造工程においては、ステップＳ２０４のシリコン貫通加工・固定電荷膜成膜・絶縁膜埋め込み工程で、シリコン基板１２に、貫通電極部１２２の周囲の貫通電極絶縁部１２３と、第１のガードリング部１５１と、第２のガードリング部１５２とを同時に形成することができるため、貫通電極部とガードリング部が形成されたシリコン基板を有する固体撮像装置１０Ａの製造時における製造工程を削減することができる。 In the foregoing, the flow of the manufacturing process of the solid-state imaging device 10A in the case of performing silicon penetration processing from the wafer back side has been described. In this manufacturing process, in the through silicon processing / fixed charge film forming / insulating film embedding process of step S204, the through electrode insulating portion 123 around the through electrode portion 122 and the first guard ring portion are formed on the silicon substrate 12. 151 and the second guard ring portion 152 can be formed at the same time, and therefore the manufacturing process at the time of manufacturing the solid-state imaging device 10A having the silicon substrate on which the through electrode portion and the guard ring portion are formed can be reduced. it can.
＜３．変形例＞ <3. Modification>
（第３のガードリング部の他の配置例）
　図１４は、第３のガードリング部１５３の他の配置例を示す図である。また、図１４は、固体撮像装置１０の上面図となる。 (Other arrangement examples of the third guard ring portion)
FIG. 14 is a diagram illustrating another arrangement example of the third guard ring portion 153. FIG. 14 is a top view of the solid-state imaging device 10.
　図１４において、固体撮像装置１０には、その外周に沿って配置される第３のガードリング部１５３Ａと、パッド部１０１－１乃至１０１－１２の周囲に沿った第３のガードリング部１５３Ｂ－１乃至１５３Ｂ－１２のほかに、画素部１００の周囲に沿った第３のガードリング部１５３Ｃが配置されている。 In FIG. 14, the solid-state imaging device 10 includes a third guard ring portion 153A disposed along the outer periphery thereof, and a third guard ring portion 153B- along the periphery of the pad portions 101-1 to 101-12. In addition to 1 to 153B-12, a third guard ring portion 153C is disposed along the periphery of the pixel portion 100.
　第３のガードリング部１５３Ｃは、第３のガードリング部１５３Ａ，１５３Ｂと同様に、金属膜又は絶縁膜などの水分及び酸素を透過しない材料から構成される。また、第３のガードリング部１５３Ｃの底部(金属膜等の底部)は、水分等の侵入を確実に遮断するために、シリコン基板１２と接続させることが望ましい。 The third guard ring portion 153C is made of a material that does not transmit moisture and oxygen, such as a metal film or an insulating film, like the third guard ring portions 153A and 153B. Further, it is desirable that the bottom portion (the bottom portion of the metal film or the like) of the third guard ring portion 153C is connected to the silicon substrate 12 in order to reliably block the entry of moisture or the like.
　第３のガードリング部１５３Ｃによって、例えば、固体撮像装置１０の端面(チップの端面)やボンディングパッド上の開口の側面など、横方向から進入してきた水分やガスを遮断し、画素部１００の特性劣化を抑制することができる。 The third guard ring portion 153C blocks moisture and gas that have entered from the lateral direction, such as the end surface of the solid-state imaging device 10 (end surface of the chip) and the side surface of the opening on the bonding pad, and the characteristics of the pixel unit 100 Deterioration can be suppressed.
　なお、図１４においては、画素部１００に対する防湿等の保護を目的とした第３のガードリング部１５３として、第３のガードリング部１５３Ａ、第３のガードリング部１５３Ｂ－１乃至１５３Ｂ－１２、及び、第３のガードリング部１５３Ｃが配置される場合を例示しているが、第３のガードリング部１５３は必ずしも配置する必要はなく、また、それらの第３のガードリング部１５３のうち、少なくとも１つの第３のガードリング部１５３が配置されるようにしてもよい。 In FIG. 14, the third guard ring portion 153A, the third guard ring portions 153B-1 to 153B-12, as the third guard ring portion 153 for the purpose of protecting the pixel portion 100 such as moisture proofing, And, the case where the third guard ring part 153C is arranged is illustrated, but the third guard ring part 153 is not necessarily arranged, and among these third guard ring parts 153, At least one third guard ring portion 153 may be arranged.
　また、上述した第３のガードリング部１５３の配置例は一例であって、例えば、パッド部１０１－１乃至１０１－１２の周囲に沿って配置される第３のガードリング部１５３Ｂを、複数のパッド部１０１にまたがるように設けたり、あるいは、画素部１００の周囲に沿って配置される第３のガードリング部１５３Ｃを二重に設けたりするなど、様々な配置の形態を採用することができる。 Further, the above-described arrangement example of the third guard ring portion 153 is an example. For example, the third guard ring portion 153B arranged along the periphery of the pad portions 101-1 to 101-12 is provided with a plurality of pieces. Various arrangement forms such as providing the pad part 101 so as to extend over the pad part 101 or providing the third guard ring part 153C arranged along the periphery of the pixel part 100 can be adopted. .
＜４．電子機器の構成＞ <4. Configuration of electronic equipment>
　図１５は、本技術を適用した固体撮像装置を有する電子機器３００の構成例を示す図である。 FIG. 15 is a diagram illustrating a configuration example of an electronic apparatus 300 having a solid-state imaging device to which the present technology is applied.
　図１５の電子機器３００は、例えば、デジタルスチルカメラやビデオカメラ等の撮像装置や、スマートフォンやタブレット型端末等の携帯端末装置などの電子機器である。 15 is an electronic device such as an imaging device such as a digital still camera or a video camera, or a mobile terminal device such as a smartphone or a tablet-type terminal.
　図１５において、電子機器３００は、固体撮像装置３０１、DSP回路３０２、フレームメモリ３０３、表示部３０４、記録部３０５、操作部３０６、及び、電源部３０７から構成される。また、電子機器３００において、DSP回路３０２、フレームメモリ３０３、表示部３０４、記録部３０５、操作部３０６、及び、電源部３０７は、バスライン３０８を介して相互に接続されている。 15, the electronic device 300 includes a solid-state imaging device 301, a DSP circuit 302, a frame memory 303, a display unit 304, a recording unit 305, an operation unit 306, and a power supply unit 307. In the electronic device 300, the DSP circuit 302, the frame memory 303, the display unit 304, the recording unit 305, the operation unit 306, and the power supply unit 307 are connected to each other via a bus line 308.
　固体撮像装置３０１は、第１の実施の形態乃至第３の実施の形態のいずれかの固体撮像装置１０に対応しており、図２、図３、又は、図４に示した断面構造を有している。 The solid-state imaging device 301 corresponds to the solid-state imaging device 10 of any of the first to third embodiments, and has the cross-sectional structure shown in FIG. 2, FIG. 3, or FIG. is doing.
　DSP回路３０２は、固体撮像装置３０１から供給される信号を処理するカメラ信号処理回路である。DSP回路３０２は、固体撮像装置３０１からの信号を処理して得られる画像データを出力する。フレームメモリ３０３は、DSP回路３０２により処理された画像データを、フレーム単位で一時的に保持する。 The DSP circuit 302 is a camera signal processing circuit that processes a signal supplied from the solid-state imaging device 301. The DSP circuit 302 outputs image data obtained by processing a signal from the solid-state imaging device 301. The frame memory 303 temporarily holds the image data processed by the DSP circuit 302 in units of frames.
　表示部３０４は、例えば、液晶パネルや有機EL(Electro Luminescence)パネル等のパネル型表示装置からなり、固体撮像装置３０１で撮像された動画又は静止画を表示する。記録部３０５は、固体撮像装置３０１で撮像された動画又は静止画の画像データを、半導体メモリやハードディスク等の記録媒体に記録する。 The display unit 304 includes a panel type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays a moving image or a still image captured by the solid-state imaging device 301. The recording unit 305 records moving image or still image image data captured by the solid-state imaging device 301 on a recording medium such as a semiconductor memory or a hard disk.
　操作部３０６は、ユーザによる操作に従い、電子機器３００が有する各種の機能についての操作指令を出力する。電源部３０７は、DSP回路３０２、フレームメモリ３０３、表示部３０４、記録部３０５、及び、操作部３０６の動作電源となる各種の電源を、これら供給対象に対して適宜供給する。 The operation unit 306 outputs operation commands for various functions of the electronic device 300 in accordance with user operations. The power supply unit 307 appropriately supplies various power sources serving as operation power sources for the DSP circuit 302, the frame memory 303, the display unit 304, the recording unit 305, and the operation unit 306 to these supply targets.
　電子機器３００は、以上のように構成される。 The electronic device 300 is configured as described above.
＜５．固体撮像装置の使用例＞ <5. Example of use of solid-state imaging device>
　図１６は、イメージセンサとしての固体撮像装置１０の使用例を示す図である。 FIG. 16 is a diagram illustrating a usage example of the solid-state imaging device 10 as an image sensor.
　上述した固体撮像装置１０は、例えば、以下のように、可視光や、赤外光、紫外光、Ｘ線等の光をセンシングする様々なケースに使用することができる。すなわち、図１６に示すように、上述した、鑑賞の用に供される画像を撮影する鑑賞の分野だけでなく、例えば、交通の分野、家電の分野、医療・ヘルスケアの分野、セキュリティの分野、美容の分野、スポーツの分野、又は、農業の分野などにおいて用いられる装置でも、固体撮像装置１０を使用することができる。 The solid-state imaging device 10 described above can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-ray as follows. That is, as shown in FIG. 16, not only the above-mentioned field of viewing images taken for viewing, but also, for example, the field of transportation, the field of home appliances, the field of medical / healthcare, the field of security. The solid-state imaging device 10 can also be used in an apparatus used in the field of beauty, the field of sports, the field of agriculture, or the like.
　具体的には、上述したように、鑑賞の分野において、例えば、デジタルカメラやスマートフォン、カメラ機能付きの携帯電話機等の、鑑賞の用に供される画像を撮影するための装置(例えば図１５の電子機器３００)で、固体撮像装置１０を使用することができる。 Specifically, as described above, in the field of viewing, for example, a device for taking an image for viewing (eg, a digital camera, a smartphone, a mobile phone with a camera function, etc.) The solid-state imaging device 10 can be used in the electronic apparatus 300).
　交通の分野において、例えば、自動停止等の安全運転や、運転者の状態の認識等のために、自動車の前方や後方、周囲、車内等を撮影する車載用センサ、走行車両や道路を監視する監視カメラ、車両間等の測距を行う測距センサ等の、交通の用に供される装置で、固体撮像装置１０を使用することができる。 In the field of traffic, for example, in-vehicle sensors that capture images of the front, rear, surroundings, and interiors of automobiles to monitor driving vehicles and roads for safe driving such as automatic stop and recognition of driver status The solid-state imaging device 10 can be used as a device used for traffic such as a monitoring camera, a distance measuring sensor for measuring a distance between vehicles, and the like.
　家電の分野において、例えば、ユーザのジェスチャを撮影して、そのジェスチャに従った機器操作を行うために、テレビ受像機や冷蔵庫、エアーコンディショナ等の家電に供される装置で、固体撮像装置１０を使用することができる。また、医療・ヘルスケアの分野において、例えば、内視鏡や、赤外光の受光による血管撮影を行う装置等の、医療やヘルスケアの用に供される装置で、固体撮像装置１０を使用することができる。 In the field of home appliances, for example, a device that is used for home appliances such as a television receiver, a refrigerator, and an air conditioner to capture a user's gesture and perform device operations according to the gesture. Can be used. Further, in the medical / healthcare field, for example, the solid-state imaging device 10 is used in a device used for medical treatment or health care such as an endoscope or a blood vessel photographing device that receives infrared light. can do.
　セキュリティの分野において、例えば、防犯用途の監視カメラや、人物認証用途のカメラ等の、セキュリティの用に供される装置で、固体撮像装置１０を使用することができる。また、美容の分野において、例えば、肌を撮影する肌測定器や、頭皮を撮影するマイクロスコープ等の、美容の用に供される装置で、固体撮像装置１０を使用することができる。 In the field of security, for example, the solid-state imaging device 10 can be used in devices used for security, such as surveillance cameras for crime prevention and cameras for personal authentication. In the field of beauty, for example, the solid-state imaging device 10 can be used in a device used for beauty, such as a skin measuring device for photographing the skin and a microscope for photographing the scalp.
　スポーツの分野において、例えば、スポーツ用途等向けのアクションカメラやウェアラブルカメラ等の、スポーツの用に供される装置で、固体撮像装置１０を使用することができる。また、農業の分野において、例えば、畑や作物の状態を監視するためのカメラ等の、農業の用に供される装置で、固体撮像装置１０を使用することができる。 In the field of sports, for example, the solid-state imaging device 10 can be used in sports devices such as action cameras and wearable cameras for sports applications. Moreover, in the field of agriculture, for example, the solid-state imaging device 10 can be used in devices used for agriculture, such as a camera for monitoring the state of fields and crops.
　なお、本技術の実施の形態は、上述した実施の形態に限定されるものではなく、本技術の要旨を逸脱しない範囲において種々の変更が可能である。例えば、上述した複数の実施の形態の全て又は一部を組み合わせた形態を採用することができる。 Note that the embodiments of the present technology are not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present technology. For example, the form which combined all or one part of several embodiment mentioned above is employable.
　また、本技術は、以下のような構成をとることができる。 Also, the present technology can take the following configurations.
（１）
　半導体基板と、
　前記半導体基板を貫通して、入射光を受光して信号電荷に変換する光電変換素子と、前記信号電荷を保持する前記信号電荷保持部とを接続する貫通電極部と、
　前記半導体基板に形成されるガードリング部と
　を備え、
　前記半導体基板において、前記貫通電極部の周囲に形成される絶縁膜を埋め込むための溝状の埋め込み部と、前記ガードリング部を形成する絶縁膜を埋め込むための溝状の埋め込み部とは、同時に形成されたものである
　固体撮像装置。
（２）
　前記ガードリング部は、前記固体撮像装置の外周に形成される第１のガードリング部と、パッド部の周囲に形成される第２のガードリング部とを含む
　（１）に記載の固体撮像装置。
（３）
　前記貫通電極部は、前記半導体基板に、不純物をドーピングすることで形成される
　（１）又は（２）に記載の固体撮像装置。
（４）
　前記貫通電極部は、前記半導体基板に、導電材料を埋め込むことで形成される
　（１）又は（２）に記載の固体撮像装置。
（５）
　前記導電材料は、金属である
　（４）に記載の固体撮像装置。
（６）
　前記埋め込み部は、前記半導体基板の表面側から掘り込んで形成される
　（１）又は（２）に記載の固体撮像装置。
（７）
　前記埋め込み部は、前記半導体基板の裏面側から掘り込んで形成される
　（１）又は（２）に記載の固体撮像装置。
（８）
　前記埋め込み部に、固定電荷膜が堆積され、
　前記絶縁膜は、前記固定電荷膜上に埋め込まれる
　（７）に記載の固体撮像装置。
（９）
　前記第１のカードリング部と前記第２のガードリング部を形成する絶縁膜の埋め込み部の底部には、加工時のストッパ用の絶縁膜が形成される
　（７）に記載の固体撮像装置。
（１０）
　前記光電変換素子を有する画素が行列状に２次元配置される画素部の領域とその周囲の周辺領域上に形成される絶縁膜において、前記固体撮像装置の外周、前記パッド部の周囲、及び、前記画素部の周囲の少なくとも１つの領域に形成される第３のガードリング部をさらに備える
　（２）乃至（９）のいずれかに記載の固体撮像装置。
（１１）
　半導体基板を貫通して、入射光を受光して信号電荷に変換する光電変換素子と、前記信号電荷を保持する信号電荷保持部を接続する貫通電極部を形成する第１の工程と、
　前記半導体基板において、前記貫通電極部の周囲に形成される絶縁膜を埋め込むための溝状の埋め込み部と、ガードリング部を形成する絶縁膜を埋め込むための溝状の埋め込み部とを同時に形成する第２の工程と
　を含む製造方法。
（１２）
　前記ガードリング部は、固体撮像装置の外周に形成される第１のガードリング部と、パッド部の周囲に形成される第２のガードリング部とを含む
　（１１）に記載の製造方法。
（１３）
　前記貫通電極部は、前記半導体基板に、不純物をドーピングすることで形成される
　（１１）又は（１２）に記載の製造方法。
（１４）
　前記貫通電極部は、前記半導体基板に、導電材料を埋め込むことで形成される
　（１１）又は（１２）に記載の製造方法。
（１５）
　前記導電材料は、金属である
　（１４）に記載の製造方法。
（１６）
　前記第２の工程は、前記埋め込み部を、前記半導体基板の表面側から掘り込んで形成する
　（１１）又は（１２）に記載の製造方法。
（１７）
　前記第２の工程は、前記埋め込み部を、前記半導体基板の裏面側から掘り込んで形成する
　（１１）又は（１２）に記載の製造方法。
（１８）
　前記第２の工程は、前記埋め込み部に固定電荷膜を堆積し、堆積された前記固定電荷膜上に、前記絶縁膜を埋め込む
　（１７）に記載の製造方法。
（１９）
　前記光電変換素子を有する画素が行列状に２次元配置される画素部の領域とその周囲の周辺領域上に、絶縁膜を形成する第３の工程と、
　前記画素部の領域とその周囲の周辺領域上に形成される前記絶縁膜において、前記固体撮像装置の外周、前記パッド部の周囲、及び、前記画素部の周囲の少なくとも１つの領域に、第３のガードリング部を形成する第４の工程と
　をさらに含む（１２）乃至（１８）のいずれかに記載の製造方法。
（２０）
　半導体基板と、
　前記半導体基板を貫通して、入射光を受光して信号電荷に変換する光電変換素子と、前記信号電荷を保持する前記信号電荷保持部とを接続する貫通電極部と、
　前記半導体基板に形成されるガードリング部と
　を有し、
　前記半導体基板において、前記貫通電極部の周囲に形成される絶縁膜を埋め込むための溝状の埋め込み部と、前記ガードリング部を形成する絶縁膜を埋め込むための溝状の埋め込み部とは、同時に形成されたものである
　固体撮像装置を備える
　電子機器。 (1)
A semiconductor substrate;
A through-electrode portion that connects the photoelectric conversion element that passes through the semiconductor substrate and receives incident light and converts it into signal charge, and the signal charge holding portion that holds the signal charge;
A guard ring portion formed on the semiconductor substrate,
In the semiconductor substrate, the groove-shaped embedded portion for embedding the insulating film formed around the through electrode portion and the groove-shaped embedded portion for embedding the insulating film forming the guard ring portion are simultaneously Solid-state imaging device that is formed.
(2)
The said guard ring part contains the 1st guard ring part formed in the outer periphery of the said solid-state imaging device, and the 2nd guard ring part formed in the circumference | surroundings of a pad part. The solid-state imaging device as described in (1). .
(3)
The solid-state imaging device according to (1) or (2), wherein the through electrode portion is formed by doping impurities into the semiconductor substrate.
(4)
The solid-state imaging device according to (1) or (2), wherein the through electrode portion is formed by embedding a conductive material in the semiconductor substrate.
(5)
The solid-state imaging device according to (4), wherein the conductive material is a metal.
(6)
The solid-state imaging device according to (1) or (2), wherein the embedded portion is formed by digging from the surface side of the semiconductor substrate.
(7)
The solid-state imaging device according to (1) or (2), wherein the embedded portion is formed by digging from the back side of the semiconductor substrate.
(8)
A fixed charge film is deposited on the embedded portion,
The solid-state imaging device according to (7), wherein the insulating film is embedded on the fixed charge film.
(9)
The solid-state imaging device according to (7), wherein an insulating film for a stopper at the time of processing is formed on a bottom portion of a buried portion of the insulating film that forms the first card ring portion and the second guard ring portion.
(10)
In an insulating film formed on an area of a pixel portion in which pixels having the photoelectric conversion elements are two-dimensionally arranged in a matrix and a peripheral area around the area, an outer periphery of the solid-state imaging device, a periphery of the pad portion, and The solid-state imaging device according to any one of (2) to (9), further including a third guard ring unit formed in at least one region around the pixel unit.
(11)
A first step of forming a photoelectric conversion element that penetrates the semiconductor substrate, receives incident light and converts it into signal charges, and a through electrode portion that connects the signal charge holding portion holding the signal charges;
In the semiconductor substrate, a groove-shaped embedded portion for embedding an insulating film formed around the through electrode portion and a groove-shaped embedded portion for embedding an insulating film forming a guard ring portion are formed simultaneously. A manufacturing method comprising the second step.
(12)
The said guard ring part contains the 1st guard ring part formed in the outer periphery of a solid-state imaging device, and the 2nd guard ring part formed in the circumference | surroundings of a pad part.
(13)
The said penetration electrode part is formed by doping an impurity in the said semiconductor substrate. (11) Or the manufacturing method as described in (12).
(14)
The manufacturing method according to (11) or (12), wherein the through electrode portion is formed by embedding a conductive material in the semiconductor substrate.
(15)
The manufacturing method according to (14), wherein the conductive material is a metal.
(16)
The manufacturing method according to (11) or (12), wherein in the second step, the embedded portion is dug from the surface side of the semiconductor substrate.
(17)
The manufacturing method according to (11) or (12), wherein in the second step, the embedded portion is dug from the back surface side of the semiconductor substrate.
(18)
The manufacturing method according to (17), wherein in the second step, a fixed charge film is deposited on the buried portion, and the insulating film is buried on the deposited fixed charge film.
(19)
A third step of forming an insulating film on a region of the pixel portion in which pixels having the photoelectric conversion element are two-dimensionally arranged in a matrix and a peripheral region around the pixel portion;
In the insulating film formed on the region of the pixel portion and the peripheral region around the region, a third outer periphery of the solid-state imaging device, around the pad portion, and at least one region around the pixel portion The manufacturing method according to any one of (12) to (18), further including: a fourth step of forming the guard ring portion.
(20)
A semiconductor substrate;
A through-electrode portion that connects the photoelectric conversion element that passes through the semiconductor substrate and receives incident light and converts it into signal charge, and the signal charge holding portion that holds the signal charge;
A guard ring portion formed on the semiconductor substrate,
In the semiconductor substrate, the groove-shaped embedded portion for embedding the insulating film formed around the through electrode portion and the groove-shaped embedded portion for embedding the insulating film forming the guard ring portion are simultaneously An electronic device provided with a solid-state imaging device.
　１０，１０Ａ，１０Ｂ，１０Ｃ　固体撮像装置，　１１　光電変換層，　１２　シリコン基板，　１３　配線層，　１００　画素部，　１０１　パッド部，　１０２　スクライブライン部，　１１１　絶縁膜，　１１２　上部電極，　１１３　光電変換膜，　１１４　下部電極，　１２１　シリコン，　１２２，１２２－１乃至１２２－３　貫通電極部，　１２３，１２３－１乃至１２３－３　貫通電極絶縁部，　１２５，１２５－１乃至１２５－３　貫通電極部，　１２８，１２９　絶縁膜，　１５１　第１のガードリング部，　１５２　第２のガードリング部，　１５３Ａ，１５３Ｂ，１５３Ｃ　第３のガードリング部，　１７１　固定電荷膜，　３００　電子機器，　３０１　固体撮像装置 10, 10A, 10B, 10C solid-state imaging device, 11 photoelectric conversion layer, 12 silicon substrate, 13 wiring layer, 100 pixel unit, 101 pad unit, 102 scribe line unit, 111 insulating film, 112 upper electrode, 113 photoelectric conversion film, 114, lower electrode, 121 silicon, 122, 122-1 to 122-3 through electrode part, 123, 123-1 to 123-3 through electrode insulating part, 125, 125-1 to 125-3 through electrode part, 128, 129 Insulating film, 151, first guard ring, 152, second guard ring, 153A, 153B, 153C, third guard ring, 171 fixed charge film, 300 electronic device, 301 solid-state imaging device

Claims (20)

  1. 　半導体基板と、
    　前記半導体基板を貫通して、入射光を受光して信号電荷に変換する光電変換素子と、前記信号電荷を保持する前記信号電荷保持部とを接続する貫通電極部と、
    　前記半導体基板に形成されるガードリング部と
    　を備え、
    　前記半導体基板において、前記貫通電極部の周囲に形成される絶縁膜を埋め込むための溝状の埋め込み部と、前記ガードリング部を形成する絶縁膜を埋め込むための溝状の埋め込み部とは、同時に形成されたものである
    　固体撮像装置。     A semiconductor substrate;
    A through-electrode portion that connects the photoelectric conversion element that passes through the semiconductor substrate and receives incident light and converts it into signal charge, and the signal charge holding portion that holds the signal charge;
    A guard ring portion formed on the semiconductor substrate,
    In the semiconductor substrate, the groove-shaped embedded portion for embedding the insulating film formed around the through electrode portion and the groove-shaped embedded portion for embedding the insulating film forming the guard ring portion are simultaneously Solid-state imaging device that is formed.
  2. 　前記ガードリング部は、前記固体撮像装置の外周に形成される第１のガードリング部と、パッド部の周囲に形成される第２のガードリング部とを含む
    　請求項１に記載の固体撮像装置。     The solid-state imaging device according to claim 1, wherein the guard ring portion includes a first guard ring portion formed on an outer periphery of the solid-state imaging device and a second guard ring portion formed around the pad portion. .
  3. 　前記貫通電極部は、前記半導体基板に、不純物をドーピングすることで形成される
    　請求項２に記載の固体撮像装置。     The solid-state imaging device according to claim 2, wherein the through electrode portion is formed by doping impurities into the semiconductor substrate.
  4. 　前記貫通電極部は、前記半導体基板に、導電材料を埋め込むことで形成される
    　請求項２に記載の固体撮像装置。     The solid-state imaging device according to claim 2, wherein the through electrode portion is formed by embedding a conductive material in the semiconductor substrate.
  5. 　前記導電材料は、金属である
    　請求項４に記載の固体撮像装置。     The solid-state imaging device according to claim 4, wherein the conductive material is a metal.
  6. 　前記埋め込み部は、前記半導体基板の表面側から掘り込んで形成される
    　請求項２に記載の固体撮像装置。     The solid-state imaging device according to claim 2, wherein the embedded portion is formed by digging from a surface side of the semiconductor substrate.
  7. 　前記埋め込み部は、前記半導体基板の裏面側から掘り込んで形成される
    　請求項２に記載の固体撮像装置。     The solid-state imaging device according to claim 2, wherein the embedded portion is formed by digging from a back surface side of the semiconductor substrate.
  8. 　前記埋め込み部に、固定電荷膜が堆積され、
    　前記絶縁膜は、前記固定電荷膜上に埋め込まれる
    　請求項７に記載の固体撮像装置。     A fixed charge film is deposited on the embedded portion,
    The solid-state imaging device according to claim 7, wherein the insulating film is embedded on the fixed charge film.
  9. 　前記第１のカードリング部と前記第２のガードリング部を形成する絶縁膜の埋め込み部の底部には、加工時のストッパ用の絶縁膜が形成される
    　請求項７に記載の固体撮像装置。     The solid-state imaging device according to claim 7, wherein an insulating film for a stopper at the time of processing is formed at a bottom portion of a buried portion of an insulating film that forms the first card ring portion and the second guard ring portion.
  10. 　前記光電変換素子を有する画素が行列状に２次元配置される画素部の領域とその周囲の周辺領域上に形成される絶縁膜において、前記固体撮像装置の外周、前記パッド部の周囲、及び、前記画素部の周囲の少なくとも１つの領域に形成される第３のガードリング部をさらに備える
    　請求項２に記載の固体撮像装置。     In an insulating film formed on an area of a pixel portion in which pixels having the photoelectric conversion elements are two-dimensionally arranged in a matrix and a peripheral area around the area, an outer periphery of the solid-state imaging device, a periphery of the pad portion, and The solid-state imaging device according to claim 2, further comprising a third guard ring unit formed in at least one region around the pixel unit.
  11. 　半導体基板を貫通して、入射光を受光して信号電荷に変換する光電変換素子と、前記信号電荷を保持する信号電荷保持部を接続する貫通電極部を形成する第１の工程と、
    　前記半導体基板において、前記貫通電極部の周囲に形成される絶縁膜を埋め込むための溝状の埋め込み部と、ガードリング部を形成する絶縁膜を埋め込むための溝状の埋め込み部とを同時に形成する第２の工程と
    　を含む製造方法。     A first step of forming a photoelectric conversion element that penetrates the semiconductor substrate, receives incident light and converts it into signal charges, and a through electrode portion that connects the signal charge holding portion holding the signal charges;
    In the semiconductor substrate, a groove-shaped embedded portion for embedding an insulating film formed around the through electrode portion and a groove-shaped embedded portion for embedding an insulating film forming a guard ring portion are formed simultaneously. A manufacturing method comprising the second step.
  12. 　前記ガードリング部は、固体撮像装置の外周に形成される第１のガードリング部と、パッド部の周囲に形成される第２のガードリング部とを含む
    　請求項１１に記載の製造方法。     The manufacturing method according to claim 11, wherein the guard ring part includes a first guard ring part formed on an outer periphery of the solid-state imaging device and a second guard ring part formed around the pad part.
  13. 　前記貫通電極部は、前記半導体基板に、不純物をドーピングすることで形成される
    　請求項１２に記載の製造方法。     The manufacturing method according to claim 12, wherein the through electrode portion is formed by doping impurities into the semiconductor substrate.
  14. 　前記貫通電極部は、前記半導体基板に、導電材料を埋め込むことで形成される
    　請求項１２に記載の製造方法。     The manufacturing method according to claim 12, wherein the through electrode portion is formed by embedding a conductive material in the semiconductor substrate.
  15. 　前記導電材料は、金属である
    　請求項１４に記載の製造方法。     The manufacturing method according to claim 14, wherein the conductive material is a metal.
  16. 　前記第２の工程は、前記埋め込み部を、前記半導体基板の表面側から掘り込んで形成する
    　請求項１２に記載の製造方法。     The manufacturing method according to claim 12, wherein in the second step, the embedded portion is formed by digging from the surface side of the semiconductor substrate.
  17. 　前記第２の工程は、前記埋め込み部を、前記半導体基板の裏面側から掘り込んで形成する
    　請求項１２に記載の製造方法。     The manufacturing method according to claim 12, wherein in the second step, the embedded portion is formed by digging from the back side of the semiconductor substrate.
  18. 　前記第２の工程は、前記埋め込み部に固定電荷膜を堆積し、堆積された前記固定電荷膜上に、前記絶縁膜を埋め込む
    　請求項１７に記載の製造方法。     The manufacturing method according to claim 17, wherein in the second step, a fixed charge film is deposited on the buried portion, and the insulating film is buried on the deposited fixed charge film.
  19. 　前記光電変換素子を有する画素が行列状に２次元配置される画素部の領域とその周囲の周辺領域上に、絶縁膜を形成する第３の工程と、
    　前記画素部の領域とその周囲の周辺領域上に形成される前記絶縁膜において、前記固体撮像装置の外周、前記パッド部の周囲、及び、前記画素部の周囲の少なくとも１つの領域に、第３のガードリング部を形成する第４の工程と
    　をさらに含む請求項１２に記載の製造方法。     A third step of forming an insulating film on a region of the pixel portion in which pixels having the photoelectric conversion element are two-dimensionally arranged in a matrix and a peripheral region around the pixel portion;
    In the insulating film formed on the region of the pixel portion and the peripheral region around the region, a third outer periphery of the solid-state imaging device, around the pad portion, and at least one region around the pixel portion The manufacturing method according to claim 12, further comprising: a fourth step of forming the guard ring portion.
  20. 　半導体基板と、
    　前記半導体基板を貫通して、入射光を受光して信号電荷に変換する光電変換素子と、前記信号電荷を保持する前記信号電荷保持部とを接続する貫通電極部と、
    　前記半導体基板に形成されるガードリング部と
    　を有し、
    　前記半導体基板において、前記貫通電極部の周囲に形成される絶縁膜を埋め込むための溝状の埋め込み部と、前記ガードリング部を形成する絶縁膜を埋め込むための溝状の埋め込み部とは、同時に形成されたものである
    　固体撮像装置を備える
    　電子機器。     A semiconductor substrate;
    A through-electrode portion that connects the photoelectric conversion element that passes through the semiconductor substrate and receives incident light and converts it into signal charge, and the signal charge holding portion that holds the signal charge;
    A guard ring portion formed on the semiconductor substrate,
    In the semiconductor substrate, the groove-shaped embedded portion for embedding the insulating film formed around the through electrode portion and the groove-shaped embedded portion for embedding the insulating film forming the guard ring portion are simultaneously An electronic device provided with a solid-state imaging device.
PCT/JP2016/070651 2015-07-27 2016-07-13 Solid-state imaging device, method for manufacturing same, and electronic device WO2017018216A1 (en)

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