WO2017006398A1

WO2017006398A1 - Interrupt control device and interrupt control method

Info

Publication number: WO2017006398A1
Application number: PCT/JP2015/069312
Authority: WO
Inventors: 寿和加藤; 寿好黒澤
Original assignee: 三菱電機株式会社
Priority date: 2015-07-03
Filing date: 2015-07-03
Publication date: 2017-01-12

Abstract

An interrupt control mechanism (213) manages the classification of an interrupt process that has been generated as a system monitoring interrupt process (211), a control interrupt process (203) generated while the monitoring interrupt process (211) is in operation, and a control interrupt process (203) generated while said process (211) is not in operation. In an entry process when an interrupt process is generated and an exit process when an interrupt process has finished, a stack area in which the stack pointer (SP) of a CPU is saved and from which the SP is restored is determined by the interrupt control mechanism (213) based on whether the generated or finished interrupt process is the monitoring interrupt process (211) or the control interrupt process (203), and on the classification of the interrupt process being generated.

Description

Interrupt control device and interrupt control method

The present invention relates to a technique for controlling an interrupt of a computer in which a control module for system control and a monitoring module for system monitoring are executed.

CPUs (Central Processing Units) for small embedded systems often have only one SP (stack pointer) mounted.
Small-scale embedded software installed in white goods includes a main task that is a single task process that performs basic processing and a plurality of control interrupt processes that are interrupt processes having different priorities. The embedded software has two stack areas: a task stack which is a stack area used by the main task, and a control stack which is a stack area used by interrupt processing.

Patent Document 1 describes an interrupt control method in an embedded system.
In the interrupt control method described in Patent Document 1, it is determined whether an interrupt has occurred during execution of the main task or whether multiple interrupts have occurred during execution of the control interrupt process.
When an interrupt occurs during execution of the main task, the stack area pointed to by SP is switched from the task stack to the control stack. When switching is performed, the SP value indicating the task stack area used up to that point is stored. When the interrupt process ends and the process returns to the main task, the stack area pointed to by the SP is returned to a position in the middle of using the task stack by the stored SP value.

Patent Document 2 describes an interrupt control method for controlling interrupts from a plurality of programs having different interrupt priorities.
In the interrupt control method described in Patent Document 2, it is recognized that the CPU SP is provided as many as the number corresponding to the stage of the interrupt priority and whether the program is at the privilege level or the non-privilege level. Then, it is recognized that a stack area corresponding to the corresponding priority is set in advance for each SP. When an interrupt occurs, the SP to be used is selected and switched from the interrupt priority and the number of times the interrupt is multiplexed.

JP-A-2005-050208 Japanese Patent Laid-Open No. 08-320794

In recent years, there has been a demand for improving the safety of systems, and it has been required to comply with functional safety standards such as IEC61508.
As one method for complying with the functional safety standard, there is a method of adding monitoring interrupt processing, which is interrupt processing for periodically monitoring the system state, in addition to the main task and control interrupt processing. In this method, it must be ensured that the control interrupt process does not affect the operation of the monitor interrupt process. For this reason, it is essential to separate the code area, data area, and stack area of the control interrupt process and the monitoring interrupt process as different load modules. In other words, the monitoring stack, which is a stack area used for monitoring interrupt processing, must be separated from the control stack used for control interrupt processing.

It is assumed that a control module that is a load module that performs control interrupt processing and a monitoring module that is a load module that performs monitoring interrupt processing are operated on a single CPU.
In the interrupt control method described in Patent Document 1, there is no means for switching the stack area pointed to by SP when a control interrupt process having a higher priority occurs during execution of the monitor interrupt process using the monitor stack. Therefore, high priority control interrupt processing will continue to use the monitoring stack. Therefore, it cannot be guaranteed that the control interrupt process does not affect the monitoring interrupt process.
In the interrupt control method described in Patent Document 2, it is necessary that the number of SPs corresponding to the interrupt priority level is mounted on the CPU. Therefore, it cannot be applied to a CPU on which only one SP is mounted.

In the present invention, even when the CPU has only one SP, and even when the CPU has two or more SPs and only one SP is used due to software settings, the control interrupt processing is performed. The purpose is not to affect the monitoring interrupt processing.

The interrupt control device according to the present invention is:
The type of interrupt processing that is occurring is divided into monitoring interrupt processing that monitors the system and control interrupt processing that controls the system, and the control interrupt processing is processed during the operation of the monitoring interrupt processing, and An interrupt management unit that manages and manages the processing that occurs during non-operation of the monitoring interrupt processing,
When a new interrupt process occurs, whether the newly generated new interrupt process is the monitoring interrupt process or the control interrupt process, the type of the interrupt process being generated managed by the interrupt management unit, and From the control pointer area for the control stack used in the control interrupt processing and the monitoring pointer area for the monitoring stack used in the monitoring interrupt processing, the stack indicating the data reading destination of the arithmetic unit An entry stack determination unit that determines whether to store the address value set in the pointer;
A stack storage unit for switching the address value of the stack pointer after storing the address value set in the stack pointer in the storage destination determined by the entry stack determination unit.

In the present invention, the SP storage destination is determined from the generation source of the new interrupt and the interrupt processing that is occurring. This makes it possible to prevent the control interrupt processing from affecting the monitoring interrupt processing even when the CPU can use only one SP.

1 is a hardware configuration diagram of an interrupt control device 100 according to Embodiment 1. FIG. 1 is a functional configuration diagram of an interrupt control device 100 according to Embodiment 1. FIG. 3 is a flowchart showing the operation of the interrupt control device 100 according to the first embodiment. 3 is a flowchart showing entrance processing according to the first embodiment. 3 is a flowchart showing entrance processing according to the first embodiment. 5 is a flowchart showing exit processing according to the first embodiment. 5 is a flowchart showing exit processing according to the first embodiment.

Embodiment 1 FIG.
*** Explanation of configuration ***
FIG. 1 is a hardware configuration diagram of the interrupt control device 100 according to the first embodiment.
The interrupt control device 100 includes a CPU 101, a ROM 102 (Read Only Memory), a RAM 103 (Random Access Memory), and a peripheral device 104.

The CPU 101 is an arithmetic device that controls the interrupt control device 100. The CPU 101 includes a PC 105 (program counter), a PSW 106 (processor status word), an SP 107, and a general-purpose register 108.
The PC 105 holds an address value in which an instruction to be executed next is stored. The PSW 106 holds the internal state of the processor. The SP 107 holds the address value of the stack area to which the CPU 101 reads data. The general-purpose register 108 is a register that can be used for various purposes.

The ROM 102 includes an interrupt vector area 109, a control module code area 110, and a monitoring module code area 111.
The interrupt vector area 109 stores an address value indicating a movement destination when accepting interrupt processing. The control module code area 110 stores the program code of the control module 201. The monitoring module code area 111 stores the program code of the monitoring module 210.
Note that the interrupt vector area 109 may store an address value for each interrupt factor, or may store one address value shared by all interrupt factors. Here, in the interrupt vector area 109, an address value indicating a position where a program code to be executed first of an interrupt control mechanism 213 described later is stored is stored as one address value shared by all interrupt factors. Suppose that

The RAM 103 includes a control module data area 112, a monitoring module data area 113, a control module stack area 114, and a monitoring module stack area 115.
In the control module data area 112, data used by the control module 201 is stored. The monitoring module data area 113 stores data used by the monitoring module 210. The control module stack area 114 and the monitoring module stack area 115 store information held in the PC 105 and the PSW 106. The control module stack area 114 and the monitoring module stack area 115 are selectively used according to the value of SP107. In the following description, when the term “stack area” is simply used, it means both the control module stack area 114 and the monitoring module stack area 115.

Peripheral device 104 is an input / output device such as a timer and an A / D (Analog / Digital) converter. The peripheral device 104 notifies the CPU 101 of an interrupt signal under conditions set by software.

When the interrupt signal is notified, the CPU 101 performs interrupt mask comparison or priority comparison, and determines whether or not to accept interrupt processing. If the CPU 101 determines to accept the interrupt processing, the CPU 101 saves the information held in the PC 105 and the PSW 106 in the stack area indicated by the SP 107, and then executes the instruction stored in the address value stored in the interrupt vector area 109. Execute.

FIG. 2 is a functional configuration diagram of the interrupt control device 100 according to the first embodiment.
Here, the interrupt control device 100 includes a control module 201 for system control and a monitoring module 210 for system monitoring. The control module 201 and the monitoring module 210 are stored in the ROM 102 and the RAM 103 as different load modules, and operate on the CPU 101.

The control module 201 includes a main task 202 that performs basic processing, a plurality of control interrupt processes 203 having different priorities, a task stack 204, a control stack 205, and an interrupt handler table 206.
The main task 202 uses the task stack 204 that is the control module stack area 114 during execution.
Each control interrupt process 203 shares and uses one control stack 205 which is the control module stack area 114 during execution. The control interrupt process 203 includes a process having a lower interrupt priority than the monitor interrupt process 211 and a process having a higher interrupt priority.
The interrupt handler table 206 is a table in which an address value indicating a position where a program code to be executed at the beginning of the corresponding control interrupt process 203 is stored is held for each interrupt factor.

The monitoring module 210 includes a monitoring interrupt process 211, a monitoring stack 212, and an interrupt control mechanism 213.
The monitoring interrupt process 211 is periodically executed by an interrupt using a timer device which is the peripheral device 104, and monitors the system state. The monitoring interrupt process 211 uses the monitoring stack 212 which is the monitoring module stack area 115 during execution. Here, there is only one monitoring interrupt process 211.
When a new interrupt process occurs, the interrupt control mechanism 213 executes an entrance process until the interrupt process corresponding to the interrupt factor is called, an interrupt process call, and an exit process when the interrupt process ends. . The interrupt control mechanism 213 includes an interrupt entry processing unit 220, an interrupt process calling unit 221, an interrupt exit processing unit 222, an interrupt management unit 223, and an SP storage unit 224.

The interrupt entry processing unit 220 executes entry processing. The interrupt entry processing unit 220 includes a general-purpose register storage unit 225, an entry stack determination unit 226, and a stack storage unit 227.
The general-purpose register storage unit 225 stores information on the general-purpose register 108 that is not stored in the stack area by the CPU 101 when an interrupt occurs in the stack area indicated by the SP 107.
The entrance stack determination unit 226 determines the address of the SP 107 based on whether the new interrupt processing is the monitoring interrupt processing 211 or the control interrupt processing 203 and the type of interrupt processing that is being managed, which is managed by the interrupt management unit 223 described later. Determine where to save the value. The entry stack determination unit 226 determines which of the control pointer area 235, the monitoring pointer area 236, and the task pointer area 237 is to be the storage destination of the address value of the SP 107. In addition, the entrance stack determination unit 226 switches the SP 107 based on whether the new interrupt processing is the monitoring interrupt processing 211 or the control interrupt processing 203 and the type of interrupt processing being generated managed by the interrupt management unit 223. Determine the value. The switching value is the address value of the stack area to be used next.
The stack storage unit 227 stores the address value set in the SP 107 in the storage destination determined by the entry stack determination unit 226, and then switches the address value of the SP 107 to a switching value.

The interrupt process call unit 221 calls the interrupt process corresponding to the interrupt factor of the newly generated interrupt.
Note that when calling the control interrupt process 203, the interrupt process calling unit 221 refers to the interrupt handler table 206 and obtains an address value that is executed first in the control interrupt process 203 corresponding to the interrupt factor. Then, the interrupt process calling unit 221 calls the program code stored at the position indicated by the acquired address value.

The interrupt exit processing unit 222 executes exit processing. The interrupt exit processing unit 222 includes an exit stack determination unit 228, a stack restoration unit 229, and a general-purpose register restoration unit 230.
When the interrupt processing is completed, the exit stack determination unit 228 determines whether the completed end interrupt processing is the control interrupt processing 203 or the monitoring interrupt processing 211, and the interrupt processing that is being managed, which is managed by the interrupt management unit 223. From which the address value of SP 107 is read. The exit stack determination unit 228 determines which of the control pointer area 235, the monitoring pointer area 236, and the task pointer area 237 is to be the address value reading destination of the SP 107.
The stack return unit 229 sets the address value stored in the read destination determined by the exit stack determination unit 228 in the SP 107.
The general-purpose register return unit 230 sets the information set in the stack area indicated by the address value set in the SP 107 by the stack return unit 229 in the general-purpose register 108.
Finally, the interrupt exit processing unit 222 sets the PC 105 and the PSW 106 in the CPU 101 by using the interrupt return instruction provided by the CPU 101, and returns control to the CPU 101.

The interrupt management unit 223 manages information used for determining the stack area to be used in the interrupt entry processing unit 220 and the interrupt exit processing unit 222. In particular, the interrupt management unit 223 determines the type of interrupt processing that is occurring as a monitoring interrupt processing 211, a high-priority control interrupt processing that is a control interrupt processing 203 that occurs during the operation of the monitoring interrupt processing 211, and a monitoring interrupt processing. Management is divided into low-priority control interrupt processing which is control interrupt processing 203 generated during non-operation of 211. The interrupt management unit 223 includes a monitoring interrupt identification information storage unit 231, a high priority counter 232, a low priority counter 233, and a monitoring stack use flag 234.
The monitoring interrupt identification information storage unit 231 stores information for determining whether or not the new interrupt processing is the monitoring interrupt processing 211. Here, the monitoring interrupt identification information storage unit 231 stores the interrupt factor number used in the monitoring interrupt processing 211.
The high priority counter 232 counts the number of high priority control interrupt processes that are occurring. The high priority counter 232 is incremented by 1 when a high priority control interrupt process occurs, and is decremented by 1 when it is completed.
The low priority counter 233 counts the number of low priority control interrupt processes that are occurring. The low priority counter 233 is incremented by 1 when a low priority control interrupt process occurs, and is decremented by 1 when it is completed.
The monitoring stack use flag 234 is set when the monitoring interrupt processing 211 is generated, and is cleared when the monitoring stack processing is finished.

The SP storage unit 224 stores the address value of the SP 107 before switching the stack area. The SP storage unit 224 includes a control pointer area 235, a monitoring pointer area 236, and a task pointer area 237.
The control pointer area 235 is an area for storing a storage position in the control stack 205 used in the control interrupt process 203. The monitoring pointer area 236 is an area for storing a storage position in the monitoring stack 212 used in the monitoring interrupt process 211. The task pointer area 237 is an area for storing a storage position in the task stack 204 used by the main task 202 that is executed when neither a control interrupt nor a monitoring interrupt occurs.

*** Explanation of operation ***
FIG. 3 is a flowchart showing the operation of the interrupt control device 100 according to the first embodiment.
The operation of the interrupt control device 100 according to the first embodiment corresponds to the interrupt control method according to the first embodiment. The operation of the interrupt control device 100 according to the first embodiment corresponds to the processing of the interrupt control program according to the first embodiment.

In the entrance processing of S1, the interrupt entrance processing unit 220 executes entrance processing when a new interrupt processing occurs. By the entry process, the address value of SP 107 and the information of general register 108 are saved, and the address value of SP 107 is switched.

In the call process of S2, the interrupt process call unit 221 calls the interrupt process corresponding to the interrupt factor of the new interrupt process.

In the exit process of S3, the interrupt exit processing unit 222 executes the exit process when the interrupt process ends. By the exit process, the address value of the SP 107 and the information of the general register 108 are returned to the information before the interrupt, and the process is returned to the process before the interrupt.

4 and 5 are flowcharts showing the entrance processing according to the first embodiment.
In the start process of S101, when a new interrupt process occurs and the CPU 101 executes an instruction indicated by the address value of the interrupt control mechanism 213 stored in the interrupt vector area 109, the interrupt entry processing unit 220 starts the entry process.
It is assumed that the value of the interrupt vector area 109 is set in advance. Here, it is assumed that it is set when the interrupt control device 100 is initialized.

In the register saving process of S102, the general-purpose register saving unit 225 saves the information of the general-purpose register 108 that is not saved in the stack by the CPU 101 in the stack area indicated by the address value of the SP 107.

In the interrupt determination process of S103, the entrance stack determination unit 226 determines whether or not the new interrupt process is the monitoring interrupt process 211. Here, the entry stack determination unit 226 acquires the new interrupt processing factor number from the register of the ICU (Interrupt Control Unit), and when it matches the factor number stored in the monitoring interrupt identification information storage unit 231, It is determined that the process is the monitoring interrupt process 211.
If the new interrupt process is the monitor interrupt process 211 (YES in S103), the entrance stack determination unit 226 advances the process to S104. On the other hand, when the new interrupt process is not the monitor interrupt process 211 (NO in S103), the entrance stack determination unit 226 advances the process to S111.

In the switching value determination processing in S104, the entrance stack determination unit 226 determines the bottom value of the monitoring stack 212 as the switching value when the new interrupt processing is the monitoring interrupt processing 211.

In the process determination process of S105, the entry stack determination unit 226 determines whether the process being executed is the main task 202 or the control interrupt process 203 having a lower priority than the monitoring interrupt process 211. Determine using. Specifically, if the value of the low priority counter 233 is 0, the entry stack determination unit 226 determines that the process being executed is the main task 202, and the value of the low priority counter 233 is other than 0. If there is, it is determined that the process being executed is the control interrupt process 203.
If the process being executed is the main task 202 (YES in S105), the entrance stack determination unit 226 advances the process to S106. On the other hand, when the process being executed is the control interrupt process 203 (NO in S105), the entrance stack determination unit 226 advances the process to S110.

In the SP value saving process of S106, when the process being executed is the main task 202, the stack saving unit 227 saves the address value of SP107 in the task pointer area 237.

In the flag setting process of S107, the entrance stack determination unit 226 sets the monitoring stack use flag 234.

In the SP value switching process of S108, the stack storage unit 227 switches the SP107 address value to the determined switching value.

In the end process of S109, the interrupt entrance processing unit 220 ends the entrance process.

In the SP value saving process of S110, the stack saving unit 227 saves the address value of SP107 in the control pointer area 235 when the process being executed is the control interrupt process 203.
The processing from S108 to S109 is as described above.

In the monitoring stack determination process of S111, the entrance stack determination unit 226 determines whether the monitoring stack 212 is in use by using the monitoring stack use flag 234. Specifically, the entrance stack determination unit 226 determines that the monitoring stack 212 is in use if the monitoring stack use flag 234 is set.
If the monitoring stack 212 is in use (YES in S111), the entrance stack determination unit 226 advances the process to S112. On the other hand, when the monitoring stack 212 is not in use (NO in S111), the entrance stack determination unit 226 advances the process to S118.

In the high priority counter determination process of S112, the entrance stack determination unit 226 determines whether the high priority counter 232 is 0 when the monitoring stack 212 is in use. When the high priority counter 232 is 0, it means that multiple high priority control interrupt processes have not occurred.
When the high priority counter 232 is 0 (YES in S112), the entrance stack determination unit 226 advances the process to S113. On the other hand, when the high priority counter 232 is not 0 (NO in S112), the entrance stack determination unit 226 advances the process to S116.

In the low priority counter determination process of S113, the entrance stack determination unit 226 determines whether the low priority counter 233 is 0 when the high priority counter 232 is 0. When the low priority counter 233 is 0, the low priority control interrupt process has not occurred before the monitoring interrupt process 211 occurs.
When the low priority counter 233 is 0 (YES in S113), the entrance stack determination unit 226 advances the process to S114. On the other hand, when the low priority counter 233 is not 0 (NO in S113), the entrance stack determination unit 226 advances the process to S117.

In the switching value determination process of S114, the entry stack determination unit 226 uses the bottom value of the control stack 205 as the switching value because the control stack 205 is unused when the low priority counter 233 is 0. decide.

In the SP value saving process of S115, the stack saving unit 227 saves the SP107 value in the monitoring pointer area 236.

In the count process of S <b> 116, the entrance stack determination unit 226 adds 1 to the value of the high priority counter 232.
The processing from S108 to S109 is as described above.

In the switching value determination process of S117, the entry stack determination unit 226 uses the value stored in the control pointer area 235 because the control stack 205 is in use when the low priority counter 233 is not 0. Determine the switching value.
The processing from S115 to S116 and the processing from S108 to S109 are as described above.

In S112, when the high priority counter 232 is not 0, the control stack 205 is continuously used. For this reason, the value of SP 107 is not switched, and the high priority counter 232 is incremented by 1 in S116.

In the low priority counter determination process of S118, the entrance stack determination unit 226 determines whether the low priority counter 233 is 0 when the monitoring stack 212 is not in use. When the low priority counter 233 is 0, the low priority control interrupt process has not occurred and the main task 202 has been executed before the monitoring interrupt process 211 occurs.
If the low priority counter 233 is 0 (YES in S118), the entrance stack determination unit 226 advances the process to S119. On the other hand, when the low priority counter 233 is not 0 (NO in S118), the entrance stack determination unit 226 advances the process to S121.

In the switching value determination processing in S119, the entrance stack determination unit 226 uses the bottom value of the control stack 205 as the switching value because the control stack 205 is unused when the low priority counter 233 is 0. decide.

In the SP value saving process in S120, the stack saving unit 227 saves the SP107 value in the task pointer area 237.

In the count process of S121, the entrance stack determination unit 226 adds 1 to the value of the low priority counter 233.
The processing from S108 to S109 is as described above.

In S118, when the low priority counter 233 is not 0, the control stack 205 is continuously used. Therefore, the value of SP 107 is not switched, and 1 is added to the low priority counter 233 in S116.

6 and 7 are flowcharts showing the exit processing according to the first embodiment.
In the start processing of S301, the interrupt processing ends, control is transferred from the interrupt processing calling unit 221 to the interrupt exit processing unit 222, and the interrupt exit processing unit 222 starts exit processing.

In the interrupt determination process of S302, the exit stack determination unit 228 determines whether or not the completed end interrupt process is the monitoring interrupt process 211. Here, the exit stack determination unit 228 acquires the cause number of the end interrupt process from the register of the ICU, and when the exit interrupt process matches the cause number stored in the monitor interrupt identification information storage unit 231, the exit interrupt process is the monitor interrupt process. 211.
If the end interrupt process is the monitoring interrupt process 211 (YES in S302), the exit stack determination unit 228 advances the process to S303. On the other hand, when the end interrupt process is not the monitoring interrupt process 211 (NO in S302), the exit stack determination unit 228 advances the process to S310.

In the flag clear process of S303, the exit stack determining unit 228 clears the monitor stack use flag 234 when the end interrupt process is the monitor interrupt process 211.

In the low priority counter determination process of S304, the exit stack determination unit 228 determines whether the low priority counter 233 is zero. When the low priority counter 233 is 0, the low priority control interrupt process has not occurred before the monitoring interrupt process 211 occurs.
If the low priority counter 233 is 0 (YES in S304), the exit stack determination unit 228 advances the process to S305. On the other hand, when the low priority counter 233 is not 0 (NO in S304), the exit stack determination unit 228 advances the process to S309.

In the SP value recovery process of S305, the stack recovery unit 229 uses the value stored in the task pointer area 237 as the SP107 because the low priority control interrupt process has not occurred when the low priority counter 233 is 0. Set to.

In the register restoration process in S306, the general-purpose register restoration unit 230 stores the information stored in the stack area indicated by the address value set in the SP 107 in the general-purpose register 108.

In the return instruction process of S307, the interrupt exit processing unit 222 executes the interrupt return instruction.

In the termination process of S308, the interrupt exit processing unit 222 terminates the exit process.

In the SP value return process of S309, the stack return unit 229 generates a low priority control interrupt process when the low priority counter 233 is not 0, so the value stored in the control pointer area 235 is set to SP107. Set.
The processing from S306 to S308 is as described above.

In the monitoring stack determination process of S310, the exit stack determination unit 228 determines whether the monitoring stack 212 is in use by using the monitoring stack use flag 234. Specifically, the exit stack determination unit 228 determines that the monitoring stack 212 is in use if the monitoring stack use flag 234 is set.
If the monitoring stack 212 is in use (YES in S310), the exit stack determination unit 228 advances the process to S311. On the other hand, when the monitoring stack 212 is not in use (NO in S310), the exit stack determination unit 228 advances the process to S316.

In the count process of S311, the exit stack determination unit 228 subtracts 1 from the value of the high priority counter 232 because the high priority control interrupt process is completed when the monitoring stack 212 is in use.

In the high priority counter determination process of S312, the exit stack determination unit 228 determines whether the high priority counter 232 is zero. If the high priority counter 232 is 0, no other high priority control interrupt processing has occurred.
If the high priority counter 232 is 0 (YES in S312), the exit stack determination unit 228 advances the process to S313. On the other hand, when the high priority counter 232 is not 0 (NO in S312), the exit stack determination unit 228 advances the process to S306.

In the low priority counter determination process of S313, when the high priority counter 232 is 0, the exit stack determination unit 228 determines whether the low priority counter 233 is 0. When the low priority counter 233 is 0, the low priority control interrupt process has not occurred before the monitoring interrupt process 211 occurs.
If the low priority counter 233 is 0 (YES in S313), the exit stack determination unit 228 advances the process to S314. On the other hand, when the low priority counter 233 is not 0 (NO in S313), the exit stack determination unit 228 advances the process to S315.

In the SP value recovery process of S314, when the low priority counter 233 is 0, the stack recovery unit 229 sets the value stored in the monitoring pointer area 236 to SP107.
The processing from S306 to S308 is as described above.

In the SP value saving process of S315, the stack restoration unit 229 saves the value of SP107 in the control pointer area 235 when the low priority counter 233 is not zero. After that, the stack restoration unit 229 sets the value stored in the monitoring pointer area 236 in S <b> 314 in the SP 107. By storing the value of SP 107 in the control pointer area 235, it is possible to return the process from the middle of the control stack 205 when the monitoring interrupt process 211 is completed.
The processing from S306 to S308 is as described above.

In S312, when the high priority counter 232 is not 0, the control stack 205 is continuously used. For this reason, the value of SP 107 is not switched.

In the count process of S316, when the monitoring stack 212 is not in use, the exit stack determination unit 228 subtracts 1 from the value of the low priority counter 233 because the low priority control interrupt process is completed.

In the low priority counter determination processing in S317, the exit stack determination unit 228 determines whether the low priority counter 233 is zero. When the low priority counter 233 is 0, no other low priority control interrupt processing has occurred, and the main task 202 has been executed before the occurrence of the interrupt processing.
If the low priority counter 233 is 0 (YES in S317), the exit stack determination unit 228 advances the process to S318. On the other hand, when the low priority counter 233 is not 0 (NO in S317), the exit stack determination unit 228 advances the process to S306.

In the SP value return process of S318, when the low priority counter 233 is 0, the stack return unit 229 sets the value stored in the task pointer area 237 to SP107.
The processing from S306 to S308 is as described above.

In S317, when the low priority counter 233 is not 0, the control stack 205 is continuously used. For this reason, the value of SP 107 is not switched.

*** Effects of Embodiment 1 ***
As described above, the interrupt control device 100 according to the first embodiment has an appropriate process based on the interrupt processing that has occurred or ended in the interrupt entry processing and exit processing, and the type of interrupt processing that is occurring. Switch to the stack area.
As a result, even when a high priority control interrupt process occurs during the execution of the monitoring interrupt process 211, it is possible to control so that the high priority control interrupt process does not use the monitoring stack 212. Therefore, it is possible to ensure that the control interrupt process 203 does not affect the monitoring interrupt process 211 even when the CPU 101 can use only one SP 107.
Even if a monitoring interrupt occurs during execution of a low priority control interrupt and a high priority control interrupt occurs during execution of the monitoring interrupt processing 211, the position from which the low priority control interrupt was used later The control stack 205 can be used. Therefore, it is possible to share and use one stack in the control interrupt process 203.

*** Other configurations ***
In the configuration shown in FIG. 2, the interrupt vector area 109 is provided in the ROM 102. However, the interrupt vector area 109 may be provided in the RAM 103.

In the configuration shown in FIG. 2, the value stored in the SP storage unit 224 is stored in the RAM 103 as a global variable. However, the value stored in the SP storage unit 224 may be stored in a stack area used in the interrupt processing that has occurred.

100 interrupt control device, 101 CPU, 102 ROM, 103 RAM, 104 peripheral device, 105 PC, 106 PSW, 107 SP, 108 general purpose register, 109 interrupt vector area, 110 control module code area, 111 monitoring module code area, 112 control Module data area, 113 Monitor module data area, 114 Control module stack area, 115 Monitor module stack area, 201 Control module, 202 Main task, 203 Control interrupt processing, 204 Task stack, 205 Control stack, 206 Interrupt handler table, 210 Monitor Module, 211 monitoring interrupt processing, 212 monitoring stack, 213 interrupt control mechanism, 220 interrupt entry processing unit, 2 1 interrupt processing call unit, 222 interrupt exit processing unit, 223 interrupt management unit, 224 SP storage unit, 225 general register storage unit, 226 entrance stack determination unit, 227 stack storage unit, 228 exit stack determination unit, 229 stack return unit, 230 General register return unit, 231 monitoring interrupt specific information storage unit, 232 high priority counter, 233 low priority counter, 234 monitoring stack use flag, 235 control pointer area, 236 monitoring pointer area, 237 task pointer area.

Claims

The type of interrupt processing that is occurring is divided into monitoring interrupt processing that monitors the system and control interrupt processing that controls the system, and the control interrupt processing is processed during the operation of the monitoring interrupt processing, and An interrupt management unit that manages and manages the processing that occurs during non-operation of the monitoring interrupt processing,
When a new interrupt process occurs, whether the newly generated new interrupt process is the monitoring interrupt process or the control interrupt process, the type of the interrupt process being generated managed by the interrupt management unit, and From the control pointer area for the control stack used in the control interrupt processing and the monitoring pointer area for the monitoring stack used in the monitoring interrupt processing, the stack indicating the data reading destination of the arithmetic unit An entry stack determination unit that determines whether to store the address value set in the pointer;
An interrupt control device comprising: a stack storage unit that switches the address value of the stack pointer after storing the address value set in the stack pointer in the storage destination determined by the entry stack determination unit.
The entry stack determination unit includes a task pointer area for a task stack used in a main task that is executed when neither of the control interrupt process and the monitoring interrupt process occurs, and the control The interrupt control apparatus according to claim 1, wherein a pointer area or the monitoring pointer area is determined as the storage destination.
The entrance stack determination unit
If the new interrupt process is the monitoring interrupt process and there is no control interrupt process that occurred during the non-operation, the task pointer area is determined as the storage destination,
When the new interrupt process is the monitoring interrupt process and there is the control interrupt process generated during the non-operation, the control pointer area is determined as the storage destination,
If the new interrupt process is the control interrupt process, the monitor interrupt process has occurred, and there is no control interrupt process that has occurred during the operation, the monitor pointer area is stored in the storage destination area. Decided on
If the new interrupt process is the control interrupt process, the monitor interrupt process has not occurred, and there is no control interrupt process that occurred during the non-operation, the task pointer area is The interrupt control device according to claim 2, wherein the interrupt control device is determined as a storage destination.
The interrupt control device further includes:
When the interrupt process is completed, the control is determined based on whether the ended interrupt process is the control interrupt process or the monitoring interrupt process and the type of the interrupt process that is being managed and managed by the interrupt management unit. An exit stack determination unit that determines which of the pointer area and the monitoring pointer area is to be read destination of the address value set in the stack pointer;
The interrupt control device according to claim 1, further comprising: a stack return unit that sets an address value stored in a read destination determined by the exit stack determination unit in the stack pointer.
The exit stack determination unit includes a task pointer area for a task stack used in a main task that is executed when neither of the control interrupt processing and the monitoring interrupt processing occurs, and the control The interrupt control device according to claim 4, wherein a pointer area or the monitoring pointer area is determined as the reading destination.
The exit stack determining unit
If the end interrupt process is the monitoring interrupt process and there is no control interrupt process that occurred during the non-operation, the task pointer area is determined as the read destination,
When the end interrupt process is the monitoring interrupt process and there is the control interrupt process that occurs during the non-operation, the control pointer area is determined as the read destination,
When the end interrupt process is the control interrupt process, the monitor interrupt process is generated, and there is no control interrupt process generated during the operation, the monitor pointer area is set to the read destination. Decided on
If the end interrupt process is the control interrupt process, the monitoring interrupt process has not occurred, and there is no control interrupt process generated during the non-operation, the task pointer area is The interrupt control apparatus according to claim 5, wherein the interrupt control apparatus determines a reading destination.
The stack return unit is configured such that the end interrupt process is the control interrupt process, the monitoring interrupt process is generated, the control interrupt process is not generated during the operation, and the non-operation is performed. If there is the control interrupt processing that has occurred in the memory, the address value set in the stack pointer is stored in the control pointer area, and the address value stored in the read destination is set in the stack pointer. The interrupt control device according to claim 6.
The entrance stack determination unit determines whether the new interrupt processing is the control interrupt processing or the monitoring interrupt processing, and the type of interrupt processing being generated managed by the interrupt management unit. Determine the switching value,
The interrupt control device according to claim 1, wherein the stack storage unit switches the address value of the stack pointer to a switching value determined by the entry stack determination unit.
The entrance stack determination unit
If the new interrupt processing is the monitoring interrupt processing, the bottom value of the monitoring stack is determined as the switching value,
The new interrupt process is the control interrupt process, the monitoring interrupt process has occurred, the control interrupt process has not occurred during the operation, and the control has occurred during the non-operation When there is no interrupt processing, the bottom value of the control stack is determined as the switching value,
The new interrupt process is the control interrupt process, the monitoring interrupt process has occurred, the control interrupt process has not occurred during the operation, and the control has occurred during the non-operation If there is an interrupt process, the value stored in the control pointer area is determined as the switching value,
If the new interrupt process is the control interrupt process, the monitor interrupt process has not occurred, and there is no control interrupt process that occurred during the non-operation, the bottom value of the control stack The interrupt control device according to claim 8, wherein the switching value is determined.
The type of interrupt processing that is occurring is divided into monitoring interrupt processing that monitors the system and control interrupt processing that controls the system, and the control interrupt processing is processed during the operation of the monitoring interrupt processing, and It is managed separately from the processing that occurred during non-operation of the monitoring interrupt processing,
When a new interrupt process occurs, the control interrupt is determined based on whether the newly generated new interrupt process is the monitoring interrupt process or the control interrupt process and the type of the interrupt process currently being managed. Either the control pointer area for the control stack used in the processing or the monitoring pointer area for the monitoring stack used in the monitoring interrupt process is set as the stack pointer indicating the data reading destination of the arithmetic device Decide whether to save the address value,
An interrupt control method for switching an address value of the stack pointer after storing an address value set in the stack pointer in a determined storage destination.