WO2016204112A1

WO2016204112A1 - Silicon carbide semiconductor device and production method for same

Info

Publication number: WO2016204112A1
Application number: PCT/JP2016/067510
Authority: WO
Inventors: 雄斎藤; 透日吉; 築野　孝
Original assignee: 住友電気工業株式会社
Priority date: 2015-06-18
Filing date: 2016-06-13
Publication date: 2016-12-22
Also published as: JP6500628B2; JP2017011031A

Abstract

According to the present invention, a gate-insulating film contacts a first drift region at a bottom section and contacts a second drift region, a second impurities region, and a third impurities region at side sections. A profile that indicates the relationship, within a region that is constituted by the second impurities region, the second drift region, and the first drift region, between positions in a direction that is orthogonal to a second main surface and the absolute value of the difference between the concentration of a first conductive impurity and the concentration of a second conductive impurity has a first minimum value and a second minimum value. The position that indicates the first minimum value is between the position of a third main surface and the position of a fourth main surface. The position that indicates the second minimum value is between the position of a first main surface and the position of the fourth main surface.

Description

Silicon carbide semiconductor device and manufacturing method thereof

The present invention relates to a silicon carbide semiconductor device and a method for manufacturing the same. This application claims priority based on Japanese Patent Application No. 2015-123052, which was filed on June 18, 2015, and uses all the contents described in the Japanese Patent Application.

In recent years, silicon carbide has been increasingly adopted as a material for semiconductor devices in order to enable the use of high-voltage, low-loss and high-temperature environments in semiconductor devices such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). It is being For example, International Publication No. 2012/017798 (Patent Document 1) discloses a method for manufacturing a trench MOSFET in which a trench is formed on the surface of a breakdown voltage holding layer.

International Publication No. 2012/017798

A silicon carbide semiconductor device according to one embodiment of the present invention includes a silicon carbide substrate and a gate insulating film. The silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. The silicon carbide substrate includes a first impurity region having a first conductivity type, a second impurity region provided on the first impurity region and having a second conductivity type different from the first conductivity type, and separated from the first impurity region. And a third impurity region which is provided on the second impurity region and forms the first main surface and has the first conductivity type. The first impurity region has a first drift region and a second drift region sandwiched between the first drift region and the second impurity region. The maximum value of the first conductivity type impurity concentration in the second drift region is larger than the maximum value of the first conductivity type impurity concentration in the first drift region. The first main surface includes a side part that penetrates the second drift region, the second impurity region, and the third impurity region and reaches the first drift region, and a bottom portion that is provided continuously with the side portion. A trench defined by is formed. The gate insulating film is in contact with the first drift region at the bottom, and is in contact with the second drift region, the second impurity region, and the third impurity region at the side. The gate insulating film has a third main surface in contact with the bottom and a fourth main surface opposite to the third main surface. In the region constituted by the second impurity region, the second drift region, and the first drift region, the position in the direction perpendicular to the second main surface is x, and the concentration of the first conductivity type impurity and the second conductivity type Assuming that the absolute value of the difference from the impurity concentration is y, the profile showing the relationship between x and y is the first minimum value and the second minimum value located closer to the first main surface than the first minimum value. And have. In the direction perpendicular to the second main surface, the position showing the first minimum value is between the position of the third main surface and the position of the fourth main surface. In the direction perpendicular to the second main surface, the position showing the second minimum value is between the position of the first main surface and the position of the fourth main surface.

The method for manufacturing a silicon carbide semiconductor device according to one aspect of the present invention includes the following steps. A silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface is prepared. The silicon carbide substrate includes a first impurity region having a first conductivity type, a second impurity region provided on the first impurity region and having a second conductivity type different from the first conductivity type, and separated from the first impurity region. And a third impurity region which is provided on the second impurity region and forms the first main surface and has the first conductivity type. The first impurity region has a first drift region and a second drift region sandwiched between the first drift region and the second impurity region. The maximum value of the first conductivity type impurity concentration in the second drift region is larger than the maximum value of the first conductivity type impurity concentration in the first drift region. The first drift region and the second drift region are formed by epitaxial growth. The second impurity region is formed by performing ion implantation on the second drift region. The first main surface includes a side part penetrating the second drift region, the second impurity region, and the third impurity region and reaching the first drift region, and a bottom portion provided continuously with the side portion. A defined trench is formed. A gate insulating film is formed in contact with the first drift region at the bottom and in contact with the second drift region, the second impurity region, and the third impurity region at the side. The gate insulating film has a third main surface in contact with the bottom and a fourth main surface opposite to the third main surface. In the region constituted by the second impurity region, the second drift region, and the first drift region, the position in the direction perpendicular to the second main surface is x, and the concentration of the first conductivity type impurity and the second conductivity type Assuming that the absolute value of the difference from the impurity concentration is y, the profile showing the relationship between x and y is the first minimum value and the second minimum value located closer to the first main surface than the first minimum value. And have. In the direction perpendicular to the second main surface, the position showing the first minimum value is between the position of the third main surface and the position of the fourth main surface. In the direction perpendicular to the second main surface, the position showing the second minimum value is between the position of the first main surface and the position of the fourth main surface.

It is a cross-sectional schematic diagram which shows the structure of the silicon carbide semiconductor device which concerns on embodiment. 1 is a schematic perspective view showing a configuration of a silicon carbide substrate included in a silicon carbide semiconductor device according to an embodiment. FIG. 2 is a diagram schematically showing a profile of | N _d −N _a | in a direction along an arrow L in FIG. 1. It is a cross-sectional schematic diagram which shows the structure of the modification of the silicon carbide semiconductor device which concerns on embodiment. It is a fragmentary sectional view showing roughly the fine structure of the surface of a silicon carbide layer which a silicon carbide semiconductor device has. FIG. 3 is a diagram showing a crystal structure of a (000-1) plane in polytype 4H hexagonal crystal. FIG. 7 is a diagram showing a crystal structure of a (11-20) plane along line VII-VII in FIG. FIG. 6 is a view showing a crystal structure in the vicinity of the surface of the composite surface in FIG. 5 in the (11-20) plane. FIG. 6 is a view of the composite surface of FIG. 5 as viewed from the (01-10) plane. FIG. 5 is a graph showing an example of the relationship between the channel surface mobility and the angle between the channel surface and the (000-1) surface viewed macroscopically, when thermal etching is performed and when it is not performed. is there. It is a graph which shows an example of the relationship between the angle between a channel direction and the <0-11-2> direction, and channel mobility. It is a figure which shows the modification of FIG. It is a flowchart which shows schematically the manufacturing method of the silicon carbide semiconductor device which concerns on embodiment. It is a flowchart which shows schematically the manufacturing process which the process of forming a silicon carbide substrate includes. It is a cross-sectional schematic diagram which shows the 1st process of the manufacturing method of the silicon carbide semiconductor device which concerns on embodiment. The profile of the N _d in the direction along the arrow X of FIG. 15 is a diagram schematically showing. It is a figure which shows schematically the implantation profile of the p-type impurity ion in the process of forming a body region. It is a cross-sectional schematic diagram which shows the 2nd process of the manufacturing method of the silicon carbide semiconductor device which concerns on embodiment. FIG. 19 is a diagram schematically showing a profile of | N _d −N _a | in a direction along an arrow X in FIG. 18. It is a figure which shows roughly the implantation profile of the n-type impurity ion in the process of forming a source region. It is a cross-sectional schematic diagram which shows the 3rd process of the manufacturing method of the silicon carbide semiconductor device which concerns on embodiment. It is a cross-sectional schematic diagram which shows the 4th process of the manufacturing method of the silicon carbide semiconductor device which concerns on embodiment. It is a flowchart which shows schematically the manufacturing process which the process of forming a gate insulating film includes. It is a cross-sectional schematic diagram which shows the 5th process of the manufacturing method of the silicon carbide semiconductor device which concerns on embodiment. It is a cross-sectional schematic diagram which shows the 6th process of the manufacturing method of the silicon carbide semiconductor device which concerns on embodiment. It is a cross-sectional schematic diagram which shows the 7th process of the manufacturing method of the silicon carbide semiconductor device which concerns on embodiment. It is a cross-sectional schematic diagram which shows the 8th process of the manufacturing method of the silicon carbide semiconductor device which concerns on embodiment. It is a cross-sectional schematic diagram which shows the 9th process of the manufacturing method of the silicon carbide semiconductor device which concerns on embodiment. It is a cross-sectional schematic diagram which shows the 1st process of the modification of the process of forming a gate insulating film. It is a cross-sectional schematic diagram which shows the 2nd process of the modification of the process of forming a gate insulating film.

[Problems to be solved by the present disclosure]
In the trench MOSFET manufacturing method, a p-type body region is formed by ion-implanting a p-type impurity such as aluminum into the surface of the breakdown voltage holding layer. The p-type body region has an impurity concentration profile having a p-type impurity concentration peak in the depth direction of the breakdown voltage holding layer. At a position deeper than the position showing the peak of the p-type impurity concentration, the concentration of the p-type impurity monotonously decreases. That is, the p-type impurity reaches a deep region of about 1 μm or more and about 2 μm or less from the position showing the peak of the concentration of the p-type impurity due to channeling effect. This increases the effective channel length and increases the on-resistance of the MOSFET.

Also, due to the channeling effect of the p-type impurity, the position of the bottom of the body region in the depth direction of the breakdown voltage holding layer is close to the position of the bottom of the trench. In particular, when a thick gate insulating film is formed on the bottom of the trench, the thickness of the gate insulating film in contact with the bottom of the body region increases. That is, the thickness of the gate insulating film on the channel region in the body region is increased. Therefore, the channel is not easily inverted, and the on-resistance of the MOSFET is increased.

In order to prevent the p-type impurity from reaching the deep region of the breakdown voltage holding layer, it is conceivable to increase the concentration of the n-type impurity in the breakdown voltage holding layer and compensate the concentration of the p-type impurity. However, when the concentration of the n-type impurity in the breakdown voltage holding layer is increased, the concentration of the n-type impurity near the corner of the trench is also increased. Therefore, the extension width of the depletion layer from the electric field relaxation region is shortened, and the electric field concentration at the corners of the trench cannot be sufficiently relaxed. That is, there is a trade-off relationship between reduction of on-resistance and electric field relaxation at the corners of the trench.

An object of one embodiment of the present invention is to provide a silicon carbide semiconductor device capable of reducing on-resistance and alleviating electric field concentration at a corner of a trench, and a method for manufacturing the same.

[Effects of the present disclosure]
According to one embodiment of the present invention, it is possible to provide a silicon carbide semiconductor device capable of reducing on-resistance and alleviating electric field concentration at a corner of a trench, and a method for manufacturing the same.

[Description of Embodiment of Present Invention]
(1) Silicon carbide semiconductor device 1 according to one aspect of the present invention includes a silicon carbide substrate 10 and a gate insulating film 15. Silicon carbide substrate 10 has a first main surface 10a and a second main surface 10b opposite to the first main surface 10a. Silicon carbide substrate 10 includes a first impurity region 12 having a first conductivity type, a second impurity region 13 provided on first impurity region 12 and having a second conductivity type different from the first conductivity type, And a third impurity region 14 provided on second impurity region 13 so as to be separated from impurity region 12 and constituting first main surface 10a and having the first conductivity type. The first impurity region 12 includes a first drift region 12 a and a second drift region 12 b sandwiched between the first drift region 12 a and the second impurity region 13. The maximum concentration of the first conductivity type impurity in the second drift region 12b is larger than the maximum value of the concentration of the first conductivity type impurity in the first drift region 12a. In the first main surface 10a, a side SW that penetrates the second drift region 12b, the second impurity region 13, and the third impurity region 14 and reaches the first drift region 12a is continuous with the side SW. A trench TR defined by the bottom portion BT provided in this manner is formed. Gate insulating film 15 is in contact with first drift region 12a at bottom BT, and is in contact with second drift region 12b, second impurity region 13, and third impurity region 14 at side SW. Gate insulating film 15 has third main surface 15b1 in contact with bottom portion BT, and fourth main surface 15b2 opposite to third main surface 15b1. In the region constituted by the second impurity region 13, the second drift region 12b, and the first drift region 12a, the position in the direction perpendicular to the second main surface 10b is x, and the concentration of the first conductivity type impurity is Assuming that the absolute value of the difference from the concentration of the second conductivity type impurity is y, the profile indicating the relationship between x and y is the first minimum value C3 and the first main surface 10a side of the first minimum value C3. And a second minimum value C4. In a direction perpendicular to the second main surface 10b, the position a1 indicating the first minimum value C3 is between the position b1 of the third main surface 15b1 and the position b2 of the fourth main surface 15b2. In a direction perpendicular to the second main surface 10b, the position a2 indicating the second minimum value C4 is between the position 0 of the first main surface 10a and the position b2 of the fourth main surface 15b2.

According to silicon carbide semiconductor device 1 according to (1) above, position a2 indicating second minimum value C4 in the direction perpendicular to second main surface 10b is equal to

positions

0 and 4 of first main surface 10a. It is between the position b2 of the main surface 15b2. The position a2 indicating the second minimum value C4 corresponds to the position a2 at the bottom of the body region 13. That is, the position a2 at the bottom of the body region 13 is between the position 0 of the first main surface 10a and the position b2 of the fourth main surface 15b2. Therefore, it is possible to suppress an increase in the thickness of the gate insulating film 15 on the channel region in the body region 13. Therefore, the on-resistance of silicon carbide semiconductor device 1 is reduced as compared with the case where position a2 at the bottom of body region 13 is between position b1 of third main surface 15b1 and position b2 of fourth main surface 15b2. can do.

According to silicon carbide semiconductor device 1 according to (1) above, position a1 indicating first minimum value C3 in the direction perpendicular to second main surface 10b is equal to position b1 of third main surface 15b1. Between the four principal surfaces 15b2 and the position b2. Therefore, it is possible to reduce the concentration of the first conductivity type impurity in the portion of the first drift region 12a in the vicinity of the bottom portion BT of the trench TR. As a result, since the extension width of the depletion layer from the electric field relaxation region 17 can be increased, it is possible to suppress the concentration of the electric field at the corners of the trench TR.

(2) In silicon carbide semiconductor device 1 according to (1) above, gate insulating film 15 includes first portion 15a in contact with second impurity region 13 at side SW and first drift region 12a at bottom BT. 2 part 15b may be included. The thickness _{t b} of the second portion 15b in a direction perpendicular to the bottom portion BT may be greater than the thickness _{t s} of the first portion 15a in a direction perpendicular to the sides SW. When the thickness t _s of the first portion 15a is small, because the channel is easily reversed, it is possible to reduce the on-resistance of the silicon carbide semiconductor device. When the thickness t _b of the second portion 15b is large, it is possible to gate insulating film 15 on the bottom portion BT is prevented from being destroyed.

(3) In the silicon carbide semiconductor device 1 according to the above (2), the value of the thickness _{t b} divided by the thickness _{t s} of the first portion 15a of the second portion 15b may be of 1.5 to 8 . With divided by the value of 1.5 or more in the thickness t _s of the thickness t _b of the second portion 15b first portion 15a, it is possible to relax the electric field applied to the gate insulating film of the trench bottom. By value than 8 obtained by dividing the thickness t _b of the second portion 15b the thickness t _s of the first portion 15a, maintaining a low on-resistance without interfering the second portion 15b to the second impurity region 13 be able to.

(4) In silicon carbide semiconductor device 1 according to any of (1) to (3) above, the distance H1 between first main surface 10a and bottom portion BT in the direction perpendicular to second main surface 10b is It may be 1 μm or more and 1.5 μm or less. By setting the distance H <b> 1 to 1 μm or more, the trench bottom is located outside the second impurity region 13, thereby suppressing an increase in on-resistance. By setting the distance H1 to 1.5 μm or less, the electric field applied to the gate insulating film at the bottom corner of the trench can be relaxed.

(5) In silicon carbide semiconductor device 1 according to any of (1) to (4) above, thickness H2 of second impurity region 13 in the direction perpendicular to second main surface 10b is 0.4 μm or more and 0 It may be 8 μm or less. By setting the thickness H2 to 0.4 μm or more, the gate threshold voltage can be increased and the drain breakdown voltage can be maintained high. By setting the thickness H2 to 0.8 μm or less, the on-resistance can be kept low without causing the second impurity region 13 to interfere with the second portion 15b.

(6) In silicon carbide semiconductor device 1 according to any one of (1) to (5) above, the maximum concentration of the first conductivity type impurity in second drift region 12b is set to the first conductivity type in first drift region 12a. The value divided by the maximum impurity concentration may be 5 or more and 10 or less. By dividing the maximum value of the first conductivity type impurity concentration of the second drift region 12b by the maximum value of the first conductivity type impurity concentration of the first drift region 12a to 5 or more, the second impurity region 13 By compensating for the second conductivity type impurity existing from the first to the first drift region, the effective channel length can be controlled and the on-resistance can be lowered. By dividing the maximum value of the first conductivity type impurity concentration of the second drift region 12b by the maximum value of the first conductivity type impurity concentration of the first drift region 12a to 10 or less, the second impurity region 13 The effective concentration of the second conductivity type impurity can be maintained, and the electric field applied to the gate insulating film in contact with the bottom corner of the trench can be reduced. As a result, the drain breakdown voltage can be maintained.

(7) In silicon carbide semiconductor device 1 according to any of (1) to (6) above, the maximum concentration of the second conductivity type impurity in second impurity region 13 is set to the first conductivity type in second drift region 12b. The value divided by the maximum impurity concentration may be 10 or more and 100 or less. The gate threshold voltage is increased by setting the value obtained by dividing the maximum concentration of the second conductivity type impurity in the second impurity region 13 by the maximum concentration of the first conductivity type impurity in the second drift region 12b to 10 or more. In addition, the drain breakdown voltage can be kept high. By dividing the maximum value of the second conductivity type impurity concentration of the second impurity region 13 by the maximum value of the first conductivity type impurity concentration of the second drift region 12b to 100 or less, the second impurity region 13 By compensating for the second conductivity type impurity existing from the first to the first drift region, the effective channel length can be controlled and the on-resistance can be lowered.

(8) In silicon carbide semiconductor device 1 according to any of (1) to (7) above, side SW may include a surface S1 having a plane orientation {0-33-8}. Thereby, the channel resistance in the side part SW can be reduced.

(9) The method for manufacturing silicon carbide semiconductor device 1 according to one aspect of the present invention includes the following steps. A silicon carbide substrate having a first main surface 10a and a second main surface 10b opposite to the first main surface 10a is prepared. Silicon carbide substrate 10 includes a first impurity region 12 having a first conductivity type, a second impurity region 13 provided on first impurity region 12 and having a second conductivity type different from the first conductivity type, And a third impurity region 14 provided on second impurity region 13 so as to be separated from impurity region 12 and constituting first main surface 10a and having the first conductivity type. The first impurity region 12 includes a first drift region 12 a and a second drift region 12 b sandwiched between the first drift region 12 a and the second impurity region 13. The maximum concentration of the first conductivity type impurity in the second drift region 12b is larger than the maximum value of the concentration of the first conductivity type impurity in the first drift region 12a. The first drift region 12a and the second drift region 12b are formed by epitaxial growth. The second impurity region 13 is formed by performing ion implantation on the second drift region 12b. A side SW that penetrates the second drift region 12b, the second impurity region 13, and the third impurity region 14 and reaches the first drift region 12a in the first main surface 10a is continuous with the side SW. A trench TR defined by the bottom portion BT provided is formed. Gate insulating film 15 is formed in contact with first drift region 12a at bottom BT and in contact with second drift region 12b, second impurity region 13, and third impurity region 14 at side SW. Gate insulating film 15 has third main surface 15b1 in contact with bottom portion BT, and fourth main surface 15b2 opposite to third main surface 15b1. In the region constituted by the second impurity region 13, the second drift region 12b, and the first drift region 12a, the position in the direction perpendicular to the second main surface 10b is x, and the concentration of the first conductivity type impurity is Assuming that the absolute value of the difference from the concentration of the second conductivity type impurity is y, the profile indicating the relationship between x and y is the first minimum value C3 and the first main surface 10a side of the first minimum value C3. And a second minimum value C4. In a direction perpendicular to the second main surface 10b, the position a1 indicating the first minimum value C3 is between the position b1 of the third main surface 15b1 and the position b2 of the fourth main surface 15b2. In a direction perpendicular to the second main surface 10b, the position a2 indicating the second minimum value C4 is between the position 0 of the first main surface 10a and the position b2 of the fourth main surface 15b2.

According to the method for manufacturing silicon carbide semiconductor device 1 according to (9) above, second impurity region 13 is second to second drift region 12b having a first conductivity type impurity concentration higher than first drift region 12a. It is formed by ion implantation of two conductivity type impurities. Therefore, channeling of the second conductivity type impurity can be suppressed. As a result, since the thickness H2 of the second impurity region 13 can be reduced, the channel length can be shortened. Therefore, the on-resistance of silicon carbide semiconductor device 1 can be reduced.

Further, according to the method for manufacturing silicon carbide semiconductor device 1 according to (9) above, the position a1 indicating the first minimum value C3 in the direction perpendicular to the second main surface 10b is the position of the third main surface 15b1. Between b1 and the position b2 of the fourth major surface 15b2. Therefore, it is possible to reduce the concentration of the first conductivity type impurity in the portion of the first drift region 12a in the vicinity of the bottom portion BT of the trench TR. As a result, since the extension width of the depletion layer from the electric field relaxation region can be increased, it is possible to suppress the concentration of the electric field at the corners of the trench TR.

(10) In the method for manufacturing silicon carbide semiconductor device 1 according to (9), the step of forming gate insulating film 15 includes the steps of forming silicon layer 4 in contact with side SW and bottom BT, and facing bottom BT. Forming a mask layer 5 on a portion of the silicon layer 4 to be removed, removing a part of the silicon layer 4 using the mask layer 5, removing the mask layer 5, and removing the mask layer 5. After the step, a step of thermally oxidizing silicon carbide substrate 10 in a state where a part of silicon layer 4 is left on bottom portion BT may be included. Thereby, the gate insulating film 15 in which the thickness of the portion of the gate insulating film 15 on the bottom portion BT is larger than the thickness of the gate insulating film 15 on the side portion SW can be manufactured by a simple method.

(11) In the method for manufacturing silicon carbide semiconductor device 1 according to (9) or (10) above, the step of forming trench TR may be performed by thermal etching. Thereby, the side part SW of trench TR can be effectively made into a special surface. As a result, the channel resistance in the side SW can be reduced.

(12) In the method for manufacturing silicon carbide semiconductor device 1 according to any one of (9) to (11), the step of forming first drift region 12a and the step of forming second drift region 12b include carbon and silicon. It may be performed using a gas containing. The value obtained by dividing the number of silicon atoms in the step of forming the second drift region 12b by the number of carbon atoms is greater than the value obtained by dividing the number of silicon atoms in the step of forming the first drift region 12a by the number of carbon atoms. It can be large. Carbon is easier to incorporate nitrogen than silicon. Therefore, in the step of forming the second drift region 12b, nitrogen as an n-type impurity can be easily taken up. As a result, the n-type impurity concentration in the second drift region 12b can be effectively made higher than the n-type impurity concentration in the first drift region 12a.

(13) In the method for manufacturing silicon carbide semiconductor device 1 according to any one of (9) to (12), first main surface 10a is on the carbon surface side, and second main surface 10b is on the silicon surface side. There may be. The carbon surface is easier to capture nitrogen than the silicon surface. Therefore, the concentration of the n-type impurity in the second drift region 12b formed on the first main surface 10a side can be effectively made higher than the concentration of the n-type impurity in the first drift region 12a. Further, the side portion SW of the trench TR can be a special surface. As a result, the channel resistance in the side SW can be reduced.

[Details of the embodiment of the present invention]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated. In the crystallographic description in this specification, the individual orientation is indicated by [], the collective orientation is indicated by <>, the individual plane is indicated by (), and the collective plane is indicated by {}. In addition, a negative crystallographic index is usually expressed by adding “-” (bar) above a number. In this specification, a negative sign is added before the number. Yes.

First, the configuration of a MOSFET as a silicon carbide semiconductor device according to an embodiment of the present invention will be described.

As shown in FIG. 1, MOSFET 1 according to the present embodiment includes a silicon carbide substrate 10, a gate insulating film 15, a gate electrode 27, an interlayer insulating film 22, a source electrode 16, a source wiring 19, The drain electrode 20 is mainly included. Silicon carbide substrate 10 includes a silicon carbide single crystal substrate 11 and a silicon carbide epitaxial layer 24 provided on silicon carbide single crystal substrate 11. Silicon carbide substrate 10 has a first main surface 10a and a second main surface 10b opposite to the first main surface 10a. Silicon carbide epitaxial layer 24 constitutes first main surface 10a, and silicon carbide single crystal substrate 11 constitutes second main surface 10b.

The first main surface 10a is, for example, a surface that is off 2 ° or more and 8 ° or less from the {000-1} surface or the {000-1} surface. Preferably, the first main surface 10a is on the carbon surface side, and the second main surface 10b is on the silicon surface side. The first major surface 10a is, for example, a surface that is off 2 ° or more and 8 ° or less from the (000-1) plane or the (000-1) plane. Silicon carbide single crystal substrate 11 is, for example, polytype 4H hexagonal silicon carbide. Silicon carbide single crystal substrate 11 includes an n-type impurity such as nitrogen and has an n-type (first conductivity type) conductivity type. Silicon carbide epitaxial layer 24 mainly includes drift region 12 (first impurity region 12), body region 13 (second impurity region 13), source region 14 (third impurity region 14), and contact region 18. Have.

The drift region 12 includes an n-type impurity such as nitrogen and has an n-type conductivity type. The concentration of n-type impurities contained in drift region 12 may be lower than the concentration of n-type impurities contained in silicon carbide single crystal substrate 11. The drift region 12 has a first drift region 12a and a second drift region 12b. The second drift region 12b is sandwiched between the first drift region 12a and the body region 13. Second drift region 12 b is in contact with first drift region 12 a and body region 13. The maximum value of the n-type impurity concentration in the second drift region 12b is larger than the maximum value of the n-type impurity concentration in the first drift region 12a.

The body region 13 is provided on the drift region 12. Body region 13 includes a p-type impurity such as aluminum and has a p-type (second conductivity type) conductivity type. A thickness H2 of body region 13 in a direction perpendicular to second main surface 10b is, for example, not less than 0.4 μm and not more than 0.8 μm.

The source region 14 is provided on the body region 13 so as to be separated from the drift region 12 by the body region 13. Source region 14 includes an n-type impurity such as nitrogen or phosphorus and has an n-type conductivity type. Source region 14 constitutes first main surface 10a of silicon carbide substrate 10. The concentration of the n-type impurity included in the source region 14 may be higher than the concentration of the n-type impurity included in the second drift region 12b.

The contact region 18 is in contact with the body region 13 and the source region 14. Contact region 18 contains a p-type impurity such as aluminum and has p-type conductivity. The concentration of the p-type impurity included in the contact region 18 may be higher than the concentration of the p-type impurity included in the body region 13. Contact region 18 is provided through source region 14 so as to connect body region 13 and first major surface 10a.

A trench TR is formed in the first main surface 10 a of the silicon carbide substrate 10. Trench TR is defined by side SW and bottom BT. The side SW passes through the second drift region 12b, the body region 13, and the source region 14, and reaches the first drift region 12a. The bottom part BT is provided continuously with the side part SW. The bottom portion BT is located in the drift region 12. Preferably, the angle θ formed by the side part SW and the bottom part BT is greater than 90 °. The distance H1 between the first main surface 10a and the bottom portion BT in the direction perpendicular to the second main surface 10b is, for example, not less than 1 μm and not more than 1.5 μm.

Side view SW may be inclined so that the width of trench TR narrows in a tapered shape toward bottom portion BT in a cross-sectional view (a visual field viewed from a direction parallel to second main surface 10b of silicon carbide substrate 10). . The side SW is preferably inclined at 52 ° or more and 72 ° or less with respect to the (000-1) plane. Note that the side portion SW may be formed perpendicular to the first main surface 10a. The bottom portion BT may have a flat shape substantially parallel to the first main surface 10a. In cross-sectional view, the shape of the trench TR may be U-shaped or V-shaped. Preferably, the side part SW includes a special surface. Details of the configuration of the special surface will be described later.

FIG. 2 is a diagram showing silicon carbide substrate 10 taken out from MOSFET 1 shown in FIG. As shown in FIG. 2, source region 14, body region 13 and drift region 12 are exposed at side SW of trench TR. Drift region 12 is exposed at each of side SW and bottom BT of trench TR. A portion where bottom portion BT and side portion SW are connected constitutes a corner portion of trench TR. Trench TR may extend so as to form a mesh having a honeycomb structure in a plan view (a visual field viewed from a direction perpendicular to second main surface 10b of silicon carbide substrate 10).

As shown in FIG. 2, in plan view, first main surface 10a of silicon carbide substrate 10 constituted by source region 14 and contact region 18 has a hexagonal shape. Preferably, in plan view, body region 13, source region 14 and contact region 18 have a hexagonal outer shape. Preferably, the unit cell has a hexagonal shape, more preferably a regular hexagonal shape. The shape of the unit cell may be a polygon such as a quadrangle. The shapes of the body region 13, the source region 14, and the contact region 18 in plan view are preferably the same as the shape of the unit cell.

As shown in FIG. 1, the gate insulating film 15 is in contact with the bottom portion BT and the side portion SW of the trench TR and a part of the first main surface 10a. Gate insulating film 15 is made of, for example, a material containing silicon dioxide. The gate insulating film 15 is a thermal oxide film, for example. Gate insulating film 15 is in contact with first drift region 12 a at bottom BT, and is in contact with second drift region 12 b, body region 13, and source region 14 at side SW. Gate insulating film 15 has third main surface 15b1 in contact with bottom portion BT, and fourth main surface 15b2 opposite to third main surface 15b1.

The gate insulating film 15 may include a first portion 15a in contact with the body region 13 in the side portion SW and a second portion 15b in contact with the first drift region 12a in the bottom portion BT. The thickness _{t b} of the second portion 15b in a direction perpendicular to the bottom portion BT may be greater than the thickness _{t s} of the first portion 15a in a direction perpendicular to the sides SW. Value the thickness _{t b} divided by the thickness _{t s} of the first portion 15a of the second portion 15b is, for example, 1.5 to 8.

Next, the profile of the impurity concentration in the silicon carbide epitaxial layer will be described.

FIG. 3 is a diagram schematically showing a profile of | N _d −N _a | in the direction along the arrow L in FIG. Here, _Nd is the concentration of an n-type impurity (first conductivity type impurity). N _a is the concentration of a p-type impurity (second conductivity type impurity). | N _d −N _a | is the absolute value y of the difference between the n-type impurity concentration and the p-type impurity concentration. The position x is a position in a direction perpendicular to the second major surface 10b. The position 0 is the position of the portion of the first major surface 10a configured by the source region 14. Position e is the position of boundary surface 11 a between silicon carbide single crystal substrate 11 and silicon carbide epitaxial layer 24. The region from position 0 to position a3 is the source region 14. The region from the position a3 to the position a2 is the body region 13. A region from the position a2 to the position a1 is the second drift region 12b. The region from the position a1 to the position e is the first drift region 12a.

In the region constituted by the body region 13, the second drift region 12b, and the first drift region 12a, the relationship between the position x and the absolute value y of the difference between the n-type impurity concentration and the p-type impurity concentration is shown. The profile has a first minimum value C3 and a second minimum value C4 located closer to the first main surface 10a than the first minimum value C3. In a direction perpendicular to the second main surface 10b, the position a1 indicating the first minimum value C3 is between the position b1 of the third main surface 15b1 of the gate insulating film 15 and the position b2 of the fourth main surface 15b2. is there. In a direction perpendicular to the second main surface 10b, the position a2 indicating the second minimum value C4 is between the position 0 of the first main surface 10a and the position b2 of the fourth main surface 15b2 of the gate insulating film 15. is there. The position a2 at which the absolute value y of the difference between the n-type impurity concentration and the p-type impurity concentration indicates the first minimum value C3 may be the boundary between the first drift region 12a and the second drift region 12b.

Preferably, a value obtained by dividing the maximum value of the n-type impurity concentration of the second drift region 12b by the maximum value of the n-type impurity concentration of the first drift region 12a is 5 or more and 10 or less. The concentration of the n-type impurity included in the first drift region 12a is, for example, 3 × 10 ¹⁵ cm ⁻³ or more and 2 × 10 ¹⁶ cm ⁻³ or less. The concentration of the n-type impurity included in second drift region 12b is, for example, not less than 2 × 10 ¹⁶ cm ^{−3 and not} more than 1 × 10 ¹⁷ cm ⁻³ .

Preferably, a value obtained by dividing the maximum value of the concentration of the p-type impurity in the body region 13 by the maximum value of the concentration of the n-type impurity in the second drift region 12b may be 10 or more and 100 or less.

As shown in FIG. 3, a profile indicating the relationship between the position x and the absolute value y of the difference between the concentration of the n-type impurity and the concentration of the p-type impurity at the position a3 of the boundary between the source region 14 and the body region 13. Has a local minimum. The position a3 is between the position a2 and the position 0. The maximum value C7 of the absolute value y of the difference between the n-type impurity concentration and the p-type impurity concentration in the source region 14 is the absolute value y of the difference between the n-type impurity concentration and the p-type impurity concentration in the body region 13. It may be larger than the maximum value C5. The absolute value y of the difference between the n-type impurity concentration and the p-type impurity concentration at position 0 may be smaller than the maximum value C7. The maximum value C5 of the absolute value y of the difference between the n-type impurity concentration and the p-type impurity concentration in the body region 13 is the absolute difference between the n-type impurity concentration and the p-type impurity concentration in the second drift region 12b. It may be larger than the maximum value C2 of the value y.

As shown in FIG. 1, the gate electrode 27 is provided inside the trench TR so as to be in contact with the gate insulating film 15 inside the trench TR. The gate electrode 27 is made of polysilicon containing impurities, for example. The gate electrode 27 is provided so as to face the source region 14, the body region 13, and the drift region 12.

The source electrode 16 is in contact with each of the source region 14 and the contact region 18 on the first main surface 10a. The source electrode 16 is made of a material containing, for example, Ti, Al, and Si. Preferably, source electrode 16 is in ohmic contact with source region 14 and contact region 18. The source wiring 19 is in contact with the source electrode 16. Source wiring 19 is made of, for example, a material containing aluminum.

The interlayer insulating film 22 is provided in contact with the gate electrode 27 and the gate insulating film 15. Interlayer insulating film 22 is made of, for example, a material containing silicon dioxide. The interlayer insulating film 22 electrically insulates the gate electrode 27 and the source electrode 16 from each other. Drain electrode 20 is in contact with silicon carbide single crystal substrate 11 on second main surface 10 b and is electrically connected to drift region 12. The drain electrode 20 is made of a material containing, for example, NiSi or TiAlSi.

First, a configuration of a modification of the MOSFET according to the present embodiment will be described.
As shown in FIG. 4, silicon carbide substrate 10 may include an electric field relaxation region 17. Electric field relaxation region 17 includes a p-type impurity such as aluminum and has p-type conductivity. The maximum value of the concentration of the p-type impurity included in the electric field relaxation region 17 is, for example, 7 × 10 ¹⁷ cm ⁻³ . The electric field relaxation region 17 may face the body region 13. The electric field relaxation region 17 is in contact with, for example, the first drift region 12a. Preferably, electric field relaxation region 17 is located between position b1 and position e in the direction perpendicular to second main surface 10b. The electric field relaxation region 17 may be connected to the body region 13 or may be separated from the body region 13.

Next, the configuration of the special surface will be described.
The side portion SW described above has a special surface, particularly in a portion on the body region 13. As shown in FIG. 5, the side portion SW having the special surface includes a surface S1 (first surface) having a surface orientation {0-33-8}. In other words, the surface including the surface S1 is provided in the body region 13 on the side portion SW of the trench TR. The plane S1 preferably has a plane orientation (0-33-8).

More preferably, the side SW includes the surface S1 microscopically, and the side SW further microscopically includes the surface S2 (second surface) having the surface orientation {0-11-1}. Here, “microscopic” means that the dimensions are as detailed as at least a dimension of about twice the atomic spacing. As a microscopic structure observation method, for example, TEM can be used. The plane S2 preferably has a plane orientation (0-11-1).

Preferably, the surface S1 and the surface S2 of the side SW constitute a composite surface SR having a surface orientation {0-11-2}. That is, the composite surface SR is configured by periodically repeating the surfaces S1 and S2. Such a periodic structure can be observed by, for example, TEM or AFM (Atomic Force Microscopy). In this case, the composite surface SR has an off angle of 62 ° macroscopically with respect to the {000-1} plane. Here, “macroscopic” means ignoring a fine structure having a dimension on the order of atomic spacing. As such a macroscopic off-angle measurement, for example, a general method using X-ray diffraction can be used. Preferably, composite surface SR has a plane orientation (0-11-2). In this case, the composite surface SR has an off angle of 62 ° macroscopically with respect to the (000-1) plane.

As the TEM, for example, JEM-2100F manufactured by JEOL Ltd. can be used. The sample analysis area is, for example, 10 μm × 10 μm × 0.1 μm. The acceleration voltage is 200 kV, for example. As the AFM, for example, Dimension Icon SPM System made by Nippon Bico Co., Ltd. can be used. The sample analysis area is, for example, 90 μm × 90 μm. The scan rate is, for example, 0.2 Hz. The chip speed is, for example, 8 μm / second. The amplitude set point is 15.5 nm, for example. The Z range is, for example, 1 μm. The above parameters are adjusted according to the sample. As the X-ray diffractometer, for example, SmartLab manufactured by Rigaku Corporation can be used. The sample analysis region is, for example, not less than 0.3 mmφ and not more than 0.8 mmφ. The tube used is, for example, Cu. The output is, for example, 45 kV and 80 mA. For example, after confirming that the first major surface 10a is the (000-1) plane with an X-ray diffractometer, the side SW of the trench TR is measured by AFM.

Preferably, the channel direction CD, which is the direction in which carriers flow on the channel surface, is along the direction in which the above-described periodic repetition is performed.

Next, the detailed structure of the composite surface SR will be described.
In general, when a silicon carbide single crystal of polytype 4H is viewed from the (000-1) plane, as shown in FIG. 6, Si atoms (or C atoms) are atoms of A layer (solid line in the figure), B layer atoms (broken line in the figure) located below, C layer atoms (dotted line in the figure) located below, and B layer atoms (not shown) located below this It is provided repeatedly. That is, a periodic laminated structure such as ABCBABCBABCB... Is provided with four layers ABCB as one period.

As shown in FIG. 7, on the (11-20) plane (cross section taken along line VII-VII in FIG. 6), the atoms in each of the four layers ABCB constituting one cycle described above are (0-11-2) It is not arranged to be completely along the plane. In FIG. 7, the (0-11-2) plane is shown so as to pass through the position of atoms in the B layer. In this case, the atoms in the A layer and the C layer are separated from the (0-11-2) plane. You can see that it is shifted. For this reason, even if the macroscopic plane orientation of the surface of the silicon carbide single crystal, that is, the plane orientation when ignoring the atomic level structure is limited to (0-11-2), the surface is microscopic. Can take various structures.

As shown in FIG. 8, in the composite surface SR, a surface S1 having a surface orientation (0-33-8) and a surface S2 connected to the surface S1 and having a surface orientation different from the surface orientation of the surface S1 are alternately provided. It is configured by being. The length of each of the surface S1 and the surface S2 is twice the atomic spacing of Si atoms (or C atoms). The surface obtained by averaging the surfaces S1 and S2 corresponds to the (0-11-2) surface (FIG. 7).

As shown in FIG. 9, the single crystal structure when the composite surface SR is viewed from the (01-10) plane periodically includes a structure (surface S1 portion) equivalent to a cubic crystal when viewed partially. Specifically, in the composite surface SR, a surface S1 having a surface orientation (001) in a structure equivalent to the above-described cubic crystal and a surface S2 connected to the surface S1 and having a surface orientation different from the surface orientation of the surface S1 are alternated. It is comprised by being provided in. Thus, a plane (plane S1 in FIG. 5) having a plane orientation (001) in a structure equivalent to a cubic crystal, and a plane connected to this plane and having a plane orientation different from this plane orientation (plane in FIG. 5) It is also possible for polytypes other than 4H to constitute the surface according to S2). The polytype may be 6H or 15R, for example.

Next, the relationship between the crystal plane of the side SW and the mobility MB of the channel plane will be described with reference to FIG. In the graph of FIG. 10, the horizontal axis indicates the angle D1 formed by the macroscopic surface orientation of the side SW having the channel surface and the (000-1) plane, and the vertical axis indicates the mobility MB. The plot group CM corresponds to the case where the side SW is finished as a special surface by thermal etching, and the plot group MC corresponds to the case where such thermal etching is not performed.

The mobility MB in the plot group MC was maximized when the macroscopic surface orientation of the channel surface was (0-33-8). This is because, when thermal etching is not performed, that is, when the microscopic structure of the channel surface is not particularly controlled, the macroscopic plane orientation is set to (0-33-8). This is probably because the ratio of the formation of the visual plane orientation (0-33-8), that is, the plane orientation (0-33-8) considering the atomic level, stochastically increased.

On the other hand, the mobility MB in the plot group CM was maximized when the macroscopic surface orientation of the channel surface was (0-11-2) (arrow EX). The reason for this is that, as shown in FIGS. 8 and 9, a large number of surfaces S1 having a plane orientation (0-33-8) are regularly and densely arranged via the surface S2, so that the surface of the channel surface is minute. This is probably because the proportion of the visual plane orientation (0-33-8) has increased.

The mobility MB has an orientation dependency on the composite surface SR. In the graph shown in FIG. 11, the horizontal axis indicates the angle D2 between the channel direction and the <0-11-2> direction, and the vertical axis indicates the mobility MB (arbitrary unit) of the channel surface. A broken line is added to make the graph easier to see. From this graph, in order to increase the channel mobility MB, the angle D2 of the channel direction CD (FIG. 5) is preferably 0 ° or more and 60 ° or less, and more preferably approximately 0 °. all right.

As shown in FIG. 12, the side SW may further include a surface S3 (third surface) in addition to the composite surface SR. More specifically, the side portion SW may include a composite surface SQ configured by periodically repeating the surface S3 and the composite surface SR. In this case, the off angle of the side SW with respect to the {000-1} plane deviates from 62 ° which is the ideal off angle of the composite surface SR. This deviation is preferably small and preferably within a range of ± 10 °. As a surface included in such an angle range, for example, there is a surface whose macroscopic plane orientation is a {0-33-8} plane. More preferably, the off angle of the side SW with respect to the (000-1) plane deviates from 62 ° which is the ideal off angle of the composite surface SR. This deviation is preferably small and preferably within a range of ± 10 °. As a surface included in such an angle range, for example, there is a surface whose macroscopic plane orientation is a (0-33-8) plane.

Such a periodic structure can be observed by, for example, TEM or AFM. Specific examples of the measurement apparatus, the sample analysis region, and the measurement conditions are as described above.

Next, a method for manufacturing MOSFET 1 according to the present embodiment will be described.
First, a step of preparing a silicon carbide substrate (S10: FIG. 13) is performed. As shown in FIG. 14, the step of preparing the silicon carbide substrate includes the step of epitaxially growing the first drift region (S11: FIG. 14), the step of epitaxially growing the second drift region (S12: FIG. 14), The injection step (S13: FIG. 14) is mainly included. The step of epitaxially growing the first drift region (S11: FIG. 14) is performed using, for example, a gas containing carbon and silicon. Specifically, for example, by a CVD (Chemical Vapor Deposition) method using a mixed gas of silane (SiH ₄ ) and propane (C ₃ H ₈ ) as a source gas and using, for example, hydrogen gas (H ₂ ) as a carrier gas. First drift region 12 a is formed on silicon carbide single crystal substrate 11. In the epitaxial growth, for example, nitrogen (N) or phosphorus (P) is introduced as an impurity.

Next, a step of epitaxially growing the second drift region (S12: FIG. 14) is performed. The step of epitaxially growing the second drift region is performed using, for example, a gas containing carbon and silicon. Specifically, the first drift region is obtained by a CVD method using, for example, a mixed gas of silane (SiH ₄ ) and propane (C ₃ H ₈ ) as a source gas and using, for example, hydrogen gas (H ₂ ) as a carrier gas. A second drift region 12b is formed on 12a (see FIG. 15). In the epitaxial growth, for example, nitrogen (N) or phosphorus (P) is introduced as an impurity.

As shown in FIG. 16, the first drift region 12 a and the second drift region are formed such that the concentration of the n-type impurity included in the second drift region 12 b is higher than the concentration of the n-type impurity included in the first drift region 12 a. Region 12b is formed by epitaxial growth. Preferably, the value obtained by dividing the number of silicon atoms in the step of forming the second drift region by the number of carbon atoms is greater than the value obtained by dividing the number of silicon atoms in the step of forming the first drift region by the number of carbon atoms. Is also big. That is, the Si / C ratio of the atmospheric gas in the step of forming the second drift region is larger than the Si / C ratio of the atmospheric gas in the step of forming the first drift region.

As shown in FIG. 16, in the direction perpendicular to the second major surface 10b, the concentration C1 of the n-type impurity included in the first drift region 12a and the concentration C2 of the n-type impurity included in the second drift region 12b are Is almost constant. Preferably, the value obtained by dividing the concentration C2 of the n-type impurity in the second drift region 12b by the concentration C1 of the n-type impurity in the first drift region 12a is 5 or more and 10 or less.

Next, an ion implantation step (S13: FIG. 14) is performed. Specifically, a p-type impurity such as aluminum is ion-implanted into second drift region 12b and first drift region 12a. As shown in FIG. 17, the concentration of the p-type impurity at the position a1 at the boundary between the first drift region 12a and the second drift region 12b is lower than the concentration C1 of the n-type impurity in the first drift region 12a, and The maximum value C8 (maximum value C8) of the concentration of the p-type impurity in the second drift region 12b (region between the position 0 and the position a1) is higher than the concentration C2 of the n-type impurity of the second drift region 12b. As described above, the p-type impurity is introduced into both the first drift region 12a and the second drift region 12b. Thereby, body region 13 in contact with second drift region 12b is formed (see FIG. 18). Body region 13 constitutes first main surface 10a. In FIG. 17, the profile indicated by the alternate long and short dash line is the same as the profile shown in FIG.

FIG. 19 is a diagram schematically showing a profile of | N _d −N _a | in the direction along the arrow X in FIG. The position 0 is the position of the portion of the first major surface 10a configured by the body region 13. Position e is the position of boundary surface 11 a between silicon carbide single crystal substrate 11 and silicon carbide epitaxial layer 24. A region from position 0 to position a2 is a body region 13 having a p-type. A region from the position a2 to the position a1 is a second drift region 12b having an n-type. The region from the position a1 to the position e is a first drift region 12a having an n type.

Profile showing the relationship between the position x and the absolute value y of the difference between the concentration of the n-type impurity and the concentration of the p-type impurity in the region constituted by the body region 13, the second drift region 12b, and the first drift region 12a Has a first minimum value C3 and a second minimum value C4 located closer to the first main surface 10a than the first minimum value C3. A position a1 at which the absolute value y of the difference between the n-type impurity concentration and the p-type impurity concentration indicates the first minimum value C3 is a boundary between the first drift region 12a and the second drift region 12b. A position a2 at which the absolute value y of the difference between the n-type impurity concentration and the p-type impurity concentration indicates the second minimum value C4 is a boundary between the body region 13 and the second drift region 12b. The maximum value C5 of the absolute value y of the difference between the n-type impurity concentration and the p-type impurity concentration in the body region 13 is the absolute difference between the n-type impurity concentration and the p-type impurity concentration in the second drift region 12b. It becomes larger than the maximum value C2 of the value y. The maximum value C2 of the absolute value y of the difference between the n-type impurity concentration and the p-type impurity concentration in the second drift region 12b is the difference between the n-type impurity concentration and the p-type impurity concentration in the first drift region 12a. Is greater than the maximum value C1 of the absolute value y. The value C9 of the absolute value y of the difference between the n-type impurity concentration and the p-type impurity concentration at position 0 is the maximum of the absolute value y of the difference between the n-type impurity concentration and the p-type impurity concentration in the body region 13. It may be smaller than the value C5.

Next, an n-type impurity such as phosphorus is ion-implanted into the body region 13. As shown in FIG. 20, the p-type impurity concentration P10 in the body region 13 is higher than the maximum p-type impurity concentration C5 in the body region 13 by p. Type impurities are introduced. Thereby, the source region 14 in contact with the body region 13 is formed (see FIG. 21). The source region 14 constitutes the first major surface 10a. In FIG. 20, the profile indicated by the alternate long and short dash line is the same as the profile shown in FIG.

Next, a contact region 18 is formed by ion implantation of a p-type impurity such as aluminum into the source region 14. The contact region 18 is formed so as to penetrate the source region 14 and contact the body region 13. Next, activation annealing is performed to activate the impurities ion-implanted into silicon carbide substrate 10. The temperature of activation annealing is preferably 1500 ° C. or higher and 1900 ° C. or lower, for example, about 1700 ° C. The activation annealing time is, for example, about 30 minutes. The atmosphere of activation annealing is preferably an inert gas atmosphere, for example, an Ar atmosphere.

Thus, a silicon carbide substrate having the first main surface 10a and the second main surface 10b opposite to the first main surface 10a is prepared. Silicon carbide substrate 10 is provided on drift region 12 having n type, body region 13 having p type different from n type, and provided on body region 13 so as to be separated from drift region 12. And the first main surface 10a and the source region 14 having n-type. The drift region 12 has a first drift region 12 a and a second drift region 12 b sandwiched between the first drift region 12 a and the body region 13. The maximum value of the n-type impurity concentration in the second drift region 12b is larger than the maximum value of the n-type impurity concentration in the first drift region 12a. The first main surface 10a may be on the carbon surface side, and the second main surface 10b may be on the silicon surface side. The first major surface 10a is, for example, a surface that is off 2 ° or more and 8 ° or less from the (000-1) plane or the (000-1) plane.

Next, a step of forming a trench (S20: FIG. 13) is performed. For example, mask layer 3 having an opening at a position where trench TR (FIG. 1) is formed is formed on first main surface 10 a configured from source region 14 and contact region 18. Using the mask layer 3, the source region 14, the body region 13, and a part of the drift region 12 are removed by etching. As an etching method, for example, reactive ion etching, particularly inductively coupled plasma reactive ion etching can be used. Specifically, for example, inductively coupled plasma reactive ion etching using SF ₆ or a mixed gas of SF ₆ and O ₂ as a reaction gas can be used. By etching, in a region where trench TR (FIG. 1) is to be formed, a side portion substantially perpendicular to first main surface 10a and a side portion are provided continuously and substantially parallel to first main surface 10a. A recess having a bottom is formed.

Next, thermal etching is performed in the recess. The thermal etching can be performed, for example, by heating in an atmosphere containing a reactive gas having at least one kind of halogen atom in a state where the mask layer 3 is formed on the first main surface 10a. The at least one or more types of halogen atom includes at least one of a chlorine (Cl) atom and a fluorine (F) atom. The atmosphere includes, for example, Cl ₂ , BCL ₃ , SF ₆ , or CF ₄ . For example, thermal etching is performed using a mixed gas of chlorine gas and oxygen gas as a reaction gas and a heat treatment temperature of, for example, 700 ° C. or more and 1000 ° C. or less. Note that the reaction gas may contain a carrier gas in addition to the above-described chlorine gas and oxygen gas. As the carrier gas, for example, nitrogen (N ₂ ) gas, argon gas, helium gas or the like can be used. During the thermal etching, the mask layer is not substantially etched during the etching of SiC because the selectivity to SiC is very large.

As shown in FIG. 22, trench TR is formed in first main surface 10a of silicon carbide substrate 10 by the thermal etching. Trench TR includes a side SW passing through second drift region 12b, body region 13, and source region 14 and reaching first drift region 12a, and bottom BT provided continuously with side SW. It is prescribed by. The angle θ formed by the bottom portion BT and the side portion SW is, for example, not less than 110 ° and not more than 130 °. Preferably, the side portion SW includes the special surface described above.

Next, a step of forming a gate insulating film (S30: FIG. 13) is performed. The step of forming a gate insulating film (S30: FIG. 23) includes, for example, a step of forming a silicon layer (S31: FIG. 23), a step of forming a mask layer (S32: FIG. 23), and a part of the silicon layer. The process mainly includes a step of removing (S33: FIG. 23), a step of removing the mask layer (S34: FIG. 23), and a step of thermally oxidizing the silicon carbide substrate (S35: FIG. 23).

In the step of forming the silicon layer (S31: FIG. 23), the silicon layer 4 in contact with the side SW and bottom BT of the trench TR and in contact with the first main surface 10a is formed (see FIG. 24). Silicon layer 4 does not completely fill trench TR. The thickness of the silicon layer 4 is smaller than the depth H1 (see FIG. 1) of the trench TR. Silicon layer 4 is in contact with source region 14 and contact region 18 on first main surface 10a. Silicon layer 4 is in contact with source region 14, body region 13, second drift region 12b, and first drift region 12a in side SW. Silicon layer 4 is in contact with first drift region 12a at bottom BT.

Next, a step of forming a mask layer (S32: FIG. 23) is performed. As shown in FIG. 25, silicon layer 4 has a first silicon layer portion 4a facing side portion SW and a second silicon layer portion 4b facing bottom portion BT. Mask layer 5 is formed on second silicon layer portion 4b of silicon layer 4 facing bottom portion BT. Mask layer 5 is, for example, a resist. Mask layer 5 may cover a part of first silicon layer portion 4a. At least a part of the first silicon layer portion 4 a is exposed from the mask layer 5.

Next, a step of removing a part of the silicon layer (S33: FIG. 23) is performed. Using mask layer 5, silicon layer 4 is removed by etching, for example. Thereby, a part of silicon layer 4 is removed. Specifically, the first silicon layer portion 4a is removed from the side portion SW while the second silicon layer portion 4b is left on the bottom portion BT. The portion of silicon layer 4 on first main surface 10a is also removed.

Next, a step of removing the mask layer (S34: FIG. 23) is performed. For example, the mask layer 5 is removed from the second silicon layer portion 4b by any method such as dry etching or wet etching. Second silicon layer portion 4b is left in contact with first drift region 12a at bottom portion BT (see FIG. 26).

Next, a step of thermally oxidizing the silicon carbide substrate (S35: FIG. 23) is performed. After the step of removing mask layer 5, silicon carbide substrate 10 is thermally oxidized with second silicon layer portion 4b remaining on bottom portion BT. The second silicon layer portion 4b becomes silicon dioxide by thermal oxidation. For example, silicon carbide substrate 10 is heated at a temperature of, for example, 1300 ° C. or higher and 1400 ° C. or lower in an atmosphere containing oxygen. As a result, the gate insulating film 15 is formed in contact with the first drift region 12a at the bottom portion BT and in contact with the second drift region 12b, the body region 13 and the source region 14 at the side portion SW. Gate insulating film 15 has third main surface 15b1 in contact with bottom portion BT, and fourth main surface 15b2 opposite to third main surface 15b1.

The gate insulating film 15 includes a first portion 15a in contact with the body region 13 in the side portion SW and a second portion 15b in contact with the first drift region 12a in the bottom portion BT. The thickness of the second portion 15b in the direction perpendicular to the bottom portion BT may be larger than the thickness of the first portion 15a in the direction perpendicular to the side portion SW. A value obtained by dividing the thickness of the second portion 15b by the thickness of the first portion 15a is, for example, 1.5 or more and 8 or less.

Referring to FIG. 3 again, in the region constituted by body region 13, second drift region 12b, and first drift region 12a, the position in the direction perpendicular to second main surface 10b is x, and n-type Assuming that the absolute value of the difference between the impurity concentration and the p-type impurity concentration is y, the profile indicating the relationship between x and y is the first main surface than the first minimum value C3 and the first minimum value C3. And a second minimum value C4 located on the 10a side. In a direction perpendicular to the second main surface 10b, the position a1 indicating the first minimum value C3 is between the position b1 of the third main surface 15b1 and the position b2 of the fourth main surface 15b2. In a direction perpendicular to the second main surface 10b, the position a2 indicating the second minimum value C4 is between the position 0 of the first main surface 10a and the position b2 of the fourth main surface 15b2.

After thermally oxidizing silicon carbide substrate 10, heat treatment (NO annealing) may be performed on silicon carbide substrate 10 in a nitrogen monoxide (NO) gas atmosphere. In NO annealing, silicon carbide substrate 10 is held for about 1 hour under conditions of, for example, 1100 ° C. or higher and 1300 ° C. or lower. As a result, nitrogen atoms are introduced into the interface region between the gate insulating film 15 and the body region 13. As a result, the formation of interface states in the interface region is suppressed, so that channel mobility can be improved. As long as nitrogen atoms can be introduced, a gas other than NO gas (for example, N ₂ O) may be used as the atmospheric gas. Ar annealing using argon (Ar) as an atmospheric gas may be further performed after the NO annealing. The heating temperature for Ar annealing is, for example, equal to or higher than the heating temperature for NO annealing. The Ar annealing time is, for example, about 1 hour. As a result, the formation of interface states in the interface region between the gate insulating film 15 and the body region 13 is further suppressed.

Next, a step of forming a gate electrode is performed. For example, gate electrode 27 in contact with gate insulating film 15 is formed inside trench TR. Gate electrode 27 is arranged inside trench TR and is formed on gate insulating film 15 so as to face each of side portion SW and bottom portion BT of trench TR. The gate electrode 27 is formed, for example, by LPCVD (Low Pressure Chemical Vapor Deposition) method.

Next, a step of forming an interlayer insulating film is formed. For example, the interlayer insulating film 22 is formed so as to cover the gate electrode 27 and to be in contact with the gate insulating film 15. Preferably, the interlayer insulating film 22 is formed by a deposition method, more preferably a chemical vapor deposition method. Interlayer insulating film 22 is made of, for example, a material containing silicon dioxide. Next, part of interlayer insulating film 22 and gate insulating film 15 is etched so that an opening is formed on source region 14 and contact region 18. As a result, the contact region 18 and the source region 14 are exposed from the gate insulating film 15 (see FIG. 28).

Next, a step of forming a source electrode is performed. Next, source electrode 16 in contact with source region 14 and contact region 18 is formed on first main surface 10a. The source electrode 16 is formed by, for example, a sputtering method. The source electrode 16 is made of a material containing, for example, Ti, Al, and Si. Next, alloying annealing is performed. Specifically, the source electrode 16 in contact with the source region 14 and the contact region 18 is held for about 5 minutes at a temperature of 900 ° C. or higher and 1100 ° C. or lower, for example. Thereby, at least a part of source electrode 16 reacts with silicon included in silicon carbide substrate 10 to be silicided. As a result, the source electrode 16 that is in ohmic contact with the source region 14 is formed. Preferably, the source electrode 16 is in ohmic contact with the contact region 18.

Next, a source wiring 19 electrically connected to the source electrode 16 is formed. The source wiring 19 is formed on the source electrode 16 and the interlayer insulating film 22. Next, drain electrode 20 is formed in contact with second main surface 10b of silicon carbide substrate 10. Thus, MOSFET 1 (FIG. 1) according to the present embodiment is completed.

Next, a modification of the step of forming the gate insulating film will be described.
As shown in FIG. 29, after trench TR is formed in first main surface 10a, silicon layer 4 may be formed on first main surface 10a so as to completely fill trench TR. The thickness of the portion of the silicon layer 4 on the bottom BT is larger than the depth H1 (see FIG. 1) of the trench TR. Silicon layer 4 is in contact with source region 14 and contact region 18 on first main surface 10a. Silicon layer 4 is in contact with source region 14, body region 13, second drift region 12b, and first drift region 12a in side SW. Silicon layer 4 is in contact with first drift region 12a at bottom BT.

Next, most of the silicon layer 4 is removed by performing, for example, dry etching on the entire surface of the first main surface 10a. Specifically, part of silicon layer 4 is removed from side SW and first main surface 10a while part 4b of silicon layer 4 remains on bottom BT (see FIG. 30). Next, silicon carbide substrate 10 is thermally oxidized with a portion 4b of silicon layer 4 left on bottom portion BT. Thereby, the gate insulating film 15 may be formed in contact with the first drift region 12a at the bottom BT and in contact with the second drift region 12b, the body region 13, and the source region 14 at the side SW (FIG. 27). reference).

In the above embodiment, the silicon carbide semiconductor device is described as being a MOSFET, but the silicon carbide semiconductor device is not limited to a MOSFET. The silicon carbide semiconductor device may be, for example, an IGBT (Insulated Gate Bipolar Transistor). In the above embodiment, the n-type is the first conductivity type and the p-type is the second conductivity type. However, the p-type may be the first conductivity type and the n-type may be the second conductivity type. .

Next, functions and effects of the MOSFET according to the embodiment will be described.
According to the MOSFET 1 according to the embodiment, the position a2 indicating the second minimum value C4 in the direction perpendicular to the second main surface 10b is the position 0 of the first main surface 10a and the position of the fourth main surface 15b2. It is between b2. The position a2 indicating the second minimum value C4 corresponds to the position a2 at the bottom of the body region 13. That is, the position a2 at the bottom of the body region 13 is between the position 0 of the first main surface 10a and the position b2 of the fourth main surface 15b2. Therefore, it is possible to suppress an increase in the thickness of the gate insulating film 15 on the channel region in the body region 13. Therefore, the on-resistance of MOSFET 1 can be reduced as compared with the case where the position a2 at the bottom of the body region 13 is between the position b1 of the third main surface 15b1 and the position b2 of the fourth main surface 15b2. .

According to MOSFET 1 according to the embodiment, the position a1 indicating the first minimum value C3 in the direction perpendicular to the second main surface 10b is the position b1 of the third main surface 15b1 and the position of the fourth main surface 15b2. It is between position b2. Therefore, the concentration of the n-type impurity in the portion of the first drift region 12a in the vicinity of the bottom portion BT of the trench TR can be reduced. As a result, since the extension width of the depletion layer from the electric field relaxation region 17 can be increased, it is possible to suppress the concentration of the electric field at the corners of the trench TR.

Furthermore, according to the MOSFET 1 according to the embodiment, the gate insulating film 15 includes the first portion 15a in contact with the second impurity region 13 in the side portion SW and the second portion 15b in contact with the first drift region 12a in the bottom portion BT. Contains. The thickness _{t b} of the second portion 15b in a direction perpendicular to the bottom portion BT is greater than the thickness _{t s} of the first portion 15a in a direction perpendicular to the sides SW. When the thickness _{t s} of the first portion 15a is small, because the channel is easily reversed, it is possible to reduce the on resistance of the MOSFET 1. When the thickness t _b of the second portion 15b is large, it is possible to gate insulating film 15 on the bottom portion BT is prevented from being destroyed.

According to MOSFET1 according to still embodiment, the values of the thickness _{t b} divided by the thickness _{t s} of the first portion 15a of the second portion 15b is 1.5 or more and 8 or less. With divided by the value of 1.5 or more in the thickness t _s of the thickness t _b of the second portion 15b first portion 15a, it is possible to relax the electric field applied to the gate insulating film of the trench bottom. By value than 8 obtained by dividing the thickness t _b of the second portion 15b the thickness t _s of the first portion 15a, to be kept low on-resistance without interfering the second portion 15b to the body region 13 it can.

Furthermore, according to MOSFET 1 according to the embodiment, distance H1 between first main surface 10a and bottom portion BT in the direction perpendicular to second main surface 10b is not less than 1 μm and not more than 1.5 μm. By setting the distance H1 to be 1 μm or more, an increase in on-resistance can be suppressed because the trench bottom is located outside the body region 13. By setting the distance H1 to 1.5 μm or less, the electric field applied to the gate insulating film at the bottom corner of the trench can be relaxed.

Furthermore, according to MOSFET 1 according to the embodiment, thickness H2 of body region 13 in the direction perpendicular to second main surface 10b may be not less than 0.4 μm and not more than 0.8 μm. By setting the thickness H2 to 0.4 μm or more, the gate threshold voltage can be increased and the drain breakdown voltage can be maintained high. By setting the thickness H2 to 0.8 μm or less, the on-resistance can be kept low without causing the second portion 15b to interfere with the body region 13.

Furthermore, according to MOSFET 1 according to the embodiment, the value obtained by dividing the maximum value of the n-type impurity concentration of second drift region 12b by the maximum value of the concentration of n-type impurity of first drift region 12a is 5 or more and 10 or less. It may be. By dividing the maximum value of the first conductivity type impurity concentration of the second drift region 12b by the maximum value of the first conductivity type impurity concentration of the first drift region 12a to 5 or more, By compensating for the second conductivity type impurity existing over one drift region, the effective channel length can be controlled and the on-resistance can be lowered. By dividing the maximum value of the first conductivity type impurity concentration of the second drift region 12b by the maximum value of the first conductivity type impurity concentration of the first drift region 12a to 10 or less, The effective concentration of the two conductivity type impurities can be maintained, and the electric field applied to the gate insulating film in contact with the bottom corner portion of the trench can be reduced. As a result, the drain breakdown voltage can be maintained.

Furthermore, according to MOSFET 1 according to the embodiment, the value obtained by dividing the maximum value of the p-type impurity concentration in body region 13 by the maximum value of the n-type impurity concentration in second drift region 12b is 10 or more and 100 or less. May be. By dividing the maximum value of the p-type impurity concentration in the body region 13 by the maximum value of the n-type impurity concentration in the second drift region 12b to 10 or more, the gate threshold voltage is increased and the drain breakdown voltage is increased. Can be maintained. The value obtained by dividing the maximum value of the concentration of the p-type impurity in the body region 13 by the maximum value of the concentration of the n-type impurity in the second drift region 12b is set to 100 or less, thereby existing from the body region 13 to the first drift region. By compensating the p-type impurity, the effective channel length can be controlled and the on-resistance can be lowered.

Furthermore, according to MOSFET 1 according to the embodiment, side SW may include a plane S1 having a plane orientation {0-33-8}. Thereby, the channel resistance in the side part SW can be reduced.

According to the method of manufacturing MOSFET 1 according to the embodiment, body region 13 is subjected to ion implantation of p-type impurities into second drift region 12b having an n-type impurity concentration higher than that of first drift region 12a. It is formed by. Therefore, channeling of p-type impurities can be suppressed. As a result, since the thickness H2 of the body region 13 can be reduced, the channel length can be shortened. Therefore, the on-resistance of MOSFET 1 can be reduced.

Further, according to the method for manufacturing MOSFET 1 according to the embodiment, the position a1 indicating the first minimum value C3 in the direction perpendicular to the second main surface 10b is the same as the position b1 of the third main surface 15b1 and the fourth main surface 15b1. Between the position b2 of the surface 15b2. Therefore, the concentration of the n-type impurity in the portion of the first drift region 12a in the vicinity of the bottom portion BT of the trench TR can be reduced. As a result, since the extension width of the depletion layer from the electric field relaxation region 17 can be increased, it is possible to suppress the concentration of the electric field at the corners of the trench TR.

Furthermore, according to the method for manufacturing MOSFET 1 according to the embodiment, the step of forming gate insulating film 15 includes the step of forming silicon layer 4 in contact with side SW and bottom BT, and the step of forming silicon layer 4 facing bottom BT. After the step of forming mask layer 5 on the portion, the step of removing part of silicon layer 4 using mask layer 5, the step of removing mask layer 5, the step of removing mask layer 5, the bottom BT And a step of thermally oxidizing silicon carbide substrate 10 with a portion of silicon layer 4 remaining thereon. Thereby, the gate insulating film 15 in which the thickness of the portion of the gate insulating film 15 on the bottom portion BT is larger than the thickness of the gate insulating film 15 on the side portion SW can be manufactured by a simple method.

Furthermore, according to the method for manufacturing MOSFET 1 according to the embodiment, the step of forming trench TR is performed by thermal etching. Thereby, the side part SW of trench TR can be effectively made into a special surface. As a result, the channel resistance in the side SW can be reduced.

Furthermore, according to the method for manufacturing MOSFET 1 according to the embodiment, the step of forming first drift region 12a and the step of forming second drift region 12b may be performed using a gas containing carbon and silicon. The value obtained by dividing the number of silicon atoms in the step of forming the second drift region 12b by the number of carbon atoms is greater than the value obtained by dividing the number of silicon atoms in the step of forming the first drift region 12a by the number of carbon atoms. It can be large. Carbon is easier to incorporate nitrogen than silicon. Therefore, in the step of forming the second drift region 12b, nitrogen as an n-type impurity can be easily taken up. As a result, the n-type impurity concentration in the second drift region 12b can be effectively made higher than the n-type impurity concentration in the first drift region 12a.

Furthermore, according to the method for manufacturing MOSFET 1 according to the embodiment, first main surface 10a is on the carbon surface side, and second main surface 10b is on the silicon surface side. The carbon surface is easier to capture nitrogen than the silicon surface. Therefore, the concentration of the n-type impurity in the second drift region 12b formed on the first main surface 10a side can be effectively made higher than the concentration of the n-type impurity in the first drift region 12a. Further, the side portion SW of the trench TR can be a special surface. As a result, the channel resistance in the side SW can be reduced.

The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 silicon carbide semiconductor device (MOSFET), 3, 5 mask layer, 4 silicon layer, 4a first silicon layer part, 4b second silicon layer part (part), 10 silicon carbide substrate, 10a first main surface, 10b first 2 main surface, 11 silicon carbide single crystal substrate, 11a boundary surface, 12 first impurity region (drift region), 12a first drift region, 12b second drift region, 13 second impurity region (body region), 14 third Impurity region (source region), 15 gate insulating film, 15a first part, 15b1, third main surface, 15b2, fourth main surface, 15b second part, 16 source electrode, 17 electric field relaxation region, 18 contact region, 19 source wiring , 20 drain electrode, 22 interlayer insulating film, 24 silicon carbide epitaxial layer, 27 gate electrode, BT bottom, CD channel Direction, H1 distance (depth), H2, tb, ts thickness, S1, S2, S3 surface, SQ, SR complex surface, SW side, TR trench.

Claims

A silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface;
The silicon carbide substrate includes a first impurity region having a first conductivity type;
A second impurity region provided on the first impurity region and having a second conductivity type different from the first conductivity type;
A third impurity region provided on the second impurity region so as to be separated from the first impurity region, constituting the first main surface, and having the first conductivity type;
The first impurity region includes a first drift region, and a second drift region sandwiched between the first drift region and the second impurity region,
The maximum concentration of the first conductivity type impurity in the second drift region is greater than the maximum concentration of the first conductivity type impurity in the first drift region,
The first main surface includes a side portion that passes through the second drift region, the second impurity region, and the third impurity region and reaches the first drift region, and is continuous with the side portion. And a trench defined by a bottom portion provided, and further,
A gate insulating film in contact with the first drift region at the bottom and in contact with the second drift region, the second impurity region, and the third impurity region at the side;
The gate insulating film has a third main surface in contact with the bottom, and a fourth main surface opposite to the third main surface,
In the region constituted by the second impurity region, the second drift region, and the first drift region, the position in the direction perpendicular to the second main surface is x, and the concentration of the first conductivity type impurity When the absolute value of the difference between the first conductivity type impurity concentration and the second conductivity type impurity is y, the profile indicating the relationship between x and y is the first minimum value and the first main surface side of the first minimum value. A second local minimum located at
In a direction perpendicular to the second main surface, the position showing the first minimum value is between the position of the third main surface and the position of the fourth main surface,
The silicon carbide semiconductor device, wherein the position showing the second minimum value is between the position of the first main surface and the position of the fourth main surface in a direction perpendicular to the second main surface.
The gate insulating film includes a first portion in contact with the second impurity region at the side portion, and a second portion in contact with the first drift region at the bottom portion,
2. The silicon carbide semiconductor device according to claim 1, wherein a thickness of said second portion in a direction perpendicular to said bottom portion is greater than a thickness of said first portion in a direction perpendicular to said side portion.
The silicon carbide semiconductor device according to claim 2, wherein a value obtained by dividing the thickness of the second portion by the thickness of the first portion is 1.5 or more and 8 or less.
The distance between the first main surface and the bottom in a direction perpendicular to the second main surface is 1 μm or more and 1.5 μm or less. Silicon carbide semiconductor device.
The silicon carbide semiconductor according to any one of claims 1 to 4, wherein a thickness of the second impurity region in a direction perpendicular to the second main surface is not less than 0.4 µm and not more than 0.8 µm. apparatus.
The value obtained by dividing the maximum value of the concentration of the first conductivity type impurity in the second drift region by the maximum value of the concentration of the first conductivity type impurity in the first drift region is 5 or more and 10 or less. The silicon carbide semiconductor device according to any one of claims 1 to 5.
The value obtained by dividing the maximum value of the second conductivity type impurity concentration in the second impurity region by the maximum value of the first conductivity type impurity concentration in the second drift region is 10 or more and 100 or less. The silicon carbide semiconductor device according to any one of claims 1 to 6.
The silicon carbide semiconductor device according to any one of claims 1 to 7, wherein the side portion includes a plane having a plane orientation {0-33-8}.
Providing a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface;
The silicon carbide substrate includes a first impurity region having a first conductivity type;
A second impurity region provided on the first impurity region and having a second conductivity type different from the first conductivity type;
A third impurity region provided on the second impurity region so as to be separated from the first impurity region, constituting the first main surface, and having the first conductivity type;
The first impurity region includes a first drift region, and a second drift region sandwiched between the first drift region and the second impurity region,
The maximum concentration of the first conductivity type impurity in the second drift region is greater than the maximum concentration of the first conductivity type impurity in the first drift region,
The first drift region and the second drift region are formed by epitaxial growth,
The second impurity region is formed by performing ion implantation on the second drift region, and
In the first main surface, a side portion that penetrates the second drift region, the second impurity region, and the third impurity region and reaches the first drift region, and the side portion is continuous. Forming a trench defined by the provided bottom;
Forming a gate insulating film in contact with the first drift region at the bottom and in contact with the second drift region, the second impurity region, and the third impurity region at the side;
The gate insulating film has a third main surface in contact with the bottom, and a fourth main surface opposite to the third main surface,
In the region constituted by the second impurity region, the second drift region, and the first drift region, the position in the direction perpendicular to the second main surface is x, and the concentration of the first conductivity type impurity When the absolute value of the difference between the first conductivity type impurity concentration and the second conductivity type impurity is y, the profile indicating the relationship between x and y is the first minimum value and the first main surface side of the first minimum value. A second local minimum located at
In a direction perpendicular to the second main surface, the position showing the first minimum value is between the position of the third main surface and the position of the fourth main surface,
Manufacturing a silicon carbide semiconductor device, wherein the position indicating the second minimum value is between the position of the first main surface and the position of the fourth main surface in a direction perpendicular to the second main surface Method.
The step of forming the gate insulating film includes:
Forming a silicon layer in contact with the side and the bottom;
Forming a mask layer on the portion of the silicon layer facing the bottom;
Removing a portion of the silicon layer using the mask layer;
Removing the mask layer;
The silicon carbide semiconductor device according to claim 9, further comprising a step of thermally oxidizing the silicon carbide substrate in a state where a part of the silicon layer is left on the bottom after the step of removing the mask layer. Production method.
The method for manufacturing a silicon carbide semiconductor device according to claim 9 or 10, wherein the step of forming the trench is performed by thermal etching.
The step of forming the first drift region and the step of forming the second drift region are performed using a gas containing carbon and silicon,
The value obtained by dividing the number of silicon atoms in the step of forming the second drift region by the number of carbon atoms is obtained by dividing the number of silicon atoms in the step of forming the first drift region by the number of carbon atoms. 12. The method for manufacturing a silicon carbide semiconductor device according to claim 9, wherein the method is larger than the measured value.
13. The method for manufacturing a silicon carbide semiconductor device according to claim 9, wherein the first main surface is a carbon surface side, and the second main surface is a silicon surface side.