WO2016194090A1

WO2016194090A1 - Electronic device

Info

Publication number: WO2016194090A1
Application number: PCT/JP2015/065683
Authority: WO
Inventors: 正義柳生; 照典横井; 諭村岡
Original assignee: 株式会社日立製作所
Priority date: 2015-05-29
Filing date: 2015-05-29
Publication date: 2016-12-08

Abstract

The present invention provides a power supply technology with low power consumption to supply an appropriate voltage to a plurality of semiconductor chips from a single power supply circuit. This electronic device provided with a plurality of circuit blocks and a power supply circuit that supplies power to the plurality of circuit blocks is characterized by comprising: a voltage determining unit that determines the power voltages of the plurality of circuit blocks; a detection result outputting unit that combines the determination results on the respective power voltages by the voltage determining unit, to output a detection result; an output setting unit that determines the output voltage by the power supply circuit on the basis of the output by the detection result outputting unit; and an individual voltage adjusting unit that adjusts the power voltages in the respective circuit blocks, wherein the output voltage by the power supply circuit is adjusted by combining the determination results on the power voltages of the plurality of circuit blocks, and the power voltages in the circuit blocks are adjusted respectively by the individual voltage adjusting unit.

Description

Electronics

The present invention relates to an electronic apparatus including a plurality of circuit blocks and a power supply circuit that supplies power to the plurality of circuit blocks.

In an electronic device using a plurality of semiconductor chips, a power supply voltage is supplied to all semiconductor chips having the same power supply voltage, for example, as described in Japanese Patent Application Laid-Open No. 2012-8869 (Patent Document 1). Generally, a power feeding circuit and a plurality of semiconductor chips are connected. In this publication, “a voltage detection unit that is connected to a starting end portion of a power supply line that connects the power supply adapter and the circuit element unit group and outputs a power information signal based on a power supply voltage supplied from the power supply adapter; A power control unit that controls the power consumption of the circuit element unit group stepwise according to the power information signal from the voltage detection unit, and reduces the power consumption as the power supply voltage is lower. Information processing apparatus characterized by the above. "

JP 2012-8869 A

In Patent Document 1, it is not assumed that the power supply voltage supplied to each semiconductor chip deviates from each power supply voltage specification range, and a chip in which the supply voltage exceeds the upper limit value and a chip below the lower limit value are mixed. . Such a state is caused by the difference in impedance of the power supply line from the power supply circuit to each semiconductor chip and the temporal change in power consumption of the plurality of semiconductor chips, and the power actually supplied to each semiconductor chip. This occurs because the voltage varies spatially and temporally.

Therefore, an object of the present invention is to provide a low power consumption power supply technology that supplies an appropriate voltage to each of a plurality of semiconductor chips from one power supply circuit.

In order to solve the above problems, one of the power supply techniques of the present invention is based on the power supply voltage information of each of a plurality of semiconductor chips, and the voltage of one power supply circuit arranged in common, It controls both voltages of each semiconductor chip.

An example of a representative electronic device of the present invention is an electronic device that includes a plurality of circuit blocks and a power supply circuit that supplies power to the plurality of circuit blocks, and each of the plurality of circuit blocks. Based on the output of the detection result output unit, the detection result output unit that outputs the detection result by combining the respective power supply voltage determination results of the voltage determination unit, and the output of the detection result output unit An output setting unit that determines an output voltage of the supply circuit; and an individual voltage adjustment unit that adjusts a power supply voltage in each of the circuit blocks. The determination results of the power supply voltages of the plurality of circuit blocks are combined. The output voltage of the power supply circuit is adjusted, and the power supply voltage of each circuit block is adjusted by the individual voltage adjustment unit.

According to the present invention, the power supply voltage supplied to each of the plurality of semiconductor chips can be stably fed by one power supply circuit without deviating from the power supply voltage specification range.

Issues, configurations, and effects other than those described above will be clarified by the following description of embodiments.

It is a block diagram which shows the power supply technique by the 1st Example of this invention. It is a figure which shows the structure of the semiconductor chip in FIG. It is a flowchart which shows the process sequence of VDD setting circuit in FIG. It is a flowchart which shows the process sequence of the voltage adjustment circuit in FIG. It is a block diagram which shows the power supply technique by the 2nd Example of this invention. It is a figure which shows the 1st structure of the power supply circuit in FIG. It is a figure which shows the 2nd structure of the power supply circuit in FIG. It is a figure which shows the function structure of the microcomputer in FIG.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a power supply technology according to the first embodiment of the present invention. A power supply voltage VDD is supplied from a single power supply circuit 12 mounted on the printed circuit board 11 to a plurality of

semiconductor chips

13a, 13b, and 13c. Signals are transmitted from the signal output terminals Ho and Lo of the semiconductor chip 13a to the signal input terminals Hin and Lin of the semiconductor chip 13b. Similarly, a signal is transmitted from the semiconductor chip 13b to the semiconductor chip 13c. A signal is transmitted from the signal output terminal VRo of the semiconductor chip 13 c to the signal input terminal VRin of the power supply circuit 12.

The signal output terminal VRo of the semiconductor chip 13c outputs information specifying the output voltage value VDD of the power supply circuit 12. In the power supply circuit 12, the output voltage VDD is set by a signal from the signal input terminal VRin.

In FIG. 1, information transmitted via signal terminals Hin, Ho, Lin, Lo is sequentially sent from the semiconductor chip 13a to 13b, 13c, and is processed by the VDD setting circuit 29 in the last semiconductor chip 13c. . Therefore, it is possible to control the output voltage of the power supply circuit 12 by comprehensively determining the power supply voltage detection result information of all the semiconductor chips.

Next, functions of the signal terminals Hin, Lin, Ho, Lo of the

semiconductor chips

13a, 13b, 13c will be described with reference to FIG.

FIG. 2 is a diagram showing the configuration of the

semiconductor chips

13a, 13b, and 13c according to the embodiment of FIG. A power supply voltage VDD is applied to the semiconductor chip 13 from the outside of the chip. The applied power supply voltage VDD is converted to the power supply voltage VDDi by the voltage adjustment circuit 20 and supplied to the logic circuit 22 in the semiconductor chip.

The voltage determination circuit 23 compares the upper limit reference voltage VrH determined based on the upper limit value of the specified power supply voltage specification range with the power supply voltage VDDi. When VDDi is higher than the upper limit reference voltage VrH, the voltage determination circuit 23 applies a logic to the terminal 25. Outputs “H” signal. In other cases, a logic “L” signal is output to the terminal 25. The signal at the terminal 25 is input to the OR circuit 27 together with the power supply voltage determination result information of another semiconductor chip transmitted from outside the chip. The OR circuit 27 generates a logic “H” when either the power supply voltage VDDi of its own semiconductor chip or the power supply voltage of another semiconductor chip transmitted through the terminal Hin is high outside the power supply voltage specification range. "The signal is transmitted to the signal output terminal Ho.

・ A pull-down resistor RHin is added to the terminal Hin. Thereby, even if the signal input terminal Hin of the semiconductor chip 13a in FIG. 1 is in an open state, the OR circuit 27 in the semiconductor chip 13a operates correctly.

The voltage determination circuit 24 compares the lower limit reference voltage VrL determined based on the lower limit value of the specified power supply voltage specification range with the power supply voltage VDDi, and if VDDi is lower than the lower limit reference voltage VrL, the voltage is determined at the terminal 26. The “H” signal is output. In other cases, a logic “L” signal is output to the terminal 26. The signal of the terminal 26 is input to the AND circuit 28 together with the power supply voltage determination result information of another semiconductor chip transmitted from outside the chip. The AND circuit 28 outputs a logic “H” when both the power supply voltage VDDi of its own semiconductor chip and the power supply voltage of another semiconductor chip transmitted via the terminal Lin are low outside the power supply voltage specification range. The signal is transmitted to the signal output terminal Lo.

A pull-up resistor RLin is added to the terminal Lin. Thereby, even if the signal input terminal Lin of the semiconductor chip 13a in FIG. 1 is in an open state, the AND circuit 28 in the semiconductor chip 13a operates correctly.

The voltage adjustment amount setting circuit 21 determines the voltage adjustment value of the voltage adjustment circuit 20 from the information of the

terminals

25 and 26. Details will be described with reference to FIG.

The VDD setting circuit 29 determines information to be transmitted to the signal output terminal VRo from the information of the terminal Ho and the terminal Lo. Details will be described with reference to FIG.

2, the

voltage determination circuits

23 and 24 constitute a voltage determination unit 81. The logical sum circuit 27 and the logical product circuit 28 constitute a detection result output unit 82. The VDD setting circuit 29 constitutes a power supply circuit output setting unit 83. The voltage adjustment circuit 20 and the voltage adjustment amount setting circuit 21 constitute an individual voltage adjustment unit 84.

FIG. 3 is a flowchart showing a processing procedure of the VDD setting circuit 29. The operation based on the flowchart of FIG. 3 is as follows.

Step 31: Output the initial voltage setting value of the power supply circuit 12 to the terminal VRo. A specific method for encoding the voltage setting value is determined by the specification of the power supply circuit 12, but it is not the essence of the present invention, so the description is omitted.
Step 32: If the signal at the terminal Ho is logic “H”, execute Steps 33, 34 and 35, and return to Step 32. If the signal at terminal Ho is not logic “H”, step 36 is executed.
Step 33: The current setting value of VRo is changed in the direction in which the voltage decreases. For example, the amount of change may be about 1/2 to 1/10 of the difference between the upper limit reference voltage VrH and the center value of the specification of the power supply voltage VDD.
Step 34: The setting value changed in step 33 is stored as a new VRo setting value.
Step 35: A new set value is output to the terminal VRo.
Step 36: If the signal at the terminal Lo is logic “H”, execute Steps 37, 38 and 39 and return to Step 32. If the signal at the terminal Lo is not logic “H”, the process returns to step 32.
Step 37: The current setting value of VRo is changed to increase the voltage. The amount of change may be, for example, about 1/2 to 1/10 of the difference between the center value of the specification of the power supply voltage VDD and the lower limit reference voltage VrL.
Step 38: The setting value changed in step 37 is stored as a new VRo setting value.
Step 39: Output a new set value to the terminal VRo.

The output voltage VDD of the power supply circuit 12 is adjusted by executing the operations from step 32 to step 39 described above at appropriate time intervals.

In step 33 or 37, when the current set value reaches the lower limit value or the upper limit value of the range that can be specified for the signal terminal VRin of the power supply circuit 12, no further change is made.

FIG. 4 is a flowchart showing a processing procedure of the voltage adjustment amount setting circuit 21. The operation based on the flowchart of FIG. 4 is as follows.

Step 41: An initial voltage adjustment amount of the voltage adjustment circuit 20 is set. The initial voltage adjustment amount may be a differential voltage between the initial set value of the power supply voltage VDD and the center value of the specification range of the power supply voltage VDDi in the semiconductor chip 13.
Step 42: If the signal at the terminal 25 is logic “H”, execute Steps 43, 44 and 45, and return to Step 42. If the signal at terminal 25 is not logic "H", step 46 is executed.
Step 43: The current set value of the voltage adjustment circuit 20 is changed in the direction in which the voltage decreases. The amount of change may be, for example, about 1/2 to 1/10 of the difference between the upper limit reference voltage VrH and the center value of the specification of the power supply voltage VDDi.
Step 44: The setting value changed in step 43 is stored as a new setting value of the voltage adjustment circuit 20.
Step 45: The voltage drop amount of the voltage adjustment circuit 20 is adjusted.
Step 46: If the signal at the terminal 26 is logic "H", execute steps 47, 48 and 49, and return to step 42. If the signal at terminal 26 is not logic "H", the process returns to step 42.
Step 47: The current set value of the voltage adjustment circuit 20 is changed in the direction in which the voltage increases. The amount of change may be, for example, about 1/2 to 1/10 of the difference between the center value of the specification of the power supply voltage VDDi and the lower limit reference voltage VrL.
Step 48: The setting value changed in Step 47 is stored as a new setting value of the voltage adjustment circuit 20.
Step 49: The voltage drop amount of the voltage adjustment circuit 20 is adjusted.

The voltage drop amount of the voltage adjustment circuit 20 is adjusted by executing the operations from step 42 to step 49 described above at appropriate time intervals. This time interval may be the same as or different from the time interval for executing the flowchart described in FIG.

In step 43 or 47, if the current set value reaches the lower limit value or upper limit value of the range that can be specified for the voltage adjustment circuit 20 voltage effect amount, no further change is made.

As described above, the adjustment of the output voltage VDD of the power supply circuit 12 described with reference to FIGS. 1 to 4 and the adjustment of the VDDi of the plurality of

semiconductor chips

13a, 13b, and 13c are repeated, so that the power supply voltage VDDi of all the semiconductor chips. Is set within the specification range. This effect is obtained by observing the power supply voltage value VDDi of each semiconductor chip and adjusting the power supply voltage in each semiconductor chip, and the observation result of the power supply voltage VDDi of each semiconductor chip. This is obtained by providing a second voltage control loop for adjusting the output voltage of the power supply circuit 12 by controlling the first loop and the second loop at the same time. Therefore, it is possible to supply an appropriate voltage to each of a plurality of semiconductor chips from one power supply circuit, which is an object of the present invention.

According to the first embodiment, if the power supply voltage VDDi of any one of the

semiconductor chips

13a, 13b, 13c is higher than any upper reference voltage VrH, the power supply circuit 12 decreases the output voltage VDD. To do. This is because the logical sum information of the voltage detection results 25 of the

semiconductor chips

13a, 13b, and 13c is processed by the VDD setting circuit 29 of the chip 13c.

Also, the output voltage VDD of the power supply circuit 12 is increased only when all the power supply voltages VDDi of the

semiconductor chips

13a, 13b, and 13c are lower than exceeding the respective lower limit reference voltages VrL. This is because the logical product information of the voltage detection results 26 of the

semiconductor chips

13a, 13b, and 13c is processed by the VDD setting circuit 29 of the chip 13c.

Except for the above two cases, the output voltage VDD of the power supply circuit 12 is not changed. Therefore, in FIG. 1, the voltage VDD applied from the outside to the

semiconductor chips

13a, 13b, and 13c is controlled to be as low as possible. Therefore, the voltage drop amount of the voltage adjustment circuit 20 necessary for setting the power supply voltage VDDi of the logic circuit 22 in FIG. 2 within the power supply voltage specification range is reduced, and the power consumed by the voltage adjustment circuit 20 is reduced. This effect can also be obtained by simultaneously controlling the two control loops and setting the power supply voltage VDD as low as possible. For this reason, it is possible to provide a power supply technology with low power consumption, which is an object of the present invention.

FIG. 5 is a diagram showing the configuration of the second embodiment of the present invention. A power supply circuit 52 is disposed on the printed circuit board 51, and a power supply voltage is supplied to the

power supply circuits

54 a, 54 b and 54 c through the power supply wiring 55. The

power supply circuits

54a, 54b, and 54c supply power supply voltages to the

semiconductor chips

53a, 53b, and 53c, respectively. The printed circuit board 51 is equipped with a microcomputer 57 incorporating an analog-digital conversion circuit. The power supply voltages applied to the

respective semiconductor chips

53a, 53b, and 53c are monitored from the

power supply wirings

56a, 56b, and 56c in the vicinity of the

semiconductor chips

53a, 53b, and 53c, and transmitted to the microcomputer 57. The microcomputer 57 transmits a signal to the signal input terminal VRin of the power supply circuit 52 and adjusts the voltage value of the power supply wiring 55.

FIG. 6 is a diagram illustrating a first configuration example of the

power supply circuits

54a, 54b, and 54c in FIG. The power supply circuit 60 includes

voltage observation circuits

63 and 64, a voltage detection unit 80 including an upper limit reference voltage VrH and a lower limit reference voltage VrL, an individual voltage adjustment unit 84 including a voltage adjustment circuit 20 and a voltage adjustment amount setting circuit 21. Is included. The voltage output from the power supply circuit 60 to the outside is compared with the upper limit reference voltage VrH and the lower limit reference voltage VrL. If the voltage deviates from the specification range, the output voltage is set via the voltage adjustment amount setting circuit 21 and the voltage adjustment circuit 20. Adjust so that it is within the specification range.

FIG. 7 is a diagram illustrating a second configuration example of the

power supply circuits

54a, 54b, and 54c in FIG. In this configuration example, the power supply circuit 70 uses a commercially available power supply IC. The voltage detection function 72 and the output voltage adjustment function 71 that the power supply IC generally has are used to adjust the output voltage of the power supply circuit 70 within the specification range. The voltage detection function 72 corresponds to the voltage detection unit 80 in FIG. The output voltage adjustment function 71 corresponds to the individual voltage adjustment unit 84.

FIG. 8 is a block diagram showing a functional configuration of the microcomputer 57 in FIG. The microcomputer 57 includes a voltage determination unit 81, a detection result output unit 82, and a voltage supply circuit output setting unit 83 configured by a program. The

power supply voltages

56a, 56b, and 56c in the vicinity of the

ICs

53a, 53b, and 53c are input to the voltage determination unit 81, and it is detected whether the power supply voltages of the respective ICs are out of the specification range. The detection result of each power supply voltage is processed by the detection result output unit 82 to determine the operation of the power supply circuit 52. The determination result of the detection result output unit 82 is sent to the voltage supply circuit output setting unit 83, and a signal to be transmitted to the terminal VRin of the power supply circuit 52 is generated by the same processing as the flowchart described in FIG. Output.

The power supply voltage VDD in FIG. 1 corresponds to the voltage of the power supply wiring 55 in FIG. The power supply voltage VDDi in the semiconductor chip 13 in FIG. 2 corresponds to the voltages at the

locations

56a, 56b, and 56c where the power supply voltage is monitored in FIG.

Also in the second embodiment, the same power supply voltage control method as in the first embodiment can be realized.

According to this embodiment, since all the circuits necessary for the present invention are mounted on the printed circuit board 51, it is not necessary to arrange them in the

semiconductor chips

53a, 53b, 53c. Therefore, the

semiconductor chips

53a, 53b, and 53c can use components that are generally commercially available as they are, and an increase in the design period and manufacturing cost of the semiconductor chip can be prevented.

In the first and second embodiments described so far, the case where the power supply circuit and the semiconductor chip are mounted on the printed board has been described as an example. For example, all of them are arranged in one semiconductor chip. Is also possible. In this configuration, the

semiconductor chips

13a, 13b, and 13c in FIG. 1 correspond to logic blocks in one semiconductor chip.

Also, the present invention can be applied to HBM (High Bandwidth Memory) and HMC (Hybrid Memory Cube) in which a plurality of memory chips and a memory controller chip are stacked. This configuration corresponds to a plurality of memory chips in which the

semiconductor chips

53a, 53b, and 53c in FIG. 5 are stacked. A configuration in which a function corresponding to the power supply circuit 52, the

power supply circuits

54a, 54b, 54c, and the microcomputer 57 is built in the memory controller chip may be considered.

In the first and second embodiments, the case where the power supply circuit and the semiconductor chip are mounted on the printed circuit board has been described as an example. However, it is not necessary to mount the power supply circuit and the semiconductor chip on the same printed circuit board. A plurality of circuit blocks are not limited to the chip.

In addition, this invention is not limited to the above-mentioned Example, Various modifications are included. For example, the above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described. Further, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. Further, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.

For example, in the first embodiment, three semiconductor chips are arranged, but the number of semiconductor chips is not necessarily limited to three, and the present invention is not limited to three. The essence of is unchanged.

Further, in the first embodiment, when there is another power supply circuit in the preceding stage of the power supply circuit 12, the output voltage is similarly controlled for this power supply circuit using the method of the present invention. Is possible. In this configuration, the loop for controlling the power supply voltage is tripled, but the essence of the present invention is not impaired.

In the first embodiment, the upper limit reference voltage VrH and the lower limit reference voltage VrL shown in FIG. 2 may be the same in the

semiconductor chips

13a, 13b, and 13c shown in FIG. 1, and are different for each chip. May be.

DESCRIPTION OF SYMBOLS 11 ... Printed circuit board, 12 ... Power supply circuit, VDD ... Power supply voltage, 13a, 13b, 13c ... Semiconductor chip, Hin, Lin, Ho, Lo ... Signal terminal, 13 ... Semiconductor chip, 20 ... Voltage adjustment circuit, VDDi ... Power supply Voltage, 21 ... Voltage adjustment amount setting circuit, 22 ... Logic circuit, 23, 24 ... Voltage determination circuit, 27 ... Logical sum circuit, 28 ... Logical product circuit, 29 ... VDD setting circuit, VrH ... Upper limit reference voltage, VrL ... Lower limit Reference voltage 51 ... Printed circuit board 52 ...

Power supply circuit

53a, 53b, 53c ...

Semiconductor chip

54a, 54b, 54c ... Power supply circuit 57 ...

Microcomputer

60, 70 ...

Power supply circuit

63, 64 ... Voltage observation circuit , 80 ... voltage detection unit, 81 ... voltage determination unit, 82 ... detection result output unit, 83 ... voltage supply circuit output setting unit, 84 ... individual voltage adjustment unit

Claims

An electronic device comprising a plurality of circuit blocks and a power supply circuit for supplying power to the plurality of circuit blocks,
A voltage determination unit for determining a power supply voltage of each of the plurality of circuit blocks;
A detection result output unit that outputs a detection result by combining the power supply voltage determination results of the voltage determination unit;
An output setting unit for determining an output voltage of the power supply circuit based on an output of the detection result output unit;
An individual voltage adjusting unit for adjusting a power supply voltage in each of the circuit blocks,
The output voltage of the power supply circuit is adjusted by integrating the determination results of the power supply voltages of the plurality of circuit blocks, and the power supply voltage of each circuit block is adjusted by the individual voltage adjustment unit. machine.
The electronic device according to claim 1,
The said individual voltage adjustment part adjusts the power supply voltage of a circuit block based on the power supply voltage determination result of the said voltage determination part, The electronic device characterized by the above-mentioned.
The electronic device according to claim 1,
The electronic device, wherein the circuit block is a semiconductor chip.
The electronic device according to claim 3,
An electronic apparatus, wherein at least the voltage determination unit, the detection result output unit, and the individual voltage adjustment unit are incorporated in the semiconductor chip.
The electronic device according to claim 1,
The plurality of circuit blocks, the power supply circuit, the voltage determination unit, the detection result output unit, the output setting unit, and the individual voltage adjustment unit are provided on the same printed circuit board. machine.
The electronic device according to claim 1,
The voltage determination unit determines whether the power supply voltage of the circuit block is higher than a preset upper limit reference voltage and lower than a preset lower limit reference voltage,
The output setting unit lowers the output voltage of the power supply circuit when the determination result of the power supply voltage of one or more circuit blocks is higher than the upper limit reference voltage, and the determination result of the power supply voltage of all circuit blocks is the lower limit reference When the voltage is lower than the voltage, the output voltage of the power supply circuit is increased.
The electronic device according to claim 6,
The detection result output unit logically sums the determination results of a plurality of circuit blocks for a determination result that is higher than a preset upper limit reference voltage, and a plurality of determination results that are lower than a preset lower limit reference voltage. An electronic apparatus that outputs a logical product of determination results of circuit blocks.
The electronic device according to claim 1,
Each of the plurality of circuit blocks includes at least the voltage determination unit and the detection result output unit, and
It has a terminal that receives a voltage determination result from another circuit block, and a terminal that outputs the determination result to another circuit block.
The detection result output unit combines the power supply voltage determination result of its own circuit block and the power supply voltage determination result from another circuit block, and outputs the result to another circuit block.
The electronic device according to claim 8,
An electronic device characterized in that an output to another circuit block is determined by a logical sum or a logical product of a power supply voltage determination result of its own circuit block and a power supply voltage determination result from another circuit block.
The electronic device according to claim 1,
The individual voltage adjustment unit is configured by an individual power supply circuit provided for each circuit block,
The voltage determination unit, the detection result output unit, and the output setting unit are configured by a microcomputer.
The electronic device according to claim 10,
The individual power supply circuit includes a voltage detection unit that detects a power supply voltage of the circuit block, a voltage adjustment amount setting circuit that sets a voltage adjustment amount based on the detected power supply voltage, and a power supply voltage based on the set voltage adjustment amount A power supply circuit comprising a voltage adjustment circuit for adjusting the voltage.
The electronic device according to claim 11,
The voltage detection unit detects whether the power supply voltage of the circuit block is higher than a preset upper limit reference voltage and lower than a preset lower limit reference voltage,
When the detection result of the power supply voltage of the circuit block is higher than the upper limit reference voltage, the voltage adjustment amount setting circuit lowers the output voltage of the voltage adjustment circuit and when the detection result of the power supply voltage of the circuit block is lower than the lower limit reference voltage An electronic apparatus characterized by raising an output voltage of the voltage regulator circuit
The electronic device according to claim 10,
An electronic apparatus using general-purpose parts for the power supply circuit, the individual power supply circuit, and the microcomputer.
The electronic device according to claim 10,
The electronic device, wherein the plurality of circuit blocks, the power supply circuit, the individual power supply circuit, and the microcomputer are provided on the same printed circuit board.