WO2016192045A1 - 存储器的访问系统及方法 - Google Patents

存储器的访问系统及方法 Download PDF

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Publication number
WO2016192045A1
WO2016192045A1 PCT/CN2015/080609 CN2015080609W WO2016192045A1 WO 2016192045 A1 WO2016192045 A1 WO 2016192045A1 CN 2015080609 W CN2015080609 W CN 2015080609W WO 2016192045 A1 WO2016192045 A1 WO 2016192045A1
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Prior art keywords
data block
group
record
read data
storage
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PCT/CN2015/080609
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English (en)
French (fr)
Inventor
宋风龙
张广飞
汪涛
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201580080676.9A priority Critical patent/CN107710172B/zh
Priority to EP15893701.1A priority patent/EP3296880B1/en
Priority to PCT/CN2015/080609 priority patent/WO2016192045A1/zh
Publication of WO2016192045A1 publication Critical patent/WO2016192045A1/zh
Priority to US15/827,746 priority patent/US10901640B2/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/064—Management of blocks
    • G06F3/0641—De-duplication techniques
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0608—Saving storage space on storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1041—Resource optimization
    • G06F2212/1044—Space efficiency improvement
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to the field of memory technologies, and in particular, to a memory access system and method.
  • the on-chip cache is an essential component in many types of processors, such as single-core processors, multi-core processors, and many-core processors.
  • the current cache structure generally adopts a path group associative structure. However, when accessing the cache connected to the way group, all the cache lines (N way) in the cache need to be enabled, and all the flag bits (Tag) fetched from the fetch address and the cache line corresponding to the fetch address are all. The flag bits are compared in parallel and a comparison result is obtained whether it is the same as one of the flag bits in the cache line. Each parallel comparison, up to one of the flag bits in the cache line, and this is called Cache Hit, which means at least N-1 redundancy even in the case of a hit. Access; if all the flag bits in the cache line are different, a cache miss occurs, causing at least N redundant accesses.
  • a multi-core processor such as an SMT processor
  • the probability that the cache block in the same cache line belongs to the same thread is reduced, that is, if a cache block has been occupied by a thread.
  • another thread needs to access the cache block, it needs to enable all the storage paths.
  • N times of tag comparison it can determine the access missing, and then replace the data in the cache block, and the data to be accessed from the memory. The replacement is made, thus increasing the proportion of cache blocks occupied by different threads to each other, which makes the problem of cache redundant access more serious.
  • Embodiments of the present invention provide a data write control apparatus and method for improving program execution efficiency of a write apparatus and method by converting two different write modes.
  • a first aspect of the embodiments of the present invention provides a memory access system, including: a memory, a controller, and a redundancy elimination unit;
  • the memory includes M ⁇ N storage blocks, each row of storage blocks constitutes one storage group, and each column of storage blocks constitutes one storage path, and each storage group is provided with a group identifier, and the M or N is greater than or equal to 2 Integer
  • the redundancy elimination unit is configured to record M records, each record item corresponding to each of the storage groups, wherein each record item is used to save a label of the stored data block in each storage group ;
  • the controller is configured to receive a data read request, determine a read data block and a target storage group of the read data block, and send a query message to the redundancy elimination unit, where the query message carries a target of the read data block a group identifier of the storage group and a label of the read data block;
  • the redundancy eliminating unit is configured to determine, according to the group identifier of the target storage group of the read data block, a record corresponding to the group identifier of the target storage group, and the label of the read data block and the read data.
  • the tags of the stored data blocks in the record entry corresponding to the target storage group of the block are matched, and if the match fails, a query response message of the read data miss is sent to the controller.
  • the controller is further configured to receive a data write request, determine a target storage group of the write data block, and a label of the write data block, and write the data The block is stored to the target storage block in the target storage group, and the group identifier of the target storage group of the write data block and the label of the write data block are sent to the redundancy elimination unit;
  • the redundancy elimination unit is further configured to: record, according to the group identifier of the target storage group of the write data block, a label of the write data block in a record corresponding to the group identifier of the target storage group of the write data block .
  • the each record item in the redundancy elimination unit includes N record bits, and each record Bits correspond to each of the storage blocks in each of the storage groups;
  • the redundancy elimination unit records the label of the stored data block into a corresponding record bit in a record item corresponding to the storage group in which the stored data block is located.
  • the redundancy eliminating unit is further configured to: target a label of the read data block and a target of the read data block The label of the stored data block in the record entry corresponding to the storage group is performed. If the matching is successful, the storage path of the storage block corresponding to the record bit that is successfully matched is determined, and the determined storage path information is sent to the controller, and the controller enables the storage path according to the storage path information. The storage path corresponding to the information.
  • the label of the data block includes a thread identifier corresponding to the data block or identifier information of the data block or a data block corresponding to the data block A combination of thread identification and identification of data blocks.
  • the rest canceling unit is specifically configured to: according to the group identifier of the target storage group of the read data block, corresponding to the target storage group of the read data block
  • the thread information of the stored data block in the record entry is compared, if the thread identifier of the read data block matches the thread information of the stored data block in the record entry corresponding to the target storage group of the read data block Successfully, matching the identification information of the read data block with the data block identifier of the successfully stored data block in the record corresponding to the target storage group of the read data block, if the thread of the read data block Notifying that the thread information of the stored data block in the record item corresponding to the target storage group of the read data block fails to match, sending a read data miss to the controller
  • a second aspect of an embodiment of the present invention provides a memory access system, including: a memory, a controller, and a redundancy eliminating unit;
  • the memory includes M ⁇ N storage blocks, each row of storage blocks constitutes one storage group, and each column of storage blocks constitutes one storage path, and each storage group is provided with a group identifier, and the M or N is greater than or equal to 2 Integer
  • the redundancy elimination unit is configured to record M records, each record item corresponding to each of the storage groups, wherein each record item is used to save a label of the stored data block in each storage group ;
  • the controller is configured to receive a data read request, determine a read data block and a target storage group of the read data block, and set a label of the read data block according to a group identifier of a target storage group of the read data block
  • the read record corresponding to the target storage group of the read data block has been
  • the tags of the stored data blocks are matched, and if the matching fails, the read data block miss information is returned.
  • the controller is further configured to receive a data write request, determine a write data block, and a target storage group of the write data block, and store the write data block Going to the target storage block in the target storage group, and recording the write data in a record corresponding to the group identifier of the target storage group of the write data block according to the group identifier of the target storage group of the write data block The label of the block.
  • the each record item in the redundancy elimination unit includes N record bits, each record Bits correspond to each of the storage blocks in each of the storage groups;
  • the controller records the label of the stored data block into a corresponding record bit in a record item corresponding to the storage group where the stored data block is located.
  • the controller is further configured to: perform a label of the read data block and a target storage group of the read data block When the matching of the tags of the stored data blocks in the corresponding record item is successful, the storage path of the storage block corresponding to the record bit that is successfully matched is determined, and the storage path corresponding to the storage path information is enabled.
  • the label of the data block includes a thread identifier corresponding to the data block or identifier information of the data block or a data block corresponding to the data block A combination of thread identification and identification of data blocks.
  • the label of the data block includes a thread identifier corresponding to the data block and identifier information of the data block, where the control Comparing the thread identifier of the read data block with the thread information of the stored data block in the record item corresponding to the target storage group of the read data block according to the group identifier of the target storage group of the read data block If the match fails, the miss information is returned. If the match is successful, the identifier information of the read data block is matched with the data block identifier of the successfully stored data block in the record corresponding to the target storage group. If the match fails, and the information that is missing is returned.
  • a third aspect of the embodiments of the present invention provides a memory access method, which is applied to save a memory access system, the access system comprising a memory and a redundancy elimination unit, comprising M ⁇ N storage blocks, each row of storage blocks forming a storage group, each column of storage blocks forming a storage path, and each storage group is provided with a group
  • the M or N is a positive integer greater than or equal to 2
  • the redundancy elimination unit records M records, each record corresponding to each storage group, and each record is used for saving
  • the label of the data block is stored in each storage group; and the method includes:
  • the method includes:
  • the each record item in the redundancy elimination unit includes N record bits, and each record Bits correspond to each of the storage blocks in each of the storage groups;
  • the method further includes: recording a label of the stored data block into a corresponding record bit in a record item corresponding to the storage group in which the stored data block is located.
  • the method further includes: corresponding to a label of the read data block and a target storage group of the read data block When the matching of the tags of the stored data blocks in the record item is successful, the storage path of the storage block corresponding to the record bit that is successfully matched is determined, and the storage path corresponding to the storage path information is enabled.
  • the label of the data block includes a thread identifier corresponding to the data block or identifier information of the data block or a thread of the data block. A combination of the identification and the identification of the data block.
  • the manager when the label of the data block includes the thread identifier corresponding to the data block and the identifier information of the data block, after receiving the query message, the manager is specifically configured to: according to the read data Comparing the group identifier of the target storage group of the block, comparing the thread identifier of the read data block with the thread information of the stored data block in the record item corresponding to the target storage group of the read data block, if the read data And the thread identifier of the block is successfully matched with the thread information of the stored data block in the record item corresponding to the target storage group of the read data block, and the identifier information of the read data block is matched with the record item corresponding to the target storage group. Matching the data block identifier of the successfully stored data block to match, if the thread identifier of the read data block matches the thread information of the stored data block in the record item corresponding to the target storage group of the read data block Failed
  • a fourth aspect of the embodiments of the present invention provides a computer device, including: a processor, a first memory, a bus and a communication interface, and a second memory, where the second memory includes M ⁇ N memory blocks, each The row storage blocks form a storage group, and each column of storage blocks constitutes one storage path, and each storage group is provided with a group identifier, and the M or N is a positive integer greater than or equal to 2;
  • the first memory is configured to store a computer execution instruction
  • the processor is coupled to the first memory via the bus, and when the computing device is in operation, the processor executes a location stored in the first memory
  • the computer executes instructions to cause the computer device to perform the following methods:
  • a fifth aspect of the embodiments of the present invention provides a computer readable medium, comprising computer executed instructions, when the processor of the computer executes the computer to execute an instruction, the computer performs the following method:
  • the memory includes M ⁇ N storage blocks, the M row storage blocks constitute M storage groups, and the N columns storage blocks constitute N Storage paths, each storage group is set with a group identifier, M or N is a positive integer greater than or equal to 2, and the M or N is a positive integer greater than or equal to 2;
  • the redundancy elimination unit Querying a redundancy elimination unit according to the group identification of the target storage group of the read data block, the redundancy elimination unit recording M record items, each record item corresponding to each of the storage groups, each of the record items a label for storing the stored data blocks in each of the storage groups;
  • Embodiments of the present invention provide a redundancy elimination unit in which tags of each data block in each of the storage groups in the multiplexed memory are recorded, and when there is a read data request, The label of the read data block included in the read data request is compared with the label of each data block in the storage group of the target recorded in the redundancy elimination unit. If the match fails, the target storage group of the current access request is There is no data block to be accessed. Therefore, it is not necessary to enable each storage path in the multiplexed memory to perform tag alignment of the data block, thereby effectively reducing redundant access and improving memory access performance. , reducing the consumption of electrical energy due to redundant access.
  • FIG. 1 is a structural diagram of a multiplexer memory in an embodiment of the present invention.
  • FIG. 2 is a structural diagram of an access system of a memory according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a redundancy eliminating unit in the access system of the memory shown in FIG. 2.
  • FIG. 4 is a schematic diagram of an access system of the memory shown in FIG. 2 processing a data read request.
  • FIG. 5 is a schematic diagram of an access system of the memory shown in FIG. 2 processing a data write request.
  • FIG. 6 is a flowchart of a method for accessing a memory according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a computer device according to an embodiment of the present invention.
  • the multiplexed memory is generally used as a cache of memory.
  • the multiplexed memory generally includes M ⁇ N storage blocks, and each row of storage blocks constitutes one storage group (Set0-SetM), and each column of storage blocks constitutes one storage path (Way0-WayN), and each storage group is set with a group.
  • Identification such as Set0-SetM, where M or N is a positive integer greater than or equal to 2.
  • Each memory block includes data blocks and data block identification information.
  • the data block is data stored in each storage block, and the data block identification information is a flag (Tag) of each data block, and is used to mark a memory address of the data block, that is, by using the flag.
  • the bit can locate the location of the data block in memory, and since each data block has an address in memory that is unique, the flag bit can uniquely identify the data block.
  • the memory access request includes a memory address of the accessed data block, and the memory address generally includes a tag, an index, and an offset of the accessed data block.
  • the N tags in the locating storage group are matched. If the matching is successful, the requested data is obtained from the data block corresponding to the successfully matched tag according to the offset Offset, that is, the access hit, if the matching is unsuccessful, If the access is missing, you need to load the data block of this access from the memory.
  • the multiplexed memory is used by multiple threads, if the storage group accessed by the current thread is already occupied by other threads, the current thread still needs to open all the storage paths to match the flag bits of the data block.
  • the current thread In order to determine whether there is a data block that needs to be accessed in the accessed storage group, there is no data block that needs to be accessed this time, and the current thread needs to replace the data block of other threads, and this access is Data blocks are loaded from memory, and when other threads access the data block again, the same operation is required, which results in more severe redundant access.
  • Embodiments of the present invention provide a redundancy elimination unit in which tags of each data block in each storage group in the multiplex memory are recorded, and when there is a data access request, the requirements included in the access request are included.
  • the tag of the accessed data block is compared with the tag of each data block in the storage group of the target recorded in the redundancy elimination unit. If the matching fails, it indicates that there is no data to be accessed in the target storage group of the current access request.
  • Block in this way, it is not necessary to enable each memory path in the multiplexed memory to perform tag alignment of the data block, thus effectively reducing redundant access, improving memory access performance, and reducing redundancy The consumption of electrical energy generated by the access.
  • FIG. 2 is a structural diagram of an access system of a memory in an embodiment of the present invention.
  • the memory access system 20 includes a multiplexed memory 21, a redundancy eliminating unit 22, and a control unit 23 as shown in FIG.
  • the redundancy eliminating unit 22 records M items of records (Item0-ItemM), each of which corresponds to each of the storage groups, and each of the items includes N pieces of recording bits.
  • Each record bit corresponds to each of the storage blocks in the storage group for holding a tag of a stored data block in the corresponding storage block.
  • the label of the data block includes identification information of the data block, thread information, or identification information of the data block and the thread. A combination of information.
  • the controller 23 is configured to receive a data read request, acquire a read data block label in the read request, and a group identifier of a target storage group of the read data block, to the redundancy elimination unit. 22 sending a query message, where the query message carries a group identifier of a target storage group of the read data block and a label of the read data block;
  • the redundancy eliminating unit 22 is configured to determine, according to the group identifier of the target storage group of the read data block, a record corresponding to the group identifier of the target storage group, and the label of the read data block and the read data.
  • the tags of the stored data blocks in the record entry corresponding to the target storage group of the block are matched. If the match fails, the query response message of the read data miss is sent to the controller 23, so that the controller 23 does not need to
  • Each storage path of the memory 21 is opened to compare the flag bits of each data block in the target storage group, thereby effectively reducing redundant access.
  • the redundancy eliminating device 22 determines the storage path where the storage block corresponding to the successfully matched record bit is located, and the determined The storage path information is sent to the controller 23, and the controller 23 enables the storage path corresponding to the storage path information based on the storage path information. In this way, the controller 23 does not need to open all the storage channels for the comparison of the data block flag bits, but only needs to open the storage path where the storage block corresponding to the successfully matched recording bit is located, thereby reducing redundant access.
  • the label of the data block recorded in the redundancy eliminating unit 22 is a tag of each data block in the memory 21, or a thread information TID occupying each data block, or a tag and a data block of each data block.
  • the controller 23 sends a tag of the read data block in the data read request to the redundancy elimination unit 22 for matching, and the matching fails.
  • the matching failure information is sent to the controller 23, so that the controller 2 does not need to obtain the data block from the memory 21, and when the matching is successful, only the matching is successful. It is sufficient to record the storage path where the memory block corresponding to the bit is located, so redundant access to the memory is eliminated.
  • the data read request further includes reading the thread information TID of the read data block, and the label of the read data block is the thread information of the read data block. TID.
  • the record bit of each record in the redundancy elimination unit 22 also records the thread information TID of the stored data block in each storage group. Then, when receiving the data read request, the controller 23 sends the thread information of the read data block in the data read request to the redundancy canceling unit 22 for matching, and when the matching fails, sends a match.
  • the failed information is given to the controller 23, such that the controller 23 does not need to enable each storage path of the memory 21 to determine whether the read data block exists in the target storage group, and when the matching is successful
  • the redundancy controller 23 determines a storage path where the storage block corresponding to the successfully recorded record bit is located, and then sends the storage path information to the controller 23, and the controller 23 enables the storage path information. Corresponding storage path.
  • the number of entries that the redundant access cancellation unit 22 matches successfully may be multiple, so that the controller 23 is still Multiple storage paths are enabled, and then the flag bits of the read data block and the flag bits of the data block in the target storage group are further compared in the enabled storage path, and if the matching fails, the return is returned. Information, if the match is successful, the data is read.
  • the thread information TID when used for the redundant access elimination operation, since one thread may occupy a plurality of data blocks of the target storage group, only redundant access elimination can be reduced.
  • the operation does not completely eliminate the redundant access cancellation operation.
  • the label of the data block may be a combination of the thread information of the data block and the identification information of the data block.
  • the redundant access cancellation operation of the redundancy eliminating unit 22 is specifically: a target storage group according to the read data block. And the group identifier, the thread identifier of the read data block is compared with the thread information of the stored data block in the record item corresponding to the target storage group of the read data block, and if the matching fails, the controller is Sending a query response message of the read data miss, if the matching is successful, identifying the identification information of the read data block and the The data block identifier of the successfully stored stored data block in the record entry corresponding to the target storage group is matched, and if the match fails, the query response message of the read data miss is sent to the controller 23. In this way, redundant access cancellation operations in a multi-threaded system can be completely eliminated.
  • the controller 23 is further configured to receive a data write request, determine a target storage group of the write data block, and a label of the write data block, and store the write data block into the target storage group. a target storage block, and transmitting a group identifier of the target storage group of the write data block and a label of the write data block to the redundancy elimination unit.
  • the redundancy elimination unit 22 is further configured to record, according to the group identifier of the target storage group of the write data block, a label of the write data block in a record corresponding to the group identifier of the target storage group of the write data block. .
  • the label of the data block recorded in each of the redundancy elimination units 22 is changed along with the change of the data block stored in the storage block in the multiplex memory, for example, when the memory 21
  • the record entry stored in the recording bit corresponding to the storage block in the redundancy elimination unit 22 is also marked by the mark A. Transform to marker B.
  • the redundancy cancellation unit 22 is not a separate hardware component, but is stored as a data structure in the memory 21 or in a register in the controller 23 that stores control instructions. .
  • the controller 23 determines the read data block and the target storage group of the read data block, and queries the redundancy elimination unit according to the group identifier of the target storage group of the read data block. And matching the label of the read data block with the label of the stored data block in the record item corresponding to the target storage group of the read data block, and if the matching fails, returning the read data block miss information.
  • the controller 23 Upon receiving the data write request, the controller 23 determines a write data block and a target storage group of the write data block, stores the write data block to a target storage block in the target storage group, and according to the Decoding a group identifier of a target storage group of the data block, and recording a label of the write data block in a record corresponding to the group identifier of the target storage group of the write data block.
  • FIG. 6 is a flowchart of a memory access method in an embodiment of the present invention.
  • the memory access method is applied to a memory access system that includes a memory and a redundancy cancellation unit.
  • the memory comprises M ⁇ N storage blocks, each row of storage blocks forming a storage group, and each column of storage blocks constitutes one storage path, and each storage group is provided with a group identifier, the M or N is a positive integer greater than or equal to 2; the redundancy elimination unit records M records, each record corresponding to each storage group, and each record item is used for saving A tag of the data block has been stored in each of the storage groups.
  • the memory access method includes:
  • Step S601 receiving a data read request, determining a read data block and a target storage group of the read data block;
  • Step S602 determining, according to the group identifier of the target storage group of the read data block, a record item of the redundancy elimination unit corresponding to the target storage group of the read data block;
  • Step S603 matching, by the label of the read data block, the label of the stored data block in the record item of the redundancy elimination unit corresponding to the target storage group of the read data block;
  • Step S604 it is determined whether the match is successful, if the match fails, step S605 is performed, if the match is successful, step S606 is performed;
  • Step S605 returning read data block miss information
  • Step S606 if the matching is successful, determining a storage path where the storage block corresponding to the successfully recorded record bit is located;
  • Step S604 enabling a storage path corresponding to the storage path information.
  • FIG. 7 is a schematic structural diagram of a computer device according to an embodiment of the present invention.
  • the computer of the embodiment of the present invention may include:
  • the processor 701, the memory 702, and the communication interface 705 are connected by the system bus 704 and complete communication with each other.
  • Processor 701 may be a single core or multi-core central processing unit, or a particular integrated circuit, or one or more integrated circuits configured to implement embodiments of the present invention.
  • the memory 702 may be a high speed RAM memory or a non-volatile memory such as at least one disk memory.
  • Memory 702 is used by computer to execute instructions 703.
  • the computer execution instructions 703 may include program code.
  • the processor 701 runs computer execution instructions 703, which may perform the method flow described in FIG.
  • the embodiment of the present invention further provides a computer readable medium, comprising computer execution instructions, when the processor of the computer executes the computer execution instruction, the computer executes the method flow described in FIG.
  • the program may be stored in a computer readable storage medium, and the storage medium may include: ROM, RAM, disk or CD.

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Abstract

一种存储器的访问系统及方法，所述系统包括：存储器（21）、控制器（23）与冗余消除单元（22）；所述存储器为多路组存储器（21）；所述冗余消除单元（22）记录M条记录项，所述每条记录项用于保存所述每个存储组中已存储数据块的标签；所述控制器（23）确定读数据块和所述读数据块的目标存储组，向所述冗余消除单元（22）发送查询消息，所述查询消息携带所述读数据块的目标存储组的组标识和所述读数据块的标签；所述冗余消除单元（22）根据所述读数据块的目标存储组的组标识，确定所述目标存储组的组标识对应的记录项，将所述读数据块的标签与所述读数据块的目标存储组对应的记录项中的已存储的数据块的标签进行匹配，若匹配失败，向所述控制器（23）发送读数据未命中的查询响应消息。

Description

存储器的访问系统及方法 技术领域
本发明涉及存储器技术领域，特别涉及存储器的访问系统及方法。
背景技术
片内高速缓存(Cache)是当前单核处理器、多核处理器和众核处理器等多种类型处理器中的必备部件，当前的高速缓存结构普遍采用路组相联结构。但是在访问路组相连的高速缓存时，需要使能高速缓存中的所有缓存路(N路)，并将访存地址中取出的标志位(Tag)与访存地址对应的缓存行中的所有标志位并行比较，并且得到是否与缓存行中其中一个标志位相同的比较结果。每次并行比较，最多与缓存行中的一项标志位相同，且此时称为高速缓存访问命中(Cache Hit)，即即使在命中的情况下，也会造成至少N-1次的冗余访问；如果与缓存行中的所有标志位比较都不相同，则发生缓存访问缺失(Cache Miss)，即造成至少N次冗余访问。
在多核处理器，如SMT处理器中，当多个硬件线程共享高速缓存时，同一个缓存行中的缓存块属于同一个线程的概率降低，即在一个缓存块已经被一个线程占用之后，如果另外一个线程也需要访问这个缓存块时，需要使能所有的存储路，在经过N次tag比较之后，才能确定访问缺失，然后再将缓存块中的数据替换出去，将需要访问的数据从内存中替换进来，因而使不同线程所占有的高速缓存块彼此替换的比例增高，从而使得高速缓存冗余访问的问题更为严重。
发明内容
本发明实施例提供数据写入控制装置及方法，通过两种不同写入模式的转换，提高写入装置及方法的程序执行效率。
本发明实施例的第一方面提供一种存储器的访问系统，包括：存储器、控制器与冗余消除单元；
所述存储器，包括M×N个存储块，每行存储块组成一个存储组，每列存储块组成一个存储路，每个存储组设置有组标识，所述M或N为大于等于2的正整数；
所述冗余消除单元，用于记录M条记录项，每条记录项对应于所述每个存储组，所述每条记录项用于保存所述每个存储组中已存储数据块的标签；
所述控制器，用于接收数据读请求，确定读数据块和所述读数据块的目标存储组，向所述冗余消除单元发送查询消息，所述查询消息携带所述读数据块的目标存储组的组标识和所述读数据块的标签；
所述冗余消除单元，用于根据所述读数据块的目标存储组的组标识，确定所述目标存储组的组标识对应的记录项，将所述读数据块的标签与所述读数据块的目标存储组对应的记录项中的已存储的数据块的标签进行匹配，若匹配失败，向所述控制器发送读数据未命中的查询响应消息。
结合第一方面，在第一种可能的实现方式中，所述控制器，还用于接收数据写请求，确定写数据块的目标存储组和所述写数据块的标签，将所述写数据块存储到所述目标存储组中的目标存储块，并将所述写数据块的目标存储组的组标识以及所述写数据块的标签发送到所述冗余消除单元；
所述冗余消除单元，还用于根据所述写数据块的目标存储组的组标识，在所述写数据块的目标存储组的组标识对应的记录项中记录所述写数据块的标签。
结合第一方面或者第一方面的第一种可能的实现方式，在第二种可能的实现方式中，所述冗余消除单元中的所述每条记录项包含N个记录位，每个记录位对应于所述每个存储组中每个存储块；
所述冗余消除单元将所述已存储的数据块的标签记录到所述已存储的数据块所在的存储组对应的记录项中对应的记录位中。
结合第一方面的第二种可能的实现方式，在第三种可能的实现方式中，所述冗余消除单元还用于，在将所述读数据块的标签与所述读数据块的目标存储组对应的记录项中的已存储的数据块的标签进行 匹配成功时，则确定匹配成功的记录位对应的存储块所在的存储路，将所确定的存储路信息发送至所述控制器，所述控制器根据所述存储路信息使能所述存储路信息对应的存储路。
结合第一方面或者第一方面的以上任何一种实现方式，在第四种可能的实现方式中，所述数据块的标签包括数据块对应的线程标识或者数据块的标识信息或者数据块对应的线程标识及数据块的标识的组合。
结合第一方面或者第一方面的以上任何一种实现方式，在第五种可能的实现方式中，当所述数据块的标签包括数据块对应的线程标识及数据块的标识信息，所述冗余消除单元在接收到所述查询消息后，具体用于：根据所述读数据块的目标存储组的组标识，将所述读数据块的线程标识与所述读数据块的目标存储组对应的记录项中的已存储的数据块的线程信息进行比较，若所述读数据块的线程标识与所述读数据块的目标存储组对应的记录项中的已存储的数据块的线程信息匹配成功，将所述读数据块的标识信息与所述读数据块的目标存储组对应的记录项中的匹配成功的已存储的数据块的数据块标识进行匹配，若所述读数据块的线程标识与所述读数据块的目标存储组对应的记录项中的已存储的数据块的线程信息匹配失败，则向所述控制器发送读数据未命中的查询响应消息。
本发明的实施例的第二方面提供一种存储器的访问系统，包括：存储器、控制器与冗余消除单元；
所述存储器，包括M×N个存储块，每行存储块组成一个存储组，每列存储块组成一个存储路，每个存储组设置有组标识，所述M或N为大于等于2的正整数；
所述冗余消除单元，用于记录M条记录项，每条记录项对应于所述每个存储组，所述每条记录项用于保存所述每个存储组中已存储数据块的标签；
所述控制器，用于接收数据读请求，确定读数据块和所述读数据块的目标存储组，根据所述读数据块的目标存储组的组标识，将所述读数据块的标签与所述读数据块的目标存储组对应的记录项中的已 存储的数据块的标签进行匹配，若匹配失败，返回读数据块未命中信息。
结合第二方面，在第一种可能的实现方式中，所述控制器，还用于接收数据写请求，确定写数据块和所述写数据块的目标存储组，将所述写数据块存储到所述目标存储组中的目标存储块，并根据所述写数据块的目标存储组的组标识，在所述写数据块的目标存储组的组标识对应的记录项中记录所述写数据块的标签。
结合第二方面或者第一方面的第一种可能的实现方式，在第二种可能的实现方式中，所述冗余消除单元中的所述每条记录项包含N个记录位，每个记录位对应于所述每个存储组中每个存储块；
所述控制器将所述已存储的数据块的标签记录到所述已存储的数据块所在的存储组对应的记录项中对应的记录位中。
结合第二方面的第二种可能的实现方式，在第三种可能的实现方式中，所述控制器还用于，在将所述读数据块的标签与所述读数据块的目标存储组对应的记录项中的已存储的数据块的标签进行匹配成功时，则确定匹配成功的记录位对应的存储块所在的存储路，并使能所述存储路信息对应的存储路。
结合第二方面或者第二方面的以上任何一种实现方式，在第四种可能的实现方式中，所述数据块的标签包括数据块对应的线程标识或者数据块的标识信息或者数据块对应的线程标识及数据块的标识的组合。
结合第二方面的第三种或者第四种可能的实现方式，在第五种可能的实现方式中，所述数据块的标签包括数据块对应的线程标识及数据块的标识信息，所述控制器根据所述读数据块的目标存储组的组标识，将所述读数据块的线程标识与所述读数据块的目标存储组对应的记录项中的已存储的数据块的线程信息进行比较，若匹配失败，则返回未命中信息，若匹配成功，则将所述读数据块的标识信息与目标存储组对应的记录项中的匹配成功的已存储的数据块的数据块标识进行匹配，若匹配失败，并返回未命中的信息。
本发明实施例的第三方面提供一种存储器的访问方法，应用于存 储器访问系统，所述访问系统包括存储器及冗余消除单元，包括M×N个存储块，每行存储块组成一个存储组，每列存储块组成一个存储路，每个存储组设置有组标识，所述M或N为大于等于2的正整数；所述冗余消除单元，记录M条记录项，每条记录项对应于所述每个存储组，所述每条记录项用于保存所述每个存储组中已存储数据块的标签；其特征在于，所述方法包括：
接收数据读请求，确定读数据块和所述读数据块的目标存储组；
根据所述读数据块的目标存储组的组标识，将所述读数据块的标签与所述读数据块的目标存储组对应的所述冗余消除单元的记录项中的已存储的数据块的标签进行匹配，若匹配失败，返回读数据块未命中信息。
结合第三方面，在第一种可能的实现方式中，所述方法包括：
接收数据写请求，确定写数据块和所述写数据块的目标存储组；
将所述写数据块存储到所述目标存储组中的目标存储块；
根据所述写数据块的目标存储组的组标识，在所述写数据块的目标存储组的组标识对应的记录项中记录所述写数据块的标签。
结合第三方面或者第一方面的第一种可能的实现方式，在第二种可能的实现方式中，所述冗余消除单元中的所述每条记录项包含N个记录位，每个记录位对应于所述每个存储组中每个存储块；
所述方法还包括：将所述已存储的数据块的标签记录到所述已存储的数据块所在的存储组对应的记录项中对应的记录位中。
结合第三方面的第二种可能的实现方式，在第三种可能的实现方式中，所述方法还包括：在将所述读数据块的标签与所述读数据块的目标存储组对应的记录项中的已存储的数据块的标签进行匹配成功时，则确定匹配成功的记录位对应的存储块所在的存储路，并使能所述存储路信息对应的存储路。
结合第三方面或者第三方面的以上任何一种实现方式，在第四种可能的实现方式中，所述数据块的标签包括数据块对应的线程标识或者数据块的标识信息或者数据块的线程标识及数据块的标识的组合。
结合第三方面或者第三方面的以上任何一种实现方式，在第五种 可能的实现方式中，当所述数据块的标签包括数据块对应的线程标识及数据块的标识信息时，在接收到所述查询消息后，所述管理器具体用于：根据所述读数据块的目标存储组的组标识，将所述读数据块的线程标识与所述读数据块的目标存储组对应的记录项中的已存储的数据块的线程信息进行比较，若所述读数据块的线程标识与所述读数据块的目标存储组对应的记录项中的已存储的数据块的线程信息匹配成功，则将所述读数据块的标识信息与目标存储组对应的记录项中的匹配成功的已存储的数据块的数据块标识进行匹配，若所述读数据块的线程标识与所述读数据块的目标存储组对应的记录项中的已存储的数据块的线程信息匹配失败，并返回未命中的信息。
本发明实施例的第四方面提供一种计算机设备，其特征在于，包括：处理器、第一存储器、总线和通信接口、第二存储器，所述第二存储器包括M×N个存储块，每行存储块组成一个存储组，每列存储块组成一个存储路，每个存储组设置有组标识，所述M或N为大于等于2的正整数；
所述第一存储器用于存储计算机执行指令，所述处理器与所述第一存储器通过所述总线连接，当所述计算设备运行时，所述处理器执行所述第一存储器中存储的所述计算机执行指令，以使所述计算机设备执行如下方法：
接收数据读请求，确定读数据块和所述读数据块的目标存储组；
根据所述读数据块的目标存储组的组标识，将所述读数据块的标签与所述读数据块的目标存储组对应的所述冗余消除单元的记录项中的已存储的数据块的标签进行匹配，若匹配失败，返回读数据块未命中信息。
本发明实施例的第五方面提供一种计算机可读介质，包括计算机执行指令，当计算机的处理器执行所述计算机执行指令时，所述计算机执行如下方法：
接收数据读请求，确定读数据块和所述读数据块所在的存储器的目标存储组，所述存储器包括M×N个存储块，M行存储块组成M个存储组，N列存储块组成N个存储路，每个存储组设置有组标识，所 述M或N为大于等于2的正整数，所述M或N为大于等于2的正整数；
根据所述读数据块的目标存储组的组标识查询冗余消除单元，所述冗余消除单元记录M条记录项，每条记录项对应于所述每个存储组，所述每条记录项用于保存所述每个存储组中已存储数据块的标签；
将所述读数据块的标签与所述读数据块的目标存储组对应的所述冗余消除单元的记录项中的已存储的数据块的标签进行匹配；
若匹配失败，返回读数据块未命中信息。
本发明的实施例通过提供一个冗余消除单元，所述冗余消除单元中记录了多路组存储器中的每个存储组中的每个数据块的标签，则在有读数据请求时，将读数据请求中包含的读数据块的标签与冗余消除单元中记录的目标的存储组中的每个数据块的标签进行比对，若匹配失败，则说明本次访问请求的目标存储组中没有需要访问的数据块，如此，则不需要使能多路组存储器中的每个存储路进行数据块的标签的比对，如此，有效的减少了冗余访问，提高存储器的访问性能，同时，减少了由于冗余访问而产生的电能的消耗。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本发明一实施例中的多路组存储器的结构图。
图2为本发明实施例中的一种存储器的访问系统的架构图。
图3为图2所示的存储器的访问系统中的冗余消除单元的示意图。
图4为图2所示的存储器的访问系统处理数据读请求的示意图。
图5为图2所示的存储器的访问系统处理数据写请求的示意图。
图6为本发明实施例中的一种存储器的访问方法的流程图。
图7为本发明实施例提供的计算机设备的结构组成示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
如图1所示，为多路组存储器的结构图，所述多路组存储器一般作为内存的缓存。所述多路组存储器一般包括M×N个存储块，每行存储块组成一个存储组(Set0-SetM)，每列存储块组成一个存储路(Way0-WayN)，每个存储组设置有组标识，如Set0-SetM，所述M或N为大于等于2的正整数。
每个存储块包括数据块(data)及数据块标识信息。所述数据块即为每个存储块中存储的数据，所述数据块标识信息即为每个数据块的标志位(Tag)，用于标记所述数据块的内存地址，即通过所述标志位可以定位所述数据块在的内存中的位置，由于每个数据块在内存中的地址是唯一的，所以所述标志位可以唯一标识所述数据块。
内存访问请求中包括所访问数据块的内存地址，内存地址一般包括所访问数据块的标志位(tag)、索引(index)、及偏移量(Offset)。在进行数据访问时，首先通过所述索引(index)定位到所访问数据块所在的存储组，然后使能所述多路组存储器的所有存储路，然后用所述访问请求中的tag与所定位的存储组中的N个tag进行匹配，若匹配成功，则根据所述偏移量Offset从匹配成功的Tag对应的数据块中获取所请求的数据，即访问命中，若匹配不成功，即访问缺失，则需要从内存中调入本次访问的数据块。
由于在数据访问过程中，即使本次访问没有命中的数据，也需要使能多路组存储器中的所有存储路，然后再将访问请求中所访问数据 块的标识位与所述访问请求所对应的存储组中的所有数据块的标志位进行比对，这样，即造成了冗余访问，即使在匹配成功的情况下，由于匹配成功的数据块可能只有一个，但却需要将所有的存储路都打开，而且如果有N个存储路，则需要匹配N次，这就会造成N-1次的冗余访问。
另外，如果所述多路组存储器被多个线程使用时，如果当前线程所访问的存储组已被其他线程占用，则当前线程也还是需要打开所有的存储路，进行数据块的标志位的匹配，才能确定所访问的存储组中是否存在本次需要访问的数据块，在其中不存在本次需要访问的数据块，当前线程则需要将其他线程的数据块替换出去，而将本次访问的数据块从内存中调入，而当其他线程再次访问这个数据块时，则需要做同样的操作，如此，则造成更为严重的冗余访问。
本发明的实施例即提供一个冗余消除单元，其中记录了多路组存储器中的每个存储组中的每个数据块的标签，则在有数据访问请求时，将访问请求中包含的需要访问的数据块的标签与冗余消除单元中记录的目标的存储组中的每个数据块的标签进行比对，若匹配失败，则说明本次访问请求的目标存储组中没有需要访问的数据块，如此，则不需要使能多路组存储器中的每个存储路进行数据块的标签的比对，如此，有效的减少了冗余访问，提高存储器的访问性能，同时，减少了由于冗余访问而产生的电能的消耗。
下面结合具体实施例描述如何减少对图1中的多路组存储器的冗余访问。
如图2所示，为本发明实施例中的一种存储器的访问系统的架构图。所述存储器访问系统20包括：如图1所示的多路组存储器21、冗余消除单元22、及控制单元23。
如图3所示，所述冗余消除单元22记录了M条记录项(Item0-ItemM)，每条记录项对应于所述每个存储组，所述每条记录项包括N个记录位，每个记录位对应于所述每个存储组中每个存储块，用于保存对应存储块中已存储的数据块的标签。所述数据块的标签包括数据块的标识信息、线程信息、或者数据块的标识信息与线程 信息的组合。
如图4所示，所述控制器23用于接收数据读请求，获取所述读请求中的读数据块标签和所述读数据块的目标存储组的组标识，向所述冗余消除单元22发送查询消息，所述查询消息携带所述读数据块的目标存储组的组标识和所述读数据块的标签；
所述冗余消除单元22用于根据所述读数据块的目标存储组的组标识，确定所述目标存储组的组标识对应的记录项，将所述读数据块的标签与所述读数据块的目标存储组对应的记录项中的已存储的数据块的标签进行匹配，若匹配失败，向所述控制器23发送读数据未命中的查询响应消息，这样所述控制器23就不需要打开所述存储器21的各个存储路，去对目标存储组中的各数据块的标志位进行比较，从而有效的减少了冗余访问。
另外，在所述读数据块的标签与所述读数据块的目标存储组对应的记录项中的已存储的数据块的标签匹配成功后，在将所述读数据块的标签与所述读数据块的目标存储组对应的记录项中的已存储的数据块的标签进行匹配成功时，则所述冗余消除装置22确定匹配成功的记录位对应的存储块所在的存储路，将所确定的存储路信息发送至所述控制器23，所述控制器23根据所述存储路信息使能所述存储路信息对应的存储路。这样，控制器23无需打开所有存储路进行数据块标志位的比较，而只需要打开匹配成功的记录位对应的存储块所在的存储路，从而减少冗余访问。
本实施例中，所述冗余消除单元22中记录的数据块的标签为存储器21中每个数据块的Tag，或者占用每个数据块的线程信息TID，或者为每个数据块的Tag与占用每个数据块的线程信息TID的组合。
当所述数据块的标签为每个数据块的Tag时，所述控制器23即将所述数据读请求中所述读数据块的tag发送至所述冗余消除单元22进行匹配，在匹配失败的时候，则发送匹配失败的信息给所述控制器23，这样所述控制器2则不需要从所述存储器21中获取所述数据块，而在匹配成功时，则只需要打开匹配成功的记录位对应的存储块所在的存储路即可，所以消除了对所述存储器的冗余访问。
在所述存储器21应用于多线程的系统时，所述数据读请求中还包括读取所述读数据块的线程信息TID，则所述读数据块的标签为所述读数据块的线程信息TID。而所述冗余消除单元22中的每条记录项的记录位也记录的是每个存储组中已存储数据块的线程信息TID。则在接收到数据读请求时，所述控制器23即将所述数据读请求中所述读数据块的线程信息发送至所述冗余消除单元22进行匹配，在匹配失败的时候，则发送匹配失败的信息给所述控制器23，这样所述控制器23则不需要使能所述存储器21的各存储路去确定所述目标存储组中是否存在所述读数据块，而在匹配成功时，所述冗余控制器23确定匹配成功的记录位对应的存储块所在的存储路路，然后发送所述存储路信息至所述控制器23，所述控制器23使能所述存储路信息对应的存储路。
需要注意的时，由于一个线程可能占用所述目标存储组中的多个数据块，所以，所述冗余访问消除单元22所匹配成功的记录项可能为多个，这样所述控制器23还是会使能多个存储路，然后在所使能的存储路中，进一步比较所述读数据块的标志位与所述目标存储组中的数据块的标志位，若匹配失败，则返回未命中信息，若匹配成功，则读取数据。
由上面的描述可知，在多线程的系统中，使用线程信息TID进行冗余访问消除操作时，由于一个线程可能占用所述目标存储组的多个数据块，所以，只能减少冗余访问消除操作，并不能完全消除冗余访问消除操作，为了完全消除在多线程系统中的冗余访问消除操作，则所述数据块的标记可以为数据块的线程信息及数据块的标识信息的组合。
在所述数据块的标识信息为数据块的线程信息及数据块的标识信息的组合时，所述冗余消除单元22的冗余访问消除操作具体为：根据所述读数据块的目标存储组的组标识，将所述读数据块的线程标识与所述读数据块的目标存储组对应的记录项中的已存储的数据块的线程信息进行比较，若匹配失败，则向所述控制器发送读数据未命中的查询响应消息，若匹配成功，则将所述读数据块的标识信息与所述 目标存储组对应的记录项中的匹配成功的已存储的数据块的数据块标识进行匹配，若匹配失败，则向所述控制器23发送读数据未命中的查询响应消息。如此，可完全消除多线程系统中的冗余访问消除操作。
如图5所示，所述控制器23还用于接收数据写请求，确定写数据块的目标存储组和所述写数据块的标签，将所述写数据块存储到所述目标存储组中的目标存储块，并将所述写数据块的目标存储组的组标识以及所述写数据块的标签发送到所述冗余消除单元。所述冗余消除单元22还用于根据所述写数据块的目标存储组的组标识，在所述写数据块的目标存储组的组标识对应的记录项中记录所述写数据块的标签。
且所述冗余消除单元22中每个记录项记录的数据块的标签随着所述多路组存储器中的存储块中存储的数据块的变更而变更，例如，当所述存储器21中的存储块组Item 2中位于存储路way2的存储块的数据块由data1更新为data2时，则所述冗余消除单元22中与所述存储块对应的记录位处所存储的记录项也由标记A变换为标记B。
在其他实施例中，所述冗余消除单元22并非一独立的硬件元件，而是作为一种数据结构存储在所述存储器21中，或者存储在所述控制器23中存储控制指令的寄存器中。如此，在接收到数据读请求时，所述控制器23确定读数据块和所述读数据块的目标存储组，根据所述读数据块的目标存储组的组标识查询所述冗余消除单元，将所述读数据块的标签与所述读数据块的目标存储组对应的记录项中的已存储的数据块的标签进行匹配，若匹配失败，返回读数据块未命中信息。
在接收到数据写请求时，所述控制器23确定写数据块和所述写数据块的目标存储组，将所述写数据块存储到所述目标存储组中的目标存储块，并根据所述写数据块的目标存储组的组标识，在所述写数据块的目标存储组的组标识对应的记录项中记录所述写数据块的标签。
如图6所示，为本发明实施例中的存储器访问方法的流程图。所述存储器访问方法应用于存储器访问系统，所述存储器访问系统包括存储器及冗余消除单元。所述存储器包括M×N个存储块，每行存储块组成一个存储组，每列存储块组成一个存储路，每个存储组设置有 组标识，所述M或N为大于等于2的正整数；所述冗余消除单元记录M条记录项，每条记录项对应于所述每个存储组，所述每条记录项用于保存所述每个存储组中已存储数据块的标签。
所述存储器访问方法包括：
步骤S601，接收数据读请求，确定读数据块和所述读数据块的目标存储组；
步骤S602，根据所述读数据块的目标存储组的组标识，确定所述读数据块的目标存储组对应的所述冗余消除单元的记录项；
步骤S603，将所述读数据块的标签与所述读数据块的目标存储组对应的所述冗余消除单元的记录项中的已存储的数据块的标签进行匹配；
步骤S604，判断匹配是否成功，若匹配失败，则执行步骤S605，若匹配成功，则执行步骤S606；
步骤S605，返回读数据块未命中信息；
步骤S606，若匹配成功，则确定匹配成功的记录位对应的存储块所在的存储路；
步骤S604，使能所述存储路信息对应的存储路。
如图7所示，为本发明实施例提供的计算机设备的结构组成示意图。本发明实施例的计算机可包括：
处理器701、内存702、系统总线704和通信接口705。处理器701、内存702和通信接口705之间通过系统总线704连接并完成相互间的通信。
处理器701可能为单核或多核中央处理单元，或者为特定集成电路，或者为被配置成实施本发明实施例的一个或多个集成电路。
存储器702可以为高速RAM存储器，也可以为非易失性存储器(non-volatile memory)，例如至少一个磁盘存储器。
存储器702用于计算机执行指令703。具体的，计算机执行指令703中可以包括程序代码。
当计算机运行时，处理器701运行计算机执行指令703，可以执行图6所述的方法流程。
本发明实施例还提供一种计算机可读介质，包括计算机执行指令，当计算机的处理器执行所述计算机执行指令时，所述计算机执行图6所述的方法流程。
本领域普通技术人员可以理解上述实施例的各种方法中的全部或部分步骤是可以通过程序来指令相关的硬件来完成，该程序可以存储于一计算机可读存储介质中，存储介质可以包括：ROM、RAM、磁盘或光盘等。
以上对本发明实施例所提供的数据写入装置及方法进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想；同时，对于本领域的一般技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。

Claims (20)

  1. 一种存储器的访问系统，包括：存储器、控制器与冗余消除单元；
    所述存储器，包括M×N个存储块，M行存储块组成M个存储组，N列存储块组成N个存储路，每个存储组设置有组标识，所述M或N为大于等于2的正整数；
    所述冗余消除单元，用于记录M条记录项，每条记录项对应于所述每个存储组，所述每条记录项用于保存所述每个存储组中已存储数据块的标签；
    所述控制器，用于接收数据读请求，确定读数据块和所述读数据块的目标存储组，向所述冗余消除单元发送查询消息，所述查询消息携带所述读数据块的目标存储组的组标识和所述读数据块的标签；
    所述冗余消除单元，用于根据所述读数据块的目标存储组的组标识，确定所述目标存储组的组标识对应的记录项，将所述读数据块的标签与所述读数据块的目标存储组对应的记录项中的已存储的数据块的标签进行匹配，若匹配失败，向所述控制器发送读数据块未命中的查询响应消息。
  2. 根据权利要求1所述的系统，其特征在于，
    所述控制器，还用于接收数据写请求，确定写数据块和所述写数据块的目标存储组，将所述写数据块存储到所述目标存储组中的目标存储块，并将所述写数据块的目标存储组的组标识以及所述写数据块的标签发送到所述冗余消除单元；
    所述冗余消除单元，还用于根据所述写数据块的目标存储组的组标识，在所述写数据块的目标存储组的组标识对应的记录项中记录所述写数据块的标签。
  3. 根据权利要求2所述的系统，其特征在于，所述冗余消除单元中的所述每条记录项包含N个记录位，每个记录位对应于所述每个存储组中每个存储块；
    所述冗余消除单元还用于将所述已存储的数据块的标签记录到所述已存储的数据块所在的存储组对应的记录项中对应的记录位中。
  4. 根据权利要求3所述的系统，其特征在于，所述冗余消除单元还用于，在将所述读数据块的标签与所述读数据块的目标存储组对应的记录项中的已存储的数据块的标签进行匹配成功时，确定匹配成功的记录位对应的存储块所在的存储路，将所述确定的存储路信息发送至所述控制器；
    所述控制器还用于根据所述确定的存储路信息使能所述确定的存储路信息对应的存储路。
  5. 根据权利要求1-4任意一项所述的系统，其特征在于，所述数据块的标签包括数据块对应的线程标识或者数据块的标识信息或者数据块对应的线程标识及数据块的标识的组合。
  6. 根据权利要求1-4所述的系统，其特征在于，当所述数据块的标签包括数据块对应的线程标识及数据块的标识信息，所述冗余消除单元在接收到所述查询消息后，具体用于：根据所述读数据块的目标存储组的组标识，将所述读数据块的线程标识与所述读数据块的目标存储组对应的记录项中的已存储的数据块的线程信息进行比较，若所述读数据块的线程标识与所述读数据块的目标存储组对应的记录项中的已存储的数据块的线程信息匹配成功，将所述读数据块的标识信息与所述读数据块的目标存储组对应的记录项中的匹配成功的已存储的数据块的数据块标识进行匹配，若所述读数据块的线程标识与所述读数据块的目标存储组对应的记录项中的已存储的数据块的线程信息匹配失败，则向所述控制器发送读数据未命中的查询响应消息。
  7. 一种存储器的访问系统，包括：存储器、控制器与冗余消除单元；
    所述存储器，包括M×N个存储块，M行存储块组成M个存储组，N列存储块组成N个存储路，每个存储组设置有组标识，所述M或N为大于等于2的正整数；
    所述冗余消除单元，用于记录M条记录项，每条记录项对应于所述每个存储组，所述每条记录项用于保存所述每个存储组中已存储数 据块的标签；
    所述控制器，用于接收数据读请求，确定读数据块和所述读数据块的目标存储组，根据所述读数据块的目标存储组的组标识查询所述冗余消除单元，将所述读数据块的标签与所述读数据块的目标存储组对应的记录项中的已存储的数据块的标签进行匹配，若匹配失败，返回读数据块未命中信息。
  8. 根据权利要求7所述的系统，其特征在于，
    所述控制器，还用于接收数据写请求，确定写数据块和所述写数据块的目标存储组，将所述写数据块存储到所述目标存储组中的目标存储块，并根据所述写数据块的目标存储组的组标识，在所述写数据块的目标存储组的组标识对应的记录项中记录所述写数据块的标签。
  9. 根据权利要求8所述的系统，其特征在于，所述冗余消除单元中的所述每条记录项包含N个记录位，每个记录位对应于所述每个存储组中每个存储块；
    所述控制器还用于将所述已存储的数据块的标签记录到所述已存储的数据块所在的存储组对应的记录项中对应的记录位中。
  10. 根据权利要求9所述的系统，其特征在于，所述控制器还用于，在将所述读数据块的标签与所述读数据块的目标存储组对应的记录项中的已存储的数据块的标签进行匹配成功时，确定匹配成功的记录位对应的存储块所在的存储路，并使能所述确定的存储路。
  11. 根据权利要求7-10任意一项所述的系统，其特征在于，所述数据块的标签包括数据块对应的线程标识或者数据块的标识信息或者数据块对应的线程标识及数据块的标识的组合。
  12. 根据权利要求7-10所述的系统，其特征在于，当所述数据块的标签包括数据块对应的线程标识及数据块的标识信息时，所述控制器在接收到所述查询消息后，具体用于：根据所述读数据块的目标存储组的组标识，将所述读数据块的线程标识与所述读数据块的目标存储组对应的记录项中的已存储的数据块的线程信息进行比较，若所述读数据块的线程标识与所述读数据块的目标存储组对应的记录项中的已存储的数据块的线程信息匹配成功，将所述读数据块的标识信息 与目标存储组对应的记录项中的匹配成功的已存储的数据块的数据块标识进行匹配，若所述读数据块的线程标识与所述读数据块的目标存储组对应的记录项中的已存储的数据块的线程信息匹配失败，则返回未命中的信息。
  13. 一种存储器的访问方法，应用于存储器访问系统，所述存储器访问系统包括存储器及冗余消除单元，所述存储器包括M×N个存储块，M行存储块组成M个存储组，N列存储块组成N个存储路每个存储组设置有组标识，所述M或N为大于等于2的正整数；所述冗余消除单元，记录M条记录项，每条记录项对应于所述每个存储组，所述每条记录项用于保存所述每个存储组中已存储数据块的标签；其特征在于，所述方法包括：
    接收数据读请求，确定读数据块和所述读数据块的目标存储组；
    根据所述读数据块的目标存储组的组标识查询所述冗余消除单元，将所述读数据块的标签与所述读数据块的目标存储组对应的所述冗余消除单元的记录项中的已存储的数据块的标签进行匹配，若匹配失败，返回读数据块未命中信息。
  14. 根据权利要求13所述的方法，其特征在于，还包括：
    接收数据写请求，确定写数据块和所述写数据块的目标存储组；
    将所述写数据块存储到所述目标存储组中的目标存储块；
    根据所述写数据块的目标存储组的组标识，在所述写数据块的目标存储组的组标识对应的记录项中记录所述写数据块的标签。
  15. 根据权利要求14所述的方法，其特征在于，所述冗余消除单元中的所述每条记录项包含N个记录位，每个记录位对应于所述每个存储组中每个存储块；
    所述方法还包括：将所述已存储的数据块的标签记录到所述已存储的数据块所在的存储组对应的记录项中对应的记录位中。
  16. 根据权利要求15所述的方法，其特征在于，所述方法还包括：在将所述读数据块的标签与所述读数据块的目标存储组对应的记录项中的已存储的数据块的标签进行匹配成功时，确定匹配成功的记录位对应的存储块所在的存储路，并使能所述确定的存储路。
  17. 根据权利要求13-16任意一项所述的方法，其特征在于，所述数据块的标签包括数据块对应的线程标识或者数据块的标识信息或者数据块的线程标识及数据块的标识的组合。
  18. 根据权利要求13-16任意一项所述的方法，其特征在于，当所述数据块的标签包括数据块对应的线程标识及数据块的标识信息时，在接收到所述查询消息后，所述方法具体包括：根据所述读数据块的目标存储组的组标识，将所述读数据块的线程标识与所述读数据块的目标存储组对应的记录项中的已存储的数据块的线程信息进行比较，若所述读数据块的线程标识与所述读数据块的目标存储组对应的记录项中的已存储的数据块的线程信息匹配成功，则将所述读数据块的标识信息与目标存储组对应的记录项中的匹配成功的已存储的数据块的数据块标识进行匹配，若所述读数据块的线程标识与所述读数据块的目标存储组对应的记录项中的已存储的数据块的线程信息匹配失败，并返回未命中的信息。
  19. 一种计算机设备，其特征在于，包括：处理器、第一存储器、总线、通信接口及第二存储器，所述第二存储器包括M×N个存储块，M行存储块组成M个存储组，N列存储块组成N个存储路，每个存储组设置有组标识，所述M或N为大于等于2的正整数，所述M或N为大于等于2的正整数；
    所述第一存储器用于存储计算机执行指令，所述处理器与所述第一存储器通过所述总线连接，当所述计算设备运行时，所述处理器执行所述第一存储器中存储的所述计算机执行指令，以使所述计算机设备执行如下方法：
    接收数据读请求，确定读数据块和所述读数据块的目标存储组；
    根据所述读数据块的目标存储组的组标识查询冗余消除单元，所述冗余消除单元记录M条记录项，每条记录项对应于所述每个存储组，所述每条记录项用于保存所述每个存储组中已存储数据块的标签；
    将所述读数据块的标签与所述读数据块的目标存储组对应的所述冗余消除单元的记录项中的已存储的数据块的标签进行匹配；
    若匹配失败，返回读数据块未命中信息。
  20. 一种计算机可读介质，其特征在于，包括计算机执行指令，当计算机的处理器执行所述计算机执行指令时，所述计算机执行如下方法：
    接收数据读请求，确定读数据块和所述读数据块所在的存储器的目标存储组，所述存储器包括M×N个存储块，M行存储块组成M个存储组，N列存储块组成N个存储路，每个存储组设置有组标识，所述M或N为大于等于2的正整数，所述M或N为大于等于2的正整数；
    根据所述读数据块的目标存储组的组标识查询冗余消除单元，所述冗余消除单元记录M条记录项，每条记录项对应于所述每个存储组，所述每条记录项用于保存所述每个存储组中已存储数据块的标签；
    将所述读数据块的标签与所述读数据块的目标存储组对应的所述冗余消除单元的记录项中的已存储的数据块的标签进行匹配；
    若匹配失败，返回读数据块未命中信息。
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