WO2016187790A1 - 一种otg外设、供电方法、终端及系统 - Google Patents

一种otg外设、供电方法、终端及系统 Download PDF

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Publication number
WO2016187790A1
WO2016187790A1 PCT/CN2015/079735 CN2015079735W WO2016187790A1 WO 2016187790 A1 WO2016187790 A1 WO 2016187790A1 CN 2015079735 W CN2015079735 W CN 2015079735W WO 2016187790 A1 WO2016187790 A1 WO 2016187790A1
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WO
WIPO (PCT)
Prior art keywords
power
usb interface
interface
circuit
terminal
Prior art date
Application number
PCT/CN2015/079735
Other languages
English (en)
French (fr)
Inventor
袁江峰
常智
崔罡
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2015/079735 priority Critical patent/WO2016187790A1/zh
Priority to EP15892871.3A priority patent/EP3291050A4/en
Priority to US15/576,699 priority patent/US10564697B2/en
Priority to CN201580014521.5A priority patent/CN106537286B/zh
Publication of WO2016187790A1 publication Critical patent/WO2016187790A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3253—Power saving in bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/263—Arrangements for using multiple switchable power supplies, e.g. battery and AC
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0042—Universal serial bus [USB]
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries

Definitions

  • the present invention relates to the field of power supply technologies, and in particular, to an OTG peripheral, a power supply method, a terminal, and a system.
  • the existing terminals support the USB OTG (Universal Serial Bus, On-The-Go) function.
  • OTG is a complementary standard to the USB specification that enables a USB device, such as a mobile phone, to become a USB host (Host).
  • the smart terminal as a USB host device can be connected to a USB peripheral such as a mobile hard disk with a USB interface, an input device, and a card reader to access and communicate.
  • the USB peripherals such as the mobile hard disk, the input device, and the card reader connected to the smart terminal are powered by the smart terminal, so that the power consumption of the smart terminal is excessively fast.
  • the USB peripheral needs to be removed to charge the smart terminal, and the OTG communication between the smart terminal and the USB peripheral is interrupted.
  • Embodiments of the present invention provide an OTG peripheral, a power supply method, a terminal, and a system, which are capable of simultaneously implementing a master device connected to the OTG peripheral and a slave connected to the OTG peripheral during an OTG communication process.
  • the device is powered.
  • an OTG peripheral including: a delay conduction circuit, a detection circuit, a first USB interface, a power interface, and a second USB interface, wherein:
  • the first USB interface is connected to the second USB interface; the ID pin of the first USB interface is connected to a low level;
  • the power interface is connected to the power pin of the first USB interface through the delay conduction circuit, and is configured to delay power supply to the first USB interface after the power interface is powered on;
  • the detecting circuit is respectively connected to the ID pin of the first USB interface and the power interface, and the detecting circuit is configured to send an ID tube to the first USB interface when detecting that the power interface is powered on.
  • the foot outputs a high level pulse for triggering the connection at the terminal of the first USB interface to stop to the second USB interface power supply;
  • the power interface is connected to the power pin of the second USB interface, and is configured to supply power to the second USB interface after the power interface is powered on.
  • the detecting circuit is further configured to output a high-level pulse to an ID pin of the first USB interface when detecting that the power interface is powered off.
  • the terminal for triggering connection on the first USB interface supplies power to the second USB interface;
  • the peripheral device further includes: a power storage circuit, the power storage circuit, and the power source An interface is connected to the power supply pin of the second USB interface, and is configured to store power of the power interface after the power interface is powered on, and send the power to the second USB after the power interface is powered off. Interface power supply.
  • the power terminal of the detecting circuit is connected to the power pin of the second USB interface, And for receiving power from the power interface or the first USB interface.
  • a power terminal of the detecting circuit is connected to a power pin of the second USB interface, and is configured to receive the power source An interface, or the first USB interface, or a power supply of the power storage circuit.
  • the delay conducting circuit includes: Switching circuit and delay circuit, wherein:
  • the delay circuit controls an on time of the switch circuit
  • the switch circuit When the switch circuit is turned on, the circuit between the power interface and the power pin of the first USB interface is a path; when the switch circuit is turned off, the power interface and the power pipe of the first USB interface The circuit between the feet is an open circuit.
  • the detecting circuit includes: dual-stable a trigger circuit, wherein: a falling edge trigger input terminal of the first monostable trigger circuit of the dual monostable trigger circuit is connected to the power interface, and a rising edge trigger input end of the first monostable trigger circuit Connected to a low level;
  • a falling edge trigger input terminal of the second monostable trigger circuit of the dual monostable trigger circuit is connected to a power pin of the second USB interface; and a second one-shot trigger of the dual one-shot trigger circuit a rising edge trigger input of the circuit is coupled to the power interface;
  • An output end of the first monostable trigger circuit and an output end of the second monostable trigger circuit output a signal through an OR gate, and an output end of the OR gate circuit and an ID tube of the first USB interface Connected to the feet;
  • the dual monostable trigger circuit is configured to output the high level pulse signal through the OR gate circuit on both a rising edge and a falling edge of a signal of the power interface.
  • the delay conducting circuit further includes a second resistor;
  • the switching circuit is a P-type MOS transistor switching circuit;
  • the delay circuit includes: a first capacitor connected in series and a first resistor, wherein: the first capacitor is connected in parallel at both ends of the gate and the source of the MOS transistor, and the gate of the MOS transistor passes the first a resistor is grounded, a source of the MOS transistor is connected to the power interface, a drain of the MOS transistor is connected to a power pin of the first USB interface; and both ends of the gate and the source of the MOS transistor
  • the second resistor is also connected in parallel, and the second resistor is used to adjust a voltage between a gate and a source of the MOS transistor.
  • the delay conducting circuit further includes a second capacitor, and the gate and the source of the P-type MOS transistor The second capacitor is further connected in parallel; the second capacitor is smaller than the first capacitor, and is used to raise a gate voltage of the P-type MOS transistor to the power interface when the power interface is powered on.
  • the power supply voltage is such that the P-type MOS transistor is in an off state.
  • the delay-on-conducting circuit further includes: a boosting circuit and a fourth resistor;
  • the switching circuit is an N-type MOS transistor a switching circuit, the delay circuit includes: a third resistor and a third capacitor connected in series; a source of the N-type MOS transistor is connected to a power pin of the first USB interface, and a drain of the N-type MOS transistor The power interface is connected, the gate of the N-type MOS transistor is grounded through the third capacitor; the power input end of the booster circuit is connected to the power interface, and the power output terminal of the booster circuit passes through The third resistor is connected to the gate of the N-type MOS transistor for increasing the gate voltage of the N-type MOS transistor; the fourth resistor is connected in parallel with the third capacitor for adjusting the N-type The gate voltage of the MOS transistor.
  • the power storage circuit includes: a fifth resistor and a fourth capacitor connected in series, wherein: the fifth resistor and the power pin of the second USB interface Connected, the fourth capacitor is grounded.
  • the peripheral device further includes: a unidirectional conduction device, the first unidirectional conduction device is connected in series between the delay conduction circuit and a power pin of the first USB interface, and the first unidirectional conduction device is used to cut off the first A USB interface flows back to the power supply interface through the delay-on conduction circuit that is turned on.
  • the peripheral device further includes:
  • the second unidirectional pass device is connected in series between the detecting circuit and an ID pin of the first USB interface, and the second unidirectional pass device is used to cut off the detecting circuit
  • the high level pulse of the output is directed to the first USB interface.
  • the peripheral device further includes: a third unidirectional pass device, the third unidirectional pass device is connected in series between the power pin of the second USB interface and the power interface, the third unidirectional pass device And a reverse current for cutting off the first USB interface to the power interface.
  • the peripheral device further includes: a third unidirectional pass device, the third unidirectional pass device is connected in series between the power pin of the second USB interface and the power interface, and the third A one-way pass device is used to cut back the current flowing from the power storage circuit and/or the first USB interface to the power interface.
  • the peripheral device further includes: a fourth unidirectional device, wherein the fourth unidirectional device is connected in series The fourth unidirectional pass device is configured to cut off a current of the power interface to the first USB interface between a power pin of the first USB interface and a power pin of the second USB interface.
  • the peripheral device further includes: a fourth unidirectional device, the fourth unidirectional device is connected in series at the first USB interface Between the power pin of the second USB interface and the power pin of the second USB interface, the fourth unidirectional pass device is configured to cut off the current of the power storage circuit and/or the power interface to the first USB interface.
  • a power supply method including:
  • the terminal recognizes that the OTG peripheral is inserted into the preset USB interface; the OTG peripheral includes: a delay conducting circuit, a detecting circuit, a first USB interface, a power interface, and a second USB interface, wherein: the first USB interface is The second USB interface is connected; the ID pin of the first USB interface is connected to a low level; the power interface is connected to the power pin of the first USB interface through the delay conduction circuit, and is used for Delaying power supply to the first USB interface after the power interface is powered on; the detecting circuit is respectively connected to the ID pin of the first USB interface and the power interface, and the detecting circuit is configured to detect When the power interface is powered on or off, the high-level pulse is output to the ID pin of the first USB interface; the power interface is connected to the power pin of the second USB interface, and is used to After the power interface is powered on, the second USB interface is powered;
  • the terminal When the terminal detects a high level pulse at the ID pin of the preset USB interface, the terminal responds to the high level pulse to determine whether the terminal is currently in a state of supplying power to the second USB interface, and if so, Stop supplying power to the second USB interface, and receive power supply of the power interface through the preset USB interface, and if not, supply power to the second USB interface.
  • the method further includes:
  • the terminal detects that there is power on the power pin of the preset USB interface, performing the step of stopping power supply to the second USB interface, and receiving power supply of the power interface through the preset USB interface.
  • a terminal including:
  • An identification module configured to identify that the OTG peripheral is inserted into the preset USB interface;
  • the OTG peripheral includes: a delay conduction circuit, a detection circuit, a first USB interface, a power interface, and a second USB interface, wherein: a USB interface is connected to the second USB interface; an ID pin of the first USB interface is connected to a low level; and the power interface passes through the delay conduction circuit and a power pin of the first USB interface Connected to delay power supply to the first USB interface after powering on the power interface;
  • the detecting circuit is respectively connected to an ID pin of the first USB interface and the power interface, and the detecting circuit And configured to output a high-level pulse to an ID pin of the first USB interface when the power interface is powered on or off;
  • the power interface is connected to a power pin of the second USB interface, Used to supply power to the second USB interface after the power interface is powered on;
  • a determining module configured to: when the terminal detects a high level pulse at the ID pin of the preset USB interface, determine, according to the high level pulse, whether the terminal is currently powered by the second USB interface status;
  • a first management module configured to stop supplying power to the second USB interface when the determination result output by the determining module is YES, and receive power supply of the power interface by using the preset USB interface;
  • the second management module is configured to supply power to the second USB interface when the determination result output by the determining module is negative.
  • the terminal further includes: a third management module, configured to: when the identification module recognizes that the OTG peripheral is inserted into a preset USB interface on the terminal, If the terminal detects that there is power on the power pin of the preset USB interface, performing the step of stopping power supply to the second USB interface, and receiving power supply of the power interface through the preset USB interface.
  • a third management module configured to: when the identification module recognizes that the OTG peripheral is inserted into a preset USB interface on the terminal, If the terminal detects that there is power on the power pin of the preset USB interface, performing the step of stopping power supply to the second USB interface, and receiving power supply of the power interface through the preset USB interface.
  • a terminal including:
  • the processor reads instructions stored in the memory for performing the following steps:
  • the OTG peripheral includes: a delay conducting circuit, a detecting circuit, a first USB interface, a power interface, and a second USB interface, wherein: the first USB interface Connected to the second USB interface; the ID pin of the first USB interface is connected to a low level; the power interface is connected to the power pin of the first USB interface through the delay conduction circuit, Delaying power supply to the first USB interface after powering on the power interface; the detecting circuit respectively The ID pin of the first USB interface is connected to the power interface, and the detecting circuit is configured to output a high output to the ID pin of the first USB interface when detecting that the power interface is powered on or off. a level pulse; the power interface is connected to the power pin of the second USB interface, and is configured to supply power to the second USB interface after the power interface is powered on;
  • the processor When detecting a high level pulse at the ID pin of the preset USB interface, the processor responds to the high level pulse to determine whether the terminal is currently in a state of supplying power to the second USB interface, and if And stopping power supply to the second USB interface, and receiving power supply of the power interface through the preset USB interface, and if not, supplying power to the second USB interface.
  • the method further includes: if the terminal detects the power pin of the preset USB interface If there is power, perform the step of stopping power supply to the second USB interface, and receiving power supply of the power interface through the preset USB interface.
  • a power supply system including: an OTG peripheral and a terminal, wherein:
  • the OTG peripheral includes: a delay conduction circuit, a detection circuit, a first USB interface, a power interface, and a second USB interface, wherein: the first USB interface is connected to the second USB interface; The ID pin of the USB interface is connected to the low level; the power interface is connected to the power pin of the first USB interface through the delay conduction circuit, and is configured to delay the power supply after the power interface is powered on.
  • the detection circuit is respectively connected to the ID pin of the first USB interface and the power interface, and the detecting circuit is configured to detect, when the power interface is powered on or off, Outputting a high-level pulse to the ID pin of the first USB interface;
  • the power interface is connected to the power pin of the second USB interface, and is configured to power on the second USB interface after the power interface is powered on Interface power supply;
  • the terminal identifies that the OTG peripheral is inserted into a preset USB interface of the terminal, and the preset USB interface is connected to the first USB interface; when the terminal detects the ID tube of the preset USB interface When the high-level pulse is at the foot, the terminal responds to the high-level pulse to determine whether the terminal is currently in a state of supplying power to the second USB interface, and if so, stops supplying power to the second USB interface. Receiving power to the power interface through the preset USB interface, and if not, supplying power to the second USB interface.
  • the OTG peripheral is an OTG peripheral described in the foregoing first aspect, and details are not described herein again.
  • the terminal is a terminal described in the foregoing third aspect, and details are not described herein again.
  • the system further includes: a USB slave device, wherein the USB slave device is connected to the OTG peripheral through a second USB interface of the OTG peripheral .
  • the system further includes: a power source, wherein the power source is connected to the OTG peripheral through a power interface of the OTG peripheral.
  • the OTG peripheral when the power is inserted into the OTG peripheral, the OTG peripheral outputs a high-level pulse to the terminal through the first USB interface, so as to trigger the terminal to stop supplying power to the USB slave device, and is powered on.
  • the power supply supplies power to the USB slave device, and waits for a preset safety time to enable the power supply to supply power to the USB slave device after the terminal stops supplying power to the terminal, thereby simultaneously connecting to the OTG peripheral during the OTG communication process.
  • the master device and the slave device connected to the OTG peripheral are powered.
  • FIG. 1 is a schematic structural diagram of a power supply system according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of an OTG peripheral device according to an embodiment of the present invention.
  • FIG. 3 is a flowchart of a power supply method on a terminal side according to an embodiment of the present invention.
  • FIG. 4 is a circuit structural diagram of an OTG peripheral provided by an embodiment of the present invention.
  • FIG. 5 is another circuit structural diagram of an OTG peripheral provided by an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a first embodiment of a terminal according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of a second embodiment of a terminal according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a third embodiment of a terminal according to an embodiment of the present invention.
  • the embodiment of the invention discloses a power supply system, an OTG peripheral, a power supply method on the terminal side, and a terminal, which can be implemented as a main device connected to the OTG peripheral and a slave device connected to the OTG peripheral. And does not interrupt OTG communication between the master device and the slave device.
  • FIG. 1 is a schematic structural diagram of a power supply system according to an embodiment of the present invention.
  • the power supply system may include an OTG peripheral 100, a terminal 200, a USB slave device 300, and a power source 400.
  • the terminal 200 is connected to the OTG peripheral 100 through the first USB interface 101
  • the USB slave device 300 is connected to the OTG peripheral 100 through the second USB interface 103.
  • the terminal 200 and the USB slave device 300 have OTG communication. among them:
  • the power supply 400 is configured to supply power to the terminal 200 and the USB slave device 300 connected to the OTG peripheral 100 after being connected to the OTG peripheral 100;
  • the OTG peripheral 100 is configured to output a high level pulse to the terminal 200 through the first USB interface 101 when the power source 400 is inserted into the OTG peripheral 100, to trigger the terminal 200 to stop supplying power to the USB slave device 300; the OTG peripheral 100 is used to When the power supply 400 is pulled out of the OTG peripheral 100, a high-level pulse is output to the terminal 200 through the first USB interface 101 to trigger the terminal 200 to supply power to the USB slave device 300;
  • the OTG peripheral device 100 is further configured to wait for a preset safety time after the power source 400 is inserted into the OTG peripheral device 100, so that the power source 400 supplies power to the terminal 200 after the terminal 200 stops supplying power to the USB slave device 300.
  • the terminal 200 is configured to receive a high-level pulse output by the first USB interface 101, and determine, according to the high-level pulse, that the power supply 400 is inserted or removed from the OTG peripheral device 100. When it is determined that the power source 400 is inserted into the OTG peripheral 100, the terminal 200 stops supplying power to the USB slave device 300 and receives power supply from the power source 400; when it is determined that the power source 400 is pulled out of the OTG peripheral 100, the terminal 200 supplies power to the USB slave device 300. .
  • the working principle of the foregoing power supply system may include:
  • the OTG peripheral 100 When the power supply 400 is plugged into the OTG peripheral 100 (the power interface 102 is powered), the OTG peripheral 100 The power supply voltage is quickly directed to the second USB interface 103 to cause the USB slave device 300 to receive power from the power source 400. At the same time, the OTG peripheral 100 waits for the preset safety time, and then directs the power supply voltage to the first USB interface 101 to cause the terminal 200 to receive power from the power supply 400.
  • the OTG peripheral 100 When the power supply 400 is inserted into the OTG peripheral 100 (the power interface 102 is powered on), the OTG peripheral 100 also outputs a high level pulse through the first USB interface 101 to trigger the terminal 200 to stop supplying power to the USB slave device 300.
  • the terminal 200 After receiving the high level pulse outputted by the first USB interface 101, the terminal 200 determines that the power source 400 is inserted into the OTG peripheral 100 according to the high level pulse, and stops supplying power to the USB slave device 300.
  • the terminal 200 After stopping the supply of power to the USB slave device 300, the terminal 200 receives the power of the power source 400. It should be noted that the foregoing security time that the OTG peripheral 100 waits may be long enough to enable the terminal 200 to complete the process of stopping the supply of power to the USB slave device 300, and to securely receive the power of the power source 400.
  • the OTG peripheral 100 When the power supply 400 pulls out the OTG peripheral 100 (the power interface 102 is powered off), the OTG peripheral 100 outputs a high level pulse through the first USB interface 101 to trigger the terminal 200 to start supplying power to the USB slave device 300.
  • the terminal 200 After receiving the high-level pulse outputted by the first USB interface 101, the terminal 200 determines, according to the high-level pulse, that the power supply 400 pulls out the OTG peripheral 100 and starts supplying power to the USB slave device 300.
  • FIG. 2 is a schematic structural diagram of an OTG peripheral provided by an embodiment of the present invention.
  • the OTG peripheral includes: a delay conduction circuit 104, a detection circuit 105, a first USB interface 101, a power interface 102, and a second USB interface 103, wherein:
  • the first USB interface 101 is connected to the second USB interface 103; the ID pin of the first USB interface 101 is connected to a low level;
  • the power interface 102 is connected to the power pin of the first USB interface 101 through the delay conduction circuit 104, and is configured to delay power supply to the first USB interface 101 after the power interface 102 is powered on;
  • the detecting circuit 105 is respectively connected to the ID pin of the first USB interface 101 and the power interface 102.
  • the detecting circuit 105 is configured to output to the ID pin of the first USB interface 101 when detecting that the power interface 102 is powered on. a high level pulse for triggering the terminal connected to the first USB interface 101 to stop supplying power to the second USB interface 103;
  • the power interface 102 is connected to the power pin of the second USB interface 103 for supplying power to the second USB interface 103 after the power interface 102 is powered on.
  • the first USB interface 101 is connected to the second USB interface 103, and may include: a digital pin (D+, D-) of the first USB interface 101 and a second USB interface 103.
  • the digital pins (D+, D-) are connected to enable OTG communication between the terminal connected to the first USB interface 101 and the USB slave device connected to the second USB interface 103.
  • the first USB interface 101 is connected to the second USB interface 103, and may further include: the power pin of the first USB interface 101 is connected to the power pin of the second USB interface 103.
  • the terminal connected to the first USB interface 101 and the USB slave device connected to the second USB interface 103 perform OTG communication, the terminal supplies power to the USB slave device, that is, the terminal supplies power to the power bus. .
  • the power bus involved in the embodiment refers to a bus formed by connecting a power pin of the first USB interface 101 and a power pin of the second USB interface 103 to provide power to the USB slave device in the OTG communication.
  • the USB bus that is connected to the ID pin is always powered to the power bus. That is, in the embodiment of the present invention, when the power interface 102 is not powered, the terminal connected to the first USB interface 101 always supplies power to the power bus, that is, the terminal supplies power to the USB slave device.
  • the power supply state of the terminal to the power bus can be further determined by the detection circuit 105.
  • the detection circuit 105 When the power interface 102 is powered on, the detection circuit 105 outputs high power to the ID pin of the first USB interface 101.
  • the flat pulse triggers the terminal to stop supplying power to the power bus; when the power interface 102 is powered off, the detecting circuit 105 outputs a high level pulse to the ID pin of the first USB interface 101 to trigger the terminal to start supplying power to the power bus.
  • the delay conduction circuit 104 is first in an off state, and is in a conduction state after waiting for a preset safety time.
  • the preset safety time is used to ensure that the terminal connected to the first USB interface 101 detects the high level pulse outputted by the detection circuit 105 and stops supplying power to the power bus before the delay conduction circuit 104 is turned on. .
  • the OTG peripheral device shown in FIG. 2 may further include: a power storage circuit 106.
  • the power storage circuit 106 is connected to the power interface 102 for storing the power of the power interface 102 after the power interface 102 is powered on.
  • the power storage circuit 106 is connected to the power pin of the second USB interface 103 for supplying power to the second USB interface 103 after the power interface 102 is powered off.
  • the power storage circuit 106 can realize the timely connection after the power interface 102 is powered off before the terminal supplies power to the power bus (because the circuit unit connected to the terminal of the first USB interface 101 and the detection circuit 105 may generate a delay) Powering the USB slave device of the second USB interface 103 can avoid interruption of OTG communication between the terminal and the USB slave device.
  • the OTG peripheral provided by the embodiment of the present invention may further include: a first unidirectional device 107 as shown in FIG. 2 .
  • the first unidirectional via device 107 is connected in series between the delay conducting circuit 104 and the power pin of the first USB interface 101 for turning off the first USB interface 101 and flowing to the power interface 102 through the turned-on delay conducting circuit 104. Reverse current.
  • the OTG peripheral may further include a second unidirectional device 108 as shown in FIG. 2 .
  • the second unidirectional pass device 108 is connected in series between the detecting circuit 105 and the ID pin of the first USB interface 101, and the high-level pulse for the output of the cut-off detecting circuit 105 is supplied to the first USB interface 101.
  • the OTG peripheral may further include a third unidirectional device as shown in FIG. 2 . 109.
  • the third unidirectional pass device 109 is connected in series between the power pin of the second USB interface 103 and the power interface 102 for turning off the first USB interface 101 to the power interface 102 (when the first USB interface supplies power to the second USB interface 103) ) the reverse current.
  • the third unidirectional pass device 109 can also be used to cut off the reverse current flowing from the power storage circuit 106 to the power interface 102.
  • the OTG peripheral provided by the embodiment of the present invention may further As shown in FIG. 2, a fourth unidirectional pass device 110 is included.
  • the fourth unidirectional pass device 110 is connected in series between the power pin of the first USB interface 101 and the power pin of the second USB interface 103, and is used for cutting off the power interface 102 to directly flow to the first USB interface 101. Current through the circuit).
  • the fourth unidirectional conduction device 110 can also be used to cut off the reverse current flowing from the power storage circuit 106 to the power interface 102.
  • first unidirectional pass device 107, the second unidirectional pass device 108, the third unidirectional pass device 109 or the fourth unidirectional pass device 110 may be an active diode or an ultra low dropout diode, such as Xiao. Special base diode.
  • other embodiments having the one-way rectification and conduction function can also be used in the implementation of the embodiment, which is not limited herein.
  • the power terminal of the detecting circuit 105 can be connected to the power pin of the second USB interface 103.
  • the power pin of the second USB interface 103 can receive power from the power interface 102, or the first USB interface 101, or the power storage circuit 106. Therefore, the level of the power pin of the second USB interface 103 can be maintained at a high level to provide stable power supply to the detecting circuit 105.
  • the level of the power pin of the second USB interface 103 is always a high level, which can provide stable power supply to the USB slave device connected to the second USB interface 103, and ensure the OTG between the terminal and the terminal. Communication is not interrupted.
  • the power interface 102 in the embodiment of the present invention may be a USB interface that does not provide a digital pin, or may be another standard power interface that can provide a matching voltage to the first USB interface 101, which is not limited herein.
  • the second USB interface 103 in the embodiment of the present invention may be a USB interface (ID foot floating) that provides an ID pin, or a USB interface that does not provide an ID pin.
  • FIG. 3 is a flowchart of a power supply method on the terminal side according to an embodiment of the present invention.
  • the power supply system shown in FIG. 1 and the OTG peripheral device shown in FIG. 2 are explained in detail below, and the power supply method on the terminal side is explained in detail.
  • the method includes:
  • the terminal recognizes that the OTG peripheral is inserted into the preset USB interface.
  • the terminal may be the terminal 200 in FIG. 1
  • the OTG peripheral device may be the OTG peripheral device 100 in FIG. 1 or the OTG peripheral device 100 shown in FIG. 2 , and details are not described herein again.
  • the preset USB interface is a USB interface connected to the first USB interface 101 of the OTG peripheral 100 on the terminal.
  • the terminal may determine whether the OTG peripheral device 100 is inserted into the preset USB interface by using a level of an ID pin of the preset USB interface. If the level of the ID pin of the preset USB interface is low, the terminal may determine that the OTG peripheral 100 is inserted into the preset USB interface. It can be understood that the ID pin of the first USB interface 101 of the OTG peripheral 100 is connected to a low level, so when the OTG peripheral 100 passes the first USB When the interface 101 is connected to the preset USB interface of the terminal, the ID pin of the preset USB interface is also at a low level.
  • the terminal determines whether it is currently in a state of supplying power to the second USB interface.
  • the detecting circuit 105 of the OTG peripheral 100 detects that the power interface 102 is powered on or off, the detecting circuit 105 outputs a high level pulse to the ID pin of the first USB interface 101. That is, when the detecting circuit 105 in the OTG peripheral 100 detects that the power interface 102 is powered on or off, the terminal can receive the high level pulse outputted by the detecting circuit 105 through the preset USB interface.
  • the terminal may determine that the high level pulse is generated by the power source 400 being inserted into the power interface 102 of the OTG peripheral 100. If the terminal is not in a state of supplying power to the second USB interface through the preset USB interface, the terminal may determine that the high level pulse is extracted from the power interface 102 of the OTG peripheral 100 by the power source 400. produced.
  • the terminal can locally maintain the state in which the power source 400 is inserted or removed from the OTG peripheral 100.
  • the terminal may invert the plugged state of the currently maintained power source 400.
  • the initial state of the power supply 400 maintained locally by the terminal is that the power supply 400 pulls out the OTG peripheral 100. Then, when the terminal receives a high level pulse, the state of the power supply 400 locally maintained by the terminal is reversed as: the power source 400 is inserted into the OTG peripheral 100.
  • the terminal may execute S105; when the determination structure of S103 is NO, the terminal may perform S107.
  • S105 The terminal stops supplying power to the second USB interface, and receives power supply of the power interface of the OTG peripheral through the preset USB interface.
  • the terminal can immediately stop outputting the voltage to the second USB interface through the preset USB interface.
  • the terminal receives power from the power interface 102 through the power pin of the preset interface.
  • the terminal supplies power to the second USB interface.
  • the terminal 102 can immediately start outputting a voltage to the second USB interface through the preset USB interface for supplying power to the USB slave device connected to the second USB interface 103 of the OTG peripheral 100, which can be avoided.
  • the OTG communication between the USB slave device and the terminal is interrupted.
  • the power storage circuit 106 in the OTG peripheral 100 shown in FIG. 2 can realize that after the power supply 400 is pulled out of the OTG peripheral 100, the power storage circuit 106 is connected before the terminal supplies power to the second USB interface.
  • the USB slave device of the second USB interface 103 of the OTG peripheral 100 supplies power to avoid an OTG communication terminal between the USB slave device and the terminal.
  • the terminal when the S101 is executed, the terminal may further detect whether there is power on the power pin of the preset USB interface, and if there is power on the power pin of the preset USB interface, execute S105.
  • the terminal may determine that the power supply 400 has been inserted into the power interface 102 of the OTG peripheral 100 before the OTG peripheral 100 is inserted into the preset USB interface of the terminal. Then, the terminal does not need to supply power to the second USB interface, and the power supply from the power interface 102 can be directly received through the preset USB interface.
  • the terminal determines whether the power is inserted into the OTG peripheral according to the high level pulse outputted by the OTG peripheral. If the power is inserted into the OTG peripheral, the terminal stops connecting to the OTG peripheral.
  • the upper USB slave device supplies power and receives power from the power source after a preset safe time. If the power source pulls out the OTG peripheral, the terminal starts to supply power to the USB slave device connected to the OTG peripheral, which can be implemented as A master device connected to the OTG peripheral and a slave device connected to the OTG peripheral are powered without interrupting OTG communication between the master device and the slave device.
  • FIG. 4 further shows a circuit structure diagram of an OTG peripheral provided by an embodiment of the present invention.
  • the embodiment of FIG. 4 is an implementation of the embodiment of FIG. 2. What is not mentioned in the embodiment of FIG. 4, reference may be made to the description of the embodiment of FIG. 2.
  • the switching circuit in the delay conducting circuit 104 is a P-type MOS transistor switching circuit. The basic structure of each circuit unit in the OTG peripheral will be described in detail below with reference to FIG. among them:
  • the delay conduction circuit 104 in the rectangular dotted frame may include: a switching circuit (P-type MOSFET (PMOSFET) in a circular dotted frame) and a delay circuit (first capacitor C1 and first resistor) R1, second resistor R2).
  • a switching circuit P-type MOSFET (PMOSFET) in a circular dotted frame
  • a delay circuit first capacitor C1 and first resistor R1, second resistor R2.
  • the delay circuit controls an on-time of the switch circuit, that is, the preset safety time.
  • the switch circuit When the switch circuit is turned on, the circuit between the power interface 102 and the power pin of the first USB interface 101 is a path.
  • the switch circuit When the switch circuit is turned off, the circuit between the power interface 102 and the power pin of the first USB interface 101 is open.
  • the first capacitor C1 and the first resistor R1 are connected in series; the first capacitor C1 is connected in parallel to the gate (G pole) and the source (S pole) of the P-type MOS transistor. Both ends; the gate of the P-type MOS transistor is grounded through the first resistor R1, the source of the P-type MOS transistor is connected to the power interface 102, the drain of the P-type MOS transistor (D-pole) and the power supply of the first USB interface 101
  • the pin (VBUS pin) is connected; the second resistor R2 is also connected in parallel between the gate and the source of the P-type MOS transistor, and the second resistor R2 is used to adjust the voltage between the gate and the source of the P-type MOS transistor. .
  • the first capacitor C1 and the first resistor R1 determine the delay time of the P-type MOS transistor in FIG. 2 to delay the conduction.
  • the size of the first resistor R1 and the first capacitor C1 is selected, where: R is the first resistor R1, C is the first capacitor C1, U is the output voltage of the power interface 102, and Uc is the voltage across the first capacitor C1.
  • the first resistor R1 and the second resistor R2 determine the voltage that finally falls between the gate and the source of the P-type MOS transistor, that is, after the power interface 102 is powered on, after the preset safety time.
  • the gate voltage of the P-type MOS transistor is the voltage division across the first resistor R1.
  • after the preset safety time, the P-type MOS transistor can finally be stabilized.
  • Ugs(th) is the turn-on voltage of the P-type MOS transistor
  • Ug is the gate voltage of the P-type MOS transistor
  • Us is the source voltage of the P-type MOS transistor.
  • the delay conducting circuit 104 further includes: a second capacitor C2 connected in parallel across the gate and the source of the P-type MOS transistor.
  • the second capacitor C2 is smaller than the first capacitor C1.
  • a nano-level (nF) capacitor can be used for quickly raising the gate voltage of the P-type MOS transistor to the P-type when the power interface 102 is powered on.
  • the source voltage of the MOS transistor is such that the P-type MOS transistor is in an off state, preventing the P-type MOS transistor from being mis-conductive.
  • the switch circuit according to the embodiment of the present invention may include: a triode switch circuit, a FET switch circuit, or other circuit unit capable of simulating a switch function, which is not limited herein.
  • the delay circuit according to the embodiment of the invention may include: an RC delay circuit, a timer delay circuit, and the like The circuit unit of the delay function is not limited herein.
  • the detection circuit 105 within the rectangular dashed box may include a dual monostable trigger circuit U1.
  • the dual monostable trigger circuit U1 includes a first monostable trigger circuit U1A and a second monostable trigger circuit U1B. among them:
  • the function table of the first monostable trigger circuit U1A provided in the embodiment of FIG. 4 is as shown in Table 1:
  • the function table of the second monostable trigger circuit U1B provided in the embodiment of FIG. 4 is as shown in Table 2:
  • the first monostable trigger circuit U1A of the dual monostable trigger circuit U1 The falling edge trigger input terminal 4 (input: High to Low triggered) is connected to the power interface 102, and the rising edge of the first monostable trigger circuit U1A triggers the input terminal 5 (input: Low to High triggered) to be connected to the low level (or Ground).
  • the external capacitor C3 and the resistor R3 can be used to control the pulse width of the output of the output terminal Q1.
  • the falling edge trigger input terminal 10 of the second monostable trigger circuit U1 of the dual monostable trigger circuit U1 is connected to the power pin of the second USB interface 103; the dual monostable trigger circuit U1
  • the rising edge trigger input terminal 11 of the second monostable trigger circuit U1B is connected to the power interface 102.
  • the level of the power pin of the second USB interface 103 is always at a high level, that is, the falling edge trigger input terminal 10 is always at a high level.
  • the external capacitor C4 and the resistor R4 can be used to control the pulse width of the output of the output terminal Q2.
  • the detection circuit 105 further comprises: an OR circuit U2.
  • the output terminal 6 of the first monostable trigger circuit U1A and the output terminal 8 of the second monostable trigger circuit U1B output a signal via the OR circuit U2, or the output terminal of the gate circuit U2 and the ID pin of the first USB interface 101 Connected.
  • the detection circuit provided in the embodiment of FIG. 4 can realize that the high-level pulse signal is output through the OR circuit U2 on both the rising edge and the falling edge of the signal of the power interface 102. That is, when the power interface 102 is powered on (generating a rising edge signal), or when the power interface 102 is powered off (generating a falling edge signal), the OR circuit U2 outputs a high level pulse to the first USB interface 101.
  • the ID pin is used to trigger the device connected to the first USB interface 101 to stop or start external power supply.
  • the power storage circuit 106 in the rectangular dotted line frame may include: a fifth resistor R7 and a fourth capacitor C3 connected in series, wherein the fifth resistor R7 is connected to the power pin of the second USB interface 103, and fourth Capacitor C3 is grounded.
  • the fourth capacitor C3 begins to conserve power.
  • the fourth capacitor C3 starts to discharge power and is discharged to the outside through the fifth resistor R7.
  • the power storage circuit 106 can realize power supply to the device connected to the second USB interface through the power storage circuit 106 when the external power source is pulled out of the power interface 102, and prevent the OTG communication from being interrupted due to power failure of the device connected to the second USB interface.
  • the ID pin of the first USB interface 101 can be grounded through a resistor R5.
  • the first unidirectional pass device 107, the second unidirectional pass device 108, the third unidirectional pass device 109, or the fourth unidirectional pass device 110 may employ a diode to implement a unidirectional rectification conduction function.
  • FIG. 5 further illustrates another circuit configuration diagram of an OTG peripheral provided by an embodiment of the present invention.
  • the embodiment of FIG. 5 is another implementation of the embodiment of FIG. 2. What is not mentioned in the embodiment of FIG. 5, reference may be made to the description of the embodiment of FIG. 2 or FIG. 4.
  • the switching circuit in the delay conducting circuit 104 is an N-type MOS transistor switching circuit. The basic structure of each circuit unit in the OTG peripheral will be described in detail below with reference to FIG. among them:
  • the delay conduction circuit 104 in the rectangular dotted frame may include: a switching circuit (N-type MOS transistor (NMOSFET) in a circular dotted frame) and a delay circuit (boost circuit, third resistor R9) , a third capacitor C6 and a fourth resistor R8).
  • a switching circuit N-type MOS transistor (NMOSFET) in a circular dotted frame
  • a delay circuit boost circuit, third resistor R9
  • third capacitor C6 and a fourth resistor R8.
  • the delay circuit controls an on-time of the switch circuit, that is, the preset safety time.
  • the switch circuit When the switch circuit is turned on, the circuit between the power interface 102 and the power pin of the first USB interface 101 is a path.
  • the switch circuit When the switch circuit is turned off, the circuit between the power interface 102 and the power pin of the first USB interface 101 is open.
  • the third capacitor C6 and the third resistor R9 are connected in series; the source (S pole) of the N-type MOS transistor is connected to the power pin of the first USB interface 101, and the N-type The drain (D pole) of the MOS transistor is connected to the power interface 102, and the gate (G pole) of the N-type MOS transistor is grounded through the third capacitor C6; the power input terminal (IN) of the booster circuit is connected to the power interface 102, The power output terminal (OUT) of the voltage circuit is connected to the gate of the N-type MOS transistor through the third resistor R9 for increasing the gate voltage of the N-type MOS transistor; the fourth resistor R8 is connected in parallel with the third capacitor C6 for The third resistor R9 collectively adjusts the gate voltage that ultimately falls on the N-type MOS transistor.
  • the gate voltage of the N-type MOS transistor needs to be higher than the source voltage.
  • the output voltage of the booster circuit is finally divided by the voltage across the fourth resistor R8 (Ug).
  • the source voltage (Us) larger than the N-type MOS transistor is required, and the difference between the two is larger than the turn-on voltage (Ugs(th)) of the N-type MOS transistor.
  • the gate voltage of the N-type MOS transistor can also be obtained from other high-level nodes, and the ON condition of the N-type MOS transistor can be satisfied.
  • the third capacitor C6 and the third resistor R9 determine the delay time of the N-type MOS transistor in FIG.
  • R is the third resistor R9
  • C is the third capacitor C6
  • U is the output voltage of the booster circuit
  • Uc is the voltage across the third capacitor C6.
  • FIG. 6 is a schematic structural diagram of a first embodiment of a terminal according to an embodiment of the present invention.
  • the terminal 60 shown in FIG. 6 may include: an identification module 601, a determination module 603, a first management module 605, and a second management module 607.
  • the terminal 60 can be used to perform the method described in the embodiment of FIG. 3 above.
  • FIG. 6 For the content not mentioned in the embodiment shown in FIG. 6, reference may be made to the description in the corresponding embodiments of FIG. 1 to FIG.
  • the identification module 601 is configured to identify that the OTG peripheral is inserted into the preset USB interface
  • the determining module 603 is configured to: when the terminal detects a high level pulse at the ID pin of the preset USB interface, determine whether the terminal is currently supplying power to the second USB interface by responding to the high level pulse status;
  • the first management module 605 is configured to stop supplying power to the second USB interface when the determination result output by the determining module 603 is YES, and receive power supply of the power interface by using the preset USB interface;
  • the second management module 607 is configured to supply power to the second USB interface when the determination result output by the determination module 603 is negative.
  • the OTG peripheral device may be the OTG peripheral device 100 shown in FIG. 2, and details are not described herein again.
  • the terminal 60 includes: an identification module 601, a determination module 603, a first management module 605, and a second management module 607, and a third management module 609 for identifying the module.
  • the 601 identifies that the OTG peripheral is inserted into the preset USB interface on the terminal, if the terminal detects that there is power on the power pin of the preset USB interface, performing the stopping to supply power to the second USB interface, And receiving, by the preset USB interface, a step of supplying power to the power interface.
  • FIG. 8 is a schematic structural diagram of a third embodiment of a terminal according to an embodiment of the present invention.
  • the terminal 80 may include: an input device 803, an output device 804, a memory 802, and a processor 801 coupled to the memory 802 (the number of the processors 801 in the terminal 80 may be one or more, and one processing is performed in FIG. For example).
  • the input device 803, the output device 804, The memory 802 and the processor 801 may be connected by a bus or other means, wherein the bus connection is taken as an example in FIG.
  • the memory 802 is configured to store program code, and the processor 801 is configured to invoke the program code stored in the memory to perform the following steps:
  • the processor When detecting a high level pulse at the ID pin of the preset USB interface, the processor responds to the high level pulse to determine whether the terminal is currently in a state of supplying power to the second USB interface, and if And stopping power supply to the second USB interface, and receiving power supply of the power interface through the preset USB interface, and if not, supplying power to the second USB interface.
  • the input device 803 may be the preset USB interface
  • the output device 804 may also be the preset USB interface.
  • the OTG peripheral device may be the OTG peripheral device 100 shown in FIG. 2, and details are not described herein again.
  • the processor 801 when it is recognized that the OTG peripheral is inserted into the preset USB interface, if the terminal detects that there is power on the power pin of the preset USB interface, the processor 801 performs the stopping to the second The USB interface is powered, and the step of receiving power from the power interface is received through the preset USB interface.
  • the OTG peripheral 400 when the power supply 400 is inserted into the OTG peripheral 400, the OTG peripheral 400 outputs a high-level pulse to the terminal 200 through the first USB interface 101 to trigger the terminal 200 to stop.
  • the USB slave device 300 is powered, and at the same time, waits for a preset safety time, so that the power source 400 supplies power to the terminal 200 after the terminal 200 stops supplying power to the USB slave device 300; when the power source 400 pulls out the OTG peripheral device 100, the OTG is externally
  • the device 100 outputs a high-level pulse to the terminal 200 through the first USB interface 101 for triggering the terminal 200 to supply power to the USB slave device 300, and can be implemented as the terminal 200 and the USB slave device 300 connected to the OTG peripheral device 100, and
  • the OTG communication between the terminal 200 and the USB slave device 300 is not interrupted.
  • the storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

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Abstract

本发明实施例公开了一种供电系统、OTG外设、终端侧的供电方法以及终端。在所述供电系统中，当电源插入所述OTG外设的电源接口时，所述电源向连接在所述OTG外设的第二USB接口上的USB从设备供电；当电源插入所述OTG外设的电源接口时，所述OTG外设通过所述OTG的第一USB接口向外输出高电平脉冲，用以触发连接在所述第一USB接口上的终端停止向所述USB从设备供电，同时，所述OTG外设延迟预设安全时间后再使所述电源向连接在所述第一USB接口的终端供电。采用本发明实施例，可实现为连接在所述OTG外设上的终端和所述USB从设备供电，并且不中断所述终端和所述USB从设备之间的OTG通信。

Description

一种OTG外设、供电方法、终端及系统 技术领域
本发明涉及供电技术领域，尤其涉及一种OTG外设、供电方法、终端及系统。
背景技术
现有的终端都支持USB OTG(Universal Serial Bus，On-The-Go)功能。OTG是USB规格的补充标准，可使USB设备，例如手机，成为USB主设备(Host)。作为USB主设备的智能终端能与带有USB接口的移动硬盘、输入设备、读卡器等USB外设相连，访问和通信。
但是，在OTG通信中，连接在智能终端上的移动硬盘、输入设备、读卡器等USB外设都是由智能终端供电的，使得智能终端的电量消耗过快。此时，需要移除USB外设给智能终端充电，并会导致智能终端与USB外设之间的OTG通信中断。
发明内容
本发明实施例提供了一种OTG外设、供电方法、终端及系统，可实现在OTG通信过程中同时为连接在所述OTG外设上的主设备和连接在所述OTG外设上的从设备供电。
第一方面，提供了一种OTG外设，包括：延时导通电路，检测电路，第一USB接口，电源接口，第二USB接口，其中：
所述第一USB接口与所述第二USB接口相连；所述第一USB接口的ID管脚接低电平；
所述电源接口通过所述延时导通电路与所述第一USB接口的电源管脚相连，用于在所述电源接口上电后延迟向所述第一USB接口供电；
所述检测电路分别与所述第一USB接口的ID管脚和所述电源接口相连，所述检测电路用于在检测到所述电源接口上电时，向所述第一USB接口的ID管脚输出高电平脉冲，用以触发连接在所述第一USB接口的终端停止向所述第二 USB接口供电；
所述电源接口与所述第二USB接口的电源管脚相连，用于在所述电源接口上电后向所述第二USB接口供电。
结合第一方面，在第一种可能的实现方式中，所述检测电路还用于在检测到所述电源接口断电时，向所述第一USB接口的ID管脚输出高电平脉冲，用以触发连接在所述第一USB接口的终端向所述第二USB接口供电；
结合第一方面，或者，结合第一方面的第一种可能的实现方式，在第二种可能的实现方式中，所述外设还包括：蓄电电路，所述蓄电电路和所述电源接口相连，并且和所述第二USB接口的电源管脚相连，用于在所述电源接口上电后存储所述电源接口的供电，并在所述电源接口断电后向所述第二USB接口供电。
结合第一方面，或者，结合第一方面的第一种可能的实现方式，在第三种可能的实现方式中，所述检测电路的电源端与所述第二USB接口的电源管脚相连，用于接收来自所述电源接口，或所述第一USB接口的供电。
结合第一方面的第二种可能的实现方式，在第四种可能的实现方式中，所述检测电路的电源端与所述第二USB接口的电源管脚相连，用于接收来自所述电源接口，或所述第一USB接口，或所述蓄电电路的供电。
结合第一方面，或者，结合第一方面的第一种至第四种可能的实现方式中的任意一种实现方式，在第五种可能的实现方式中，所述延时导通电路包括：开关电路和延时电路，其中：
所述延时电路控制所述开关电路的导通时间；
所述开关电路导通时，所述电源接口与所述第一USB接口的电源管脚之间电路是通路；所述开关电路截止时，所述电源接口与所述第一USB接口的电源管脚之间的电路是开路。
结合第一方面，或者，结合第一方面的第一种至第五种可能的实现方式中的任意一种实现方式，在第六种可能的实现方式中，所述检测电路包括：双单稳态触发电路，其中：所述双单稳态触发电路的第一单稳态触发电路的下降沿触发输入端和所述电源接口相连，所述第一单稳态触发电路的上升沿触发输入端接低电平；
所述双单稳态触发电路的第二单稳态触发电路的下降沿触发输入端和所述第二USB接口的电源管脚相连；所述双单稳态触发电路的第二单稳态触发电路的上升沿触发输入端与所述电源接口相连；
所述第一单稳态触发电路的输出端和所述第二单稳态触发电路的输出端经过或门电路输出信号，所述或门电路的输出端与所述第一USB接口的ID管脚相连；
所述双单稳态触发电路用于在所述电源接口的信号的上升沿和下降沿均通过所述或门电路输出所述高电平脉冲信号。
结合第一方面的第五种可能的实现方式，在第七种可能的实现方式中，所述延时导通电路还包括第二电阻；所述开关电路为P型MOS管开关电路；所述延时电路包括：串联的第一电容和第一电阻，其中：所述第一电容并联在所述MOS管的栅极和源极的两端，所述MOS管的栅极通过所述第一电阻接地，所述MOS管的源极与所述电源接口相连，所述MOS管的漏极与所述第一USB接口的电源管脚相连；所述MOS管的栅极和源极的两端还并联有所述第二电阻，所述第二电阻用于调节所述MOS管的栅极和源极之间的电压。
结合第一方面的第七种可能的实现方式，在第八种可能的实现方式中，所述延时导通电路还包括第二电容，所述P型MOS管的栅极和源极两端还并联有所述第二电容；所述第二电容小于所述第一电容，用于在所述电源接口上电时，将所述P型MOS管的栅极电压抬高至所述电源接口的电源电压，以使所述P型MOS管处于截止状态。
结合第一方面的第五种可能的实现方式，在第九种可能的实现方式中，所述延时导通电路还包括：升压电路和第四电阻；所述开关电路为N型MOS管开关电路，所述延时电路包括：串联的第三电阻和第三电容；所述N型MOS管的源极与第一USB接口的电源管脚相连，所述N型MOS管的漏极与所述电源接口相连，所述N型MOS管的栅极通过所述第三电容接地；所述升压电路的电源输入端与所述电源接口相连，所述升压电路的电源输出端通过所述第三电阻与所述N型MOS管的栅极相连，用于提高所述N型MOS管的栅极电压；所述第四电阻与所述第三电容并联，用于调节所述N型MOS管的栅极电压。
结合第一方面的第二种可能的实现方式，或者，结合第一方面的第四种可 能的实现方式，在第十种可能的实现方式中，所述蓄电电路包括：串联的第五电阻和第四电容，其中：所述第五电阻与所述第二USB接口的电源管脚相连，所述第四电容接地。
结合第一方面，或者，结合第一方面的第一种至第十种可能的实现方式中任一种实现方式，在第十一种可能的实现方式中，所述外设还包括：第一单向导通器件，所述第一单向导通器件串联在所述延时导通电路与所述第一USB接口的电源管脚之间，所述第一单向导通器件用于截止所述第一USB接口通过导通的所述延时导通电路流向所述电源接口的反灌电流。
结合第一方面，或者，结合第一方面的第一种至第十一种可能的实现方式中任一种实现方式，在第十二种可能的实现方式中，所述外设还包括：
第二单向导通器件，所述第二单向导通器件串联在所述检测电路与所述第一USB接口的ID管脚之间，所述第二单向导通器件用于截止所述检测电路输出的所述高电平脉冲灌向所述第一USB接口。
结合第一方面，或者，结合第一方面的第一种可能的实现方式，或者，结合第一方面的第三种可能的实现方式，或者，结合第一方面的第五种至第九种可能的实现方式中的任意一种实现方式，或者，结合第一方面的第十一种至第十二种可能的实现方式中的任意一种实现方式，在第十三种可能的实现方式中，所述外设还包括：第三单向导通器件，所述第三单向导通器件串联在所述第二USB接口的电源管脚与所述电源接口之间，所述第三单向导通器件用于截止所述第一USB接口流向所述电源接口的反灌电流。
结合第一方面的第二种可能的实现方式，或者，结合第一方面的第四种可能的实现方式，或者，结合第一方面的第十种可能的实现方式，在第十四种可能的实现方式中，所述外设还包括：第三单向导通器件，所述第三单向导通器件串联在所述第二USB接口的电源管脚与所述电源接口之间，所述第三单向导通器件用于截止所述蓄电电路和/或所述第一USB接口流向所述电源接口的反灌电流。
结合第一方面，或者，结合第一方面的第一种可能的实现方式，或者，结合第一方面的第三种可能的实现方式，或者，结合第一方面的第五种至第九种可能的实现方式中的任意一种实现方式，或者，结合第一方面的第十一种至第 十三种可能的实现方式中的任意一种实现方式，在第十五种可能的实现方式中，所述外设还包括：第四单向导通器件，所述第四单向导通器件串联在所述第一USB接口的电源管脚与第二USB接口的电源管脚之间，所述第四单向导通器件用于截止所述电源接口灌向所述第一USB接口的电流。
结合第一方面的第二种可能的实现方式，或者，结合第一方面的第四种可能的实现方式，或者，结合第一方面的第十种可能的实现方式，或者，结合第一方面的第十四种可能的实现方式，在第十六种可能的实现方式中，所述外设还包括：第四单向导通器件，所述第四单向导通器件串联在所述第一USB接口的电源管脚与第二USB接口的电源管脚之间，所述第四单向导通器件用于截止所述蓄电电路和/或所述电源接口灌向所述第一USB接口的电流。
第二方面，提供了一种供电方法，包括：
终端识别到OTG外设插入预设USB接口；所述OTG外设包括：延时导通电路，检测电路，第一USB接口，电源接口，第二USB接口，其中：所述第一USB接口与所述第二USB接口相连；所述第一USB接口的ID管脚接低电平；所述电源接口通过所述延时导通电路与所述第一USB接口的电源管脚相连，用于在所述电源接口上电后延迟向所述第一USB接口供电；所述检测电路分别与所述第一USB接口的ID管脚和所述电源接口相连，所述检测电路用于在检测到所述电源接口上电或断电时，向所述第一USB接口的ID管脚输出高电平脉冲；所述电源接口与所述第二USB接口的电源管脚相连，用于在所述电源接口上电后向所述第二USB接口供电；
当终端检测到所述预设USB接口的ID管脚处的高电平脉冲时，终端响应所述高电平脉冲，判断终端当前是否处于向所述第二USB接口供电的状态，若是，则停止向所述第二USB接口供电，并通过所述预设USB接口接收所述电源接口的供电，若否，则向所述第二USB接口供电。
结合第二方面，在第一种可能的实现方式中，在所述终端识别到OTG外设插入预设USB接口时，还包括：
如果终端检测到所述预设USB接口的电源管脚上有电，则执行所述停止向所述第二USB接口供电，并通过所述预设USB接口接收所述电源接口的供电的步骤。
第三方面，提供了一种终端，包括：
识别模块，用于识别到OTG外设插入预设USB接口；所述OTG外设包括：延时导通电路，检测电路，第一USB接口，电源接口，第二USB接口，其中：所述第一USB接口与所述第二USB接口相连；所述第一USB接口的ID管脚接低电平；所述电源接口通过所述延时导通电路与所述第一USB接口的电源管脚相连，用于在所述电源接口上电后延迟向所述第一USB接口的供电；所述检测电路分别与所述第一USB接口的ID管脚和所述电源接口相连，所述检测电路用于在检测到所述电源接口上电或断电时，向所述第一USB接口的ID管脚输出高电平脉冲；所述电源接口与所述第二USB接口的电源管脚相连，用于在所述电源接口上电后向所述第二USB接口供电；
判断模块，用于当终端检测到所述预设USB接口的ID管脚处的高电平脉冲时，响应所述高电平脉冲，判断终端当前是否通过处于向所述第二USB接口供电的状态；
第一管理模块，用于当所述判断模块输出的判断结果为是时，停止向所述第二USB接口供电，并通过所述预设USB接口接收所述电源接口的供电；
第二管理模块，用于当所述判断模块输出的判断结果为否时，向所述第二USB接口供电。
结合第三方面，在第一种可能的实现方式中，所述终端还包括：第三管理模块，用于在所述识别模块识别到OTG外设插入所述终端上的预设USB接口时，如果终端检测到所述预设USB接口的电源管脚上有电，则执行所述停止向所述第二USB接口供电，并通过所述预设USB接口接收所述电源接口的供电的步骤。
第四方面，提供了一种终端，包括：
输入装置、输出装置、存储器和与所述存储器耦合的处理器，其中：
所述处理器读取所述存储器中存储的指令，用于执行以下步骤：
识别到OTG外设插入预设USB接口；其中，所述OTG外设包括：延时导通电路，检测电路，第一USB接口，电源接口，第二USB接口，其中：所述第一USB接口与所述第二USB接口相连；所述第一USB接口的ID管脚接低电平；所述电源接口通过所述延时导通电路与所述第一USB接口的电源管脚相连，用于在所述电源接口上电后延迟向所述第一USB接口的供电；所述检测电路分别与 所述第一USB接口的ID管脚和所述电源接口相连，所述检测电路用于在检测到所述电源接口上电或断电时，向所述第一USB接口的ID管脚输出高电平脉冲；所述电源接口与所述第二USB接口的电源管脚相连，用于在所述电源接口上电后向所述第二USB接口供电；
当检测到所述预设USB接口的ID管脚处的高电平脉冲时，所述处理器响应所述高电平脉冲，判断终端当前是否处于向所述第二USB接口供电的状态，若是，则停止向所述第二USB接口供电，并通过所述预设USB接口接收所述电源接口的供电，若否，则向所述第二USB接口供电。
结合第四方面，在第一种可能的实现方式中，在所述处理器识别到OTG外设插入预设USB接口时，还包括：如果终端检测到所述预设USB接口的电源管脚上有电，则执行所述停止向所述第二USB接口供电，并通过所述预设USB接口接收所述电源接口的供电的步骤。
第五方面，提供了一种供电系统，包括：OTG外设和终端，其中：
所述OTG外设包括：延时导通电路，检测电路，第一USB接口，电源接口，第二USB接口，其中：所述第一USB接口与所述第二USB接口相连；所述第一USB接口的ID管脚接低电平；所述电源接口通过所述延时导通电路与所述第一USB接口的电源管脚相连，用于在所述电源接口上电后延迟向所述第一USB接口的供电；所述检测电路分别与所述第一USB接口的ID管脚和所述电源接口相连，所述检测电路用于在检测到所述电源接口上电或断电时，向所述第一USB接口的ID管脚输出高电平脉冲；所述电源接口与所述第二USB接口的电源管脚相连，用于在所述电源接口上电后向所述第二USB接口供电；
所述终端识别到所述OTG外设插入所述终端的预设USB接口，所述预设USB接口与所述第一USB接口相连；当所述终端检测到所述预设USB接口的ID管脚处的高电平脉冲时，所述终端响应所述高电平脉冲，判断所述终端当前是否处于向所述第二USB接口供电的状态，若是，则停止向所述第二USB接口供电，并通过所述预设USB接口接收所述电源接口的供电，若否，则向所述第二USB接口供电。
结合第五方面，在第一种可能的实现方式中，所述OTG外设是前述第一方面的全部内容描述的OTG外设，这里不再赘述。
结合第五方面，在第二种可能的实现方式中，所述终端是前述第三方面的全部内容描述的终端，这里不再赘述。
结合第五方面，在第三种可能的实现方式中，所述系统还包括：USB从设备，其中，所述USB从设备通过所述OTG外设的第二USB接口与所述OTG外设相连。
结合第五方面，在第四种可能的实现方式中，所述系统还包括：电源，其中，所述电源通过所述OTG外设的电源接口与所述OTG外设相连。
实施本发明实施例，在电源插入所述OTG外设时，所述OTG外设通过第一USB接口向终端输出高电平脉冲，用以触发终端停止向USB从设备供电，并且由上电的电源向USB从设备供电，同时，等待预设安全时间，以使电源在终端停止向USB从设备供电之后，再向终端供电，从而在OTG通信过程中同时为连接在所述OTG外设上的主设备和连接在所述OTG外设上的从设备供电。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例提供的供电系统的结构示意图
图2是本发明实施例提供的OTG外设的结构示意图；
图3是本发明实施例提供的终端侧的供电方法的流程图；
图4是本发明实施例提供的OTG外设的一种电路结构图；
图5是本发明实施例提供的OTG外设的另一种电路结构图；
图6是本发明实施例提供的终端的第一实施例的结构示意图；
图7是本发明实施例提供的终端的第二实施例的结构示意图；
图8是本发明实施例提供的终端的第三实施例的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清 楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例公开了一种供电系统、OTG外设、终端侧的供电方法以及终端，可实现为连接在所述OTG外设上的主设备和连接在所述OTG外设上的从设备供电，并且不中断所述主设备和所述从设备之间的OTG通信。以下分别进行详细说明：
图1示出了本发明实施例提供的供电系统的结构示意图。参见图1，所述供电系统可包括：OTG外设100、终端200、USB从设备300以及电源400。终端200通过第一USB接口101与OTG外设100相连，USB从设备300通过第二USB接口103与OTG外设100相连，终端200和USB从设备300之间存在OTG通信。其中：
电源400用于在连接到OTG外设100后，向连接在OTG外设100上的终端200和USB从设备300供电；
OTG外设100用于在电源400插入OTG外设100时，通过第一USB接口101向终端200输出高电平脉冲，用以触发终端200停止向USB从设备300供电；OTG外设100用于在电源400拔出OTG外设100时，通过第一USB接口101向终端200输出高电平脉冲，用以触发终端200向USB从设备300供电；
另外，OTG外设100还用于在电源400插入OTG外设100后，等待预设安全时间，以使电源400在终端200停止向USB从设备300供电之后，再向终端200供电；
终端200用于接收第一USB接口101输出的高电平脉冲，根据该高电平脉冲判断出电源400是插入或者拔出OTG外设100。当判断出电源400插入OTG外设100时，终端200停止向USB从设备300供电，并接收电源400的供电；当判断出电源400拔出OTG外设100时，终端200向USB从设备300供电。
具体实现中，上述供电系统的工作原理可包括：
当电源400插入OTG外设100(电源接口102上电)时，OTG外设100 迅速将电源电压引导到第二USB接口103，以使USB从设备300接收电源400的供电。同时，OTG外设100等待所述预设安全时间，之后将电源电压引导到第一USB接口101，以使终端200接收电源400的供电。
当电源400插入OTG外设100(电源接口102上电)时，OTG外设100还通过第一USB接口101输出高电平脉冲，用以触发终端200停止向USB从设备300供电。
在接收到第一USB接口101输出的高电平脉冲后，终端200根据该高电平脉冲判断出电源400插入OTG外设100，停止向USB从设备300供电。
在停止向USB从设备300供电后，终端200接收电源400的供电。需要说明的，OTG外设100等待的前述安全时间可足够长，以使终端200能够完成停止向USB从设备300供电的过程，安全的接收电源400的供电。
当电源400拔出OTG外设100(电源接口102断电)时，OTG外设100通过第一USB接口101输出高电平脉冲，用以触发终端200开始向USB从设备300供电。
在接收到第一USB接口101输出的高电平脉冲后，终端200根据该高电平脉冲判断出电源400拔出OTG外设100，开始向USB从设备300供电。
实施本发明提供的供电系统，可实现在终端200和USB从设备300进行OTG通信时，为终端200和USB从设备300供电，并且不中断二者之间的OTG通信。
图2示出了本发明实施例提供的OTG外设的结构示意图。参见图2，所述OTG外设包括：延时导通电路104，检测电路105，第一USB接口101，电源接口102，第二USB接口103，其中：
第一USB接口101与第二USB接口103相连；第一USB接口101的ID管脚接低电平；
电源接口102通过延时导通电路104与第一USB接口101的电源管脚相连，用于在电源接口102上电后延迟向第一USB接口101供电；
检测电路105分别与第一USB接口101的ID管脚和电源接口102相连，检测电路105用于在检测到电源接口102上电时，向第一USB接口101的ID管脚输出 高电平脉冲，用以触发连接在第一USB接口101的终端停止向第二USB接口103供电；
电源接口102与第二USB接口103的电源管脚相连，用于在电源接口102上电后向第二USB接口103供电。
本发明实施例中，如图2所示，上述第一USB接口101与第二USB接口103相连，可包括：第一USB接口101的数字管脚(D+、D-)与第二USB接口103的数字管脚(D+、D-)相连，可实现连接在第一USB接口101的终端与连接在第二USB接口103的USB从设备进行OTG通信。
本发明实施例中，如图2所示，上述第一USB接口101与第二USB接口103相连，还可包括：第一USB接口101的电源管脚与第二USB接口103的电源管脚相连，可实现当连接在第一USB接口101的终端与连接在第二USB接口103的USB从设备进行OTG通信时，所述终端向所述USB从设备供电，即，所述终端向电源总线供电。
实施例中涉及的电源总线是指第一USB接口101的电源管脚与第二USB接口103的电源管脚相连形成的总线，为处于OTG通信中的所述USB从设备提供电源。
根据USB OTG规范，始终由ID管脚接低的USB设备向电源总线供电。也就是说，在本发明实施例中，在电源接口102没有上电时，始终由连接在第一USB接口101的终端向电源总线供电，即所述终端向所述USB从设备供电。
本发明实施例中，所述终端向电源总线供电的供电状态可进一步的结合检测电路105来确定：当电源接口102上电时，检测电路105向第一USB接口101的ID管脚输出高电平脉冲，触发所述终端停止向电源总线供电；当电源接口102断电时，检测电路105向第一USB接口101的ID管脚输出高电平脉冲，触发所述终端开始向电源总线供电。
本发明实施例中，在电源接口102上电后，延时导通电路104先处于截止状态，等待预设安全时间后呈导通状态。这里，所述预设安全时间用于确保：在延时导通电路104导通之前，连接在第一USB接口101的终端检测到检测电路105输出的高电平脉冲，并停止向电源总线供电。
作为一种优选的实施方式，图2所示的OTG外设还可包括：蓄电电路106。 其中，蓄电电路106和电源接口102相连，用于在电源接口102上电后存储电源接口102的供电。蓄电电路106和第二USB接口103的电源管脚相连，用于在电源接口102断电后向第二USB接口103供电。
蓄电电路106可实现在电源接口102断电之后，在所述终端向电源总线供电之前(因为连接在第一USB接口101的终端和检测电路105等电路单元可能产生时延)，及时向连接在第二USB接口103的USB从设备供电，可避免所述终端与所述USB从设备之间的OTG通信中断。
进一步的，本发明实施例提供的OTG外设还可如图2所示包括：第一单向导通器件107。第一单向导通器件107串联在延时导通电路104与第一USB接口101的电源管脚之间，用于截止第一USB接口101通过导通的延时导通电路104流向电源接口102的反灌电流。
更进一步的，在包括第一单向导通器件107之外，本发明实施例提供的OTG外设还可如图2所示包括：第二单向导通器件108。第二单向导通器件108串联在检测电路105与第一USB接口101的ID管脚之间，用于截止检测电路105输出的高电平脉冲灌向第一USB接口101。
更进一步的，在包括第一单向导通器件107和/或第二单向导通器件108之外，本发明实施例提供的OTG外设还可如图2所示包括：第三单向导通器件109。第三单向导通器件109串联在第二USB接口103的电源管脚与电源接口102之间，用于截止第一USB接口101流向电源接口102(第一USB接口向第二USB接口103供电时)的反灌电流。
当本发明实施例提供的OTG外设如图2所示还包括蓄电电路106时，第三单向导通器件109还可用于截止蓄电电路106流向电源接口102的反灌电流。
更进一步的，在包括第一单向导通器件107、第二单向导通器件108、第三单向导通器件109中的任意单向导通器件之外，本发明实施例提供的OTG外设还可如图2所示包括：第四单向导通器件110。第四单向导通器件110串联在第一USB接口101的电源管脚与第二USB接口103的电源管脚之间，用于截止电源接口102直接流向第一USB接口101(不通过延时导通电路)的电流。
当本发明实施例提供的OTG外设如图2所示还包括蓄电电路106时，第四单向导通器件110还可用于截止蓄电电路106流向电源接口102的反灌电流。
需要说明的，上述第一单向导通器件107、第二单向导通器件108、第三单向导通器件109或第四单向导通器件110可以采用有源二极管，或者超低压降二极管，例如肖特基二极管。实际应用中，实施本实施例还可以采用其他具有单向整流导通功能的装置，这里不作限制。
作为一种可选的实施方式，在图2所示的OTG外设中，检测电路105的电源端可与第二USB接口103的电源管脚相连。第二USB接口103的电源管脚可接收来自电源接口102，或第一USB接口101，或蓄电电路106的供电。因此，第二USB接口103的电源管脚的电平可保持为高电平，能对检测电路105提供稳定的供电。
同理，第二USB接口103的电源管脚的电平始终为高电平，可实现向连接在第二USB接口103的USB从设备提供稳定的供电，确保其与所述终端之间的OTG通信不中断。
需要说明的，本发明实施例中的电源接口102可以是不提供数字管脚的USB接口，也可以是能向第一USB接口101提供匹配电压的其他标准的电源接口，这里不作限制。本发明实施例中的第二USB接口103可以是提供ID管脚的USB接口(ID脚悬空)，也可以是不提供ID管脚的USB接口。
图3示出了本发明实施例提供的终端侧的供电方法的流程图。下面结合图1所示的供电系统和图2所示的OTG外设详细的解释终端侧的供电方法，该方法包括：
S101，终端识别到OTG外设插入预设USB接口。
具体的，所述终端可以是图1中的终端200，所述OTG外设可以是图1中的OTG外设100或图2所示的OTG外设100，这里不再赘述。
具体的，所述预设USB接口是终端上与OTG外设100的第一USB接口101相连的USB接口。
实施例中，终端可通过所述预设USB接口的ID管脚的电平高低来判断OTG外设100是否插入所述预设USB接口。若所述预设USB接口的ID管脚的电平为低，终端可判断出OTG外设100插入所述预设USB接口。可理解的，OTG外设100的第一USB接口101的ID管脚接低电平，因此，当OTG外设100通过第一USB 接口101与终端的所述预设USB接口相连时，所述预设USB接口的ID管脚也为低电平。
S103，当终端检测到所述预设USB接口的ID管脚处的高电平脉冲时，终端判断当前是否处于向所述第二USB接口供电的状态。
具体的，当OTG外设100的检测电路105检测到电源接口102上电或者断电时，检测电路105输出高电平脉冲至第一USB接口101的ID管脚。也就是说，当OTG外设100中的检测电路105检测到电源接口102上电或者断电时，终端可通过所述预设USB接口接收到检测电路105输出的高电平脉冲。
具体的，如果终端当前通过所述预设USB接口处于向所述第二USB接口供电的状态，则终端可判断出所述高电平脉冲是由电源400插入OTG外设100的电源接口102产生的；如果终端当前没有通过所述预设USB接口处于向所述第二USB接口供电的状态，则终端可判断出所述高电平脉冲是由电源400拔出OTG外设100的电源接口102产生的。
具体实现中，终端可以在本地维护电源400插入或拔出OTG外设100的状态。当在所述预设USB接口检测到高电平脉冲时，终端可以对当前维护的电源400的插拔状态进行反转。
举例来说，终端本地维护的电源400的初始状态为：电源400拔出OTG外设100。那么，当终端接收到一个高电平脉冲时，终端本地维护的电源400的状态反转为：电源400插入OTG外设100。
具体的，当S103的判断结果为是时，终端可执行S105；当S103的判断结构为否时，终端可执行S107。
S105，终端停止向所述第二USB接口供电，并通过所述预设USB接口接收所述OTG外设的电源接口的供电。
具体的，当判断出高电平脉冲是由电源400插入OTG外设100的电源接口102产生的，终端可立即停止通过所述预设USB接口向第二USB接口输出电压。经过预设安全时间(所述预设安全时间由OTG外设100的延时导通电路104控制)后，终端通过所述预设接口的电源管脚接收来自电源接口102的供电。
S107，终端向所述第二USB接口供电。
具体的，当判断出高电平脉冲是由电源400拔出OTG外设100的电源接口 102产生的，终端可立即开始通过所述预设USB接口向所述第二USB接口输出电压，用以向连接在OTG外设100的第二USB接口103的USB从设备供电，可避免所述USB从设备和终端之间的OTG通信中断。
这里，图2所示的OTG外设100中的蓄电电路106可实现：在电源400拔出OTG外设100之后，在终端向所述第二USB接口供电之前，蓄电电路106向连接在OTG外设100的第二USB接口103的USB从设备供电，可避免所述USB从设备与终端之间的OTG通信终端。
本发明实施例中，在执行S101时，终端还可以检测所述预设USB接口的电源管脚上是否有电，如果所述预设USB接口的电源管脚上有电，则执行S105。
可理解的，在OTG外设100插入预设USB接口时，如果所述预设USB接口的电源管脚上已经有电，且所述预设USB接口的ID管脚的电平为低，则终端可判定：在所述OTG外设100插入终端的所述预设USB接口之前，电源400已经插入了OTG外设100的电源接口102。那么，终端不需要向所述第二USB接口供电，可直接通过所述预设USB接口接收来自电源接口102的供电。
实施本发明实施例，终端根据所述OTG外设输出的高电平脉冲来判断电源是否插入所述OTG外设，如果电源插入所述OTG外设，则终端停止对连接在所述OTG外设上的USB从设备供电，并在预设安全时间后接收来自电源的供电，如果电源拔出所述OTG外设，终端开始对连接在所述OTG外设上的USB从设备供电，可实现为连接在所述OTG外设上的主设备和连接在所述OTG外设上的从设备供电，并且不中断所述主设备和所述从设备之间的OTG通信。
图4进一步示出了本发明实施例提供的OTG外设的一种电路结构图。图4实施例是图2实施例的一种实现方式，图4实施例没有提及的内容，可以参考图2实施例的描述。如图4所示，延时导通电路104中的开关电路为P型MOS管开关电路。下面结合图4来详细说明所述OTG外设中各个电路单元的基本结构。其中：
根据图4实施例，矩形虚线框内的延时导通电路104可包括：开关电路(圆形虚线框内的P型MOS管(PMOSFET))和延时电路(第一电容C1和第一电阻R1、第二电阻R2)。
其中，所述延时电路控制所述开关电路的导通时间，即所述预设安全时间。当所述开关电路导通时，电源接口102与第一USB接口101的电源管脚之间电路是通路。当所述开关电路截止时，电源接口102与第一USB接口101的电源管脚之间的电路是开路。
在图4所示的延时导通电路104中：第一电容C1和第一电阻R1串联；第一电容C1并联在P型MOS管的栅极(G极)和源极(S极)的两端；P型MOS管的栅极通过第一电阻R1接地，P型MOS管的源极与电源接口102相连，P型MOS管的漏极(D极)与第一USB接口101的电源管脚(VBUS管脚)相连；P型MOS管的栅极和源极的两端还并联有第二电阻R2，第二电阻R2用于调节P型MOS管的栅极和源极之间的电压。
可理解的，第一电容C1和第一电阻R1决定了图2中的P型MOS管延时导通的延时时间。具体实现中，如果设定延时时间为前述预设安全时间，则可以根据RC延时电路的延时时间的计算公式：T＝-R*C*ln[（U-Uc)/U]来选择第一电阻R1和第一电容C1的大小，其中：R为第一电阻R1，C为第一电容C1，U为电源接口102的输出电压，Uc为第一电容C1两端的电压。
可理解的，第一电阻R1和第二电阻R2决定了最终落在P型MOS管栅极和源极之间的电压，即：在电源接口102上电后，经过所述预设安全时间后，最终P型MOS管的栅极电压为第一电阻R1两端的分压。这里，根据P型MOS管的导通条件：Ug-Us<0,且|Ug-Us|>|Ugs(th)|可知，经过所述预设安全时间后，P型MOS管最终可处于稳定的导通状态。其中，Ugs(th)是P型MOS管的开启电压，Ug是P型MOS管的栅极电压，Us是P型MOS管的源极电压。
优选的，延时导通电路104还可包括：第二电容C2，第二电容C2并联在P型MOS管的栅极和源极两端。第二电容C2小于第一电容C1，实际应用中可采用纳法级(nF)的电容，用于在电源接口102上电时，快速地将P型MOS管的栅极电压抬高至P型MOS管的源极电压，以使P型MOS管处于截止状态，防止P型MOS管误导通。
需要说明的，本发明实施例涉及的开关电路可包括：三极管开关电路、场效应管开关电路或者其他能模拟开关功能的电路单元，这里不作限制。本发明实施例涉及的延时电路可包括：RC延时电路、定时器延时电路以及其他具有 时延功能的电路单元，这里不作限制。
根据图4实施例，矩形虚线框内的检测电路105可包括：双单稳态触发电路U1。双单稳态触发电路U1包括：第一单稳态触发电路U1A和第二单稳态触发电路U1B。其中：
图4实施例中提供的第一单稳态触发电路U1A的功能表如表1所示：
Figure PCTCN2015079735-appb-000001
表1
图4实施例中提供的第二单稳态触发电路U1B的功能表如表2所示：
Figure PCTCN2015079735-appb-000002
表2
其中，上述表1和表2中的“H”表示高电平，“L”表示低电平，“X”表示不需要考虑，“↑”表示输入信号的上升沿(positive-going transition),“↓”表示输入信号的下降沿(negative-going transition)，
Figure PCTCN2015079735-appb-000003
表示高电平输出脉冲(HIGH level output pulse)。引脚3和引脚12均为复位引脚，高电平有效。
根据图4对应的实施例，双单稳态触发电路U1的第一单稳态触发电路U1A 的下降沿触发输入端4(input:High to Low triggered)和电源接口102相连，第一单稳态触发电路U1A的上升沿触发输入端5(input:Low to High triggered)接低电平(或接地)。另外，外挂电容C3和电阻R3可用于控制输出端Q1输出的脉冲宽度。
根据图4对应的实施例，双单稳态触发电路U1的第二单稳态触发电路U1B的下降沿触发输入端10和第二USB接口103的电源管脚相连；双单稳态触发电路U1的第二单稳态触发电路U1B的上升沿触发输入端11与电源接口102相连。这里，根据图2对应的实施例中描述的内容，第二USB接口103的电源管脚的电平始终为高电平，也就是说，下降沿触发输入端10始终为高电平。另外，外挂电容C4和电阻R4可用于控制输出端Q2输出的脉冲宽度。
根据图4实施例，检测电路105还包括：或门电路U2。第一单稳态触发电路U1A的输出端6和第二单稳态触发电路U1B的输出端8经过或门电路U2输出信号，或门电路U2的输出端与第一USB接口101的ID管脚相连。
因此，图4实施例提供的检测电路可实现在电源接口102的信号的上升沿和下降沿均通过或门电路U2输出高电平脉冲信号。也就是说，在电源接口102上电时(产生上升沿信号)，或者，在电源接口102断电时(产生下降沿信号)，或门电路U2均输出高电平脉冲至第一USB接口101的ID管脚，用以触发连接在第一USB接口101的设备停止或开始对外供电。
根据图4实施例，矩形虚线框内的蓄电电路106可包括：串联的第五电阻R7和第四电容C3，其中，第五电阻R7与第二USB接口103的电源管脚相连，第四电容C3接地。在电源接口102上电时，第四电容C3开始储蓄电量。在电源接口102断电时，第四电容C3开始储蓄电量通过第五电阻R7向外放电。蓄电电路106可实现在外部电源拔出电源接口102时，通过蓄电电路106对连接在第二USB接口的设备供电，防止因连接在第二USB接口的设备断电而导致OTG通信中断。
另外，如图4所示，第一USB接口101的ID管脚可以通过电阻R5接地。第一单向导通器件107、第二单向导通器件108、第三单向导通器件109或第四单向导通器件110可以采用二极管来实现单向整流导通的功能。
图5进一步示出了本发明实施例提供的OTG外设的另一种电路结构图。图5实施例是图2实施例的另一种实现方式，图5实施例没有提及的内容，可以参考图2或图4实施例的描述。如图5所示，延时导通电路104中的开关电路为N型MOS管开关电路。下面结合图5来详细说明所述OTG外设中各个电路单元的基本结构。其中：
如图5所示，矩形虚线框内的延时导通电路104可包括：开关电路(圆形虚线框内的N型MOS管(NMOSFET))和延时电路(升压电路、第三电阻R9、第三电容C6和第四电阻R8)。
其中，所述延时电路控制所述开关电路的导通时间，即所述预设安全时间。当所述开关电路导通时，电源接口102与第一USB接口101的电源管脚之间电路是通路。当所述开关电路截止时，电源接口102与第一USB接口101的电源管脚之间的电路是开路。
在图5所示的延时导通电路104中：第三电容C6和第三电阻R9串联；N型MOS管的源极(S极)与第一USB接口101的电源管脚相连，N型MOS管的漏极(D极)与电源接口102相连，N型MOS管的栅极(G极)通过第三电容C6接地；升压电路的电源输入端(IN)与电源接口102相连，升压电路的电源输出端(OUT)通过第三电阻R9与N型MOS管的栅极相连，用于提高N型MOS管的栅极电压；第四电阻R8与第三电容C6并联，用于和第三电阻R9共同调节最终落在N型MOS管的栅极电压。
可理解的，要使N型MOS管处于导通状态，N型MOS管的栅极电压需要高于源极电压。根据N型MOS管的导通条件：Ug-Us>0,且|Ug-Us|>|Ugs(th)|可知，升压电路的输出电压最终分压在第四电阻R8两端的电压(Ug)需要大于N型MOS管的源极电压(Us)，并且二者之差要大于N型MOS管的开启电压(Ugs(th))。需要说明的，实际应用中，N型MOS管的栅极电压还可以从其他高电平节点获得，满足N型MOS管的导通条件即可。
可理解的，第三电容C6和第三电阻R9决定了图3中的N型MOS管延时导通的延时时间。具体实现中，如果设定延时时间为所述预设安全时间，则可以根据RC延时电路的延时时间的计算公式：T＝-R*C*ln[（U-Uc）/U]来选择第三电容C6和第三电阻R9的大小，其中：R为第三电阻R9，C为第三电容C6， U为升压电路的输出电压，Uc为第三电容C6两端的电压。
图5所示的OTG外设中的检测电路105和蓄电电路106等其他电路单元的结构请参见图4实施例所述的内容，这里不再赘述。
图6是本发明实施例提供的终端的第一实施例的结构示意图。如图6所示的终端60可包括：识别模块601，判断模块603，第一管理模块605以及第二管理模块607。终端60可以用于执行上述图3实施例所述的方法。图6所示的实施例中没有提及的内容，可以参考图1至图3分别对应的实施例中的描述。
识别模块601，用于识别到OTG外设插入预设USB接口；
判断模块603，用于当终端检测到所述预设USB接口的ID管脚处的高电平脉冲时，响应所述高电平脉冲，判断终端当前是否通过处于向所述第二USB接口供电的状态；
第一管理模块605，用于当判断模块603输出的判断结果为是时，停止向所述第二USB接口供电，并通过所述预设USB接口接收所述电源接口的供电；
第二管理模块607，用于当判断模块603输出的判断结果为否时，向所述第二USB接口供电。
具体的，所述OTG外设可以是图2所示的OTG外设100，这里不再赘述。
进一步的，如图7所示，终端60在包括：识别模块601，判断模块603，第一管理模块605以及第二管理模块607外，还可以包括：第三管理模块609，用于在识别模块601识别到OTG外设插入所述终端上的预设USB接口时，如果终端检测到所述预设USB接口的电源管脚上有电，则执行所述停止向所述第二USB接口供电，并通过所述预设USB接口接收所述电源接口的供电的步骤。
可理解的是，终端60中各功能模块的功能可根据图3实施例中的方法具体实现，这里不再赘述。
图8是本发明实施例提供的终端的第三实施例的结构示意图。参见图8，终端80可包括：输入装置803、输出装置804、存储器802和与存储器802耦合的处理器801(终端80中的处理器801的数量可以一个或多个，图8中以一个处理器为例)。在本发明的一些实施例中，输入装置803、输出装置804、 存储器802和处理器801可通过总线或者其它方式连接，其中，图8中以通过总线连接为例。
其中，存储器802用于存储程序代码，处理器801用于调用该存储器存储的程序代码执行如下步骤：
识别到OTG外设插入预设USB接口；
当检测到所述预设USB接口的ID管脚处的高电平脉冲时，所述处理器响应所述高电平脉冲，判断终端当前是否处于向所述第二USB接口供电的状态，若是，则停止向所述第二USB接口供电，并通过所述预设USB接口接收所述电源接口的供电，若否，则向所述第二USB接口供电。
具体的，输入装置803可以是所述预设USB接口，输出装置804也可以是所述预设USB接口。
本发明实施例中，所述OTG外设可以是图2所示的OTG外设100，这里不再赘述。
本发明实施例中，在识别到OTG外设插入预设USB接口时，如果终端检测到所述预设USB接口的电源管脚上有电，则处理器801执行所述停止向所述第二USB接口供电，并通过所述预设USB接口接收所述电源接口的供电的步骤。
可理解的是，终端80中各功能模块的功能可根据图3实施例中的方法具体实现，这里不再赘述。
综上所述，在图1所示的供电系统中，在电源400插入OTG外设400时，OTG外设400通过第一USB接口101向终端200输出高电平脉冲，用以触发终端200停止向USB从设备300供电，同时，等待预设安全时间，以使电源400在终端200停止向USB从设备300供电之后，再向终端200供电；在电源400拔出OTG外设100时，OTG外设100通过第一USB接口101向终端200输出高电平脉冲，用以触发终端200向USB从设备300供电，可实现为连接在OTG外设100上的终端200和USB从设备300供电，并且不中断终端200和USB从设备300之间的OTG通信。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，是可以通过计算机程序来指令相关的硬件来完成，所述的程序可存储于一计算机可读取存储介质中，该程序在执行时，可包括如上述各方法的实施例的流程。 其中，所述的存储介质可为磁碟、光盘、只读存储记忆体(Read-Only Memory，ROM)或随机存储记忆体(Random Access Memory，RAM)等。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (28)

  1. 一种OTG外设，其特征在于，包括：延时导通电路，检测电路，第一USB接口，电源接口，第二USB接口，其中：
    所述第一USB接口与所述第二USB接口相连；所述第一USB接口的ID管脚接低电平；
    所述电源接口通过所述延时导通电路与所述第一USB接口的电源管脚相连，用于在所述电源接口上电后延迟向所述第一USB接口供电；
    所述检测电路分别与所述第一USB接口的ID管脚和所述电源接口相连，所述检测电路用于在检测到所述电源接口上电时，向所述第一USB接口的ID管脚输出高电平脉冲，用以触发连接在所述第一USB接口的终端停止向所述第二USB接口供电；
    所述电源接口与所述第二USB接口的电源管脚相连，用于在所述电源接口上电后向所述第二USB接口供电。
  2. 如权利要求1所述的外设，其特征在于，所述检测电路还用于在检测到所述电源接口断电时，向所述第一USB接口的ID管脚输出高电平脉冲，用以触发连接在所述第一USB接口的终端向所述第二USB接口供电。
  3. 如权利要求1或2所述的外设，其特征在于，所述外设还包括：蓄电电路，所述蓄电电路和所述电源接口相连，并且和所述第二USB接口的电源管脚相连，用于在所述电源接口上电后存储所述电源接口的供电，并在所述电源接口断电后向所述第二USB接口供电。
  4. 如权利要求1或2所述的外设，其特征在于，所述检测电路的电源端与所述第二USB接口的电源管脚相连，用于接收来自所述电源接口，或所述第一USB接口的供电。
  5. 如权利要求3所述的外设，其特征在于，所述检测电路的电源端与所述 第二USB接口的电源管脚相连，用于接收来自所述电源接口，或所述第一USB接口，或所述蓄电电路的供电。
  6. 如权利要求1至5中任一项所述的外设，其特征在于，所述延时导通电路包括：开关电路和延时电路，其中：
    所述延时电路控制所述开关电路的导通时间；
    所述开关电路导通时，所述电源接口与所述第一USB接口的电源管脚之间电路是通路；所述开关电路截止时，所述电源接口与所述第一USB接口的电源管脚之间的电路是开路。
  7. 如权利要求1至6中任一项所述的外设，其特征在于，所述检测电路包括：双单稳态触发电路，其中：所述双单稳态触发电路的第一单稳态触发电路的下降沿触发输入端和所述电源接口相连，所述第一单稳态触发电路的上升沿触发输入端接低电平；
    所述双单稳态触发电路的第二单稳态触发电路的下降沿触发输入端和所述第二USB接口的电源管脚相连；所述双单稳态触发电路的第二单稳态触发电路的上升沿触发输入端与所述电源接口相连；
    所述第一单稳态触发电路的输出端和所述第二单稳态触发电路的输出端经过或门电路输出信号，所述或门电路的输出端与所述第一USB接口的ID管脚相连；
    所述双单稳态触发电路用于在所述电源接口的信号的上升沿和下降沿均通过所述或门电路输出所述高电平脉冲信号。
  8. 如权利要求6所述的外设，其特征在于，所述延时导通电路还包括第二电阻；所述开关电路为P型MOS管开关电路；所述延时电路包括：串联的第一电容和第一电阻，其中：所述第一电容并联在所述MOS管的栅极和源极的两端，所述MOS管的栅极通过所述第一电阻接地，所述MOS管的源极与所述电源接口相连，所述MOS管的漏极与所述第一USB接口的电源管脚相连；所述MOS管的栅极和源极的两端还并联有所述第二电阻，所述第二电阻用于调节 所述MOS管的栅极和源极之间的电压。
  9. 如权利要求8所述的外设，其特征在于，所述延时导通电路还包括第二电容，所述P型MOS管的栅极和源极两端还并联有所述第二电容；所述第二电容小于所述第一电容，用于在所述电源接口上电时，将所述P型MOS管的栅极电压抬高至所述电源接口的电源电压，以使所述P型MOS管处于截止状态。
  10. 如权利要求6所述的外设，其特征在于，所述延时导通电路还包括：升压电路和第四电阻；所述开关电路为N型MOS管开关电路，所述延时电路包括：串联的第三电阻和第三电容；所述N型MOS管的源极与第一USB接口的电源管脚相连，所述N型MOS管的漏极与所述电源接口相连，所述N型MOS管的栅极通过所述第三电容接地；所述升压电路的电源输入端与所述电源接口相连，所述升压电路的电源输出端通过所述第三电阻与所述N型MOS管的栅极相连，用于提高所述N型MOS管的栅极电压；所述第四电阻与所述第三电容并联，用于调节所述N型MOS管的栅极电压。
  11. 如权利要求3或5所述的外设，其特征在于，所述蓄电电路包括：串联的第五电阻和第四电容，其中：所述第五电阻与所述第二USB接口的电源管脚相连，所述第四电容接地。
  12. 如权利要求1至11中任一项所述的外设，其特征在于，还包括：第一单向导通器件，所述第一单向导通器件串联在所述延时导通电路与所述第一USB接口的电源管脚之间，所述第一单向导通器件用于截止所述第一USB接口通过导通的所述延时导通电路流向所述电源接口的反灌电流。
  13. 如权利要求1至12中任一项所述的外设，其特征在于，还包括：第二单向导通器件，所述第二单向导通器件串联在所述检测电路与所述第一USB接口的ID管脚之间，所述第二单向导通器件用于截止所述检测电路输出的所述高电平脉冲灌向所述第一USB接口。
  14. 如权利要求1、2、4、6-10或12-13中任一项所述的外设，其特征在于，还包括：第三单向导通器件，所述第三单向导通器件串联在所述第二USB接口的电源管脚与所述电源接口之间，所述第三单向导通器件用于截止所述第一USB接口流向所述电源接口的反灌电流。
  15. 如权利要求3、5或11所述的外设，其特征在于，还包括：第三单向导通器件，所述第三单向导通器件串联在所述第二USB接口的电源管脚与所述电源接口之间，所述第三单向导通器件用于截止所述蓄电电路和/或所述第一USB接口流向所述电源接口的反灌电流。
  16. 如权利要求1、2、4、6-10或12-14中任一项所述的外设，其特征在于，还包括：第四单向导通器件，所述第四单向导通器件串联在所述第一USB接口的电源管脚与第二USB接口的电源管脚之间，所述第四单向导通器件用于截止所述电源接口灌向所述第一USB接口的电流。
  17. 如权利要求3、5、11或15所述的外设，其特征在于，还包括：第四单向导通器件，所述第四单向导通器件串联在所述第一USB接口的电源管脚与第二USB接口的电源管脚之间，所述第四单向导通器件用于截止所述蓄电电路和/或所述电源接口灌向所述第一USB接口的电流。
  18. 一种供电方法，其特征在于，包括：
    终端识别到OTG外设插入所述终端上的预设USB接口；所述OTG外设包括：延时导通电路，检测电路，第一USB接口，电源接口，第二USB接口，其中：所述第一USB接口与所述第二USB接口相连；所述第一USB接口的ID管脚接低电平；所述电源接口通过所述延时导通电路与所述第一USB接口的电源管脚相连，用于在所述电源接口上电后延迟向所述第一USB接口供电；所述检测电路分别与所述第一USB接口的ID管脚和所述电源接口相连，所述检测电路在检测到所述电源接口上电或断电时，向所述第一USB接口的ID管脚输出高电平脉冲 所述电源接口与所述第二USB接口的电源管脚相连，用于在所述电源接口上电后向所述第二USB接口供电；
    当终端检测到所述预设USB接口的ID管脚处的高电平脉冲时，终端响应所述高电平脉冲，判断终端当前是否处于向所述第二USB接口供电的状态，若是，则停止向所述第二USB接口供电，并通过所述预设USB接口接收所述电源接口的供电，若否，则向所述第二USB接口供电。
  19. 如权利要求18所述的方法，其特征在于，在所述终端识别到OTG外设插入所述终端上的预设USB接口时，还包括：如果终端检测到所述预设USB接口的电源管脚上有电，则执行所述停止向所述第二USB接口供电，并通过所述预设USB接口接收所述电源接口的供电的步骤。
  20. 一种终端，其特征在于，包括：
    识别模块，用于识别到OTG外设插入预设USB接口；所述OTG外设包括：延时导通电路，检测电路，第一USB接口，电源接口，第二USB接口，其中：所述第一USB接口与所述第二USB接口相连；所述第一USB接口的ID管脚接低电平；所述电源接口通过所述延时导通电路与所述第一USB接口的电源管脚相连，用于在所述电源接口上电后延迟向所述第一USB接口的供电；所述检测电路分别与所述第一USB接口的ID管脚和所述电源接口相连，所述检测电路用于在检测到所述电源接口上电或断电时，向所述第一USB接口的ID管脚输出高电平脉冲；所述电源接口与所述第二USB接口的电源管脚相连，用于在所述电源接口上电后向所述第二USB接口供电；
    判断模块，用于当终端检测到所述预设USB接口的ID管脚处的高电平脉冲时，响应所述高电平脉冲，判断终端当前是否通过处于向所述第二USB接口供电的状态；
    第一管理模块，用于当所述判断模块输出的判断结果为是时，停止向所述第二USB接口供电，并通过所述预设USB接口接收所述电源接口的供电；
    第二管理模块，用于当所述判断模块输出的判断结果为否时，向所述第二USB接口供电。
  21. 如权利要求20所述的终端，其特征在于，还包括：第三管理模块，用于在所述识别模块识别到OTG外设插入所述终端上的预设USB接口时，如果终端检测到所述预设USB接口的电源管脚上有电，则执行所述停止向所述第二USB接口供电，并通过所述预设USB接口接收所述电源接口的供电的步骤。
  22. 一种终端，其特征在于，包括：输入装置、输出装置、存储器和与所述存储器耦合的处理器，其中：
    所述处理器读取所述存储器中存储的指令，用于执行以下步骤：
    识别到OTG外设插入预设USB接口；其中，所述OTG外设包括：延时导通电路，检测电路，第一USB接口，电源接口，第二USB接口，其中：所述第一USB接口与所述第二USB接口相连；所述第一USB接口的ID管脚接低电平；所述电源接口通过所述延时导通电路与所述第一USB接口的电源管脚相连，用于在所述电源接口上电后延迟向所述第一USB接口的供电；所述检测电路分别与所述第一USB接口的ID管脚和所述电源接口相连，所述检测电路用于在检测到所述电源接口上电或断电时，向所述第一USB接口的ID管脚输出高电平脉冲；所述电源接口与所述第二USB接口的电源管脚相连，用于在所述电源接口上电后向所述第二USB接口供电；
    当检测到所述预设USB接口的ID管脚处的高电平脉冲时，响应所述高电平脉冲，判断终端当前是否处于向所述第二USB接口供电的状态，若是，则停止向所述第二USB接口供电，并通过所述预设USB接口接收所述电源接口的供电，若否，则向所述第二USB接口供电。
  23. 如权利要求22所述的终端，其特征在于，所述处理器还用于：
    当识别到OTG外设插入预设USB接口时，如果终端检测到所述预设USB接口的电源管脚上有电，则执行所述停止向所述第二USB接口供电，并通过所述预设USB接口接收所述电源接口的供电的步骤。
  24. 一种供电系统，其特征在于，包括：OTG外设和终端，其中：
    所述OTG外设包括：延时导通电路，检测电路，第一USB接口，电源接口，第二USB接口，其中：所述第一USB接口与所述第二USB接口相连；所述第一USB接口的ID管脚接低电平；所述电源接口通过所述延时导通电路与所述第一USB接口的电源管脚相连，用于在所述电源接口上电后延迟向所述第一USB接口的供电；所述检测电路分别与所述第一USB接口的ID管脚和所述电源接口相连，所述检测电路用于在检测到所述电源接口上电或断电时，向所述第一USB接口的ID管脚输出高电平脉冲；所述电源接口与所述第二USB接口的电源管脚相连，用于在所述电源接口上电后向所述第二USB接口供电；
    所述终端识别到所述OTG外设插入所述终端的预设USB接口，所述预设USB接口与所述第一USB接口相连；当所述终端检测到所述预设USB接口的ID管脚处的高电平脉冲时，所述终端响应所述高电平脉冲，判断所述终端当前是否处于向所述第二USB接口供电的状态，若是，则停止向所述第二USB接口供电，并通过所述预设USB接口接收所述电源接口的供电，若否，则向所述第二USB接口供电。
  25. 如权利要求24所述的系统，其特征在于，所述OTG外设是权利要求2-17中任一项所述的OTG外设。
  26. 如权利要求24所述的系统，其特征在于，所述终端是权利要求20-21中任一项所述的终端。
  27. 如权利要求24所述的系统，其特征在于，还包括：USB从设备，其中，所述USB从设备通过所述OTG外设的第二USB接口与所述OTG外设相连。
  28. 如权利要求24所述的系统，其特征在于，还包括：电源，其中，所述电源通过所述OTG外设的电源接口与所述OTG外设相连。
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