WO2016181805A1 - Data processing device and data processing method - Google Patents

Abstract

The present disclosure pertains to a data processing device and a data processing method with which it is possible to more effectively elicit the performance of an error correction code by using a time interleaver. This data processing device is provided with a time interleaver in which, for individual memory units, which are units for writing data into memory, cells that include data corresponding to a prescribed modulation scheme are discontinuously rearranged, whereby interleaving in the direction of time is performed. The present disclosure can be applied to, e.g., a transmitter for performing time interleaving.

Description

Data processing apparatus and data processing method

The present technology relates to a data processing device and a data processing method, and more particularly to a data processing device and a data processing method capable of more effectively extracting the capability of an error correction code by time interleaving.

In the field of digital broadcasting, it is known that on the receiving side, time interleaving is performed to disperse transmission data in the time direction in order to avoid effects such as burst errors during transmission (see, for example, Non-Patent Document 1) ).

By the way, there is a demand for further improvement of the performance of the error correction code, and it is demanded that the ability of error correction be more effectively extracted by the time interleaving.

The present technology has been made in view of such circumstances, and more effectively enables the ability of an error correction code to be derived by time interleaving.

The data processing apparatus according to the first aspect of the present technology discontinuously rearranges cells including data according to a predetermined modulation scheme for each memory unit, which is a unit for writing data in a memory, in the time direction. It is a data processing apparatus provided with the time interleaving part which performs interleaving.

The data processing device according to the first aspect of the present technology may be an independent device or an internal block that constitutes one device. A data processing method according to a first aspect of the present technology is a data processing method corresponding to the data processing device according to the first aspect of the present technology described above.

In the data processing device and the data processing method according to the first aspect of the present technology, cells including data according to a predetermined modulation scheme are discontinuously arranged for each memory unit which is a unit for writing data in a memory. By being interchanged, interleaving in the time direction is performed.

The data processing apparatus according to the second aspect of the present technology discontinuously rearranges cells including data according to a predetermined modulation scheme for each memory unit, which is a unit for writing data in a memory, in the time direction. Data provided with a time de-interleaving unit for performing de-interleaving in the time direction back to the original order, obtained from data transmitted from a transmitting apparatus having a time interleaving unit for performing interleaving It is a processing device.

The data processing device of the second aspect of the present technology may be an independent device or an internal block that constitutes one device. A data processing method according to a second aspect of the present technology is a data processing method corresponding to the data processing device according to the second aspect of the present technology described above.

In the data processing device and the data processing method according to the second aspect of the present technology, cells including data according to a predetermined modulation scheme are discontinuously arranged for each memory unit which is a unit for writing data in a memory. By replacing the sequence of cells after interleaving in the time direction obtained from the data transmitted from the transmitting apparatus having the time interleaving unit performing interleaving in the time direction, the deinterleave in the time direction in which the alignment of the cells in the time direction is returned. To be done.

According to the first and second aspects of the present technology, it is possible to more effectively extract the ability of the error correction code by time interleaving.

In addition, the effect described here is not necessarily limited, and may be any effect described in the present disclosure.

BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a diagram illustrating a configuration example of an embodiment of a transmission system to which the present technology is applied. It is a block diagram which shows the structural example of a transmitter. It is a block diagram which shows the structural example of the time interleaver corresponding to S-PLP. It is a figure explaining the fundamental operation | movement of a convolutional interleaver. It is a figure explaining the fundamental operation | movement of a convolutional interleaver. It is a figure explaining the fundamental operation | movement of a convolutional interleaver. It is a figure explaining extended interleave. It is a figure explaining the interleaving of the method 1-1. It is a figure explaining the interleaving of the method 1-1. It is a figure explaining the interleaving of the method 1-1. It is a figure explaining the interleaving of the method 1-1. It is a figure which shows the input-output relationship of the data of the method 1-1. It is a figure explaining the interleaving of method 1-2. It is a figure explaining the interleaving of method 1-2. It is a figure explaining the interleaving of method 1-2. It is a figure explaining the interleaving of method 1-2. It is a figure which shows the input-output relationship of the data of the method 1-2. It is a figure explaining the interleaving of the method 1-3. It is a figure explaining the interleaving of the method 1-3. It is a figure explaining the interleaving of the method 1-3. It is a figure explaining the interleaving of the method 1-3. It is a figure explaining the interleaving of the method 1-3. It is a figure explaining the interleaving of the method 1-3. It is a figure explaining the interleaving of the method 1-3. It is a figure which shows the input-output relationship of the data of the method 1-3. It is a figure explaining the interleaving of the system 1-4. It is a figure explaining the interleaving of the system 1-4. It is a figure explaining the interleaving of the system 1-4. It is a figure explaining the interleaving of the system 1-4. It is a figure explaining the interleaving of the system 1-4. It is a figure explaining the interleaving of the system 1-4. It is a figure which shows the input-output relationship of the data of the system 1-4. It is a block diagram which shows the structural example of the time interleaver corresponding to M-PLP. It is a figure explaining the basic operation | movement of a cell interleaver. It is a figure explaining the basic operation | movement of a block interleaver. It is a figure explaining the fundamental operation | movement of a convolutional interleaver. It is a figure explaining extended interleave. It is a figure explaining the conventional cell interleaving. It is a figure explaining cell interleaving (interleaving of method 2) of this art. It is a flow chart explaining transmission processing. It is a block diagram showing an example of composition of a receiving set. It is a block diagram which shows the structure of the time de-interleaver corresponding to S-PLP. It is a block diagram which shows the structure of the time de-interleaver corresponding to M-PLP. It is a flowchart explaining a reception process. It is a figure showing an example of composition of a computer.

Hereinafter, embodiments of the present technology will be described with reference to the drawings. The description will be made in the following order.

1. System configuration Configuration example of transmission side (1) Time interleaver corresponding to S-PLP (A) Method 1-1: Cell distribution in memory unit (input / output in cell units)
(B) Method 1-2: Cell distribution in a memory unit (cell unit input, MU unit output 1)
(C) Method 1-3: Cell distribution in a memory unit (cell unit input, MU unit output 2)
(D) Method 1-4: Cell distribution in memory unit (cell unit input, MU unit output 3)
(2) Temporal interleaver corresponding to M-PLP (A) Method 2: Cell dispersion in code word 3. Configuration example of receiving side (1) Time deinterleaver corresponding to S-PLP (2) Time deinterleaver corresponding to M-PLP Modification 5 Computer configuration

<1. System configuration>

FIG. 1 is a diagram illustrating a configuration example of an embodiment of a transmission system to which the present technology is applied. Here, the system refers to an assembly of a plurality of devices logically.

In FIG. 1, the transmission system 1 includes a transmitting device 10 and a receiving device 20. In this transmission system 1, data transmission conforming to the digital broadcast standard such as ATSC 3.0, which is the next generation Advanced Television Systems Committee (ATSC) standard, is performed.

The transmission device 10 transmits (transmits) a stream of (components of) video, audio, subtitles, and the like constituting content such as a television program as a digital broadcast signal through the transmission path 30.

The receiving device 20 receives a digital broadcast signal transmitted from the transmitting device 10 via the transmission path 30, acquires and processes a stream of (components of) video, audio, subtitles, etc., and content such as a television program Output video and audio.

In FIG. 1, as the transmission path 30, for example, a satellite circuit, a cable television network (wired circuit), etc. can be used besides the ground wave.

<2. Configuration example of sender side>

(Example of configuration of transmitting device)
FIG. 2 is a block diagram showing a configuration example of the transmitting device 10 of FIG. In FIG. 2, blocks surrounded by dotted lines are blocks used when MIMO (Multiple Input Multiple Output) is used, and the detailed description thereof is omitted here.

The transmitting apparatus 10 includes an input format (INPUT FORMAT) processing unit 101-1, a BICM (Bit Interleaved Coding and Modulation) processing unit 102-1, an FRM / INT (FRAME and INTERLEAVING) processing unit 103-1, and a waveform ( WAVEFORM) processing unit 104-1 is configured.

The input format processing unit 101-1 performs necessary processing on an input stream to be input, and distributes packets obtained by storing the data to PLP (Physical Layer Pipe). The input format processing unit 101-1 includes an encapsulation (ENCAP) processing unit 111-1, a schedule (SCHEDULING) processing unit 112-1, and a BB frame (Baseband framing) processing unit 113-1.

The encapsulation processing unit 111-1 processes the input data and encapsulates it in a transmission packet (Generic packet). The schedule processing unit 112-1 supplies the transmission packet supplied from the encapsulation processing unit 111-1 to the BB frame processing unit 113-1. The BB frame processing unit 113-1 processes the transmission packet and outputs data of one or more PLPs to the BICM processing unit 102-1.

The BICM processing unit 102-1 performs processing such as error correction processing, bit interleaving, and quadrature modulation. The BICM processing unit 102-1 includes an error correction (FEC) processing unit 114-1, a bit interleaver (BIL) 115-1, and a mapper (MAP) 116-1.

The error correction processing unit 114-1 performs BCH coding and low density parity check (LDPC) coding on data input from (the BB frame processing unit 113-1 of) the input format processing unit 101-1. And the resulting error correction code is provided to bit interleaver 115-1.

The bit interleaver 115-1 performs bit interleaving on the error correction code supplied from the error correction processing unit 114-1, and supplies the error correction code after the bit interleaving to the mapper 116-1.

The mapper 116-1 uses the error correction code supplied from the bit interleaver 115-1 as a signal point representing one symbol of orthogonal modulation in units of one or more code bits (symbol unit) of the error correction code. Mapping is performed to perform orthogonal modulation (multi-level modulation).

That is, the mapper 116-1 defines an error correction code from the bit interleaver 115-1 as an IQ plane defined by an I axis representing an I component in phase with the carrier and a Q axis representing a Q component orthogonal to the carrier. (IQ constellation) Orthogonal modulation is performed by mapping to a signal point determined by a modulation method for performing orthogonal modulation of an error correction code.

When the number of signal points determined by the modulation scheme of orthogonal modulation performed by the mapper 116-1 is 2 ^m , the m-bit code bit of the error correction code is regarded as a symbol (one symbol) by the mapper 116-1. The error correction code from bit interleaver 115-1 is mapped on a symbol basis to a signal point representing a symbol out of 2 ^m signal points.

Here, as a modulation method of orthogonal modulation performed by the mapper 116-1, for example, a modulation method adopted in ATSC 3.0, other modulation methods, that is, BPSK (Binary Phase Shift Keying), QPSK (Quadrature Phase) Shift Keying, 8 PSK (Phase-Shift Keying), 16 APSK (Amplitude Phase-Shift Keying), 32 APSK, 16 QAM (Quadrature Amplitude Modulation), 16 QAM, 64 QAM, 256 QAM, 1024 QAM, 4096 QAM, 4 PAM (Pulse Amplitude Modulation), and the like. In the mapper 116-1, it is set in advance, for example, in accordance with the operation of the operator of the transmission apparatus 10 or the like by which modulation scheme the orthogonal modulation is performed.

Data obtained by the processing in the mapper 116-1 (the mapping result of mapping the symbols to the signal points) is output to the FRM / INT processing unit 103-1.

The FRM / INT processing unit 103-1 performs processing such as interleaving in the time direction or frequency direction. The FRM / INT processor 103-1 includes a time interleaver (TIME INT) 117-1, a frame (FRAME) processor 118-1, and a frequency interleaver (FREQ INT) 119-1.

The time interleaver 117-1 performs time interleaving (interleaving in the time direction) on data input from (the mapper 116-1 of) the BICM processing unit 102-1, and the data after time interleaving is a frame. The data is supplied to the processing unit 118-1.

The frame processing unit 118-1 performs processing relating to the frame to the data supplied from the time interleaver 117-1, and supplies the data obtained as a result to the frequency interleaver 119-1.

The frequency interleaver 119-1 performs frequency interleaving (interleaving in the frequency direction) on the data supplied from the frame processing unit 118-1, and the data after the frequency interleaving is transmitted to the waveform processing unit 104-1. Output.

The waveform processing unit 104-1 processes data input from (the frequency interleaver 119-1 of) the FRM / INT processing unit 103-1 to generate an orthogonal frequency division multiplexing (OFDM) signal corresponding to a frame. And transmit via the transmission line 30.

The waveform processing unit 104-1 is a pilot (PILOTS) processing unit 120-1 that inserts pilot symbols, a MISO processing unit 121-1 that performs processing related to MISO (Multi Input Single Output), and an IFFT (Inverse Fast Fourier) IFFT processing unit 122-1 that performs transform, PAPR processing unit 123-1 that performs processing related to PAPR (peak to average power reduction), guard interval (GUARD INT) processing unit 124 that performs processing related to guard interval, A preamble (PREAMBLE) processing unit 125-1 that performs processing related to the preamble, and each unit performs processing as necessary.

Further, in FIG. 2, in the transmitting apparatus 10, when Layered Division Multiplexing (LDM) is performed, processing is also performed in the input format processing unit 101-2 and the BICM processing unit 102-2, and the BICM processing unit 102 is performed. The output from −2 is input to the FRM / INT processing unit 103-1. The configurations of the input format processing unit 101-2 and the BICM processing unit 102-2 are the same as the configurations of the input format processing unit 101-1 and the BICM processing unit 102-1, and thus the description thereof is omitted. In the following description, the descriptions of “−1” and “−2” are omitted if it is not necessary to distinguish between the configurations.

Further, PLP includes S-PLP (Single PLP) composed of one PLP and M-PLP (Multiple PLP) composed of a plurality of PLPs in a specific frequency band. In the following description, among the time interleavers 117, those corresponding to S-PLP are referred to as time interleaver 117S, while those corresponding to M-PLP are referred to as time interleaver 117M and distinguished. Do.

(1) Time interleaver compatible with S-PLP

(S-PLP time interleaver configuration example)
FIG. 3 is a block diagram showing a configuration example of the time interleaver 117S corresponding to S-PLP.

The time interleaver 117S performs time interleaving corresponding to S-PLP. In FIG. 3, the time interleaver 117S is composed of a cell memory unit mapper 141, a convolutional interleaver 142, and a memory unit cell demapper 143.

In FIG. 3, although the cell memory unit mapper 141 and the convolutional interleaver 142 are illustrated as separate blocks, in practice, the cell memory unit mapper 141 and the convolutional interleaver are illustrated. By operating in cooperation with each other 142, cells are processed in units of memory units.

When the convolutional interleaver 142 processes a cell including data according to a predetermined modulation method input from the BICM 102 (the mapper 116 of the BICM 102), the cell memory unit mapper 141 processes the cell (the memory unit). For example, one cell or two cells are mapped to one memory unit to convert a unit of cells (unit to be written to one address) input to the convolutional interleaver 142.

When processing the input cells in units of memory units, the convolutional interleaver 142 performs convolutional interleaving on cells in units of memory units input from the cell / memory unit mapper 141, and performs convolutional interleaving. The data is output to the memory unit cell demapper 143.

When the output from the convolutional interleaver 142 is in units of memory units, the memory unit / cell demapper 143 demaps the memory units into cells and converts them into cells (for example, 1 cell or 2 cells), Output to the frame processor 118 of FIG.

When the data (cells) input from (the mapper 116 of) the BICM 102 is processed not in memory unit but in cell units in the convolutional interleaver 142, the cell / memory unit mapper 141 and the memory unit · memory unit. The cell de mapper 143 is considered unused. In this case, data from (the mapper 116 of) the BICM 102 is directly input to the convolutional interleaver 142, and data after convolutional interleaving is directly output to the frame processing unit 118.

As described above, in the time interleaver 117S, convolutional interleaving is performed by the convolutional interleaver 142, whereby time interleaving corresponding to S-PLP is realized.

(Basic operation of convolutional interleaver)
The basic operation of the convolutional interleaver 142 of FIG. 3 will now be described with reference to FIGS. 4 to 6.

Note that, in FIG. 4 to FIG. 6, the squares in the convolutional interleaver 142 schematically represent a memory that stores one cell (hereinafter also referred to as a cell memory). That is, path p2 is provided with one cell memory, path p3 is provided with two cell memories, path p4 is provided with three cell memories, and path p5 is provided with four cell memories, and data is written there. Be On the other hand, no cell memory is provided in the path p1, and the input data is used as output data as it is.

Also, in FIG. 4 to FIG. 6, squares with numbers represent cells. That is, in the convolutional interleaver 142, it indicates that the input cell is convolutionally interleaved.

In FIG. 4, cells 1 to n (n is an integer of 1 or more) are sequentially input to the convolutional interleaver 142. In the convolutional interleaver 142, by switching the input switch S0 at a predetermined timing, each time a cell is input, path p1, path p2, path p3, path p4, path p5, path p1,. The path is selected in the order of, and the cell is written to the cell memory. Here, when the next cell is input, if the cell is already written to the cell memory, the cell is passed to the next cell memory, and then the next cell is written to the cell memory. Let's do it.

In addition, in the convolutional interleaver 142, the output switch S1 is switched in synchronization with the input switch S0, whereby the cell is read from the cell memory on the right side (output side) of the cell memories of the respective paths. However, since the cell memory is not provided in the path p1, the input cell is read as it is.

FIG. 5 shows a state in which the first five cells of the input cells, ie, cells 1 to 5 are input in the convolutional interleaver 142. In FIG. 5, the convolutional interleaver 142 selects the path p1 when the cell 1 is input, so the cell 1 is output as it is (0 delay).

In addition, since the convolutional interleaver 142 selects the path p2 when the cell 2 is input, the cell 2 is written to the cell memory of the path p2. Similarly, in the convolutional interleaver 142, cell 3 is written to the leftmost (input side) cell memory of path p3 and cell 4 is written to the leftmost (input side) cell memory of path 4 The cell 5 is written to the leftmost (input side) cell memory of the path p5.

Although five cells are output in FIG. 5, cells without any information are output as four cells other than the first cell 1 (squares without numbers). . That is, in the initial state in which data is transmitted from transmission apparatus 10 first, when the data becomes discontinuous, a cell (hereinafter referred to as an empty cell) having no such information appears. .

FIG. 6 shows a state in which the next five cells of the first five cells among the cells to be input, ie, the cells 6 to 10 are further input in the convolutional interleaver 142. . In FIG. 6, the convolutional interleaver 142 selects the path p1 when the cell 6 is input, so the cell 6 is output as it is (0 delay).

In addition, the convolutional interleaver 142 selects the path p2 when the cell 7 is input, but since the cell 2 is already stored in the cell memory of the path p2, the cell 7 becomes the cell 2 By pushing out one cell, the cell 2 stored in the cell memory is read. Thereby, the cell 7 is written to the cell memory of the path p2.

Furthermore, the convolutional interleaver 142 selects the path p3 when the cell 8 is input, but since the cell memory 3 of the leftmost (input side) of the path p3 stores the cell 3, The cell 3 stored in this cell memory is passed to the next cell memory. Thus, the cell 8 is written to the leftmost (input side) cell memory of the path p3.

Similarly, in the convolutional interleaver 142, in the path p4, the cell 9 pushes the cell 4 to the next cell memory, whereby the cell 9 is written to the leftmost (input side) cell memory. In the path p5, the cell 10 pushes the cell 5 to the next cell memory, whereby the cell 10 is written to the leftmost (input side) cell memory. At this time, three empty cells appear next to the cell 6 and the cell 2.

Although not shown, when the next five cells, ie, cells 11 to 15 are input to the convolutional interleaver 142, the paths p1 to 11 and the paths p2 to p2 are input. 7, the cell 3 is sequentially output from the path p3. At this time, cell 12 is stored in the cell memory of path p 2, cell 8 and cell 13 are stored in the cell memory of path p 3, cell 4 and cell 9 in the cell memory of path p 4, The cell 14 is stored, and the cell memory of the path p5 stores the cell 5, the cell 10, and the cell 15. In the convolutional interleaver 142, such data (cell) input / output is repeated.

The basic operation of the convolutional interleaver 142 has been described above.

(Extended interleave)
By the way, low-order modulation schemes such as QPSK and 16 QAM have a large number of cells per FEC block, and are used by (timely interleaver 142 of) time interleaver 117S in order to obtain interleave depth. Memory (cell memory) needs to be increased. Also, it is known that the reception performance is not significantly degraded even if the bit width representing each signal point on the IQ plane in a low order modulation scheme such as QPSK is smaller than that in the high order modulation scheme.

Therefore, in the case of using a low-order modulation scheme such as QPSK, the following equation (1) is used as a unit of cells input to the time interleaver 117S (convolutional interleaver 142): Let the relationship of) be established.

1 [MU] = k [cell] (1)

That is, by using k cells per one memory unit (MU: Memory Unit), the number of memory units per one FEC block is 1 / k, which makes it possible to gain interleaving depth. . In addition, even if the bit width per cell is 1 / k, when using a low-order modulation scheme such as QPSK, performance degradation falls within an allowable range.

For example, in ATSC 3.0, it is assumed that k = 2 is set in Equation (1) and two cells are stored in one memory unit when QPSK is used as the modulation scheme. In addition, in DVB-NGH (Digital Video Broadcasting-Next Generation broadcasting system to Handheld), when using QPSK or 16 QAM as a modulation system, k = 2 is set in Formula (1) as pairwise interleaving (Pairwise Interleaving). It is defined that two cells are stored in one memory unit.

However, when two temporally consecutive cells are stored in one memory unit, the effect of the temporal interleaver to disperse burst errors can not be obtained. That is, as shown in FIG. 7, in the case where two cells are stored in one memory unit by (timely interleaver 117S (convolutional interleaver 142)), the convolutional interleaver 142 arranges the input cells. Alternatively, two cells in one memory unit are temporally continuous cells. For example, in FIG. 7, cells remain adjacent in one memory unit, such as cell 1 and cell 2 and cell 13 and cell 14 and so on.

Therefore, in the present technology, when using a time interleaver 117S corresponding to S-PLP, when storing a plurality of cells in one memory unit as Extended Interleaving, the time is stored in one memory unit. We propose four methods for sorting so that cells that are continuous or close in time are not included.

(A) Method 1-1: Cell distribution in a memory unit (cell unit input / output)

First, the method 1-1 will be described with reference to FIGS. 8 to 12.

In FIG. 8, the convolutional interleaver 142 sequentially receives n (n is an integer of 1 or more) cells such as the cells 1 to 15 from the BICM (the mapper 116). Also, in the convolutional interleaver 142, the input cell is written to the cell memory according to the selection of the paths p1 to p5, but since one address of each cell memory is divided into k, one memory unit It is possible to write k cells each time.

In this case, each cell memory can store k cells whose bit width is reduced to 1 / k. For example, in FIG. 8, since k = 2 is set, two cells each having a bit width of 1/2 are stored in each cell memory.

In the convolutional interleaver 142, cells whose bit width is halved are sequentially input in cell units and written to the cell memory of each path. Then, in the convolutional interleaver 142, cells are sequentially read out from the cell memory on the right side (output side) of the cell memories of each path, and are output in cell units. That is, in this scheme 1-1, cells from (the mapper 116 of) the BICM 102 are input in cell units and are output in cell units.

In the following description, in the convolutional interleaver 142, the leftmost cell memory in each path is referred to as the cell memory 1, the next cell memory is referred to as the cell memory 2, and the next cell memory is further referred to. The cell memory 3 is referred to as "cell memory 3," and the cell memory 4 next to the cell memory 3 is referred to as "cell memory 4." That is, the cell memory 1 is provided in the path p1, the cell memories 1 and 2 are provided in the path p2, the cell memories 1 to 3 are provided in the path p3, and the cell memories 1 to 4 are provided in the path p4. It is done. These relationships are the same in other figures described later.

(A) Input of Cell 1 to Cell 5 FIG. 9 shows a state in which the first five cells of the input cells in the convolutional interleaver 142, that is, the cells 1 to 5 are input. ing. In FIGS. 9 to 11, it is assumed that the bit width of each cell input to the convolutional interleaver 142 is reduced to 1⁄2.

In FIG. 9, in the convolutional interleaver 142, when the cell 1 is input, since the path p1 is selected, the cell 1 is output with a 0 delay.

Also, focusing on the dotted line A1 in the figure, the cell 2 is divided into two in the cell memory 1 because the path p2 is selected in the convolutional interleaver 142 when the cell 2 is input. It is stored in the memory on the left side of my house. Similarly, in the convolutional interleaver 142, the cell 3 is stored in the memory on the left side of the cell memory 1 in the path p3 and the cell 4 is stored in the memory on the left side of the cell memory 1 in the path p4. Are stored in the memory on the left side of the cell memory 1 of the path p5. At this time, four empty cells having no information are output next to the cell 1.

(B) Input of Cell 6 to Cell 10 FIG. 10 shows a state in which the next five cells of the first five cells, ie, cell 6 to cell 10 are further input in the convolutional interleaver 142. It represents.

In FIG. 10, in the convolutional interleaver 142, when the cell 6 is input, since the path p1 is selected, the cell 6 is output with a 0 delay.

Also, focusing on the dotted line A2 in the figure, the path p2 is selected in the convolutional interleaver 142 when the cell 7 is input, but the memory on the left side of the cell memory 1 of the path p2 is selected. Since the cell 2 is already stored, the cell 7 is pushed into the memory on the right side in the cell memory 1 by one cell and then the cell 7 is written there. As a result, in the cell memory 1 divided into two of the path p2, the cells 2 and 7 whose sizes are reduced to 1⁄2 are stored.

Similarly, in the convolutional interleaver 142, in the path p3, when the cell 8 pushes out the cell 3 by one cell, the cell 3 and the cell 8 are stored in the cell memory 1. In the path p4, the cell 9 pushes out the cell 4 by one cell, whereby the cell 4 and the cell 9 are stored in the cell memory 1. Furthermore, in the path p5, the cell 10 pushes out the cell 5 by one cell, whereby the cell 5 and the cell 10 are stored in the cell memory 1. At this time, four empty cells are output next to the cell 6.

(C) Input of Cells 11 to 15 FIG. 11 shows a state in which the next five cells, ie, cells 11 to 15 are further input in the convolutional interleaver 142.

In FIG. 11, in the convolutional interleaver 142, when the cell 11 is input, since the path p1 is selected, the cell 11 is output with a 0 delay.

Also, focusing on the dotted line A3 in the figure, in the convolutional interleaver 142, when the cell 12 is input, the path p2 is selected, but in the cell memory 1 of the path p2, the cell 2 is selected. Because the cell 7 is stored, the cell 2 previously stored in the cell memory 1 is pushed out to be read from the cell memory 1. As a result, in the cell memory 1 divided into two of the path p2, the cells 7 and 12 whose sizes are reduced to 1⁄2 are stored.

Furthermore, focusing on the dotted line A3 in the figure, in the convolutional interleaver 142, when the cell 13 is input, the path p3 is selected, but in the cell memory 1 of the path p3, the cell 3 is selected. Since the cell 8 is stored, the cell 3 previously stored in the cell memory 1 is pushed out to be delivered to the next cell memory 2. Thereby, in the path p 3, the cell 8 and the cell 13 are stored in the cell memory 1, and the cell 3 is stored in the cell memory 2.

Similarly, in the convolutional interleaver 142, the cell 14 pushes out the cell 4 and the cell 9 by one cell in the path p4, so that the cell 9 and the cell 14 are stored in the cell memory 1, The cell memory 2 stores the cell 4. Further, in the path p5, the cell 15 pushes out the cell 5 and the cell 10 by one cell, so that the cell 10 and the cell 15 are stored in the cell memory 1, and the cell 5 is stored in the cell memory 2. Stored. At this time, three empty cells are output next to the cell 11 and the cell 2.

Although not shown, in the convolutional interleaver 142, similarly, when the next five or more cells are input, the input cell has a 0 delay in the path p1 and the paths p2 to p In the path p5, the cells pushed out to the input cells are sequentially output. FIG. 12 shows the relationship between data input and output when the method 1-1 is adopted.

In FIG. 12, the convolutional interleaver 142 performs convolutional interleaving and extended interleaving when n cells such as cells 1 to 30 are sequentially input in cell units, and the cells after interleaving are cell units. Output sequentially with. In the case of this example, from the convolutional interleaver 142, cell 1, 4 empty cells, cell 6, 4 empty cells, cell 11, cell 2 and 3 empty cells, cell 16, cells 7 and 3 The empty cells, the cell 21, the cell 12, the cell 3, the two empty cells, the cell 26, the cell 17, the cell 8, the two empty cells,... Are sequentially output.

In FIG. 12, the numbers (light and dark numbers) attached to the cell memory of each pass of the convolutional interleaver 142 represent the index in the cell unit of each cell memory in the initial state. Further, among the cells to be output, cells to which numbers with light and shade are attached represent empty cells, and these numbers correspond to the index in the cell unit of each cell memory in the initial state. These relationships are the same in other figures described later.

As described above, when the method 1-1 is adopted, the convolutional interleaver 142 performs convolutional interleaving and extended interleaving on cells input in cell units, and the cells after the interleaving are cells. Output in units. In this case, although the convolutional interleaver 142 performs extended interleaving, since cells are interleaved in each memory unit, the time is continuous or close in time in one memory unit. Sorted so that cells are not included.

This makes it possible to disperse burst errors during transmission, so that it is possible to more effectively extract the ability of the error correction code by time interleaving. Further, in the time interleaver 117S, each memory unit is a cell dispersed in time without providing another interleaver before the convolutional interleaver 142 and without increasing the memory. It can be configured.

(B) Method 1-2: Cell distribution in a memory unit (cell unit input, MU unit output 1)

Next, method 1-2 will be described with reference to FIGS. 13 to 17.

In FIG. 13, the convolutional interleaver 142 sequentially receives n (n is an integer of 1 or more) cells such as the cells 1 to 15 from the BICM (the mapper 116). Also, in the convolutional interleaver 142, the input cell is written to the cell memory according to the selection of the paths p1 to p5, but since one address of each cell memory is divided into k, one memory unit It is possible to write k cells each time.

In this case, each cell memory can store k cells whose bit width is reduced to 1 / k. For example, in FIG. 13, since k = 2 is set, two cells each having a bit width of 1/2 are stored in each cell memory.

In the convolutional interleaver 142, cells whose bit width is halved are sequentially input in cell units and written to the cell memory of each path. Then, in the convolutional interleaver 142, cells in memory unit units are sequentially read out from the cell memory on the right side (output side) of the cell memories in each path, and are output in memory unit units. That is, in this scheme 1-2, cells from (the mapper 116 of) the BICM 102 are input in cell units and are output in memory unit units.

However, in the path p1, since no cell memory is provided, cells input in cell units are output as they are in cell units (0 delay). In the paths p2 to p5, cells input in cell units are output in memory unit units, but are converted from memory unit units into cell units by the memory unit cell demapper 143 and then output. Although only the convolutional interleaver 142 is illustrated in FIG. 13, actually, as described above, the cell / memory unit mapper 141 and the convolutional interleaver 142 operate in cooperation with each other. , Cells are processed in units of memory units.

(A) Input of Cell 1 to Cell 5 FIG. 14 shows a state in which the first five cells of the input cells in the convolutional interleaver 142, that is, cells 1 to 5 are input. ing. In FIGS. 14 to 16, it is assumed that the bit width of each cell input to the convolutional interleaver 142 is reduced to 1⁄2.

In FIG. 14, in the convolutional interleaver 142, when the cell 1 is input, since the path p1 is selected, the cell 1 is output with 0 delay. In other words, it can be said that one memory unit is regarded as one cell in the path p1 (branch) of 0 delay.

Also, focusing on the dotted line B1 in the figure, the cell 2 is divided into two in the cell memory 1 because the path p2 is selected in the convolutional interleaver 142 when the cell 2 is input. It is stored in the memory on the left side of Similarly, in the convolutional interleaver 142, the cell 3 is stored in the memory on the left side of the cell memory 1 in the path p3 and the cell 4 is stored in the memory on the left side of the cell memory 1 in the path p4. Are stored in the memory on the left side of the cell memory 1 of the path p5. At this time, next to cell 1, eight empty cells having no information are output.

(B) Input of Cell 6 to Cell 10 FIG. 15 shows the state in which the next five cells of the first five cells, ie, cell 6 to cell 10 are further input in the convolutional interleaver 142. It represents.

In FIG. 15, in the convolutional interleaver 142, when the cell 6 is input, since the path p1 is selected, the cell 6 is output with a 0 delay.

Also, focusing on the dotted line B2 in the figure, the path p2 is selected in the convolutional interleaver 142 when the cell 7 is input, but the memory on the left side of the cell memory 1 of the path p2 is selected. Since the cell 2 is already stored, the cell 7 is pushed into the memory on the right side in the cell memory 1 by one cell and then the cell 7 is written there. As a result, the cell 2 and the cell 7 are stored in the cell memory 1 divided into two of the path p2.

Similarly, in the convolutional interleaver 142, in the path p3, when the cell 8 pushes out the cell 3 by one cell, the cell 3 and the cell 8 are stored in the cell memory 1. In the path p4, the cell 9 pushes out the cell 4 by one cell, whereby the cell 4 and the cell 9 are stored in the cell memory 1. Furthermore, in the path p5, the cell 10 pushes out the cell 5 by one cell, whereby the cell 5 and the cell 10 are stored in the cell memory 1.

(C) Input of Cells 11 to 15 FIG. 16 shows a state in which the next five cells, ie, cells 11 to 15 are further input in the convolutional interleaver 142.

In FIG. 16, in the convolutional interleaver 142, when the cell 11 is input, since the path p1 is selected, the cell 11 is output with 0 delay.

Also, focusing on the dotted line B3 in the figure, in the convolutional interleaver 142, when the cell 12 is input, the path p2 is selected, but in the cell memory 1 of the path p2, the cell 2 is selected. And cell 7 are stored, so that the cells 2 and 7 are read from the cell memory 1 by pushing out these cells by one address (two cells). As a result, the cells 2 and 7 in one memory unit are output, and the cell 12 is stored in the memory on the left side of the cell memory 1 of the path p2.

Furthermore, focusing on the dotted line B3 in the figure, the convolutional interleaver 142 selects the path p3 when the cell 13 is input, but the cell 3 in the path p3 is a cell 3 Since the cell 8 is stored, the cells 3 and 8 are transferred from the cell memory 1 to the next cell memory 2 by pushing out these cells by one address (two cells). As a result, in the path p3, in the cell memory 1, the cell 13 is stored in the memory on the left side, and in the cell memory 2, the cell 3 and the cell 8 are stored.

Similarly, in the convolutional interleaver 142, in the path p4, the cell 14 pushes out the cell 4 and the cell 9 by one address (two cells), so that only the cell 14 is stored in the cell memory 1. The cell 4 and the cell 9 are stored in the next cell memory 2. Further, in the path p5, the cell 15 pushes out the cell 5 and the cell 10 by one address (two cells), so that only the cell 15 is stored in the cell memory 1, and the memory unit 2 next to it is stored. Cell 5 and cell 10 are stored. Six empty cells are output next to the cell 11, the cell 2 and the cell 7.

Although not shown, in the convolutional interleaver 142, similarly, when the next five or more cells are input, the input cell has a 0 delay in the path p1 and the paths p2 to p In path p5, the two cells pushed out to the input cells are sequentially output in units of memory units. FIG. 17 shows the relationship between data input and output when method 1-2 is adopted.

In FIG. 17, when n cells such as cells 1 to 30 are sequentially input in cell units, the convolutional interleaver 142 performs convolutional interleaving and extended interleaving, and the cells after interleaving are cell units. Or output sequentially in units of memory units. In this example, from the convolutional interleaver 142, cell 1, eight empty cells, cell 6, cell 11, cell 2 and cell 7, six empty cells, cell 16, cell 21, cell 12 and cell 17, cell 3, cell 8, four empty cells, cell 26,... Are sequentially output.

As described above, when scheme 1-2 is adopted, convolutional interleaver 142 performs convolutional interleaving and extended interleaving on cells input in cell units, and the cells after interleaving are cells Output in units or memory units. In this case, although the convolutional interleaver 142 performs extended interleaving, since cells are interleaved in each memory unit, the time is continuous or close in time in one memory unit. Sorted so that cells are not included.

This makes it possible to disperse burst errors during transmission, so that it is possible to more effectively extract the ability of the error correction code by time interleaving. Further, in the time interleaver 117S, each memory unit is a cell dispersed in time without providing another interleaver before the convolutional interleaver 142 and without increasing the memory. It can be configured.

(C) Method 1-3: Cell distribution in a memory unit (cell unit input, MU unit output 2)

Next, methods 1-3 will be described with reference to FIGS. 18 to 25.

In FIG. 18, the convolutional interleaver 142 sequentially receives n (n is an integer of 1 or more) cells such as the cells 1 to 15 from the BICM (the mapper 116). Also, in the convolutional interleaver 142, the input cell is written to the cell memory according to the selection of the paths p1 to p5, but since one address of each cell memory is divided into k, one memory unit It is possible to write k cells each time.

In this case, each cell memory can store k cells whose bit width is reduced to 1 / k. For example, in FIG. 18, since k = 2 is set, two cells each having a half bit width are stored in each cell memory.

In the convolutional interleaver 142, cells whose bit width is halved are sequentially input in cell units and written to the cell memory of each path. Then, in the convolutional interleaver 142, cells in memory unit units are sequentially read out from the cell memory on the right side (output side) of the cell memories in each path, and are output in memory unit units. That is, in this scheme 1-3, cells from (the mapper 116 of) the BICM 102 are input in cell units and are output in memory unit units.

However, in the paths p1 to p5, cells input in cell units are output in memory unit units, but are converted from memory unit units into cell units by the memory unit cell demapper 143 and then output. Although only the convolutional interleaver 142 is illustrated in FIG. 18, in actuality, the cell / memory unit mapper 141 and the convolutional interleaver 142 operate in cooperation as described above. , Cells are processed in units of memory units.

(A) Input of Cell 1 to Cell 5 FIG. 19 shows a state in which the first five cells of the input cells in the convolutional interleaver 142, that is, the cells 1 to 5 are input. ing. In FIGS. 19 to 24, it is assumed that the bit width of each cell input to the convolutional interleaver 142 is reduced to 1⁄2.

In FIG. 19, in the convolutional interleaver 142, when the cell 1 is input, the path p1 is selected, but it is not output at 0 delay, and waits until two cells for one memory unit are aligned.

Also, focusing on the dotted line C1 in the figure, in the convolutional interleaver 142, when the cell 2 is input, the path p2 is selected. It is stored in the memory on the left side of Similarly, in the convolutional interleaver 142, the cell 3 is stored in the memory on the left side of the cell memory 1 in the path p3 and the cell 4 is stored in the memory on the left side of the cell memory 1 in the path p4. Are stored in the memory on the left side of the cell memory 1 of the path p5. At this time, eight empty cells having no information are output.

(B) Input of Cell 6 to Cell 10 FIG. 20 shows the state where the next five cells of the first five cells, ie, cell 6 to cell 10 are further input in the convolutional interleaver 142. It represents.

In FIG. 20, since the path p1 is selected when the cell 6 is input in the convolutional interleaver 142, two cells for one memory unit are aligned by this cell 6 and the cell 1 on standby. It will be. Thereby, the cell 1 and the cell 6 constituting one memory unit are simultaneously output.

Further, focusing on the dotted line C2 in the figure, the path p2 is selected in the convolutional interleaver 142 when the cell 7 is input, but the memory on the left side of the cell memory 1 of the path p2 is selected. Since the cell 2 is already stored, the cell 7 is pushed into the memory on the right side in the cell memory 1 by one cell and then the cell 7 is written there. As a result, the cell 2 and the cell 7 are stored in the cell memory 1 divided into two of the path p2.

Similarly, in the convolutional interleaver 142, in the path p3, the cell 8 pushes out the cell 3 by one cell, whereby the cell 3 and the cell 8 are stored in the cell memory 1. In the path p4, the cell 9 pushes out the cell 4 by one cell, whereby the cell 4 and the cell 9 are stored in the cell memory 1. Furthermore, in the path p5, the cell 10 pushes out the cell 5 by one cell, whereby the cell 5 and the cell 10 are stored in the cell memory 1.

(C) Input of Cells 11 to 15 FIG. 21 shows a state in which the next five cells, ie, cells 11 to 15 are further input in the convolutional interleaver 142.

In FIG. 21, in the convolutional interleaver 142, when the cell 11 is input, although the path p1 is selected, two cells for one memory unit are not aligned, so the cell 11 is made to stand by as it is.

Also, focusing on the dotted line C3 in the figure, in the convolutional interleaver 142, when the cell 12 is input, the path p2 is selected, but in the cell memory 1 of the path p2, the cell 2 is selected. And cell 7 are stored, so that these cells are pushed out by one address (two cells) to allow cell 2 and cell 7 to be read out. As a result, the cells 2 and 7 in one memory unit are output, and the cell 12 is stored in the memory on the left side of the cell memory 1 of the path p2.

Furthermore, if attention is paid to the dotted line C3 in the figure, the path p3 is selected in the convolutional interleaver 142 when the cell 13 is input, but the cell 3 in the path p3 is a cell 3 Since the cell 8 is stored, the cells 3 and 8 are transferred from the cell memory 1 to the next cell memory 2 by pushing out these cells by one address (two cells). As a result, in the path p3, in the cell memory 1, the cell 13 is stored in the memory on the left side, and in the cell memory 2, the cell 3 and the cell 8 are stored.

Similarly, in the convolutional interleaver 142, in the path p4, the cell 14 pushes out the cell 4 and the cell 9 by one address (two cells), so that only the cell 14 is stored in the cell memory 1. The cell memory 2 stores the cell 4 and the cell 9. In the path p5, the cell 15 pushes out the cell 5 and the cell 10 by one address (two cells), so that only the cell 15 is stored in the cell memory 1, and the cell 5 and the cell memory 2 are stored. Cell 10 is stored. Six empty cells are output next to the cell 2 and the cell 7.

(D) Input of Cell 16 to Cell 20 FIG. 22 shows the state in which the next five cells, ie, cell 16 to cell 20, are further input in the convolutional interleaver 142.

In FIG. 22, in the convolutional interleaver 142, when the cell 16 is input, the path p1 is selected, so that two cells for one memory unit are aligned by this cell 16 and the cell 11 on standby. It will be. Thereby, the cell 11 and the cell 16 which constitute one memory unit are simultaneously output.

Also, focusing on the dotted line C4 in the figure, the path p2 is selected in the convolutional interleaver 142 when the cell 17 is input, but the memory on the left side of the cell memory 1 of the path p2 is selected. Since the cell 12 is already stored, the cell 17 is pushed to the right memory in the cell memory 1 by one cell, and then the cell 17 is written there. As a result, the cell 12 and the cell 17 are stored in the cell memory 1 divided into two of the path p2.

Similarly, in the convolutional interleaver 142, in the path p3, the cell 18 pushes out the cell 13 by one cell, whereby the cell 13 and the cell 18 are stored in the cell memory 1. In the path p4, the cell 19 pushes out the cell 14 by one cell, whereby the cell 14 and the cell 19 are stored in the cell memory 1. Furthermore, in the path p5, the cell 20 pushes out the cell 15 by one cell, whereby the cell 15 and the cell 20 are stored in the cell memory 1.

(E) Input of Cells 21 to 25 FIG. 23 shows a state in which the next five cells, ie, cells 21 to 25 are further input in the convolutional interleaver 142.

In FIG. 23, in the convolutional interleaver 142, when the cell 21 is input, although the path p1 is selected, two cells for one memory unit are not aligned, so the cell 21 is put on standby as it is.

Also, focusing on the dotted line C5 in the figure, in the convolutional interleaver 142, when the cell 22 is input, the path p2 is selected, but in the cell memory 1 of the path p2, the cell 12 is selected. Since the cells 17 are stored, these cells are pushed out by one address (two cells) so that the cells 12 and 17 can be read out. As a result, the cells 12 and 17 in one memory unit are output, and only the cell 22 is stored in the cell memory 1 of the path p2.

Furthermore, focusing on the dotted line C5 in the figure, the path p3 is selected in the convolutional interleaver 142 when the cell 23 is input, but in the path p3, the cell memory 1 contains the cell 13 and so on. Since the cell 18 is stored and the cell 3 and the cell 8 are stored in the cell memory 2, these cells are pushed out by one address (two cells). Thereby, in the path p3, the cells 3 and 8 stored in the cell memory 2 are read out and output. In the path p3, the cell 23 is stored in the memory on the left side of the cell memory 1, and the cell 13 and the cell 18 are stored in the cell memory 2.

Similarly, in the convolutional interleaver 142, in the path p4, the cell 24 pushes out the cell 4 and the cell 9 and the cell 14 and the cell 19 by one address (two cells). Only the cell 24 is stored, the cell memory 2 stores the cell 14 and the cell 19, and the cell memory 3 stores the cell 4 and the cell 9. Further, in the path p5, the cell 25 pushes out the cell 5 and the cell 10, the cell 15 and the cell 20 by one address (two cells), so that only the cell 25 is stored in the cell memory 1, The cell 2 stores the cell 15 and the cell 20, and the cell memory 3 stores the cell 5 and the cell 10. Four empty cells are output next to the cells 12 and 17 and the cells 3 and 8.

(F) Input of Cell 26 to Cell 30 FIG. 24 shows the state in which the next five cells, ie, cell 26 to cell 30 are further input in the convolutional interleaver 142.

In FIG. 24, in the convolutional interleaver 142, when the cell 26 is input, the path p1 is selected, so that two cells for one memory unit are aligned by this cell 26 and the cell 21 on standby. It will be. As a result, the cells 21 and 26 constituting one memory unit are simultaneously output.

Also, focusing on the dotted line C6 in the figure, the path p2 is selected in the convolutional interleaver 142 when the cell 27 is input, but the memory on the left side of the cell memory of the path p2 is Since the cell 22 is already stored, the cell 22 is pushed out to the memory on the right side in the cell memory 1 by one cell, and the cell 27 is written there. As a result, the cell 22 and the cell 27 are stored in the cell memory 1 divided into two of the path p2.

Similarly, in the convolutional interleaver 142, in the path p3, the cell 28 pushes out the cell 23 by one cell, whereby the cell 23 and the cell 28 are stored in the cell memory 1. In the path p4, the cell 29 pushes out the cell 24 by one cell, whereby the cell 24 and the cell 29 are stored in the cell memory 1. Furthermore, in the path p5, the cell 30 pushes out the cell 25 by one cell, whereby the cell 25 and the cell 30 are stored in the cell memory 1.

Although not shown, in the convolutional interleaver 142, two cells after one memory unit is aligned are stored in the path p1 in the same manner even when the next five or more cells are further input. In the unit unit, in the path p2 to the path p5, the two cells pushed out to the input cell are sequentially output in the memory unit unit. FIG. 25 shows the relationship between data input and output when scheme 1-3 is adopted.

In FIG. 25, when n cells such as cells 1 to 30 are sequentially input in cell units, the convolutional interleaver 142 performs convolutional interleaving and extended interleaving, and the cells after interleaving are stored as memory units. Output sequentially in units. In this example, from the convolutional interleaver 142, eight empty cells, cell 1 and cell 6, cell 2 and cell 7, six empty cells, cell 11 and cell 16, cell 12 and cell 17, cell 3 and cell 8, four empty cells, cell 21 and cell 26,... Are sequentially output.

As described above, when scheme 1-3 is adopted, convolutional interleaver 142 performs convolutional interleaving and extended interleaving on cells input in cell units, and the cells after interleaving are stored in memory. Output in units of units. In this case, although the convolutional interleaver 142 performs extended interleaving, since cells are interleaved in each memory unit, the time is continuous or close in time in one memory unit. Sorted so that cells are not included.

This makes it possible to disperse burst errors during transmission, so that it is possible to more effectively extract the ability of the error correction code by time interleaving. Further, in the time interleaver 117S, each memory unit is a cell dispersed in time without providing another interleaver before the convolutional interleaver 142 and without increasing the memory. It can be configured.

(D) Method 1-4: Cell distribution in memory unit (cell unit input, MU unit output 3)

Finally, the scheme 1-4 will be described with reference to FIGS. 26 to 32. In scheme 1-4, paths (branches) with zero delay are eliminated.

In FIG. 26, the convolutional interleaver 142 sequentially receives n (n is an integer of 1 or more) cells such as the cells 1 to 15 from the BICM (the mapper 116). Also, in the convolutional interleaver 142, the input cell is written to the cell memory according to the selection of the paths p1 to p4, but since one address of each cell memory is divided into k, one memory unit It is possible to write k cells each time.

In this case, each cell memory can store k cells whose bit width is reduced to 1 / k. For example, in FIG. 26, since k = 2 is set, two cells each having a bit width of 1/2 are stored in each cell memory.

In the convolutional interleaver 142, cells whose bit width is halved are sequentially input in cell units and written to the cell memory of each path. Then, in the convolutional interleaver 142, cells in memory unit units are sequentially read out from the cell memory on the right side (output side) of the cell memories in each path, and are output in memory unit units. That is, in this scheme 1-4, cells from (the mapper 116 of) the BICM 102 are input in cell units and are output in memory unit units.

However, in the paths p1 to p4, cells input in cell units are output in memory unit units, but are converted from memory unit units into cell units by the memory unit cell demapper 143 and then output. Although only the convolutional interleaver 142 is illustrated in FIG. 26, actually, as described above, the cell / memory unit mapper 141 and the convolutional interleaver 142 operate in cooperation with each other. , Cells are processed in units of memory units.

(A) Input of Cell 1 to Cell 4 FIG. 27 shows a state in which the first four cells of the input cells in the convolutional interleaver 142, that is, cells 1 to 4 are input. ing. In FIGS. 27 to 31, it is assumed that the bit width of each cell input to the convolutional interleaver 142 is reduced to 1⁄2.

In FIG. 27, focusing on the dotted line D1 in the figure, the convolutional interleaver 142 selects the cell p when the cell 1 is input, so the cell 1 is divided into two cells. It is stored in the memory on the left side of 1. Similarly, in the convolutional interleaver 142, cell 2 is stored in cell memory 1 of path p2, cell 3 is stored in cell memory 1 of path p3, and cell 4 is cell memory 1 of path p4. Stored in At this time, eight empty cells having no information are output.

(B) Input of Cell 5 to Cell 8 FIG. 28 shows the state in which the next four cells of the first four cells, ie, cell 5 to cell 8 are further input in the convolutional interleaver 142. It represents.

In FIG. 28, focusing on the dotted line D2 in the figure, the convolutional interleaver 142 selects the path p1 when the cell 5 is input, but the memory on the left side of the cell memory 1 of the path p1. Since the cell 1 is already stored in the cell memory 1, the cell 5 is pushed into the memory on the right side of the cell memory 1 by one cell and then the cell 5 is written there. As a result, the cell 1 and the cell 5 are stored in the cell memory 1 of the path p1.

Similarly, in the convolutional interleaver 142, the cell 6 pushes out the cell 2 by one cell in the path p2, whereby the cell 2 and the cell 6 are stored in the cell memory 1. In the path p3, the cell 7 pushes out the cell 3 by one cell, whereby the cell 3 and the cell 7 are stored in the cell memory 1. Furthermore, in the path p4, the cell 8 pushes out the cell 4 by one cell, whereby the cell 4 and the cell 8 are stored in the cell memory 1. At this time, the cell is not read out.

(C) Input of Cell 9 to Cell 12 FIG. 29 shows a state in which the next four cells, ie, cell 9 to cell 12 are further input in the convolutional interleaver 142.

In FIG. 29, focusing on the dotted line D3 in the figure, the path p1 is selected in the convolutional interleaver 142 when the cell 9 is input, but in the cell memory 1 of the path p1, Since the cell 1 and the cell 5 are stored, these cells are pushed out by one address (two cells) so that the cell 1 and the cell 5 can be read out. As a result, the cell 1 and the cell 5 in one memory unit are output, and the cell 9 in the memory on the left side of the cell memory 1 of the path p1 is stored.

Also, focusing on the dotted line D3 in the figure, in the convolutional interleaver 142, when the cell 10 is input, the path p2 is selected, but in the cell memory 1 of the path p2, the cell 2 is selected. Since the cell 6 is stored, the cells 2 and 6 are transferred from the cell memory 1 to the next cell memory 2 by pushing out these cells by one address (two cells). As a result, in the path p2, in the cell memory 1, the cell 10 is stored in the memory on the left side, and in the memory unit 2, the cell 2 and the cell 6 are stored.

Similarly, in the convolutional interleaver 142, in the path p3, the cell 11 pushes out the cell 3 and the cell 7 by one address (two cells), so that only the cell 11 is stored in the cell memory 1. The cell memory 2 stores the cell 3 and the cell 7. Also, in the path p 4, the cell 12 pushes out the cell 4 and the cell 8 by one address (two cells), so that only the cell 12 is stored in the cell memory 1, and the cell 4 is stored in the cell memory 2. Cell 8 is stored. Six empty cells are output next to the cell 1 and the cell 5.

(D) Input of Cells 13 to 16 FIG. 30 shows a state in which the next four cells, ie, cells 13 to 16 are further input in the convolutional interleaver 142.

In FIG. 30, focusing on the dotted line D4 in the figure, the convolutional interleaver 142 selects the path p1 when the cell 13 is input, but the memory on the left side of the cell memory 1 of the path p1. Since the cell 9 is already stored in the cell memory 1, the cell 13 is pushed into the memory on the right side in the cell memory 1 by one cell, and then the cell 13 is written there. As a result, the cell 9 and the cell 13 are stored in the cell memory 1 of the path p1.

Similarly, in the convolutional interleaver 142, the cell 14 pushes out the cell 10 by one cell in the path p2, whereby the cell 10 and the cell 14 are stored in the cell memory 1. In the path p3, the cell 15 pushes out the cell 11 by one cell, whereby the cell 11 and the cell 15 are stored in the cell memory 1. Furthermore, in the path p4, the cell 16 pushes out the cell 12 by one cell, whereby the cell 12 and the cell 16 are stored in the cell memory 1. At this time, the cell is not read out.

(E) Input of Cell 17 to Cell 20 FIG. 31 shows a state in which the next four cells, ie, cell 17 to cell 20, are further input in the convolutional interleaver 142.

In FIG. 31, focusing on the dotted line D5 in the figure, the convolutional interleaver 142 selects the path p1 when the cell 17 is input, but in the cell memory 1 of the path p1, Since the cell 9 and the cell 13 are stored, these cells are pushed out by one address (two cells) so that the cell 9 and the cell 13 can be read out. As a result, the cells 9 and 13 in one memory unit are output, and only the cell 17 is stored in the cell memory 1 of the path p1.

Also, focusing on the dotted line D5 in the figure, the path p2 is selected in the convolutional interleaver 142 when the cell 18 is input, but the cell memory 1 and the cell 10 are selected in the path p2. Since the cell 14 is stored, and the cell 2 and the cell 6 are stored in the cell memory 2, these cells are pushed out by one address (two cells). As a result, in the path p2, the cell 2 and the cell 6 stored in the cell memory 2 are read out, and only the cell 18 is stored in the cell memory 1, and the cell 10 and the cell are stored in the cell memory 2. 14 will be stored.

Similarly, in the convolutional interleaver 142, in the path p3, the cell 19 pushes out the cell 3 and the cell 7 and the cell 11 and the cell 15 by one address (two cells). Only the cell 19 is stored, the cell 11 stores the cell 11 and the cell 15, and the cell memory 3 stores the cell 3 and the cell 7. In the path p4, the cell 20 pushes out the cells 4 and 8 and the cells 12 and 16 by one address (two cells), so that only the cell 20 is stored in the cell memory 1, and the cell memory 1 is stored. The cell 12 stores the cell 12 and the cell 16, and the cell memory 3 stores the cell 4 and the cell 8. It should be noted that four empty cells are output next to the cell 9 and the cell 13 and the cell 2 and the cell 6.

Although not shown, the convolutional interleaver 142 similarly pushes out the input cells in the paths p1 to p4 even when the next five or more cells are input. Two cells are sequentially output in units of memory units. FIG. 32 shows the relationship between data input and output when scheme 1-4 is adopted.

In FIG. 32, the convolutional interleaver 142 performs convolutional interleaving and extended interleaving when n cells such as cells 1 to 32 are sequentially input in cell units, and the cells after the interleaving are stored in memory. Output sequentially in units of units. In this example, from the convolutional interleaver 142, eight empty cells, cell 1 and cell 5, six empty cells, cell 9 and cell 13, cell 2 and cell 6, four empty cells, cell 17 and cell 21, cell 10 and cell 14, cell 3 and cell 7, two empty cells, cell 25 and cell 29, cell 18 and cell 22, cell 11 and cell 15, cell 4 and cell 8, ... Are output sequentially.

As described above, when scheme 1-4 is adopted, convolutional interleaver 142 performs convolutional interleaving and extended interleaving on cells input in cell units, and the cells after interleaving are stored in memory. Output in units of units. In this case, although the convolutional interleaver 142 performs extended interleaving, since cells are interleaved in each memory unit, the time is continuous or close in time in one memory unit. Sorted so that cells are not included.

This makes it possible to disperse burst errors during transmission, so that it is possible to more effectively extract the ability of the error correction code by time interleaving. Further, in the time interleaver 117S, each memory unit is a cell dispersed in time without providing another interleaver before the convolutional interleaver 142 and without increasing the memory. It can be configured.

Note that although methods 1-1 to 1-4 have been described as methods of time interleaving performed by (the convolutional interleaver 142 of) the time interleaver 117S, those four methods are an example, and one memory In the case where a plurality of cells are stored in a unit, another method is adopted as long as it can be rearranged so that temporally continuous or temporally similar cells are not included in one memory unit. You may do so.

In addition, in the time interleaver 117S, the case has been described where the convolutional interleaver 142 is provided as an interleaver for performing time interleaving, but another interleaver is provided downstream of the convolutional interleaver 142. It may be possible to

(2) A time interleaver compatible with M-PLP

(Example of configuration of time interleaver)
FIG. 33 is a block diagram showing a configuration example of the time interleaver 117M corresponding to M-PLP.

The time interleaver 117M performs time interleaving corresponding to M-PLP. In FIG. 33, the time interleaver 117M is composed of a cell interleaver 161, a cell memory unit mapper 162, a block interleaver 163, a convolutional interleaver 164, and a memory unit cell demapper 165.

Although the cell interleaver 161 and the cell memory unit mapper 162 are illustrated as separate blocks in FIG. 33, in practice, the cell interleaver 161 and the cell memory unit mapper 162 cooperate with each other. As a result, the cells are processed in units of memory units.

The cell interleaver 161 performs cell interleaving for cells including data according to a predetermined modulation scheme, which is input from (the mapper 116 of) the BICM 102. Also, the cell memory unit mapper 162 maps cells (for example, one cell or two cells) input to the cell interleaver 161 into one memory unit, and converts the unit of cells output from the cell interleaver 161 Do.

The block interleaver 163 performs block interleaving on the output from the cell memory unit mapper 162, and outputs the data after block interleaving to the convolutional interleaver 164.

The convolutional interleaver 164 performs convolutional interleaving on the output from the block interleaver 163, and outputs the data after convolutional interleaving to the memory unit cell demapper 165.

The memory unit / cell demapper 165 demaps the memory unit to a cell and converts it into a cell (for example, 1 cell or 2 cells) for the output from the convolutional interleaver 164, and then the frame processing unit 118 in the subsequent stage. Output to

As described above, in the time interleaver 117M, M-PLP is supported by performing cell interleaving by the cell interleaver 161, block interleaving by the block interleaver 163, and convolutional interleaving by the convolutional interleaver 164. Time interleaving is realized.

(Basic operation of cell interleaver)
Here, the basic operation of the cell interleaver 161 of FIG. 33 will be described with reference to FIG.

A in FIG. 34 schematically represents the write processing in the cell interleaver 161, N _cells in the column direction represent the number of cells for one code word, and N _{FEC — TI in} the row direction represents the number of columns. There is. That is, in the cell interleaver 161, when the cells output from the BICM 102 (of the mapper 116) and represented by the squares with numbers in the figure are sequentially written in the memory in the column direction, For each column, cells for one code word are written.

B in FIG. 34 schematically represents the read processing in the cell interleaver 161, N _cells in the column direction represent the number of cells for one code word, and N _{FEC — TI in} the row direction represents the number of columns. There is. That is, in the cell interleaver 161, the cells written to the memory in the column direction by the write processing in A of FIG. 34, and the cells represented by squares with numbers in the figure are the memory in the column direction. When sequentially read out of cells, cells are randomly read out for each code word of each column.

As described above, in the cell interleaver 161, cell interleaving is realized by performing the write process of A in FIG. 34 and the read process of B in FIG. 34 on the memory in the column direction.

(Basic operation of block interleaver)
Next, the basic operation of the block interleaver 163 of FIG. 33 will be described with reference to FIG.

A in FIG. 35 schematically represents the write processing in the block interleaver 163, N _cells in the column direction represent the number of cells for one code word, and N _{FEC — TI in} the row direction represents the number of columns. There is. Further, among the cells represented by squares in the drawing, hatched cells represent effective cells, and non-hatched cells represent dummy cells.

That is, block interleaver 163 is a cell output from cell interleaver 161, and when effective cells are sequentially written in the memory in the column direction, cells for one code word are written for each column. . However, in FIG. 35A, dummy cells are stored in the memories of the first and second columns. In addition, in the writing process of A in FIG. 35, N _{FEC — TI} (N _{FEC — TI} ≦ N _{FEC — TI — MAX} ) codewords are processed as one unit.

B in FIG. 35 schematically represents the read processing in the block interleaver 163, N _cells in the column direction represent the number of cells for one code word, and N _{FEC — TI in} the row direction represents the number of columns. There is.

That is, the block interleaver 163 sequentially reads out, from the memory, cells which are written in the memory in the column direction by the write processing of A in FIG. At the same time, the cells are read diagonally.

Specifically, in the block interleaver 163, the reading process is performed in the following steps S1 to S4.

In step S1, an initial value is set with i = 0, j = 0 and start_j = 0. Further, in step S2, an element of i row and j column in the memory which is a cell written by the writing process of A in FIG. 35 is read.

In step S3, i = (i + 1) mod N _{FEC_TI_MAX} , j = (j + 1) is set. However, the mod function is a function for obtaining the remainder.

In step S4, it is determined whether the relationship of j <N _cells is satisfied. If the relation of j <N _cells is satisfied, the process returns to step S2, and the subsequent processes are repeated. On the other hand, when the relation of j <N _cells is not satisfied, i = 0 and j = start_j are set as start_j = start_j + 1, and then the process returns to step S2, and the subsequent processes are repeated.

By repeating such a procedure, in the read process of B in FIG. 35, cells are read in an oblique direction. However, in this case, the dummy cell may or may not be read together with the effective cell.

As described above, in the block interleaver 163, block interleaving is realized by performing the write process of A in FIG. 35 and the read process of B in FIG.

(Basic operation of convolutional interleaver)
Next, with reference to FIG. 36, the basic operation of the convolutional interleaver 164 of FIG. 33 will be described.

In FIG. 36, a square having Mi _{and j} in the convolutional interleaver 164 represents a FIFO (First In First Out) memory of i rows and j columns. In the convolutional interleaver 164, FIFO memory of (L _IU +1) × N _{FEC_TI_MAX} stage (1 ≦ i ≦ (N _r mod N _IU )), or FIFO memory of L _IU × N _{FEC_TI_MAX} stage (i>(N>) _r mod N _IU )) is provided.

However, the relationship of L _IU = floor (N _r / N _IU ) is satisfied. Here, the floor function is a so-called floor function. Also, N _r represents the number of rows of the block interleaver 163 in the previous stage, and N _IU represents the number of divisions. Also, N _{FEC — TI — MAX} represents the number of columns of the block interleaver 163 at the _previous stage.

That is, in the convolutional interleaver 164, although the FIFO memory is not provided in the path p0, there is a lower level such as one FIFO memory in the path p1 and two FIFO memories in the path p2. There is more memory in the path of, in which data is written. However, since the FIFO memory is not provided in the path p0, the input data is used as the output data as it is. Also, in each path FIFO memory, one or more cells can be stored.

In the convolutional interleaver 164 configured as described above, the input switch S0 and the output switch S1 are switched in synchronization with each other at the timing when N _{FEC — TI — MAX} cells are input (output). The convolutional interleaving is realized by writing a cell to the FIFO memory or reading a cell from the FIFO memory. Here, for example, when the input switch S0 switches from the path p0 to the path p1, the output switch S1 also switches from the path p0 to the path p1.

(Extended interleave)
By the way, in DVB-NGH, as shown in FIG. 37, it is defined that a cell interleaver 411 is provided at the front stage of the time interleaver 412. In this case, in the cell interleaver 411, the cells are randomly rearranged for each code word in each column, so that two cells constituting one memory unit (MU) are temporally dispersed. (Pairwise interleaving). Then, the time interleaver 412 rearranges the cells rearranged by the cell interleaver 411 in units of memory units for each code word.

For example, in FIG. 37, when one code word is composed of cells 1 to 8, cell interleaver 411 rearranges those cells so that each memory unit in one code word can be replaced with cell 2 and so on. Two cells of cell 8, cell 4 and cell 6, cell 7 and cell 1, cell 5 and cell 3 are formed respectively. As a result, two cells in each memory unit are dispersed.

The time interleaver 412 then uses the cells in memory unit units rearranged by the cell interleaver 411 in the cells 4 and 6, the cells 5 and 3, the cells 2 and 8, and the cells 7 in one code word. And cell 1 in order. As a result, two cells in each memory unit are dispersed, but when viewed as one code word, they are comprised of cell 1 to cell 8 as before, and cells are dispersed in one code word. Absent.

Therefore, in the present technology, when a plurality of cells are stored in one memory unit as extended interleaving when using a time interleaver 117M corresponding to M-PLP, the cells from a plurality of code words are combined to 1 We shall propose a scheme for configuring the memory unit.

(A) Scheme 2: Cell distribution within a code word

Here, although the method 2 will be described, for comparison, the cell interleaving by the conventional cell interleaver 411 (FIG. 37) will be described with reference to FIG. 38, and then the present technology will be described with reference to FIG. Cell interleaving (and extended interleaving) by the cell interleaver 161 (FIG. 33) will be described.

(Conventional cell interleaving)
First, cell interleaving performed by the cell interleaver 411 of FIG. 37 will be described with reference to FIG. However, in this example, one memory unit is configured by two cells, and each cell contains data according to QPSK.

In FIG. 38, cells 1 to 8 constituting one code word are input to the cell interleaver 411 in that order. The cell interleaver 411 randomly arranges the cells 6, 4, 7, 3, 5, 5, 2, 8 and 1 in one code word when the cells are written to the memory. Perform cell interleaving by replacing.

When the cell interleaver 411 reads out the cells written in the memory, the cells 6 and 4, the cells 7 and 3, the cells 5 and 2, and the cells 8 and 1 are included in one code word. To each two cells constituting one memory unit.

As described above, in the cell interleaving by the cell interleaver 411, two cells in each memory unit can be dispersed, but if it is viewed as one code word, it is configured from cell 1 to cell 8 as before, and one code In words, it means that cells can not be distributed. Therefore, the number of errors in one code word is not reduced.

(Cell interleaving of this technology)
Next, with reference to FIG. 39, cell interleaving and extended interleaving performed by the cell interleaver 161 of FIG. 33 will be described. However, in this example, assuming that ATSC 3.0, one memory unit is configured by two cells, and each cell includes data according to QPSK.

In FIG. 39, cells of different code words, ie, cells 1 to 8 forming one code word and cells 11 to 18 forming another code word are simultaneously input to cell interleaver 161. ing. The cell interleaver 161 rearranges the cells randomly in one code word when writing cells of those different code words in the memory, and reduces the bit width to 1/2 and then changes the code into one memory unit. Allow 2 cells consisting of words to be written.

Specifically, the cell interleaver 161 reduces the bit width of each cell to 1⁄2, and the cells 6 and 18, the cells 4 and 16, the cells 7 and 12, the cells 3 and 15, the cell 5 As shown in FIG. 5, the memory cells are configured by two cells of different code words in one memory unit, such as cell 11, cell 2 and cell 17, cell 8 and cell 14, and cell 1 and cell 13.

As described above, in the case where one memory unit is composed of k cells, when using a low-order modulation scheme such as QPSK, even if the bit width per cell is 1 / k, the performance is degraded Here, too, the bit width of each cell is reduced to 1/2 because it falls within the allowable range.

When the cell interleaver 161 reads out the cells written in the memory, the cell 6 and the cell 18, the cell 4 and the cell 16, the cell 7 and the cell 12, and the cell 3 and the cell 15 in memory unit units of 2 cells. The cells 5 and 11, the cells 2 and 17, the cells 8 and 14, and the cells 1 and 13 are sequentially output.

As described above, here, the cell interleaver 161 and the cell memory unit mapper 162 operate in cooperation to process the cells in units of memory units.

As described above, when scheme 2 is adopted, in the case of storing a plurality of cells (for example, 2 cells) in one memory unit in the cell interleaver 161 as extended interleaving, a plurality of code words (for example, 2 codes) Words) are rearranged to combine one cell from each code word into one memory unit. That is, the memory unit is configured by cells of different code words.

This makes it possible to disperse burst errors during transmission, so that it is possible to more effectively extract the ability of the error correction code by time interleaving. Also, in the time interleaver 117M, the cell interleaver 161 and the cell memory unit mapper 162 operate in cooperation to perform processing in units of memory units, so that cells of different code words can be obtained without increasing memory. And the memory unit can be configured.

In the above description, the case where k = 2 is set is described, but even when another value is set as the value of k, processing is performed in the same manner as when one memory unit is configured by two cells. be able to. Further, in the time interleaver 117M, the block interleaver 163 and the convolutional interleaver 164 are provided downstream of the cell interleaver 161 and the cell memory unit mapper 162. Among these interleavers, A configuration in which one or both are not provided or a configuration in which another interleaver different from these interleavers is provided may be adopted.

(Transmission process)
Next, the transmission process performed by the transmission device 10 of FIG. 2 will be described with reference to the flowchart of FIG.

In step S101, the input format processing unit 101 performs input data processing. In this input data processing, necessary processing is performed on an input stream to be input, and a packet storing data obtained thereby is distributed to one or more PLPs.

In step S102, the BICM processing unit 102 performs encoding / modulation processing. In this encoding / modulation processing, processing such as error correction processing, bit interleaving, orthogonal modulation and the like is performed.

In step S103, the FRM / INT processing unit 103 performs frame interleaving processing. In this frame interleaving processing, processing such as interleaving in the time direction or frequency direction is performed.

Here, as the time interleaving, when S-PLP is input, time interleaving is performed by the time interleaver 117S (FIG. 3), and when M-PLP is input, the time interleaver 117M (FIG. The time interleaving according to FIG. 33) is performed.

In step S104, the waveform processing unit 104 performs waveform processing. In this waveform processing, an OFDM signal corresponding to a frame is generated and transmitted through the transmission line 30.

The transmission process has been described above.

<3. Configuration Example of Receiver>

(Example of configuration of receiving device)
FIG. 41 is a block diagram showing a configuration example of the receiving device 20 of FIG. In FIG. 41, blocks surrounded by dotted lines are blocks used when using MIMO.

The receiving device 20 includes a waveform (WAVEFORM) processing unit 201-1, an FRM / De-INT (FRAME and DEINTERLEAVING) processing unit 202-1, a De-BICM processing unit 203-1, and an output format (OUTPUT FORMAT). It comprises the process part 204-1.

The waveform processing unit 201-1 receives an OFDM signal transmitted from the transmission apparatus 10 (FIG. 1) through the transmission path 30, and performs signal processing of the OFDM signal. Data obtained by the signal processing performed by the waveform processing unit 201-1 is output to the FRM / De-INT processing unit 202-1.

The waveform processing unit 201-1 includes a preamble (PREAMBLE) processing unit 211-1 that performs processing related to a preamble, a guard interval (GUARD INT) processing unit 212-1 that performs processing related to a guard interval, and PAPR that performs processing related to PAPR. Processing unit 213-1, FFT processing unit 214-1 performing FFT (Fast Fourier Transform), MISO processing unit 215-1 performing processing related to MISO, and pilot (PILOTS) processing unit 216 performing processing related to pilot symbols It comprises 1 and each part processes as needed.

The FRM / De-INT processing unit 202-1 performs processing such as deinterleaving in the frequency direction or in the time direction. The FRM / De-INT processing unit 202-1 includes a frequency deinterleaver (FREQ De-INT) 217-1, a frame (FRAME) processing unit 218-1, and a time deinterleaver (TIME De-INT) 219-. It consists of one.

The frequency deinterleaver 217-1 performs frequency deinterleave (deinterleave in the frequency direction) on the data input from the waveform processing unit 201-1, and performs frame processing on the data after the frequency deinterleave. Supply to the section 218-1.

The frame processing unit 218-1 performs processing relating to the frame to the data supplied from the frequency deinterleaver 217-1, and supplies the data obtained as a result to the time deinterleaver 219-1.

The time de-interleaver 219-1 performs time de-interleaving (de-interleaving in the time direction) on the data supplied from the frame processing unit 218-1, and de-BICM processes the data after the time de-interleaving. Output to the part 203-1.

The De-BICM processing unit 203-1 performs processing such as orthogonal demodulation, bit deinterleaving, and error correction processing. The De-BICM processing unit 203-1 includes a de-mapper (De-MAP) 220-1, a bit de-interleaver (De-BIL) 221-1, and an error correction (FEC) processing unit 222-1. Ru.

The demapper 220-1 performs orthogonal modulation performed on the transmission apparatus 10 side with respect to data (data on constellation) input from (time deinterleaver 219-1 of) the FRM / De-INT processing unit 202-1. Demapping (signal point arrangement decoding) and quadrature demodulation are performed based on the arrangement (constellation) of signal points to be determined, and the resultant data is supplied to the bit deinterleaver 221-1.

The bit deinterleaver 221-1 performs bit deinterleaving on the data supplied from the demapper 220-1, and the data (error correction code) after the bit deinterleaving is transmitted to the error correction processing unit 222-1. Supply.

The error correction processing unit 222-1 performs processing of LDPC decoding and BCH decoding on the data (error correction code) supplied from the bit deinterleaver 221-1, and outputs the resulting data to an output format. The data is supplied to the processing unit 204-1.

The output format processing unit 204-1 performs necessary processing on the data input from (the error correction processing unit 222-1 of) the De-BICM processing unit 203-1 and outputs it as an output stream.

In FIG. 41, in the receiving apparatus 20, when LDM is performed, processing is also performed in the De-BICM processing unit 203-2 and the output format processing unit 204-2. The configurations of the De-BICM processing unit 203-2 and the output format processing unit 204-2 are the same as the configurations of the De-BICM processing unit 203-1 and the output format processing unit 204-1, respectively. The explanation is omitted. In the following description, the descriptions of “−1” and “−2” are omitted if it is not necessary to distinguish between the configurations.

In the following description, among the time deinterleavers 219, those corresponding to S-PLP are referred to as time deinterleaver 219S, while those corresponding to M-PLP are referred to as time deinterleaver 219M. To distinguish.

(1) A time deinterleaver compatible with S-PLP

(Example of configuration of time deinterleaver)
FIG. 42 is a block diagram showing a configuration example of the time deinterleaver 219S corresponding to S-PLP.

The time deinterleaver 219S performs time deinterleaving corresponding to S-PLP. In FIG. 42, the time deinterleaver 219S is composed of a cell memory unit mapper 241, a convolutional deinterleaver 242, and a memory unit cell demapper 243.

In FIG. 42, the cell / memory unit mapper 241 and the convolutional deinterleaver 242 are illustrated as separate blocks, but in practice, the cell / memory unit mapper 241 and the convolutional deinterleaver 242 are used. The interleaver 242 cooperates to process cells in units of memory units.

When the convolutional deinterleaver 242 processes a cell including data according to a predetermined modulation scheme, which is input from the frame processing unit 118 at the previous stage, in the memory unit unit, the cell / memory unit mapper 241 determines the cell. (For example, one cell or two cells) is mapped to one memory unit to convert the unit of cells (unit to be written to one address) input to the convolutional deinterleaver 242.

When processing the input cells in units of memory units, the convolutional deinterleaver 242 performs convolutional deinterleaving on the cells in units of memory units input from the cell / memory unit mapper 241, and performs convolutional deinterleaving on the cells. The data after interleaving is output to the memory unit cell demapper 243.

When the output from the convolutional deinterleaver 242 is in units of memory units, the memory unit / cell demapper 243 demaps the memory units into cells and converts them into cells (for example, 1 cell or 2 cells). It is output to (the demapper 220 of) the De-BICM processing unit 203 of the latter stage.

When the convolutional deinterleaver 242 processes data input from the frame processing unit 118 not in units of memory units but in units of cells, the cell / memory unit mapper 241 and the memory unit / cell demapper 243 are not yet processed. It is supposed to be used. In this case, the data from the frame processing unit 118 is directly input to the convolutional deinterleaver 242, and the data after convolutional deinterleaving is directly output to (the demapper 220 of) the De-BICM processing unit 203. Ru.

As described above, in the time deinterleaver 219S, convolutional deinterleave is performed by the convolutional deinterleaver 242, whereby time deinterleave corresponding to S-PLP is realized.

(2) A time deinterleaver compatible with M-PLP

(Example of configuration of time deinterleaver)
FIG. 43 is a block diagram showing a configuration example of a time deinterleaver 219M corresponding to M-PLP.

The time deinterleaver 219M performs time deinterleaving corresponding to M-PLP. In FIG. 43, the time deinterleaver 219M comprises a cell memory unit mapper 261, a convolutional deinterleaver 262, a block deinterleaver 263, a memory unit cell demapper 264, and a cell deinterleaver 265.

The cell memory unit mapper 261 maps cells (for example, one cell or two cells) including data according to a predetermined modulation scheme, which is input from the frame processing unit 118 at the previous stage, into one memory unit, and performs convoluting. The unit of cells (the unit to be written to one address) input to the functional deinterleaver 262 is converted.

The convolutional deinterleaver 262 performs convolutional deinterleave on the output from the cell memory unit mapper 261 and outputs the data after convolutional deinterleave to the block deinterleaver 263.

The block deinterleaver 263 performs block deinterleaving on the output from the convolutional deinterleaver 262, and outputs the data after block deinterleaving to the memory unit cell demapper 264.

The memory unit / cell demapper 264 demaps the memory unit to a cell and converts it into a cell (for example, 1 cell or 2 cells) for the output from the memory unit / cell demapper 264, and outputs it to the cell deinterleaver 265 Do.

The cell de-interleaver 265 performs cell de-interleaving on the output from the memory unit-cell de-mapper 264, and outputs the data after cell de-interleaving to (the de-mapper 220 of) the subsequent De-BICM processing unit 203. .

As described above, in the time deinterleaver 219 M, convolutional deinterleaving by the convolutional deinterleaver 262, block deinterleaving by the block deinterleaver 263, and cell deinterleaving by the cell deinterleaver 265 are performed. Thus, time deinterleaving corresponding to M-PLP is realized.

(Reception processing)
Next, the reception process performed by the reception device 20 of FIG. 41 will be described with reference to the flowchart of FIG.

In step S201, the waveform processing unit 201 performs waveform processing. In this waveform processing, an OFDM signal transmitted from the transmitter 10 (FIG. 1) via the transmission path 30 is received, and signal processing of the OFDM signal is performed.

In step S202, the FRM / De-INT processing unit 202 performs frame deinterleaving processing. In this frame de-interleaving process, processes such as de-interleaving in the frequency direction or in the time direction are performed.

Here, as time deinterleaving, when S-PLP is input, time deinterleaving is performed by time deinterleaver 219S (FIG. 42), and when M-PLP is input, time deinterleaving is performed. Time de-interleaving is performed by interleaver 219M (FIG. 43).

In step S203, the De-BICM processing unit 203 performs demodulation and decoding processing. In this demodulation and decoding process, processes such as orthogonal demodulation, bit deinterleaving, and error correction are performed.

In step S204, the output format processing unit 204 performs output data processing. In this output data processing, necessary processing is performed on the input data, and the data is output as an output stream.

The reception process has been described above.

<4. Modified example>

As the above description, ATSC (for example, ATSC 3.0) which is a system adopted in the United States and the like is described as a standard of digital broadcasting, but ISDB (Integrated Services Digital Broadcasting) or a system adopted by Japan etc. The present invention may be applied to DVB (Digital Video Broadcasting) or the like, which is a system adopted by each country in Europe.

In the above description, in ATSC 3.0, when QPSK is used as the modulation method, it is assumed that k = 2 is set in equation (1) and two cells are stored in one memory unit. However, as the modulation method, other modulation methods (for example, 16 QAM) other than QPSK may be adopted, or as the value of k, a value other than k = 2 may be set.

<5. Computer Configuration>

The series of processes described above can be performed by hardware or software. When the series of processes are performed by software, a program that configures the software is installed on a computer. FIG. 45 is a diagram showing an example of a hardware configuration of a computer that executes the series of processes described above according to a program.

In the computer 900, a central processing unit (CPU) 901, a read only memory (ROM) 902, and a random access memory (RAM) 903 are mutually connected by a bus 904. Further, an input / output interface 905 is connected to the bus 904. An input unit 906, an output unit 907, a recording unit 908, a communication unit 909, and a drive 910 are connected to the input / output interface 905.

The input unit 906 includes a keyboard, a mouse, a microphone, and the like. The output unit 907 includes a display, a speaker, and the like. The recording unit 908 includes a hard disk, a non-volatile memory, and the like. The communication unit 909 is formed of a network interface or the like. The drive 910 drives removable media 911 such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory.

In the computer 900 configured as described above, the CPU 901 loads the program stored in the ROM 902 or the recording unit 908 into the RAM 903 via the input / output interface 905 and the bus 904 and executes the program. A series of processing is performed.

The program executed by the computer 900 (CPU 901) can be provided by being recorded on, for example, a removable medium 911 as a package medium or the like. Also, the program can be provided via a wired or wireless transmission medium such as a local area network, the Internet, or digital satellite broadcasting.

In the computer 900, the program can be installed in the recording unit 908 via the input / output interface 905 by attaching the removable media 911 to the drive 910. The program can be received by the communication unit 909 via a wired or wireless transmission medium and installed in the recording unit 908. In addition, the program can be installed in advance in the ROM 902 or the recording unit 908.

Here, in the present specification, the processing performed by the computer according to the program does not necessarily have to be performed chronologically in the order described as the flowchart. That is, the processing performed by the computer according to the program includes processing executed in parallel or separately (for example, parallel processing or processing by an object). Further, the program may be processed by one computer (processor) or may be distributed and processed by a plurality of computers.

Note that the embodiments of the present technology are not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present technology.

Further, the present technology can have the following configurations.

(1)
A data processing apparatus comprising: a time interleaving unit that performs interleaving in a time direction by discontinuously arranging cells including data according to a predetermined modulation scheme for each memory unit that is a unit of writing data in a memory.
(2)
The data processing device according to (1), wherein the time interleave unit rearranges each memory unit so as not to include continuous or temporally close cells.
(3)
The data processing device according to (2), wherein the time interleave unit divides one address of the memory unit into a plurality of parts, and the cell is written to the memory according to the divided addresses.
(4)
The time interleaving unit
Has a convolutional interleaving unit that supports S-PLP (Single Physical Layer Pipe),
The data processing apparatus according to (3), wherein the convolutional interleaving unit rearranges the cells discontinuously for each of the memory units.
(5)
The data processing device according to (1), wherein the time interleaver rearranges each memory unit so that cells of different code words are included.
(6)
The data processing device according to (5), wherein the time interleaver reduces the bit width of each cell and then writes the data to the memory.
(7)
The time interleaving unit
Has a cell interleaving unit that supports M-PLP (Multiple Physical Layer Pipe),
The data processing device according to (6), wherein each cell interleaving unit rearranges the cells discontinuously for each memory unit.
(8)
The data processing apparatus according to any one of (1) to (7), wherein k = 2 when one memory unit includes k cells.
(9)
The data processing apparatus according to any one of (1) to (8), wherein the predetermined modulation scheme is QPSK (Quaternary Phase Shift Keying).
(10)
In a data processing method of a data processing device,
The data processor
A data processing method including the step of performing interleaving in the time direction by discontinuously arranging cells containing data according to a predetermined modulation scheme for each memory unit which is a unit of writing data in a memory.
(11)
It is transmitted from a transmitting apparatus having a time interleaving unit that performs interleaving in the time direction by discontinuously arranging cells containing data according to a predetermined modulation scheme for each memory unit, which is a unit for writing data in the memory. A data processing apparatus, comprising: a time de-interleaving unit that performs de-interleaving in the direction of time back to the original order in which the sequence of cells after in-terleaving in the direction of time obtained from incoming data is deallocated.
(12)
The data processing device according to (11), wherein the time interleaver rearranges each memory unit so as not to include continuous or temporally close cells.
(13)
The data processing device according to (12), wherein the time interleave unit divides one address of the memory unit into a plurality of parts, and the cell is written to the memory according to the divided addresses.
(14)
The time interleaving unit
Has a convolutional interleaving unit that supports S-PLP,
The data processing device according to (13), wherein the convolutional interleaving unit rearranges the cells discontinuously for each memory unit.
(15)
The data processing device according to (11), wherein the time interleaver rearranges each memory unit so that cells of different code words are included.
(16)
The data processing device according to (15), wherein the time interleave unit reduces the bit width of each cell and then writes the data to the memory.
(17)
The time interleaving unit
It has a cell interleaving unit that supports M-PLP,
The data processing device according to (16), wherein each cell interleaver rearranges the cells discontinuously for each memory unit.
(18)
The data processing apparatus according to any one of (11) to (17), wherein k = 2 when one memory unit is composed of k cells.
(19)
The data processing apparatus according to any one of (11) to (18), wherein the predetermined modulation scheme is QPSK.
(20)
It is transmitted from a transmitting apparatus having a time interleaving unit that performs interleaving in the time direction by discontinuously arranging cells containing data according to a predetermined modulation scheme for each memory unit, which is a unit for writing data in the memory. Performing a de-interleave in the time direction back to the original assortment of cells in the time direction after interleaving obtained from incoming data.

Reference Signs List 1 transmission system, 10 transmitters, 20 receivers, 30 transmission paths, 117 time interleaver, 117 S time interleaver (S-PLP), 117 M time interleaver (M-PLP), 141 cell memory unit mapper, 142 combo Recursive interleaver, 143 memory unit / cell demapper, 161 cell interleaver, 162 cell / memory unit mapper, 163 block interleaver, 164 convolutional interleaver, 165 memory unit / cell demapper, 219 time deinterleaver, 219s time de Interleaver (S-PLP), 219 M Time De-Interleaver (M-PLP), 241-cell memory unit mapper, 242 Convolutive Interleaver, 243 memory unit / cell demapper, 261 cell memory unit mapper, 262 convolutional deinterleaver, 263 block deinterleaver, 264 memory unit / cell demapper, 265 cell deinterleaver, 900 computers, 901 CPU

Claims (20)

1. A data processing apparatus comprising: a time interleaving unit that performs interleaving in a time direction by discontinuously arranging cells including data according to a predetermined modulation scheme for each memory unit that is a unit of writing data in a memory.
2. The data processing device according to claim 1, wherein the time interleaving unit rearranges each memory unit so as not to include cells contiguous or close in time.
3. The data processing apparatus according to claim 2, wherein the time interleaving unit divides one address of the memory unit into a plurality of parts, and the cell is written to the memory according to the divided addresses.
4. The time interleaving unit
   Has a convolutional interleaving unit that supports S-PLP (Single Physical Layer Pipe),
   The data processing apparatus according to claim 3, wherein the convolutional interleaving unit rearranges the cells discontinuously for each of the memory units.
5. The data processing apparatus according to claim 1, wherein the time interleaver rearranges each memory unit so that cells of different codewords are included.
6. The data processing apparatus according to claim 5, wherein the time interleaver reduces the bit width of each cell and then writes the data to the memory.
7. The time interleaving unit
   Has a cell interleaving unit that supports M-PLP (Multiple Physical Layer Pipe),
   The data processing apparatus according to claim 6, wherein each cell interleaver rearranges the cells discontinuously for each memory unit.
8. The data processing apparatus according to claim 1, wherein k = 2 in a case where one memory unit includes k cells.
9. The data processing apparatus according to claim 8, wherein the predetermined modulation scheme is QPSK (Quaternary Phase Shift Keying).
10. In a data processing method of a data processing device,
    The data processor
    A data processing method including the step of performing interleaving in the time direction by discontinuously arranging cells containing data according to a predetermined modulation scheme for each memory unit which is a unit of writing data in a memory.
11. It is transmitted from a transmitting apparatus having a time interleaving unit that performs interleaving in the time direction by discontinuously arranging cells containing data according to a predetermined modulation scheme for each memory unit, which is a unit for writing data in the memory. A data processing apparatus, comprising: a time de-interleaving unit that performs de-interleaving in the direction of time back to the original order in which the sequence of cells after in-terleaving in the direction of time obtained from incoming data is deallocated.
12. 12. The data processing apparatus according to claim 11, wherein the time interleave unit rearranges each memory unit so as not to include cells contiguous or close in time.
13. 13. The data processing apparatus according to claim 12, wherein the time interleaving unit divides one address of the memory unit into a plurality of parts, and the cell is written to the memory according to the divided addresses.
14. The time interleaving unit
    Has a convolutional interleaving unit that supports S-PLP,
    The data processing apparatus according to claim 13, wherein the convolutional interleaving unit rearranges the cells discontinuously for each of the memory units.
15. The data processing apparatus according to claim 11, wherein the time interleaver rearranges each memory unit so that cells of different code words are included.
16. The data processing apparatus according to claim 15, wherein the time interleaving unit reduces the bit width of each cell and then writes the data to the memory.
17. The time interleaving unit
    It has a cell interleaving unit that supports M-PLP,
    17. The data processing apparatus according to claim 16, wherein each cell interleaver rearranges the cells discontinuously for each memory unit.
18. 12. The data processing apparatus according to claim 11, wherein when one memory unit is composed of k cells, k = 2.
19. The data processing apparatus according to claim 18, wherein the predetermined modulation scheme is QPSK.
20. It is transmitted from a transmitting apparatus having a time interleaving unit that performs interleaving in the time direction by discontinuously arranging cells containing data according to a predetermined modulation scheme for each memory unit, which is a unit for writing data in the memory. Performing a de-interleave in the time direction back to the original assortment of cells in the time direction after interleaving obtained from incoming data.

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