WO2016178837A1

WO2016178837A1 - Semiconductor devices made of vertical planar elements and methods of their fabrication

Info

Publication number: WO2016178837A1
Application number: PCT/US2016/029042
Authority: WO
Inventors: Rimma Alexandovna PIROGOVA; Viktor Isakovitch KOLDIAEV
Original assignee: Finscale Inc.
Priority date: 2015-05-07
Filing date: 2016-04-22
Publication date: 2016-11-10

Abstract

A semiconductor device comprising a substrate of a semiconductor material. A bar member of the semiconductor material extends upwardly from the substrate and along the substrate surrounded by spaced-apart trenches in the substrate. Dielectric material is disposed in the trenches and engages the bar member along its vertical planar interfaces. Vertical planar elements are disposed in recesses extending along the vertical interfaces of the bar member to form electronic circuit elements such as p-n and Schottky diodes and other multi-diode electronic circuit elements. More specific circuit elements can include bipolar junction transistors, heterojunction transistors, junction field effect transistors and thyristors. The top of semiconductor device can be covered by a dielectric material to isolate it from one or more tiers comprised of semiconductor devices that may be fabricated in a stack above the device.

Description

SEMICONDUCTOR DEVICES MADE OF VERTICAL PLANAR ELEMENTS AND METHODS OF THEIR FABRICATION.

Inventors: Viktor Isakovich Koldiaev

Rimma Alexandovna Pirogova

BACKGROUND OF THE INVENTION 1. Field of invention

[0001] The present invention is generally related to the field of semiconductor devices and methods of their fabrication and more particularly to the three-dimensional multi-diode multi- terminal devices like Bipolar Junction Transistors (BJTs), JFETs, Thyristors, and other similar devices designed and fabricated with adoption of Fin-based device architectures and related fabrication methods.

2. Discussion of Related Art

[0002] The standard MOSFET device design which is widely used in the semiconductor industry is shown in FIG.1 (Prior art). The MOSFET includes the single crystalline silicon Substrate 200 doped accordingly, the LDD and Source 500 layers, the LDD and Drain 600 layers, the silicide 510 layer, the Gate dielectric stack or single layer 700, the Spacers 550, the conductive Gate electrode stack or single layer 800, and the Contact layers 560. Source 500 and Drain 600 structural details, such as a separate LDD layer and a raised (if any) SD epitaxial layer and so on are not shown for simplicity of the MOSFET schematic

representation. STI layers 300 for isolating two MOSFETs to the left and the right sides of the drawing are shown but the STI layers in the direction perpendicular to the cross-sectional drawing are not also shown.

[0003] FIG.2 (Prior Art) shows a 3D illustration of all the principle layers of the generic VSTB-FET for broad applications. Some parts are removed for clarity of the locations of the most important layers. The VSTB-FET is a MOSFET that can be fabricated on a bulk semiconductor substrate or on SOI substrate (not shown). The VSTB-FET is to be used in the fully depleted (FD) mode of MOSFET operation where the body's electrical connection to the bulk wafer substrate is essential, as illustrated in FIG.2 (Prior Art) and FIG.3 (Prior Art). The VSTB-FET device in FIG.2 (Prior Art), FIG.3 (Prior Art), and FIG.4 (Prior Art) is a semiconductor device comprising a semiconducting non-doped or low-doped vertical super- thin body 100 (VSTB, also called Fin) connected to a vertical wall of a dielectric body 300, such as the STI, having connection to the bulk semiconductor substrate at the bottom side 106, to the isolation cap at the top side 107, and the gate stack (GS) consisting of the gate dielectric 700 or gate dielectric stack (GDS) 701+702, metal gate stack (MGS) 703+704, and gate electrode filling (GEF) 800 on the same or opposite side of the dielectric body (STI side) VSTB surface 105. A dielectric layer 400 isolates GS from the substrate 200 and reduces the gate-to-substrate capacitance. If desired, the bottom of the gate trench 401/202 can be appropriately doped under the isolation 400 resulting in an appropriate doping of the sub- VSTB region. Source 500 and Drain 600 (SD) are formed in the dielectric body connected to the VSTB on the same or opposite sides of the gate resulting in the VSTB-FET. The VSTB (Fin) 100 is formed by a "spacer formation" process with a hard mask self-aligned to the STI hard mask edge on STI side before the STI is formed or on the opposite side of STI cap wall after the STI is formed, allowing very tight control of the body thickness. Source and Drain are formed before the gate stack formation ("Gate last approach") by using dummy dielectric filling (such as Si02 or the like) in the volume where the GS is to be formed. In the preferable embodiment, the Source and Drain are made by etching trenches/holes vertically into the STI adjacent to the VSTB surface 104 and forming in the trenches/holes a thin heavily in-situ appropriate type doped layer by a selective epitaxial growth (SEG) of c-Si layer or by a deposition of a poly-Si layer followed by an anneal to drive-in doping from the c-Si SEG layer or poly-Si layer into SD regions of the VSTB 502 and 602. The heavily doped SEG c-Si or poly-Si layer is covered with a low-resistivity materials stack, such as appropriate silicides or/and inert metal or metal nitrides (typically a barrier layer and a metal layer), and the rest of the volume is filled in with an inert conductive material (such as Tungsten) followed by surface planarization by using chemical-mechanical polishing (CMP). If desired, a recess in the SD filling material can be formed and then filled with a dielectric (such as SiN and the like) that is selectively etchable with respect to Si02 and the like. Both "Gate last" and "Gate first" approaches can be also easily implemented depending on the applications and lithography capabilities available. Single or multiple VSTB devices can be fabricated within a single active area using VSTB isolation by iso-plugs 900 combined with gate electrode isolation by iso-trenches 902 or simply using some extra cut-masks to remove VSTB where it is not needed. For high radiation applications or other applications where individual devices must be electrically isolated from one another and the substrate, the body can be easily made as a VSTB SOI MOSFET by using initial SOI wafers having a thick SOI layer with the current flowing horizontally from Source to Drain in the VSTB channel or vertically with Source fabricated at the bottom and Drain fabricated at the VSTB top. Also the device can be made as a set of nanowires on an isolating wall of the dielectric body such as the STI wall to be a nano wire-based VSTB-nWi-FET SOI device.

[0004] A cross-sectional view of a generic planar n-p-n or p-n-p type Bipolar Junction Transistor (BJT) is shown in FIG.5 (Prior Art). All active layers being vertically stacked on a semiconductor substrate 200 is the key feature of this device. The emitter 066 injects the carriers into the base 063 where the potential is controlled through the base contacts 064 and 065. Injected carriers diffuse through the base down into the collector 060 and get collected there. Then the carriers diffuse and drift to the collector contacts 061 and 062. The contacts 062, 065 and 067 are formed through the protective dielectric layer 310 and the transistor is isolated by the STI 300 from neighbors. The generic BJT has many design varieties and is typically used in BJT and BiCMOS technologies. In the latter case the BJT is integrated with n- and p-channel MOSFETs. To improve the operating frequency and speed performance the base 063 can be made of a compressively strained SiGe layer. A doping gradient in the base 063 with a higher doping concentration at the emitter-base junction vs. the base-collector junction is also beneficial for producing devices with higher speed. The basic feature of the device design is that all active layers 066, 063, and 060 are formed horizontally and the principle current flux in the area responsible for the device gain factor flows vertically.

[0005] The Junction FET (JFET) is one of several low noise and high input impedance devices which is widely used in SoC platform for radio-frequency (RE) applications. A cross- sectional view of the typical JFET fabricated using planar technology is shown in FIG.6 (Prior Art) with the vertical stack of all functional layers including the top gate 090 with the contact 094, the channel 075 with Source 095 and Drain 076, and the bottom gate 091 with the gate contact located behind or in front of the drawing sheet. Top Gate 090 and bottom gate 091 can be tied together as the single gate or can be controlled separately as a Dual gate device. A contact to the bottom gate is fabricated at the edge of the channel width where the contacts to the channel as Source 095 and Contact 235 as well as Drain 076 and Contact 236 are narrower than the Bottom gate 091 width. A deep n-well 211 going across the entire n- channel JFET area and under STI bottom is needed and can be formed with a special mask having the n-well made by a special ion implantation step that can be a common mask for some BJTs as well. For the p-channel JFET such layer is not necessary.

[0006] A very special class of devices, which are needed in every IC, is Electro-Static Discharge Protection (ESDP) devices. A good summary is given in papers by SH Voldman and by M-D Ker (see list of referenced papers above). Basic ESDP devices have the following components: (i) MOSFETs; (ii) diodes; (iii) resistors; (iv) BJTs being typically 2D planar objects having a structure of vertically stacked active layers with a vertical current flow; and (v) a thyristor as a vertical n-p-n BJT and a p-n-p BJT integrated horizontally into n-p-n-p planar structures. Since many components are readily available in VSTB-FET based technology and can be connected accordingly to create many known ESDP devices, only the generic thyristor and BJT are important to consider and to invent a design as standalone devices. Having technological capability to fabricate a high-gain thyristor with a horizontal structure and horizontal interaction makes the VSTB-FET based technology of outstanding quality. It is impossible to cover all the variety of the ESDP device structures known by today but if one decomposes all the known devices in terms of the simple components listed here one can easily design an ESDP device for any specifications and for any products.

[0007] A Silicon-Controlled Rectifier (SCR) is a thyristor-type device by functionality. A cross-sectional view of a p - n - p - n device having p-emitter 066 - n-base 216 - p-base 215 - n-emitter 062 SCR device on the semiconductor p-substrate 200 with STI isolation 300 is shown in FIG.7 (Prior Art). The typical structure can be made in planar technology by using the standard available layers for the n+ Source/Drain of a planar n-MOSFET as the contact 040 to the base 216 and as the contact 062 to the collector 060, for the n-well as the base 216 and as the collector 060, and for the p+ Source/Drain of the p-MOSFET as the emitter 066 and as the contact 045 to the base 215. Sometimes STI layers are used in between the active layers if the n-wells and/or p-wells are deeper than the STI to provide a higher series resistance for more voltage drop on a triggering layer and more effective switching of the thyristor to its "on" state. There are many mechanisms to trigger such a structure that have an S-type switching curve allowing fast discharge of an electrostatically-generated charge on any IC pads from the outside world. If one would not use ESDP devices the reliability of a product would be compromised. Device structures of the p-type substrate-triggered SCR device or the n-type substrate-triggered SCR device can be complemented by stacked-diode strings also made of planar Source/Drain junctions.

[0008] A list of ESDP techniques includes: 1. MOSFET snapback effect for ESDP; 2. resistor ballasting (an ESD technique widely used today); 3. SCR-based ESDP devices where the triggering current generation through the p-base 216 / 215 or the n-base 216 / 215 can be done by different methods: (a) resistor ballasting, (b) gate coupling, (c) resistor-capacitor (RC) coupling, (d) substrate triggering and (e) body coupling (the thyristor is a generic representative of such devices); 4. snubber-clamped ESD diode string network: a row of BJTs made of p+/n-well - n+-contact/p-substrate in parallel with the very last on right side of BJT connected to the middle of the row; 5. SOI ESD protection of SOI CMOS that has some specific characteristics but can be fabricated using VSTB-FET based devices on SOI substrates: (a) gated diodes, (b) gate-coupled MOSFETs, (c) Zener diodes, (d) lateral unidirectional BJT-type insulated gate transistors (Lubistors) as SOI ESDP devices for ESD protection in advanced CMOS SOI technology; 6. ESDP power clamps are typically used today: (a) BJTs, (b) thick- and thin-oxide grounded gate n-channel MOSFETs, (c) diode strings, and (d) RC-triggered p-channel MOSFETs and n-channel MOSFETs. All these ESDP structures can be fabricated using BJT and thyristor type devices and elements like diodes, resistors, and capacitors using VSTB's basic structure, as described below as inventions.

[0009] Technical aspects of the semiconductor device scaling factors are briefly summarized below. Fabrication of a super-thin body of 6 nm to 2 nm on SOI, as required for FD-SOI, with the required thickness uniformity across a 300 mm (or 450 mm in future) wafer is not possible. If a thicker and cheaper SOI substrate of 20 nm and more is used as the starting material, a key fabrication step is needed to make the SOI thinner. The only solution known by today is making SOI thinner by oxidation. This step is good for rather uniform thinning of SOI, but it has some dramatic effects on the quality of SOI in terms of mobility degradation, extensive extended defects formation, device leakage, and reliability

deterioration. Especially vulnerable is the bottom SOI interface to the BOX. The physical mechanisms causing these effects are described as follows. Oxidation of c-Si is accompanied by high-rate generation of interstitial Si atoms. This has been confirmed many years ago by direct observation of oxidation-enhanced boron diffusion, because Boron diffusion is only facilitated by silicon interstitials (Si-I). The other phenomenon is Oxygen injection into the c- Si at a level which can bring the Oxygen concentration in c-Si to the limit of its solubility. This has been confirmed by direct observation of the saturation of c-Si substrate with 018 isotopes, when 018 isotopes were used for c-Si oxidation, and those isotopes are easy to detect using Secondary Ion Mass Spectrometry (SIMS) and other material analysis techniques, because more than 99% of all naturally occurring oxygen exists as the 016 isotope. The excess Si-I and O results in their interaction through the nucleation and growth (precipitation) of extended defects in the bulk c-Si and the especially active nucleation occurs at the c-Si - a-Si02 interfaces. Oxidation Stacking Fault (OSF) formation is a very well- known direct confirmation of this mechanism. Thus the thinning by oxidation is a harmful process, as has been observed in many studies in terms of mobility degradation and leakage current increase, and these effects should be expected if the thinning by oxidation is used for SOI thinning. Actually Fin-on-SOI thinning by oxidation does also indeed result in poor device performance for the same reasons. FinFET on SOI is not yet proven to be

manufacturable for a number of reasons including those explained above and observed by many unsuccessful efforts to implement it in mass production. Bulk-FinFET (also known as Tri-Gate) with a modest aspect ratio of the Fin width to height is first implemented in the mass production at the 22 nm and 14 nm node and now has become the mainstream architecture in R&D activity across the industry, where scaling of this device concept is under scrupulous attention. For the technology nodes at and below 10 nm it seems to be rather difficult to scale the bulk-FinFET as a Tri-Gate structure to make a highly

manufacturable device, since a thin Fin of 6 nm or less is needed. A very thin Fin below 6 nm with a practical aspect ratio is difficult to fabricate due to the Fin's mechanical fragility, and for such a thin Fin the quantum confinement effects of the inversion layer formation suggest little merit in having a double gate, let alone a third gate. Thus making a Tri-Gate transistor scalable brings tremendous obstacles for achieving its acceptable manufacturability. It is worthwhile to note that the initial Fin thickness for 22nm node Tri-Gate type of Double Gate FinFET is 22 nm, and this Fin thickness becomes 8 nm at the mid-height of the final structure by the end of fabrication process through a thinning-by-oxidation process. But how can the performance still be good enough for mass production? The reason is that the Tri-Gate Fin stands on bulk c-Si and it allows for Si-I and O excess to diffuse into the substrate where they are efficiently gettered and do not produce extended defects density above the critical concentration. Two observations support this statement: first of all High-Resolution

Transmission Electron Microscopy images (HR-TEMs) do show some extended defect density and the published electrical data do show excessive device leakage. Moreover, it is known that the Tri-Gate is fabricated on the epitaxial wafers with the epi layer thickness about 2 micrometers. It is known that the standard epi layer has an O contamination concentration at or below lel6 cm-3. Whereas the standard Czochralski c-Si has about lel8 cm-3 to 3el 8 cm-3 that is almost at the saturation level at the typical high temperature range used for c-Si oxidation so that the extra O coming from the oxidation is immediately clusterized resulting in the extended defects. Thus epitaxial wafers are the material choice of necessity to offset the defect formation during fabrication because of their very low initial O contamination level. These high defect density and high leakage effects coming from the Tri- Gate process integration are prohibitive features for having high performance bipolar transistor-based devices.

[0010] A recently invented semiconductor device comprises a semiconducting low-doped Vertical Super-Thin Body (VSTB) formed on a dielectric body wall, such as the STI wall, as an isolating substrate having the VSTB body connection to the bulk semiconductor wafer on the bottom side, to isolation cap on the top side, to the Source and Drain on STI side, to the gate dielectric stack and gate electrode stack on the side opposite the STI-VSTB interface (or, if desired, on the same side as Source/Drain), resulting in a Field Effect Transistor (VSTB- FET). The VSTB body is made self-aligned to the STI hard mask edge allowing a very tight control of the VSTB body thickness. Source and Drain are made by etching trenches/holes vertically in the isolating wall on either VSTB side (like in the STI for a particular embodiment) connected on the isolating wall side to the VSTB semiconductor body, and filling them with a heavily doped SEG layer of c-Si or with a deposited poly-Si appropriately doped to p+ or n+ types and covered with a low-resistivity material or materials stack including any appropriate silicides, metal nitride barrier layers or/and metal. To this extent any heterogeneous junctions can be formed as the VSTB-FET Source/Drain stack to provide appropriate switching characteristics of the VSTB FET. "Gate first" or "Gate last" approaches can be easily implemented depending on applications and lithography capabilities available. Single or many VSTB-FET devices can be fabricated in a single active area with VSTB body isolation between devices by iso-plugs combined with gate electrode isolation by iso-trenches or simply using cut masks to remove the hard mask for forming VSTB and removing VSTB wherever it is not needed. If desired, for high radiation hardness

applications, or other applications where individual devices must be electrically isolated from one another and the substrate, the VSTB body can be easily made as a VSTB SOI MOSFET on a thick SOI substrate. The current can flow horizontally with Source and Drain at the VSTB left and right sides or vertically with Source and Drain at the VSTB bottom and top respectively. If desired, a CMOS device can also be made as a set of nanowire MOSFETs on an insulating wall such as the STI wall resulting in a nanowire-based VSTB-nWi-FET device. The high performance (HP) products like microprocessors (DP) and SoCs need to have embedded DRAM (eDRAM), embedded SRAM, and embedded NVM (NOR Flash typically). Low Power (LP) and Ultra-Low Power (ULP) SoC products designed to enable smartphones and other mobile devices have a low leakage specification at or below 0.1 nA/Dm. The absence of doping in the VSTB-FET channel results in absence of the threshold voltage (Vth) variability related to the random dopant fluctuation which is the main component of Vth variability in the standard CMOS technology because of using highly doped substrate. Low Vth variability enables the VSTB-FET to be suitable for all HP ULSI, microprocessors, SRAM, DRAM, Flash, analog IC, RF and mixed-signal ICs, CMOS IS (Image Sensors), and SoC applications. The set of devices suggested in this invention can help significantly improve the performance of those products as well as to give solutions for some versions of ESDP built-in devices which can be designed from B JT, HBT, JFET, diodes, and thyristors as building blocks. Thus the semiconductor industry needs an innovation to implement those devices, preferably using a single unified device concept like the VSTB-FET for a broad usage in the semiconductor industry.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIG.1 (Prior art). A cross-section of a standard planar MOSFET.

[0012] FIG.2 (Prior art). A 3D illustration of all the principle layers of the VSTB-FET for broad applications. Some parts are removed for clarity of the locations of the most important layers.

[0013] FIG.3 (Prior art) and FIG.4 (Prior art). Schematic views of a vertical cross-section at the gate-to-source overlap area and a horizontal cross-section at the mid-depth of VSTB to illustrate all the principle layers of the VSTB-FET.

[0014] FIG.5 (Prior art). A cross-sectional view of a generic planar n-p-n or p-n-p BIT with vertical stack of the functional layers including the emitter at the top, the base in the middle, and the collector at the bottom with the base contact located behind or in front of the drawing sheet.

[0015] FIG.6 (Prior art). A cross-sectional view of a generic IFET design with vertical stack of the functional layers including the top gate, the channel with Source and Drain, and the bottom gate with the gate contact located behind or in front of the drawing sheet.

[0016] FIG.7 (Prior art). A cross-sectional view of a SCR as an n-p-n-p or p-n-p-n thyristor type device by functioning features.

[0017] FIG.8. A cross-sectional view of the Basic Building Structure (BBS) consisting of the STI layers with their cap layers, c-Si bar layer having three caps where two VSTB-caps are attached to the STI caps and the Bar cap is in between two VSTB-caps for fabricating the Diode Based Devices (DBD) such as the BJT, JFET, and thyristors having the horizontal current injection direction, and all the vertical functional layers having the structure where the VSTB-Caps are used for selective etching of c-Si under them and for forming the gate dielectric and a very thin gate electrode in the VSTB region.

[0018] FIG.9. A cross-sectional view of the Basic Building Structure for forming a Vertical MOS-Diode (Capacitor) structure attached to the STI with the thin gate electrode and the gate dielectric formed in a trench anisotropically etched in c-Si after removing the VSTB cap.

[0019] FIG.10. A cross-sectional view of a vertical n-p junction multi-diode structure attached to the STI with an epitaxial layer or a poly-Si layer doped to a certain level in a range from a low to a moderate and to a high level, depending on the diode specifications, grown or deposited in a trench anisotropically etched in the c-Si bar after removing the VSTB cap, then having the doping driven into the bar (substrate).

[0020] FIG.11. A cross-sectional view of a Vertical Multi -Junction Structure (VMJS) with low-resistance contacts fabricated in the STI by heavily doped epitaxial layers grown on the c-Si bar wall or by heavily doped poly-Si layers deposited on the c-Si bar wall, then having the doping driven into the c-Si bar (substrate).

[0021] FIG.12. A cross-sectional view of a Vertical HBT structure attached to the STI walls having the emitter and the base on the left side and the collector on the right side where on the left side the VSTB cap having been selectively removed, followed by an anisotropic selective etching of the c-Si Bar and filling with an epitaxially grown, appropriately doped SiGe layer to form a super thin SiGe base of the HBT. The HBT emitter on the left side of the base and the collector on the right are formed in anisotropically etched trenches/holes in the STI adjusted to the base and the Bar by a heavily doped epitaxial c-Si layer grown on the SiGe base wall and the Bar wall, followed by a low-resistance metal contact formation.

[0022] FIG.13. A simplified cross-sectional view of a VSTB based Bipolar Junction Transistor (VSTB-BJT) having horizontal injection and all functional layers being vertically structured with only key active layers shown.

[0023] FIG.14. A cross-sectional view of a realistic VSTB-based BJT illustrating extra active layers that improve the performance. [0024] FIG.15. A layout view of a realistic VSTB-based BJT illustrating extra active layers that improve the performance and showing contacts to the base and to the deep n-well.

[0025] FIG.16. A cross-sectional view of a double-gate JFET based on a similar approach as the design and fabrication of the BJT, having horizontal injection and all vertical structural layers.

[0026] FIG.17. A layout view of a double- gate JFET based on a similar approach as the design and fabrication of the BJT, having horizontal injection and all vertical structural layers.

[0027] FIG.18. A cross-sectional view of a single-gate JFET based on a similar approach as the design and fabrication of the BJT, having horizontal injection and all vertical structural layers.

[0028] FIG.19. A layout view of a single gate JFET based on a similar approach as the design and fabrication of the BJT, having horizontal injection and all vertical structural layers.

[0029] FIG.20. A cross-sectional view with the key functional elements of the n-p-n-p- thyristor, having horizontal injection and all vertical structural layers.

[0030] FIG.21. A layout view with the key functional elements of the n-p-n-p-thyristor, having horizontal injection and all vertical structural layers.

[0031] Fig.22. A cross-sectional view with the key functional elements of the n-p-n-p- thyristor, with horizontal injection and all structural layers being formed vertically in the SOI layer above the BOX.

[0032] Fig.23. A cross-sectional view of a stackable architecture having, as an example, a VSTB-FET in the crystalline substrate (the first tier) and the BJT in the top (an upper tier), being isolated from the first tier and in between tears by an isolation layer.

DETAILED DESCRIPTION OF THE INVENTION

[0033] There are two main CMOS devices for mass production in technology nodes below 20nm: (i) Tri-Gate, a variation of the bulk vertical Fin Double Gate MOSFET (although it is called a three-gate structure, in a critical consideration, the device is actually of the Double Gate type); and (ii) planar Fully-Depleted SOI (FD-SOI) MOSFET fabricated on thin Buried Oxide (BOX) as the planar Single Gate device. By today there is no known BiCMOS technology integrating any Bipolar Junction Transistors, Thyristors, and other multi-diode- based devices integrated with Tri-Gate or FD-SOI for technology nodes below 20nm. Also the more compact and well performing devices in ESDP technology are based on some thyristor like structures which are not readily available in those two technologies of mass production. Using the VSTB-FET device design constructive layers one can solve the challenge to design and to integrate into CMOS or BiCMOS technologies many different types of multi-diodes devices like BJT, HBT, Thyristors, JFET, and others for the technology nodes below 20 nm as well as for nodes above 20 nm by using backscaling methodology. This invention addresses this challenge.

[0034] The present invention includes a universal set of devices usable in the many ULSI and common SoC platforms made of VSTB semiconductor on Dielectric-Wall structures and methods of their fabrication. The set includes: BiCMOS BJT with Vertical Super Thin Body of homogenous or heterogeneous junctions of semiconductor active layers (VSTB-BJT and VSTB-HBT); a JFET with vertical key functioning layers horizontally (laterally) stacked (VJFET); ESDP Devices based on n-p-n-p or p-n-p-n thyristor-like structures made of Vertical Super Thin Body of homogenous or heterogeneous junctions of semiconductor active layers (VSTB-ESDP Devices).

[0035] The present invention is related to the field of semiconductor integrated circuit manufacturing, and more particularly to a universal set of diode-based devices and methods of their fabrication usable in the CMOS and BiCMOS technologies for fabricating a plurality of IC types and System-on-Chip (SoC) designs made of the basic structures (i) crystalline or poly crystalline Vertical Super-Thin Body (VSTB) Semiconductor on a Vertical Dielectric Wall of a Shallow or Deep Trench Isolation (hereafter referred to as STI) or a Thick

Dielectric Layer (TDL) and (ii) the VSTB Protective Cap of the crystalline or poly crystalline VSTB Semiconductor placed between the Protective Cap of the corresponding STI or TDL and the Protective Cap over the Vertical Thick Body (VTB or Bar) having the TDL formed on the inter-tier dielectric layer or, if desired, on a stack of inter-tier dielectric layer(s) and quasi-substrate(s) made of a highly doped poly crystalline semiconductor layer(s) of lOnm to lOOOnm thickness, like poly-Si. The universal set of devices includes: (a) a plurality of CMOS and BiCMOS technology devices that includes Vertical Super Thin Body Bipolar Junction Transistors (VSTB-BJT) with vertical homogenous junctions or / and Vertical Super Thin Body Heterogeneous Base Transistors (VSTB-HBT) or/and, if desired, Vertical Junction Field Effect Transistors (VJFET) with a set of vertical key functioning layers formed using the basic structures for fabricating the devices; (b) Electro-Static Discharge Protection (ESDP) Devices fabricated as horizontally stacked diodes constituting some n-p-n- p or/and p-n-p-n thyristor-like structures formed using the VSTB for homogenous or heterogeneous vertical junctions of semiconductor active layers (VSTB-ESDP Devices) utilizing the basic structures for fabricating the devices; (c) a set of VSTB-FET, VSTB-BJT, VSTB-HBT, VJFET, and VSTB-ESDP Devices and an IC based on the set made as a tier on the crystalline substrate or the quasi-substrate and fabricated from the crystalline or/and poly crystalline VSTB on the STI or/and TDL vertical wall having the Source/Drain formed on one side of VSTB and the Gate formed on opposite side of VSTB or, if desired, having the Source/Drain and the Gate formed on the same side of the VSTB. STI depth can be in a range from lOnm to 3000nm or so depending on product specifications. If desired, bulk

semiconductor (silicon) wafers or silicon-on-insulator (SOI) wafers with a thick SOI layer in a range from lOnm to lOOOnm can be used for all types of products with no change of the product masks but fabricating different products for bulk or SOI specifications, because the VSTB-based device concepts are very flexible in using bulk or SOI wafers with no product mask redesign. The Schottky diodes can be readily designed and fabricated using VSTB structure in the same way as other p-n-junction based diodes are formed. Schottky diodes can be included into the Source connection in series with the channel to manipulate VSTB-FET Vth. A Tunneling MOSFET is also easy to form taking advantage of the Source/Drain formation method in the holes/trenches etched in the isolating wall such as STI wherein using appropriate materials. A skilled-in-the-art specialist can engineer and fabricate a plurality of the VSTB-based devices combining some particular device structures as described below as particular examples of such an approach to design a plurality of the devices.

[0036] The present invention includes a novel semiconductor device that can be of any suitable type. Examples of specific semiconductor devices of the invention include BJT with Vertical Super Thin Body having homogenous or heterogeneous junctions of semiconductor active layers (VSTB-BJT and VSTB-HBT) integrated into a BiCMOS technology; vertical JFET with a lateral stack of the key functioning vertical layers; ESDP Devices based on n-p- n-p or p-n-p-n thyristor-like structures made of Vertical Super Thin Body having

homogenous or heterogeneous junctions of semiconductor active layers (VSTB-ESDP). It is understood that such specific examples are not intended to limit the broad aspects of the invention. Methods for fabricating the semiconductor devices of the invention are additionally provided. In the following description numerous specific details are set forth in order to better understand the invention, but not limit the scope of the invention. In other instances, well-known semiconductor process and manufacturing techniques have not been described in particular detail, but not to unnecessarily obscure the present invention. In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to other skilled in the art. However, the present invention may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to better understand the invention. However, the present invention may be practiced without specific details. In some instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.

[0037] In a first embodiment of the invention, a semiconductor device is provided. The semiconductor device includes a substrate of a semiconductor material. A bar member of the semiconductor material extends upwardly from the substrate and along the substrate between first and second spaced-apart trenches in the substrate. A first body of a dielectric material is disposed in the first trench and engages the bar member along a first vertical planar interface extending upwardly from and along the substrate. A second body of a dielectric material is disposed in the second trench and engages the bar member along a second vertical planar interface extending upwardly from and along the substrate. At least a first vertical planar element is disposed in at least a first recess extending along the first vertical interface and at least a second vertical planar element disposed in at least a second recess extending along the second vertical interface. Each of the first and second vertical planar elements can optionally include more than one vertical planar portions, and each of the at least first and second recesses can optionally include more than one recess portion, for example to receive respective vertical planar portions.

[0038] In a second embodiment of the invention, a semiconductor device is provided. The semiconductor device includes a substrate of a semiconductor material. A bar member of the semiconductor material extends upwardly from the substrate and along the substrate surrounded by spaced-apart trenches in the substrate. Dielectric material is disposed in the trenches and engages the bar member along its vertical planar interfaces. Vertical planar elements are disposed in recesses extending along the vertical interfaces of the bar member and the dielectric material to form electronic circuit elements, or semiconductor devices, such as p-n and Schottky diodes and other multi-diode electronic circuit elements. More specific circuit elements can include bipolar junction transistors, heteroj unction transistors, junction field effect transistors and thyristors. The top of semiconductor device can optionally be covered by a dielectric material to isolate it from one or more tiers comprised of

semiconductor devices that may be fabricated in a stack above the device.

[0039] The embodiments of the invention set forth below are examples of the invention, and may in some instances be broader than the foregoing first and second embodiments of the invention but are not intended to limit the breadth of the foregoing first and second embodiments. Additional features of the invention set forth in such embodiments are optional. A feature of any embodiment set forth below can be combined with the foregoing first embodiment or the foregoing second embodiment, with or without any other feature of any embodiment set forth below.

[0040] In one embodiment, bar member 450, which can also be referred to as a bar or any other suitable name, extends upwardly from substrate 200 includes a first side 462 and a second side 463 and a first end 466 and a second end 467 extending between the sides 462, 463. Sides 462, 463 can extend parallel to each other, and ends 466, 467 can extend parallel to each other and perpendicular to sides 462, 463. The bar member has a top surface 471 extending between sides 462, 463 and ends 466, 467, which has a first border area 471 a adjacent first side 462 and an opposite second border area 471b adjacent second side 463 and a central area 471 c between the first and second border areas 471 a, 471b. First and second sides of bar member 450 are formed by spaced-apart first and second trenches 472, 473 provided in the substrate.

[0041] A first body 481, for example of a dielectric material, is disposed in the first trench 472 and engages the bar member 450 along a first vertical planar interface 486 extending upwardly from and along the substrate, for example along the first side 462 of the bar member. A second body 482, for example of a dielectric material, is disposed in the second trench 473 and engages the bar member 450 along a second vertical planar interface 487 extending upwardly from and along the substrate, for example along the second side 463 of the bar member. Each of bodies 481, 482 is sometimes referred to herein as STI 300.

[0042] At least a first vertical planar element 491 is disposed in at least a first recess 492 extending along the first vertical interface 486 and at least a second vertical planar element 493 is disposed in at least a second recess 494 extending along the second vertical interface 487. Each of the first and second vertical planar elements can optionally include more than one vertical planar portions, and each of the at least first and second recesses can optionally include more than one recess portion, for example to receive respective vertical planar portions. The at least first recess 492, and the first vertical planar element 491 disposed therein, can be on either side of the first vertical interface 486. For example, the at least first recess 492 can be formed in the portion of the first body 481 adjoining the first vertical interface 486 or in the portion of the bar member 250 adjoining the first vertical interface 486. In addition, another recess or recesses can optionally be provided on the opposite side of the first vertical interface 486 from the at least first recess 492 and additional vertical planar elements or portions can be disposed in such another recess or recesses. Similarly, the at least second recess 494, and the second vertical planar element 493 disposed therein, can be on either side of the second vertical interface 487. For example, the at least second recess 494 can be formed in the portion of the second body 482 adjoining the first vertical interface 487 or in the portion of the bar member 250 adjoining the second vertical interface 487. In addition, another recess or recesses can optionally be provided on the opposite side of the second vertical interface 487 from the at least second recess 494 and additional vertical planar elements or portions can be disposed in such another recess or recesses.

[0043] In one embodiment, a third body 571 , for example of a dielectric material, is disposed in the third trench 572 and engages the bar member 450 along a third vertical planar interface 573 extending upwardly from and along the substrate, for example along the first end 466 of the bar member. See for example FIG. 15. A fourth body 576, for example of a dielectric material, is disposed in the fourth trench 577 and engages the bar member 450 along a fourth vertical planar interface 578 extending upwardly from and along the substrate, for example along the second end 467 of the bar member. Each of bodies 571 , 576 is sometimes referred to herein as STI 300.

[0044] At least a third vertical planar element 581 is disposed in at least a third recess 582 extending along the third vertical planar interface 573 and at least a fourth vertical planar element 586 is disposed in at least a fourth recess 587 extending along the fourth vertical interface 578. Each of the third and fourth vertical planar elements can optionally include more than one vertical planar portions, and each of the at least third and fourth recesses can optionally include more than one recess portion, for example to receive respective vertical planar portions. [0045] In one embodiment, each of the first and second planar elements, for example planar elements 491, 493, includes a first vertical planar portion 496 and a second vertical planar portion 497. In one embodiment, the second vertical planar portion 497 is between the first vertical planar portion 496 and the respective vertical planar interface 486, 487. In one embodiment, for example where each of the planar elements 491 , 493 are formed in bar member 450, the first vertical planar portion 496 is formed from any suitable dielectric material and the second vertical planar portion 497 is formed from any suitable conductive material. See for example, FIG. 9. In one embodiment, for example where each of the planar elements 491, 493 are formed in bar member 450, the first vertical planar portion 496 is formed from any suitable doped semiconductor material as a doped extension layer and the second vertical planar portion 497 is formed from any suitable conductive material. See for example, FIG. 10. In one embodiment, for example where each of the first and second planar elements 491 , 493 are formed in the respective first and second body 481, 482, the first vertical planar portion 496 extending along the respective vertical planar interface 486, 487 and a second vertical planar portion 497 extends between the first vertical planar portion 496 and the respective body 481 , 482. See FIGS. 1 1-17. In one embodiment, the first vertical planar portion 496 is of a doped semiconductor material and the second vertical planar portion 497 is of a conductive material. Similar third and fourth vertical planar elements, for example third and fourth planar elements 573, 586, can optionally be provided for each of the embodiments of this paragraph.

[0046] The bar member 450 can be of any suitable size. In one embodiment, the bar member 450 has a width between the first and second vertical planar interfaces 486, 487 ranging from 20 to 3000 nanometers.

[0047] In one embodiment, each of the first and second planar elements 491 , 493 can be of any suitable size and height. In one embodiment each of the planar elements has a height to width ratio of at least 1 : 1. In one embodiment each of the planar elements 491, 493 has a height to width ratio of at least 2: 1. In one embodiment each of the planar elements 491, 493 has a height to width ratio of at least 3: 1. In one embodiment each of the planar elements 491 , 493 has a height to width ratio of at least 4: 1. In one embodiment each of the planar elements 491, 493 has a height to width ratio of at least 5: 1. In one embodiment each of the planar elements 491 , 493 has a height to width ratio of at least 10: 1 at least 20: 1. In one embodiment each of the planar elements 491, 493 has a height to width ratio ranging from 1 : 1 to 30: 1. [0048] In one embodiment, the first planar element 491 and the second planar element 493 are identical.

[0049] Each of the first and second planar elements 491, 493 can be made from any suitable material or materials. In one embodiment, each of first and second planar elements 491, 493, or a portion thereof, is a planar conductive element. In one embodiment, each of first and second planar elements 491, 493, or a portion thereof, is a planar metal element. In one embodiment, each of first and second planar elements 491, 493, or a portion thereof, is a planar dielectric element. In one embodiment, each of first and second planar elements 491, 493, or a portion thereof, is a planar semiconductor element. In one embodiment, each of first and second planar elements 491, 493, or a portion thereof, is a planar doped conductive element. In one embodiment, each of first and second planar elements 491, 493, or a portion thereof, is a planar doped semiconductor element. In one embodiment, each of first and second planar elements 491, 493, or a portion thereof, is a planar metal/semiconductor stack. In one embodiment, each of first and second planar elements 491, 493 is a planar

metal/di electric stack.

[0050] In one embodiment, the semiconductor device of the invention has a symmetrical structure relative to the bar member 450.

[0051] An example of one embodiment of the Basic Building Structure (BBS) for semiconductor devices of the invention, for example Diode-Based Devices (BBS-DBD) for the BJT, JFET, and thyristors, is illustrated in FIG.8. The BBS-DBD comprises the semiconductor substrate 200, and the first and second bodies 481, 482, or STI 300, connected to the semiconductor substrate 200 at the bottom and to the STI dielectric cap 301 at the top and to the Bar 450 on its walls 462, 463, and the Bar 450 being an apparently raised, but actually remaining part of the substrate and having the protective dielectric cap 451 at the top, and the VSTB cap 101 placed between the STI cap 301 and the protective cap 451 and connected to the Bar 450 at the bottom. The protective caps 451 and 301 can be made of different dielectric materials having high etching selectivity to the protective cap 101 and to each other. If desired and possible, the protective caps 451 and 301 can be made of the same dielectric material. Some detailed modifications of the BBS-DBD to form the vertical MOS- Diode and the vertical p-n-j unction based multi-diode structures are illustrated in FIG.9 to FIG.11. [0052] The semiconductor devices of the present invention can be fabricated in any suitable manner. In one method of fabrication, from a substrate 200 of a semiconductor material, the method includes anisotropic etching the first and second spaced-apart trenches 472, 473 in the substrate 200 to form bar member 450. The first body 481, which can be of a dielectric material, is deposited in the first trench 472 to create the first vertical planar interface 486 between the first body 481 and the bar member 450. The second body 482, which can be of a dielectric material, is deposited in the second trench 473 to create the second vertical planar interface 487 between the second body 482 and the bar member 450. The first vertical planar interface 486 can extend parallel to the second vertical planar interface 487. The first recess 472 is anisotropic etched along the first vertical planar interface 486, on the appropriate side thereof for forming the specific semiconductor device. The second recess 473 is anisotropic etched along the second vertical planar interface 487, on the appropriate side thereof for forming the specific semiconductor device. At least one material is deposited in the first recess 472 to create the first planar element 491, which extends along the first vertical planar interface 486. At least one material is deposited in the second recess 473 to create the second planar element 493, which extends along the second vertical planar interface 487.

[0053] One method of fabrication of the BBS-DBD is as follows: (i) depositing layers of the STI hard mask on the semiconductor substrate; (ii) patterning the STI hard mask with a litho step; (iii) anisotropic etching the STI hard mask layers; (iv) forming the VSTB cap 101 in the standard spacer process on the STI hard mask edge walls; (vi) fabricating the STI; (iv) recessing the STI; (vii) filling in the recess with the STI cap 301 dielectric; (viii) removing the STI hard mask; (ix) filling in the recess with the protective cap 451 dielectric. If desired, the STI hard mask can be used as the protective cap 451.

[0054] The present invention is a Vertical Gate MOS-Diode (Capacitor) device having the vertical gate to the contrary of the typical well-known horizontal gate. A cross-sectional view of two vertical gate MOS-Diode structures in accordance with a preferable embodiment of the present invention is illustrated in FIG.9. The vertical gate MOS-Diode comprises the gate electrode 087 made of heavily doped poly-Si or a metal with the gate protective cap 098 on top, the semiconductor substrate 200 with the Bar 450 having the bar protective cap 451 at the top, the gate dielectric 086 formed between the gate electrode 087 and the Bar 450, and the STI 300 connected to the substrate 200 at the bottom, to the STI cap 301 at the top, and to the gate electrode 087 and the gate dielectric 086 on the sides. [0055] The vertical gate MOS-Diode structure shown in FIG.9 can be fabricated using the BBS-DBD structure prefabricated as described above and shown in FIG.8. The steps are: (i) a litho step is done for opening the VSTB cap 101 followed by selectively etching away the cap 101; (ii) the Bar 450 is selectively anisotropically etched using the protective caps 301 and 451 as the hard masks to create a narrow trench; (iii) the gate dielectric 086 is formed on the Bar 450 vertical walls opened after the etching (if desired, the gate dielectric 086 can be formed as a gate dielectric stack having, for example, an interfacial thermal Si02 and high-k layer deposited); (iv) a thin gate electrode 087 is deposited between STI 300 and the gate dielectric 086; (v) the thin gate electrode 087 is planarized by Chemical Mechanical

Polishing (CMP) until reaching the top of the STI cap 301 and the cap 451; (vi) the thin gate electrode 087 is recessed and the recess is filled in with a dielectric and planarized by CMP to form the protective cap 098, (vii) the interlay er dielectric stack 102+103 is deposited. Such a gate structure is of a rather high resistance and can be used if the resistance is acceptable. Experienced-in-the-art engineers can use many methods for the fabrication of the contacts to the vertical gate MOS-Diode with the goal of reducing the total resistance.

[0056] A structure and a method of fabrication for vertical n-p junction structures attached to the STI are invented. A cross-sectional view of the two vertical n-p junction structures adjusted to the STI in accordance with a preferable embodiment of the present invention is illustrated in Fig.10. The structures can be formed using the BBS-DBD prefabri cation as described above and shown in FIG.8. A litho step is done for opening the VSTB cap 101 wherever it is needed and the cap 101 is selectively etched away. Then a portion of the Bar 450 is selectively anisotropically etched away under the removed VSTB cap to form a trench. The layer 560 is formed by filling in the trench with a c-Si SEG or a deposition of a poly-Si doped in-situ to a certain level in a range from lel5cm-3 to le20cm-3, or a SEG and a deposition of any other appropriately doped semiconductor material followed by CMP to remove poly-Si (or other semiconductor material) from the top surface. A doped extension layer 561 in the Bar 450 ("substrate" of diodes) is formed by a drive-in anneal. The protective cap 098 is formed by the standard set of steps: the layer 560 recess, if the layer 560 is formed by the deposition, followed by an isolation layer deposition, and followed by CMP to have the cap 098 as the leftover of the isolation layer in the recessed area only. If an SEG is used to form layer 560, the recess step is typically not needed. Then the interlay er dielectric stack 102+103 is deposited. The doping types of the left-hand side and the right-hand side layers 561 can be the same or opposite. An opposite doping type can be made by applying an extra litho step. If the doping type of the bar 450 (as a result of a well formation or as the initial substrate doping) is opposite to the doping type of the left-hand side layers 561 and the same as the right-hand side layers 561 then the diode is formed with a good low-resistance Ohmic contact to the substrate 200. If the left-hand side and the right-hand side layers 561 have the same doping type being opposite to the substrate doping, then a couple of diodes connected against each other is formed resulting in a fabricated BJT, if the distance between the two diode junctions, being typically in a range lOnm to 300nm, is much shorter than the minor carrier diffusion length being typically over 300nm. Due to the general tendency of miniaturization of all devices in ULSI and SoC products, someday such a structure will be in demand as a low current amplification device. Specialists experienced in the art can suggest many methods of fabrication for forming the contacts to the vertical diodes to reduce the diode series resistance, for example, by making strapping connection to many contacts along the vertical diode's perimeters. If desired, a vertical Schottky junction on a p-type or n-type semiconductor bar doped to a certain level that determines the reverse breakdown voltage of the Schottky diode, can be formed by an in-situ doped SEG layer having thickness less than the VSTB-cap size leaving a narrow trench (gap) between the epi layer and STI wall 300 followed by a high temperature anneal to create a doped layer 561 in the bar 450, being the Schottky diode substrate, and followed by a metal deposition to create a Schottky diode of a certain Schottky barrier height. Doped layer 561 can also be referred to herein as first vertical planar portion 496, and layer 560 can also be referred to herein as second vertical planar portion 497. The metal can be Pt, Co, Ni, NiCo-alloy, NiPt-alloy, WN, TiN, AITi, AlTiN, AlTa, and the like. A low temperature anneal in a temperature range from 200°C to 700°C for different metals and metal alloys is the next step to turn metal layer into a metal silicide layer or into an interfacial composite material having a certain Schottky barrier and a breakdown voltage. After this anneal, a low-resistance metal is deposited in the narrow trench followed by CMP to planarize the surface and to remove the metal where it is not needed. Such vertical Schottky diodes can have the barrier in a range from 0.05V to 0.5 V and can be used, for example, in a complementary technology having the Schottky diodes and CMOS transistors integrated together to constitute a Schottky-CMOS technology (also known as a Super CMOS technology).

[0057] A structure and a method of fabrication of a Vertical Multi-Junction Structure (VMJS) attached to the STI are invented. A cross-sectional view of a VMJS with the low- resistance contacts as an example of a particular invention embodiment is shown in FIG.11, which can be created from the BBS-DBD prefabrication as described above and shown in FIG.8. A litho step is done for patterning trenches/holes aligned to the edges of the caps 101 by an anisotropic etching away of the opened portion of the STI cap 301. If desired, the rest of the STI cap 301, the VSTB cap 101 and the protective cap 451 can be used as hard masks for selective anisotropic etching of holes/trenches in the STI 300. VSTB-FET Source/Drain stacks 062 are created in the holes/trenches formed in the STI 300 comprising the heavily appropriately doped SEG c-Si layer 563 on the wall of the Bar 450 or deposited in a poly crystalline form, followed by a deposition of a stack 562 comprising an low-resistance Ohmic contact made of metal nitride (TiN and the like) or metal silicide (NiSi and the like or other barrier material) and a filling-in of the rest of the trench with a low-resistance metal (W and the like) finished by a planarization step using CMP until the top of the STI cap 301 is reached. If desired, the layer 563 can be substituted by a layer of deposited heavily appropriately doped poly crystalline semiconductor being in particular embodiment a poly-Si, poly-Ge, and the like layers. Layer 563 can also be referred to herein as first vertical planar portion 496, and layer 562 can also be referred to herein as second vertical planar portion 497. The diode extension 561 is formed by drive-in anneal of the doping into the bar 450 (the diode's "substrate") before formation of the low-resistance layer 562. The diode extension 561 thickness depends on device requirements and can be typically chosen in a range from 3nm to 30nm and more for some high voltage SoC applications. The interlay er dielectric stack 102+103 is deposited on the top of the VMJS. Many vertical devices can be made from the VMJS by choosing proper doping types and designing the distance between the diode junctions as described below.

[0058] A Vertical Super Thin Body Hetero-j unction Bipolar Transistor (VSTB-HBT) device structure and a method of its fabrication are invented. A cross-sectional view of VSTB-HBT attached to the STI wall as a particular embodiment of the invention is illustrated in FIG.12. The structure can be made from the BBS-DBD prefabrication as described above and shown in FIG.8. The process integration steps can be as follows: (i) the VSTB cap 101 is opened by a Litho step only on the emitter side and then selectively etched away with continuing anisotropic selective etching of a portion of the c-Si Bar 450 under it to form a trench; (ii) the trench formed is filled with an appropriately doped compressively stressed SEG of SiGe layer 564 to form the Vertical Super Thin SiGe Body as the base of the VHBT; (iii) if desired, to improve the SiGe interface roughness for c-Si epitaxial emitter layer growth on the SiGe layer by the following c-Si SEG step in STI trench and to provide a better selectivity in anisotropic etching STI vs. SiGe layer, a portion of the emitter c-Si layer is grown by a selective epitaxy of c-Si over SiGe as an interfacial layer; (iv) the protective cap 098 is formed on the top of the SiGe base by the standard process module of "recess- deposition-planarization" (in the case of high selectivity during the SiGe growth, the "recess" step might not be needed); (v) a litho step to form openings for the low-resistance VSTB- HBT emitter 563 and a low-resistance contact to the VSTB-HBT collector 450 being self- aligned to the caps 101 and 098, followed by an anisotropic etching of the trenches/holes in the STI 300; (vi) a heavily in-situ doped c-Si SEG layer 563 on the SiGe base wall or on the partial c-Si emitter layer wall if this option is used, and the same heavily in-situ doped SEG of c-Si layer 563 on the c-Si Bar 450 wall on the opposite side of the emitter followed by formation of the low-resistance metal contact 562 served as a low-resistance contact to the VSTB-HBT main collector 450; (vii) a highly doped collector doping layer can be placed as a subcollector layer 452 being formed of the same doping type as the main collector under the VSTB-HBT main collector 450 by an ion implantation to reduce the collector parasitic resistance. Also for the same purpose of the collector parasitic resistance reduction, if desired, another collector doping layer 453 can be placed in the VSTB-HBT main collector region at the collector contact side 563, as close to the base as the collector breakdown voltage specification allows, being a subject for engineering optimization.

[0059] The VSTB-HBT with the SiGe base 564 having a thickness in a range from 3nm to 300nm being doped, for example, with p-type dopant like Boron, placed between the highly doped c-Si epitaxial emitter 563 and the c-Si collector formed in the Bar 450, having a Bar thickness in a range from 20nm to 300nm and doped for example with n-type dopant like Phosphorus for n-p-n HBT and vise versa dopant types for p-n-p HBT, has an advantage of having the same location of both types of junctions: the c-Si - c-SiGe material stack heteroj unction and the emitter-to-base doping junction, boosting the HBT performance significantly. If desired, many types of VSTB-HBTs can be designed using the described approach by an expert in the field of the art. Complementary VSTB-BJT or VSTB -HBT can be formed having the n-p-n and p-n-p transistors on the same wafer, if desired.

[0060] BiCMOS technology is widely used, exploiting the planar conventional fabrication approach for making both Bipolar Junction Transistors (BJT) and CMOS MOSFETs. For the modern CMOS technologies exploiting 3D Fin-based vertical MOSFETs, like the Tri-Gate MOSFET and the VSTB-FET, there is no vertical BJT integrated into a BiCMOS technology to the best of our knowledge. Fabrication of such a BJT using the 3D FinFET process steps and modules compatible with the general CMOS technology would bring many benefits to ULSI designers. Also many ESDP devices built on a product die could have the BJTs as a part of a portfolio of ESDP devices and circuitry. So it is important to have a BiCMOS technology capability to form and integrate the BJTs. A structure and a fabrication method of a Vertical Super Thin Body Bipolar Junction Transistor (VSTB-BJT) are invented. A simplified cross-sectional view illustrating only the key active layers of a VSTB-BJT is shown in FIG.13. In this embodiment many typical VSTB-FET processes and litho steps are used. Some layers being typical for the VSTB-FET, such as the VSTB itself and the VSTB- FET gate area are not fully formed but their corresponding protective cap layers 101 and 451 are in use and comprise the caps for the p- or n-doped c-Si area (Bar) 227. The VSTB cap layers 101 are fabricated because they will be used for making MOSFETs in the CMOS part of BiCMOS technology. If desired, they can be removed and replaced by extending the protective cap 451. The BJT emitter comprises the VSTB-FET Source/Drain stack 062 and the outdiffusion layer 066. The BJT collector comprises the VSTB-FET Source/Drain stack 062 and the outdiffusion layer 060. The BJT base consists of the c-Si Bar between the layers 066 and 060 which conducts the base current Jb down to the substrate 200. The emitter injects the J_e current into the base and the collector collects the current J_c passing through the base. If the Source/Drain stack 062 of the n-channel VSTB-FET is used, then n-p-n BJT is formed with the p-base being the p-doped well 227 in the substrate 200. If the Source/Drain stack 062 of the p-channel VSTB-FET is used then p-n-p BJT is formed with the n-base being the n-doped well 227 in the substrate 200, being typically p-doped. It is easy to notice that the BJT, having all active layers horizontally ordered, has a principle difference with respect to the prior art BJT structure on bulk silicon, where the horizontal active layers are stacked vertically and current flows vertically but "turns" in the collector contact layer to flow in the horizontal direction, which is opposite to the VSTB-BJT current flows. To improve the performance of the VSTB-BJT some extra doping layers are needed, as illustrated in FIG.14 being a cross-sectional view of a realistic VSTB-BJT. A top layout view of the realistic VSTB-BJT having some extra active layers for improving the performance and providing contacts to the base and to the deep n-well is shown in FIG.15. In an n-p-n VSTB-BJT embodiment, in order to reduce the base parasitic resistance and to improve the speed, a deep p+-doped buried layer 220 made with a mask 224 is formed having the base contacted aside of the main base area by the p-channel VSTB-FET Source/Drain stack 223 and the outdiffusion layer 221 as shown in FIG.15. [0061] To reduce the base-to-substrate coupling a screening n-doped buried layer 210 is formed with a mask 211 under the buried layer 220 and under the entire active area 227. The layer 210 is contacted outside the perimeter of the buried layer 220 by a stack 237 comprising the VSTB-FET Source/Drain stack 062 and the outdiffusion layer 066. The stack 237 and the emitter and the collector can be done using the same processes. The low-resistance n-doped stack 237 can reduce the floating potential on the deep n-well and further decouple the base potential from the substrate. The layers 062 and 223 are embedded into the STI 300 and have no contact to the substrate 200. The outdiffusion layers 060, 066 and 221 are doped during a drive-in anneal from the VSTB Source/Drain stacks 062 and 223. In order to increase the operational collector voltage and to reduce the Early effect, an extra p-doped layer 225 is needed in the base. This layer can be created on the emitter side of the base so that there is a built-in doping gradient in the base from the emitter junction to the collector junction. Such a gradient does certainly help to increase the switching speed of the BJT. Metal contacts/vias to the emitter 069, to the collector 063, to the base extension 235, and to the deep n-type layer 236 are shown schematically in FIG.15 and their form and locations are a subject for engineering optimization. A p-n-p VSTB-BJT is easier to make than the n-p-n version because of the availability of the n-well to be used as the base, and having the p-channel VSTB-FET Source/Drain stack to be used to form the emitter and the collector. All other layers mentioned above are optional, to be used depending on some specific application requirements. If desired, the stack 237 contacting the deep n-type buried layer 210 can be made common for many transistors and can be placed outside of the particular transistor shown in FIG.15, as it is illustrated for JFET below. The base thickness 230, which is the distance from the emitter Space Charge Region (SpCR) edge 072 to the collector SpCR edge 071 in the quasi-neutral base, is an important device design and process integration parameter to be a subject for engineering optimization being in a range from lOnm to 300nm. If desired, it is possible to use such VSTB-based BJTs in ESDP circuitry, but then a strong base-to- substrate coupling is needed, which requires that any deep screening/isolating doping layers explained above are not be used and that a more simple BJT structure can be designed and fabricated.

[0062] JFET device is a very attractive device for many analog applications due to its very low-noise and high input impedance characteristics. JFET-BJT technology is in use for Operational Amplifier (OpAmp) applications where the input devices are JFETs with low- noise and high impedance properties, having further signal amplification by complimentary BJTs (CBJT), having n-p-n and p-n-p BJTs integrated on a single die or BiCMOS technology using just one type of BJT and JFET devices. A VSTB-JFET structure and method of its fabrication, similar in design and fabrication to the VSTB-BJT having horizontal inj ection and all vertical structural layers is invented. A cross-sectional view and a layout view of a double-gate JFET are shown in FIG.16 and FIG.17 as a particular embodiment of the invention. The only difference is that the current flows (marked on FIG.16 as the "X" symbol in a circle) through the channel 226, being the "base" layer of the BJT and being between the two gates 060 and 066 on the opposite sides of the "emitter" and "collector" of the BJT. The SpCR thickness 071 is modulated by the applied gate voltage and controls the channel thickness 226 and the conductivity. The contacts to the channel 226 are made on both sides of the channel, and they are essentially the Source 238 and the Drain 239 of the JFET. It is easy to design and to fabricate both an n-channel VSTB-JFET with the gates made by the p- channel VSTB-FET Source/Drain process and the Source 238 and Drain 239 made by the n- channel VSTB-FET Source/Drain process, as well as a p-channel VSTB-JFET with the gates made by the n-channel VSTB-FET Source/Drain process and the Source 238 and Drain 239 made by the p-channel VSTB-FET Source/Drain process. If desired and if noise requirements are not stringent, a single gate VSTB-JFET can be fabricated in a smaller area. A cross- sectional view and a layout view of a single-gate JFET are shown in FIG.18 and FIG.19. Due to an inherent positive charge presence in the a-Si02 STI 300, a p-channel single-gate VSTB- JFET would be a preferable embodiment of such a VSTB-JFET. The threshold voltage (Vth) of the VSTB-JFET can be engineered by manipulating the thickness of the channel conductive layer 226 using an additional doping layer similar to the layer 225 in the BJT, and it can be used in the same way for engineering the BJT base.

[0063] ESDP devices are an important part of any ULSI to protect the internal devices from the harmful effects of a sudden potential rise at any ULSI pad due to discharge of the electrostatically generated charge on a conductive body suddenly connected to a pad from the outside world. Any ESDP device known can be decomposed in terms of MOSFETs, BJTs, diodes, resistors, capacitors, and thyristors. In turn a thyristor can be represented as two BJTs connected with common bases and so it can be designed by making proper interconnections from already available VSTB-based BJTs having horizontal injection described above as a particular embodiment of the invention. For the thyristor to be an ESDP device, it is necessary to have the capability to design a thyristor having horizontal injection and all vertical structural layers as a standalone structure with a more effective coupling of the bases and hence with better performance parameters and compacted into a smaller layout area. A cross-sectional view of an n-p-n-p thyristor with the key functional vertical layers is illustrated in FIG.20 as a particular embodiment of the invention. The key differences with respect to the BJT are: (i) the "emitter" is made of n+-doped layers 066 and 067 similar or the same as the "emitter" for the n-p-n BJT whereas the "collector" is made of p+-doped layers 060 and 062 similar or the same as the "collector" for the p-n-p BJT; (ii) the "base" is split into a p-doped base 216 made of the semiconductor substrate 200 and an n-doped base 215 fabricated, for example, by a drive-in n-doping diffusion from a Phosphor Silicate Glass (PSG) deposited into the 062 trench followed by removing it before the "collector" formation or made using the deep n-well available in any CMOS technology. To adjust the triggering threshold currents, parasitic resistances, and other performance parameters the doping levels of the bases 216 and 215 can be changed by additional doping steps by ion implantation of appropriate dopant ion types and energy followed by high temperature thermal anneals similar to fabricating the layer 225 in the VSTB-BJT structure. A layout view of the n-p-n-p thyristor with the key functional vertical layers is shown in FIG.21 where the contact 236 connected to the p-doped base 216 by the p-type VSTB-FET

Source/Drain stack 042 and the p-type outdiffusion layer 040, and the contact 235 connected to n-doped base 215 by the n-type VSTB-FET Source/Drain stack 045, and the n-type outdiffusion layer 043 are designed as for a standalone thyristor device with the capability to connect the bases to any desired nodes in an integrated circuit. But if desired both or one of those contacts can be omitted, having the bases left floating or connected by deep buried doped layer 210 to any node to trigger the thyristor as an ESDP device.

[0064] If desired, an SOI substrate with a thick SOI layer in a range from lOnm to 300nm can be used with no change of the product masks, enabling the fabrication of different products for bulk or SOI specifications. FIG.22 illustrates a particular example of fabricating a BJT in the SOI layer 252 on the BOX layer 250, placed on the semiconductor substrate 200. The structure and all the layers are explained in FIG.20. Any device mentioned above and all together can be formed in a single process integration on an SOI substrate featuring thick SOI.

[0065] If desired, a stackable architecture can be formed in a way illustrated in FIG.23. A cross-sectional view of a stackable architecture as a couple of tiers is shown having, as an example, a tVSTB-FET in the crystalline substrate (lower or first tier) and the BJT in the top (upper or second) tier being isolated from the first tier by an isolation layer 950 where the BJT having all the key functional vertical layers operating in horizontal injection mode with all the structural layers formed in a second semiconductor (crystalline, poly crystalline, or amorphous) layer 251. The layer numbers are kept the same as for the basic vertical BJT in the crystalline substrate in order to easily understand the structure even though they are made in the second or any upper tier. If desired, such a structure can be formed in an inverse order: BJT in the bottom tier and tVSTB-FET in the top. If desired, the STI layer in the top tier can be formed through the layer 251 till the isolation layer 950 making the device functioning similar to the SOI device concept. The known Gate first or Gate last approaches can be implemented. Many different types of devices can be fabricated in single process integration with the VSTB-FET having the isolation, if desired, between the devices by forming the iso- plugs combined with a gate electrode isolation by forming the iso-trenches. If desired, bulk semiconductor (silicon) wafers or SOI wafer with a thick SOI layer in a range from lOnm to 300nm can be used with no change of the product masks but fabricating different products for bulk or SOI specifications. If it is found that a product made on a bulk wafer is sensitive to the substrate coupling or radiation effects the product can be fabricated on SOI wafer easily by replacing the wafer. And vice versa, if a product made on SOI wafers is found to be sensitive to the floating body effects it can be fabricated on a bulk wafer easily with no mask redesign.

[0066] The placement of the planar elements, which can also be referred to as vertical planar elements, at the interface of the dielectric body and the bar member permit the formation of very thin planar elements. Such planar elements are supported by the dielectric body, the bar member or both. In one embodiment, a recess or space can be provided alongside the planar element as either the dielectric body or the bar member alone may be sufficient to support the planar element.

[0067] In one embodiment, a semiconductor device is provided and includes a substrate of a semiconductor material, a bar member of the semiconductor material extending upwardly from the substrate and along the substrate between first and second spaced-apart trenches in the substrate, a first body of a dielectric material disposed in the first trench and engaging the bar member along a first vertical planar interface extending upwardly from and along the substrate, a second body of a dielectric material disposed in the second trench and engaging the bar member along a second vertical planar interface extending upwardly from and along the substrate, a first planar element disposed in a first recess extending along the first vertical interface and a second planar element disposed in a second recess extending along the second vertical interface.

[0068] Each of the first and second planar elements can have a height to width ratio selected from the group consisting of at least 1 : 1, at least 2: 1, at least 3: 1, at least 4: 1, at least 5: 1, at least 10: 1, at least 20: 1 and ranging from 1 : 1 to 30: 1. The first planar element and the second planar element can be identical. The first planar element and the second planar element can each be selected from the group consisting of a planar semiconductor element, a planar conductive element, a planar metal element, a planar dielectric element, a planar doped semiconductor element, a planar metal/di electric stack, a planar semiconductor/dielectric stack and a planar metal/semiconductor stack. The bar member can have a width between the first and second vertical planar interfaces ranging from 20 to 1000 nanometers. The first planar element can be disposed in a first recess in the bar member extending along the first vertical interface and the second planar element can be disposed in a second recess in the bar member extending along the second vertical interface. The first and second planar elements can each be gate electrodes. The first and second gate dielectrics can be disposed between the respective gate electrodes and the bar member for providing a semiconductor device that is first and second metal-oxide-semiconductor (MOS) capacitors. Each of the first and second planar elements can include a first vertical planar portion of a doped semiconductor material and a second vertical planar portion of a conductive material between the first vertical planar portion and the respective vertical planar interface for providing a

semiconductor device that is two Schottky diodes with vertical junctions. Each of the second vertical planar portions can have a width ranging from five to ten nanometers.

[0069] The first planar element can be disposed in a first recess in the first body extending along the first vertical interface and the second planar element can be disposed in a second recess in the second body extending along the second vertical interface. Each of the first and second planar elements can include a first vertical planar portion of a doped semiconductor material extending along the respective vertical planar interface and a second vertical planar portion of a conductive material between the first vertical planar portion and the respective body. Each first vertical planar portion can have a width ranging from five to fifteen nanometers, each of the first and second recesses can have a height to width ratio ranging from 3: 1 to 20: 1 and the bar member can have a width between the first and second vertical planar interfaces ranging from 20 to 300 nanometers. The semiconductor device can include a planar semiconductor element disposed in an additional recess provided in the bar member and extending along the first vertical planar interface, the bar member having a doping type and being provided with a doped portion extending along the second vertical planar interface and a doped sub-collector portion extending along the bottom of the bar member, wherein the planar semiconductor element is of a different semiconductor material than the

semiconductor material of the bar member and wherein each of the first vertical planar portions, the planar semiconductor element has the different doping type than the bar member, the doped portion and the doped sub-collector portion have the same doping type as the bar member, the first recess height is less than the additional recess height on two to five nanometers, for providing semiconductor device that is a heteroj unction bipolar transistor (HBT) having the same location of the heteroj unction and the emitter-to-base doping junction. The planar semiconductor element can have a width ranging from three to 300 nanometers and the bar member can have a width between the first and second vertical planar interfaces ranging from 20 to 300 nanometers.

[0070] The semiconductor material can be a silicon-on-insulator substrate. The first vertical planar interface can be parallel to the second vertical planar interface.

[0071] The bar member can have opposite first and second sides and opposite first and second ends extending between the first and second sides, the first body can be disposed along the first side of the bar member and the second body disposed along the second side of the bar member, further comprising a third trench provided in the substrate along the first end of the bar member and a fourth trench provided in the substrate along the second end of the bar member, a third body of a dielectric material disposed in the third trench and engaging the bar member along a third vertical planar interface extending upwardly from and along the substrate, a fourth body of a dielectric material disposed in the fourth trench and engaging the bar member along a fourth vertical planar interface extending upwardly from and along the substrate, a third planar element disposed in a third recess extending along the third vertical interface and a fourth planar element disposed in a fourth recess extending along the fourth vertical interface.

[0072] The first vertical planar interface can be parallel to the second vertical planar interface and the third and fourth vertical planar interfaces can be perpendicular to the first and second vertical planar interfaces. [0073] Each of the first and second trenches can have opposite ends and the third trench can connect with the first end of the first and second trenches and the fourth trench can connect with the second end of the first and second trenches.

[0074] The semiconductor device can include a first outdiffusion layer extending into the bar member along the first vertical interface and a second outdiffusion layer extending into the bar member along the second vertical interface. The first vertical planar portion and the first out-diffusion layer can have an doping type opposite to the bar member doping type the second vertical planar portion and the second outdiffusion layer can have doping type as the bar member doping type for providing a semiconductor device that is a semiconductor diode with vertical junctions. The first and second vertical planar portion and each of the first and second outdiffusion layer can have opposite doping types to the bar member doping type for providing a semiconductor device that is two semiconductor diodes with vertical junctions connected against each other. Each of the planar elements can include a first vertical planar portion of a doped semiconductor material extending along the respective vertical planar interface and a second vertical planar portion of a conductive material between the first vertical planar portion and the respective body, each of the first vertical planar portion can have a width ranging from 5nm to 30nm, each of the recess can have a height to width ratio ranging from 3 : 1 to 20: 1 and the bar member can have a width ranging from 20 to 300 nanometers, all recesses can have approximately the same height and the third and the fourth recess has a distance between the each of the first and second recess ranging from 10 to 100 nanometers.

[0075] The semiconductor device can include a first out-diffusion layer extending into the bar member along the first vertical interface, a second out-diffusion layer extending into the bar member along the second vertical interface, a third out-diffusion layer extending into the bar member along the third vertical interface and a fourth out-diffusion layer extending into the bar member along the fourth vertical interface. The semiconductor device can include a buried doped sub-base layer at the bar member bottom, a doped layer extending along the first vertical interface, the first planar portion of the first and the second planar element can have the opposite doping type to the bar member doping type, the doped layer, the first planar portion of the fourth and the third planar element and buried doped sub-base layer can have the same doping type as the bar member, the bar member can have a width ranging from 20 to 300 nanometers, the bottom of the third and the fourth outdiffusion layers can be inside the buried doped sub-base layer or at least touching it for providing a semiconductor device that is a bipolar transistor (BJT) having vertical junctions with the first outdiffusion layer as the emitter, the second planar element as the collector contact, the third planar element and the forth planar element as the base contacts.

[0076] The semiconductor device can include a screening buried layer under the entire bar member bottom, the screening buried layer top and the buried doped sub-base layer top can be at the same level, the screening buried layer and the first planar portion of the fourth planar element can have the opposite doping type to the bar member doping type, the buried doped sub-base layer cannot extend under the fourth outdiffusion layer for providing a semiconductor device that is a bipolar transistor (BJT) having vertical junctions with the first outdiffusion layer as the emitter, the second planar element as the collector contact, the third planar element as the base contact and the fourth planar element as the contact to the screening buried layer.

[0077] The semiconductor device can include a screening buried layer at the entire bar member bottom, the second planar element and the second outdiffusion layer can be absent and the screening buried layer top can be at the same level as the first outdiffusion layer bottom, and the semiconductor device can be a single gate junction field effect transistor with the first planar element as the gate and the third and the fourth planar element as the contacts to the transistor channel.

[0078] The semiconductor device can include a second bar member of the semiconductor material extending upwardly from the substrate and along the substrate and adjacent to the third dielectric body, a fifth planar element can be disposed in a fifth recess in the third dielectric body extending along the fourth vertical interface of the second bar member, a fifth outdiffusion layer can extend in the second bar member along the fourth vertical interface of the second bar member, the bar members can have the same height, a screening buried layer can be positioned at the bottom of the bar members, the screening buried layer, the first planar portion of the fifth planar element and the fifth outdiffusion layer can have a different doping type than the bar members and the screening buried layer top can be at the same level or higher the fifth outdiffusion layer bottom and fifth planar element can be the contact to the screening buried layer. The first planar portion of the first and the second planar element and the first and the second outdiffusion layer can have a different doping type than the bar member, the first planar portion of the third and the fourth planar element can have the same doping type as the bar member, the screening buried layer can be positioned under the first and the second outdiffusion layers at the distance not less than 10 nanometers, the bar member can have a width ranging from 20 to 300 nanometers for providing a semiconductor device that is a double gate vertical junction field effect transistor (JFET) with the first and the second planar element as the gates, the third and the fourth planar element as the contacts to the transistor channel.

[0079] The semiconductor device can include a diffusion layer extending into the bar member along the first vertical interface, the diffusion layer can have a width ranging from 10 to 100 nanometers and a doping type the same as to the bar member doping type for providing a semiconductor device that is a double gate vertical junction field effect transistor (JFET).

[0080] The semiconductor device of can include a doped layer extending along the first vertical interface, a buried doped sub-base layer extending into and under the entire bar member at the bar member bottom, the top of the screening buried layer and the top of the buried doped sub-base layer can be at the same position, the first planar portion of the first and the second planar element can have the opposite doping type to the bar member doping type, the doped layer, the first planar portion of the fourth and the third planar element, and the buried doped sub-base layer can have the same doping type as the bar member, the bar member can have a width ranging from 20 to 300 nanometers, the bottom of the third and the fourth outdiffusion layers can be inside the buried doped sub-base layer or at least touching it for providing a semiconductor device that is a bipolar transistor (BJT) having vertical junctions with the first outdiffusion layer as the emitter, the second planar element as the collector contact, the third and the forth planar element as the base contacts.

[0081] The semiconductor device can include a second base diffusion layer extending into the bar member and into the screening buried layer and adjacent to the second outdiffusion layer, the third planar element can be absent, the second base diffusion layer and the first portion of the first planar element can be a doping type opposite the bar member doping types, the first portion of the second and fourth planar elements and the second and fourth outdiffusion layers can have the same doping type as the bar member doping type, the bar member can have a width ranging from 50 to 300 nanometers for providing a semiconductor device that is a vertical junction thyristor with the first outdiffusion layer as emitter, the second planar element as the collector contact, the fourth planar element as the first base contact and the fifth planar element as the second base contact. [0082] The semiconductor material can be a silicon-on-insulator substrate. The bar member can have a top surface, and a dielectric cap layer can be provided on the top surface of the bar member.

[0083] A method for forming a semiconductor device in a substrate of a semiconductor material can be provided and include the steps of anisotropic etching first and second spaced- apart trenches in the substrate to form a bar member of the semiconductor material extending upwardly from the substrate and along the substrate between the first and second trenches, depositing a first body of a dielectric material in the first trench to create a first vertical planar interface between the first body and the bar member that extends upwardly from and along the substrate, depositing a second body of a dielectric material in the second trench to create a second vertical planar interface between the second body and the bar member that extends upwardly from and along the substrate, the first vertical planar interface extending parallel to the second vertical planar interface, anisotropic etching a first recess extending along the first vertical planar interface, anisotropic etching a second recess extending along the second vertical planar interface, depositing at least one material in the first recess to create a first planar element that extends along the first vertical planar interface and depositing at least one material in the second recess to create a second planar element that extends along the second vertical planar interface.

[0084] The first planar element can be the same as the second planar element. The step of anisotropic etching the first recess extending along the first vertical interface can include anisotropic etching a first recess in the bar member extending along the first vertical interface and the first planar element can be disposed in a bar member, the step of anisotropic etching the second recess extending along the second vertical interface can include anisotropic etching a second recess in the bar member extending along the second vertical interface and the second planar element can be disposed in a bar member. The first and second planar elements can each be gate electrodes and the method can include the step of forming first and second gate dielectrics between the respective gate electrodes and the bar member. The first and second planar elements can each be a doped semiconductor material.

[0085] The step of anisotropic etching a first recess extending along the first vertical planar interface can include anisotropic etching a first recess in the first body extending along the first vertical planar interface and the first planar element can be disposed in the first recess, and the step of anisotropic etching a second recess extending along the second vertical planar interface can include anisotropic etching a second recess in the second body extending along the second vertical planar interface and the second planar element can be disposed in a second body. The first and second planar elements can each be a metal/semiconductor stack. The semiconductor material can be a silicon-on-insulator substrate.

[0086] The bar member can have a top surface and a first border area on the top surface adjacent the first vertical planar interface and an opposite second border area on the top surface spaced apart from the first border area and adjacent the second vertical planar interface and a central area between the first and second border areas, and the method can include the steps of depositing a first dielectric material over the first and second bodies, depositing a second dielectric material over the first and second border areas and depositing a third dielectric material over the central area, wherein the first, second and third dielectric materials are different from each other, wherein the step of anisotropic etching the first recess extending along the first vertical planar interface includes removing one of the first dielectric material over at least a portion of the first border area and the second dielectric material over at least a portion of the first body and then anisotropic etching the first recess extending along the first vertical planar interface and wherein the step of anisotropic etching the second recess extending along the second vertical planar interface includes removing one of the first dielectric material over at least a portion of the second border area and the second dielectric material over at least a portion of the second body and then anisotropic etching the second recess extending along the second vertical planar interface.

[0087] A method for forming a semiconductor device in a substrate of a semiconductor material can be provided and include the steps of anisotropic etching first and second spaced- apart trenches and third and fourth spaced-apart trenches orthogonal to and connected to first and second spaced-apart trenches in the substrate using a hard mask dielectric with spacers of a second dielectric material on vertical sides of the hard mask dielectric to form a bar member of the semiconductor material extending upwardly from the substrate and along the substrate between the trenches, depositing a dielectric material into the trenches to form the first, the second, the third and the fourth dielectric body in respective trenches to create the first, the second, the third and the fourth vertical planar interfaces between the bar member and the first, the second, the third and the fourth dielectric body respectively, the first vertical planar interface extending parallel to the second vertical planar interface, the third vertical planar interface extending parallel to the fourth vertical planar interface, anisotropic etching a first recess extending along the first vertical planar interface, anisotropic etching a second recess extending along the second vertical planar interface, depositing at least one material in the first recess to create a first planar element that extends along the first vertical planar interface and depositing at least one material in the second recess to create a second planar element that extends along the second vertical planar interface.

[0088] The first planar element can be the same as the second planar element. The step of anisotropic etching the first recess extending along the first vertical interface can include selective anisotropic etching of the spacer over at least a portion of the bar member and anisotropic etching a first recess in the bar member extending along the first vertical interface and the first planar element can be disposed in a bar member, and the step of anisotropic etching the second recess extending along the second vertical interface can include selective anisotropic etching of the spacer over at least a portion of the bar member and anisotropic etching a second recess in the bar member extending along the second vertical interface and wherein the second planar element is disposed in a bar member. The first and second planar elements can each be gate electrodes and the method can include the step of forming first and second gate dielectrics between the respective gate electrodes and the bar member. The first and second planar elements can each be a doped semiconductor material.

[0089] The step of anisotropic etching a first recess extending along the first vertical planar interface can include anisotropic etching a first recess in the first body extending along the first vertical planar interface and the first planar element can be disposed in the first recess, and the step of anisotropic etching a second recess extending along the second vertical planar interface can include anisotropic etching a second recess in the second body extending along the second vertical planar interface and wherein the second planar element is disposed in a second body. The method can include a selective anisotropic etching of the spacer over at least a portion of the bar member adjacent to the first recess and anisotropic etching a recess in the bar member extending along the first vertical interface and adj acent to the first planar member and the third planar semiconductor element can be disposed in the recess in the bar member, the semiconductor of the third planar semiconductor element can be different of the bar member semiconductor. The first and second planar elements can each be a

metal/semiconductor stack, and the method can include an anneal to create a first and a second outdiffusion layers extending into the bar member.

[0090] The method can include an ion implantation before the recesses formation using the photoresist mask to form a buried screen layer at the bar member bottom, the step of anisotropic etching of a third recess extending along the third vertical planar interface can includes anisotropic etching a third recess in the third body extending along the third vertical planar interface and the third planar element can be disposed in the third recess, and the step of anisotropic etching a fourth recess extending along the fourth vertical planar interface can include anisotropic etching a fourth recess in the fourth body extending along the fourth vertical planar interface and wherein the fourth planar element can be disposed in a fourth body, the third and fourth planar elements can each be a metal/semiconductor stack, and the method can include an anneal to create a third and a fourth outdiffusion layers extending into the bar member on 5 to 20 nanometers. The method can include an ion implantation before the recesses formation using the photoresist mask to form a buried sub-base layer at the bar member bottom. Before the second planar element deposition a deposition of an appropriate Silicate Glass into the second recess can be done, followed by a drive-in anneal, followed by removing the Silicate Glass.

[0091] The semiconductor material can be a silicon-on-insulator substrate.

[0092] The bar member can have a top surface and a first border area on the top surface adjacent the first vertical planar interface and an opposite second border area on the top surface spaced apart from the first border area and adjacent the second vertical planar interface and a central area between the first and second border areas, and the method can include the steps of depositing a first dielectric material over the first and second bodies, depositing a second dielectric material over the first and second border areas and depositing a third dielectric material over the central area, wherein the first, second and third dielectric materials are different from each other, wherein the step of anisotropic etching the first recess extending along the first vertical planar interface includes removing one of the first dielectric material over at least a portion of the first border area and the second dielectric material over at least a portion of the first body and then anisotropic etching the first recess extending along the first vertical planar interface and wherein the step of anisotropic etching the second recess extending along the second vertical planar interface includes removing one of the first dielectric material over at least a portion of the second border area and the second dielectric material over at least a portion of the second body and then anisotropic etching the second recess extending along the second vertical planar interface.

Claims

CLAIMS What is claimed is:

1. A semiconductor device, comprising a substrate of a semiconductor material, a bar member of the semiconductor material extending upwardly from the substrate and along the substrate between first and second spaced-apart trenches in the substrate, a first body of a dielectric material disposed in the first trench and engaging the bar member along a first vertical planar interface extending upwardly from and along the substrate, a second body of a dielectric material disposed in the second trench and engaging the bar member along a second vertical planar interface extending upwardly from and along the substrate, a first planar element disposed in a first recess extending along the first vertical interface and a second planar element disposed in a second recess extending along the second vertical interface.

2. The semiconductor device of Claim 1, wherein the each of the first and second planar elements has a height to width ratio selected from the group consisting of at least 1 : 1, at least 2: 1, at least 3: 1, at least 4: 1, at least 5: 1, at least 10: 1, at least 20: 1 and ranging from 1 : 1 to 30: 1.

3. The semiconductor device of Claim 1, wherein the first planar element and the second planar element are identical.

4. The semiconductor device of Claim 1, wherein the first planar element and the second planar element are each selected from the group consisting of a planar semiconductor element, a planar conductive element, a planar metal element, a planar dielectric element, a planar doped semiconductor element, a planar metal/di electric stack, a planar

semiconductor/dielectric stack and a planar metal/semiconductor stack.

5. The semiconductor device of Claim 1, wherein the bar member has a width between the first and second vertical planar interfaces ranging from 20 to 1000 nanometers.

6. The semiconductor device of Claim 1, wherein the first planar element is disposed in a first recess in the bar member extending along the first vertical interface and the second planar element is disposed in a second recess in the bar member extending along the second vertical interface.

7. The semiconductor device of Claim 6, wherein the first and second planar elements are each gate electrodes.

8. The semiconductor device of Claim 7, further comprising first and second gate dielectrics disposed between the respective gate electrodes and the bar member, wherein the semiconductor device is first and second metal-oxide-semiconductor (MOS) capacitors.

9. The semiconductor device of Claim 6, wherein each of the first and second planar elements includes a first vertical planar portion of a doped semiconductor material and a second vertical planar portion of a conductive material between the first vertical planar portion and the respective vertical planar interface and wherein the semiconductor device is two Schottky diodes with vertical junctions.

10. The semiconductor device of Claim 9, wherein each of the second vertical planar portions has a width ranging from five to ten nanometers.

1 1. The semiconductor device of Claim 1 , wherein the first planar element is disposed in a first recess in the first body extending along the first vertical interface and the second planar element is disposed in a second recess in the second body extending along the second vertical interface.

12. The semiconductor device of Claim 1 1, wherein each of the first and second planar elements includes a first vertical planar portion of a doped semiconductor material extending along the respective vertical planar interface and a second vertical planar portion of a conductive material between the first vertical planar portion and the respective body.

13. The semiconductor device of Claim 12, wherein each first vertical planar portion has a width ranging from five to fifteen nanometers, wherein each of the first and second recesses has a height to width ratio ranging from 3: 1 to 20: 1 and wherein the bar member has a width between the first and second vertical planar interfaces ranging from 20 to 300 nanometers.

14. The semiconductor device of Claim 12, further comprising a planar semiconductor element disposed in an additional recess provided in the bar member and extending along the first vertical planar interface, the bar member having a doping type and being provided with a doped portion extending along the second vertical planar interface and a doped sub-collector portion extending along the bottom of the bar member, wherein the planar semiconductor element is of a different semiconductor material than the

semiconductor material of the bar member and wherein each of the first vertical planar portions, the planar semiconductor element has the different doping type than the bar member, the doped portion and the doped sub-collector portion have the same doping type as the bar member, the first recess height is less than the additional recess height on two to five nanometers, and wherein the semiconductor device is a heteroj unction bipolar transistor (HBT) having the same location of the heteroj unction and the emitter-to-base doping junction.

15. The semiconductor device of Claim 14, wherein the planar semiconductor element has a width ranging from three to 300 nanometers and the bar member has a width between the first and second vertical planar interfaces ranging from 20 to 300 nanometers.

16. The semiconductor device of Claim 1, wherein the semiconductor material is a silicon-on-insulator substrate.

17. The semiconductor device of Claim 1, wherein the first vertical planar interface is parallel to the second vertical planar interface.

18. The semiconductor device of Claim 1, wherein the bar member has opposite first and second sides and opposite first and second ends extending between the first and second sides, the first body disposed along the first side of the bar member and the second body disposed along the second side of the bar member, further comprising a third trench provided in the substrate along the first end of the bar member and a fourth trench provided in the substrate along the second end of the bar member, a third body of a dielectric material disposed in the third trench and engaging the bar member along a third vertical planar interface extending upwardly from and along the substrate, a fourth body of a dielectric material disposed in the fourth trench and engaging the bar member along a fourth vertical planar interface extending upwardly from and along the substrate, a third planar element disposed in a third recess extending along the third vertical interface and a fourth planar element disposed in a fourth recess extending along the fourth vertical interface.

19. The semiconductor device of Claim 18, wherein the first vertical planar interface is parallel to the second vertical planar interface and the third and fourth vertical planar interfaces are perpendicular to the first and second vertical planar interfaces.

20. The semiconductor device of Claim 18, wherein each of the first and second trenches has opposite ends and wherein the third trench connects with the first end of the first and second trenches and the fourth trench connects with the second end of the first and second trenches.

21. The semiconductor device of Claim 12, further comprising a first outdiffusion layer extending into the bar member along the first vertical interface and a second outdiffusion layer extending into the bar member along the second vertical interface.

22. A semiconductor device of Claim 21, wherein the first vertical planar portion and the first out-diffusion layer have doping type opposite to the bar member doping type the second vertical planar portion and the second outdiffusion layer have doping type as the bar member doping type, wherein the semiconductor device is a semiconductor diode with vertical junctions.

23. A semiconductor device of Claim 21 , wherein the first and second vertical planar portion and each of the first and second outdiffusion layer have opposite doping types to the bar member doping type, wherein the semiconductor device is two semiconductor diodes with vertical junctions connected against each other.

24. A semiconductor device of Claim 20, wherein each of the planar elements includes a first vertical planar portion of a doped semiconductor material extending along the respective vertical planar interface and a second vertical planar portion of a conductive material between the first vertical planar portion and the respective body, wherein each of the first vertical planar portion has a width ranging from 5nm to 30nm, each of the recess has a height to width ratio ranging from 3 : 1 to 20: 1 and the bar member has a width ranging from 20 to 300 nanometers, all recesses have approximately the same height and the third and the fourth recess has a distance between the each of the first and second recess ranging from 10 to 100 nanometers.

25. A semiconductor device of Claim 24, further comprising a first out-diffusion layer extending into the bar member along the first vertical interface, a second out-diffusion layer extending into the bar member along the second vertical interface, a third out-diffusion layer extending into the bar member along the third vertical interface and a fourth outdiffusion layer extending into the bar member along the fourth vertical interface.

26. The semiconductor device of Claim 25, further comprising a buried doped sub-base layer at the bar member bottom, a doped layer extending along the first vertical interface, wherein the first planar portion of the first and the second planar element have the opposite doping type to the bar member doping type, the doped layer, the first planar portion of the fourth and the third planar element and buried doped sub-base layer have the same doping type as the bar member, the bar member has a width ranging from 20 to 300 nanometers, the bottom of the third and the fourth outdiffusion layers is inside the buried doped sub-base layer or at least touching it and the semiconductor device is a bipolar transistor (BJT) having vertical junctions with the first outdiffusion layer as the emitter, the second planar element as the collector contact, the third planar element and the forth planar element as the base contacts.

27. The semiconductor device of Claim 26, further comprising a screening buried layer under the entire bar member bottom, wherein the screening buried layer top and the buried doped sub-base layer top are at the same level, the screening buried layer and the first planar portion of the fourth planar element have the opposite doping type to the bar member doping type, the buried doped sub-base layer does not extends under the fourth outdiffusion layer, the semiconductor device is a bipolar transistor (BJT) having vertical junctions with the first outdiffusion layer as the emitter, the second planar element as the collector contact, the third planar element as the base contact and the fourth planar element as the contact to the screening buried layer.

28. The semiconductor device of Claim 25, further comprising a screening buried layer at the entire bar member bottom, wherein the second planar element and the second outdiffusion layer are absent and the screening buried layer top is at the same level as the first outdiffusion layer bottom, and the semiconductor device is a single gate junction field effect transistor with the first planar element as the gate and the third and the fourth planar element as the contacts to the transistor channel.

29. The semiconductor device of Claim 25, further comprising a second bar member of the semiconductor material extending upwardly from the substrate and along the substrate and adjacent to the third dielectric body, a fifth planar element disposed in a fifth recess in the third dielectric body extending along the fourth vertical interface of the second bar member, a fifth outdiffusion layer extending in the second bar member along the fourth vertical interface of the second bar member, the bar members have the same height, a screening buried layer positioned at the bottom of the bar members, wherein the screening buried layer, the first planar portion of the fifth planar element and the fifth outdiffusion layer have a different doping type than the bar members and the screening buried layer top is at the same level or higher the fifth outdiffusion layer bottom and fifth planar element is the contact to the screening buried layer.

30. The semiconductor device of Claim 29, wherein the first planar portion of the first and the second planar element and the first and the second outdiffusion layer have a different doping type than the bar member, the first planar portion of the third and the fourth planar element have the same doping type as the bar member, the screening buried layer positioned under the first and the second outdiffusion layers at the distance not less than 10 nanometers, the bar member has a width ranging from 20 to 300 nanometers, and the semiconductor device is a double gate vertical junction field effect transistor (JFET) with the first and the second planar element as the gates, the third and the fourth planar element as the contacts to the transistor channel.

31. The semiconductor device of Claim 30, further comprising a diffusion layer extending into the bar member along the first vertical interface, wherein the diffusion layer has the width ranging from 10 to 100 nanometers and a doping type the same as to the bar member doping type, and the semiconductor device is a double gate vertical junction field effect transistor (JFET).

32. The semiconductor device of Claim 29, further comprising a doped layer extending along the first vertical interface, a buried doped sub-base layer extending into and under the entire bar member at the bar member bottom, wherein the top of the screening buried layer and the top of the buried doped sub-base layer are at the same position, the first planar portion of the first and the second planar element has the opposite doping type to the bar member doping type, the doped layer, the first planar portion of the fourth and the third planar element, and the buried doped sub-base layer have the same doping type as the bar member, the bar member has a width ranging from 20 to 300 nanometers, the bottom of the third and the fourth outdiffusion layers is inside the buried doped sub-base layer or at least touching it and the semiconductor device is a bipolar transistor (BJT) having vertical junctions with the first outdiffusion layer as the emitter, the second planar element as the collector contact, the third and the forth planar element as the base contacts.

33. The semiconductor device of Claim 29, further comprising a second base diffusion layer extending into the bar member and into the screening buried layer and adjacent to the second outdiffusion layer, wherein the third planar element is absent, the second base diffusion layer and the first portion of the first planar element has a doping type opposite the bar member doping types, the first portion of the second and fourth planar elements and the second and fourth outdiffusion layers has the same doping type as the bar member doping type, the bar member has the width ranging from 50 to 300 nanometers, and the semiconductor device is a vertical junction thyristor with the first outdiffusion layer as emitter, the second planar element as the collector contact, the fourth planar element as the first base contact and the fifth planar element as the second base contact.

34. The semiconductor device of Claim 20, wherein the semiconductor material is a silicon-on-insulator substrate.

35. The semiconductor device of Claim 1 , wherein the bar member has a top surface, further comprising a dielectric cap layer on the top surface of the bar member.

36. A method for forming a semiconductor device in a substrate of a

semiconductor material, comprising the steps of anisotropic etching first and second spaced- apart trenches in the substrate to form a bar member of the semiconductor material extending upwardly from the substrate and along the substrate between the first and second trenches, depositing a first body of a dielectric material in the first trench to create a first vertical planar interface between the first body and the bar member that extends upwardly from and along the substrate, depositing a second body of a dielectric material in the second trench to create a second vertical planar interface between the second body and the bar member that extends upwardly from and along the substrate, the first vertical planar interface extending parallel to the second vertical planar interface, anisotropic etching a first recess extending along the first vertical planar interface, anisotropic etching a second recess extending along the second vertical planar interface, depositing at least one material in the first recess to create a first planar element that extends along the first vertical planar interface and depositing at least one material in the second recess to create a second planar element that extends along the second vertical planar interface.

37. The method of Claim 36, wherein the first planar element is the same as the second planar element.

38. The method of Claim 36, wherein the step of anisotropic etching the first recess extending along the first vertical interface includes anisotropic etching a first recess in the bar member extending along the first vertical interface and wherein the first planar element is disposed in a bar member, and wherein the step of anisotropic etching the second recess extending along the second vertical interface includes anisotropic etching a second recess in the bar member extending along the second vertical interface and wherein the second planar element is disposed in a bar member.

39. The method of Claim 38, wherein the first and second planar elements are each gate electrodes and further comprising the step of forming first and second gate dielectrics between the respective gate electrodes and the bar member.

40. The method of Claim 38, wherein the first and second planar elements are each a doped semiconductor material.

41. The method of Claim 36, wherein the step of anisotropic etching a first recess extending along the first vertical planar interface includes anisotropic etching a first recess in the first body extending along the first vertical planar interface and wherein the first planar element is disposed in the first recess, and wherein the step of anisotropic etching a second recess extending along the second vertical planar interface includes anisotropic etching a second recess in the second body extending along the second vertical planar interface and wherein the second planar element is disposed in a second body.

42. The method of Claim 41, wherein the first and second planar elements are each a metal/semiconductor stack.

43. The method of Claim 36, wherein the semiconductor material is a silicon-on- insulator substrate.

44. The method of Claim 36, wherein the bar member has a top surface and a first border area on the top surface adjacent the first vertical planar interface and an opposite second border area on the top surface spaced apart from the first border area and adjacent the second vertical planar interface and a central area between the first and second border areas, further comprising the steps of depositing a first dielectric material over the first and second bodies, depositing a second dielectric material over the first and second border areas and depositing a third dielectric material over the central area, wherein the first, second and third dielectric materials are different from each other, wherein the step of anisotropic etching the first recess extending along the first vertical planar interface includes removing one of the first dielectric material over at least a portion of the first border area and the second dielectric material over at least a portion of the first body and then anisotropic etching the first recess extending along the first vertical planar interface and wherein the step of anisotropic etching the second recess extending along the second vertical planar interface includes removing one of the first dielectric material over at least a portion of the second border area and the second dielectric material over at least a portion of the second body and then anisotropic etching the second recess extending along the second vertical planar interface.

45. A method for forming a semiconductor device in a substrate of a

semiconductor material, comprising the steps of anisotropic etching first and second spaced- apart trenches and third and fourth spaced-apart trenches orthogonal to and connected to first and second spaced-apart trenches in the substrate using a hard mask dielectric with spacers of a second dielectric material on vertical sides of the hard mask dielectric to form a bar member of the semiconductor material extending upwardly from the substrate and along the substrate between the trenches, depositing a dielectric material into the trenches to form the first, the second, the third and the fourth dielectric body in respective trenches to create the first, the second, the third and the fourth vertical planar interfaces between the bar member and the first, the second, the third and the fourth dielectric body respectively, the first vertical planar interface extending parallel to the second vertical planar interface, the third vertical planar interface extending parallel to the fourth vertical planar interface, anisotropic etching a first recess extending along the first vertical planar interface, anisotropic etching a second recess extending along the second vertical planar interface, depositing at least one material in the first recess to create a first planar element that extends along the first vertical planar interface and depositing at least one material in the second recess to create a second planar element that extends along the second vertical planar interface.

46. The method of Claim 45, wherein the first planar element is the same as the second planar element.

47. The method of Claim 45, wherein the step of anisotropic etching the first recess extending along the first vertical interface includes selective anisotropic etching of the spacer over at least a portion of the bar member and anisotropic etching a first recess in the bar member extending along the first vertical interface and wherein the first planar element is disposed in a bar member, and wherein the step of anisotropic etching the second recess extending along the second vertical interface includes selective anisotropic etching of the spacer over at least a portion of the bar member and anisotropic etching a second recess in the bar member extending along the second vertical interface and wherein the second planar element is disposed in a bar member.

48. The method of Claim 47, wherein the first and second planar elements are each gate electrodes and further comprising the step of forming first and second gate dielectrics between the respective gate electrodes and the bar member.

49. The method of Claim 47, wherein the first and second planar elements are each a doped semiconductor material.

50. The method of Claim 45, wherein the step of anisotropic etching a first recess extending along the first vertical planar interface includes anisotropic etching a first recess in the first body extending along the first vertical planar interface and wherein the first planar element is disposed in the first recess, and wherein the step of anisotropic etching a second recess extending along the second vertical planar interface includes anisotropic etching a second recess in the second body extending along the second vertical planar interface and wherein the second planar element is disposed in a second body.

51. The method of Claim 50 further comprising a selective anisotropic etching of the spacer over at least a portion of the bar member adjacent to the first recess and anisotropic etching a recess in the bar member extending along the first vertical interface and adjacent to the first planar member wherein the third planar semiconductor element is disposed in the recess in the bar member, the semiconductor of the third planar semiconductor element is different of the bar member semiconductor.

52. The method of Claim 50, wherein the first and second planar elements are each a metal/semiconductor stack, further comprising an anneal to create a first and a second outdiffusion layers extending into the bar member.

53. The method of Claim 52, further comprising an ion implantation before the recesses formation using the photoresist mask to form a buried screen layer at the bar member bottom, the step of anisotropic etching of a third recess extending along the third vertical planar interface includes anisotropic etching a third recess in the third body extending along the third vertical planar interface and wherein the third planar element is disposed in the third recess, and the step of anisotropic etching a fourth recess extending along the fourth vertical planar interface includes anisotropic etching a fourth recess in the fourth body extending along the fourth vertical planar interface and wherein the fourth planar element is disposed in a fourth body, wherein the third and fourth planar elements are each a metal/semiconductor stack, further comprising an anneal to create a third and a fourth outdiffusion layers extending into the bar member on 5 to 20 nanometers.

54. The method of Claim 53, further comprising an ion implantation before the recesses formation using the photoresist mask to form a buried sub-base layer at the bar member bottom.

55. The method of Claim 54, wherein before the second planar element deposition a deposition of an appropriate Silicate Glass into the second recess is done, followed by a drive-in anneal, followed by removing the Silicate Glass.

56. The method of Claim 45, wherein the semiconductor material is a silicon-on- insulator substrate.

57. The method of Claim 45, wherein the bar member has a top surface and a first border area on the top surface adjacent the first vertical planar interface and an opposite second border area on the top surface spaced apart from the first border area and adjacent the second vertical planar interface and a central area between the first and second border areas, further comprising the steps of depositing a first dielectric material over the first and second bodies, depositing a second dielectric material over the first and second border areas and depositing a third dielectric material over the central area, wherein the first, second and third dielectric materials are different from each other, wherein the step of anisotropic etching the first recess extending along the first vertical planar interface includes removing one of the first dielectric material over at least a portion of the first border area and the second dielectric material over at least a portion of the first body and then anisotropic etching the first recess extending along the first vertical planar interface and wherein the step of anisotropic etching the second recess extending along the second vertical planar interface includes removing one of the first dielectric material over at least a portion of the second border area and the second dielectric material over at least a portion of the second body and then anisotropic etching the second recess extending along the second vertical planar interface.