WO2016172862A1 - 一种内存管理方法、设备和系统 - Google Patents

一种内存管理方法、设备和系统 Download PDF

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Publication number
WO2016172862A1
WO2016172862A1 PCT/CN2015/077722 CN2015077722W WO2016172862A1 WO 2016172862 A1 WO2016172862 A1 WO 2016172862A1 CN 2015077722 W CN2015077722 W CN 2015077722W WO 2016172862 A1 WO2016172862 A1 WO 2016172862A1
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Prior art keywords
memory
nodes
registered
response message
area
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PCT/CN2015/077722
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English (en)
French (fr)
Inventor
刘洪宽
沈伟锋
张丰伟
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华为技术有限公司
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Priority to PCT/CN2015/077722 priority Critical patent/WO2016172862A1/zh
Priority to CN201580001237.4A priority patent/CN107003904A/zh
Publication of WO2016172862A1 publication Critical patent/WO2016172862A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]

Definitions

  • the embodiments of the present invention relate to the field of computers, and in particular, to a memory management method, device, and system.
  • RDMA Remote Direct Memory Access
  • RDMA solves the rapid interaction of existing data in units of computing devices.
  • the memory resources of computing devices are separated from computing devices to form a memory resource pool and RDMA data.
  • the interaction is also extended from the data interaction of the computing device/computing device mode to the data interaction between the computing device and the separate memory resources, and the resulting changes bring new demands to RDMA. That is, when the memory resource of the computing device is separated from the computing device, how to implement memory management of the memory resource when the computing device registers the memory region with the memory resource.
  • the embodiments of the present invention provide a remote direct data access memory management method, device, and system.
  • the computing device is separated from the memory resources, the memory resource global management function is implemented.
  • an embodiment of the present invention provides a memory management method, where a memory controller provides a unified memory resource interface, including:
  • the memory controller receives a memory registration request by using the unified memory resource interface, where the memory registration request carries a size of the registered memory area;
  • the memory controller sends a memory application message to each of the M memory nodes, where each memory application message carries the required physical memory size;
  • the memory controller receives a memory application response message sent from each of the M memory nodes, and each memory application response message carries the allocated memory information;
  • the memory controller generates information of the registered memory area according to the application response message of the M memory nodes, and sends a memory registration response message by using the unified memory resource interface, where the memory registration response message carries the registered memory area Information.
  • the memory controller maintains a remaining memory size of each of the plurality of memory nodes
  • the memory controller determines, from the plurality of memory nodes, M memory nodes that provide physical memory for the registered memory area, and a physical memory size that each of the M memory nodes needs to provide: Determining, by the memory controller, the M memory nodes and each of the M memory nodes according to a remaining memory size and a registered memory area size of each of the plurality of memory nodes maintained by the memory controller The amount of physical memory provided.
  • the allocated memory information carried by the memory application response message includes physical address information of the allocated memory
  • the method further includes: the memory controller assigning a virtual address to the registered memory area according to the size of the registered memory area, and establishing a virtual address of the registered memory area and the allocation of the M memory nodes The mapping relationship between the physical address information of the memory.
  • the memory registration response message includes a virtual address of the registered memory area and the allocation of the M memory nodes The mapping relationship between the physical address information of the memory.
  • the memory registration response message includes virtual address information of the registered memory area.
  • the memory application response message further includes queue pair information, and the queue pair and the memory allocated for the memory application message Association
  • the memory registration response message further includes each of the M memory nodes as a The memory-associated queue pair information allocated by the registered memory area.
  • the memory registration request further includes a permission identifier, where the permission identifier is used to represent an operation type allowed in the registered memory region ;
  • the memory application message further includes the permission identifier.
  • the method further includes: the memory controller generates key information, and sends the key information to the M a memory node, after receiving a key confirmation response message of each of the M memory nodes, sending the key to a computing device applying for the registered memory area, where the key information is used for characterization Access to the M memory nodes.
  • an embodiment of the present invention provides a memory management device, which provides a unified memory resource interface, including: a processor, a memory, a bus, and a communication interface;
  • the memory is for storing computer execution instructions
  • the processor is coupled to the memory via the bus, and when the computing device is running, the processor executes the computer-executed instructions stored by the memory to enable
  • the memory management device performs a method of performing the first aspect or any of the possible implementations of the first aspect.
  • the embodiment of the present invention provides a memory management device, which provides a unified memory resource interface and provides a unified memory resource interface, including:
  • a receiving unit configured to receive a memory registration request by using the unified memory resource interface, where the memory registration request carries a size of a registered memory area
  • a processing unit configured to determine, from the plurality of memory nodes, M memory nodes that provide physical memory for the registered memory area, and a physical memory size that each of the M memory nodes needs to provide, where , M is a natural number greater than 0;
  • a sending unit configured to send a memory application message to each of the M memory nodes, where each memory application message carries the required physical memory size
  • the receiving unit is further configured to receive a memory application response message sent by each of the M memory nodes, where each memory application response message carries the allocated memory information;
  • the sending unit is further configured to generate information about the registered memory area according to the application response message of the M memory nodes, and send a memory registration response message by using the unified memory resource interface, where the memory registration response message carries the registration Information about the memory area.
  • the processing unit is further used for maintenance The remaining memory size of each of the plurality of memory nodes;
  • the processing unit is configured to determine, from the plurality of memory nodes, M memory nodes that provide physical memory for the registered memory area, and a physical memory size that each of the M memory nodes needs to provide, including The processing unit determines, according to the remaining memory size and the size of the registered memory area of each of the plurality of memory nodes maintained by the processing unit, the M memory nodes, and each of the M memory nodes The amount of physical memory provided.
  • the allocated memory information carried by the memory application response message includes physical address information of the allocated memory
  • the processing unit is further configured to: allocate a virtual address to the registered memory area according to the size of the registered memory area, and establish a virtual address of the registered memory area and the allocated memory of the M memory nodes.
  • the mapping relationship between physical address information is further configured to: allocate a virtual address to the registered memory area according to the size of the registered memory area, and establish a virtual address of the registered memory area and the allocated memory of the M memory nodes. The mapping relationship between physical address information.
  • the memory registration response message includes a virtual address of the registered memory area and the allocation of the M memory nodes The mapping relationship between the physical address information of the memory.
  • the memory registration response message includes virtual address information of the registered memory area.
  • the memory application response message further includes queue pair information, and the queue pair and the memory allocated for the memory application message Association
  • the memory registration response message further includes a queue pair information of a memory association allocated by each of the M memory nodes for the registered memory area.
  • the memory registration request further includes a permission identifier, where the permission identifier is used to represent an operation type permitted by the registered memory region ;
  • the memory application message further includes the permission identifier.
  • the processing unit is further configured to: generate key information, and send the key information to the M a memory node, after receiving a key confirmation response message of each of the M memory nodes, sending the key to a computing device applying for the registered memory area, where the key information is used for characterization Access to the M memory nodes.
  • an embodiment of the present invention provides a memory management system, where a memory management device provides a unified memory resource interface, including: a computing node, multiple memory nodes, and any of the third or third aspects. Making the memory management device described in the implementation manner,
  • the computing node is configured to send a memory registration request to the memory management device by using the unified memory resource interface, where the memory registration request carries a size of a registered memory area, and receives the source through the unified memory resource interface. And a memory registration response message of the memory management device, where the memory registration response message carries information of the registered memory area.
  • the plurality of memory nodes are configured to receive a memory application message of the memory management device, allocate memory for the registered memory area according to the memory application message, and send a memory application response message to the memory management device.
  • the memory resources are provided to the computing resources in the form of a memory resource pool, and the memory resource pool includes multiple memory nodes, which can implement the memory resources.
  • the unified management of multiple memory nodes in the pool realizes the function of globally managing RDMA memory resources, so that the range of registered memory areas can span memory nodes, improving the efficiency of memory utilization, and making memory management more flexible and efficient.
  • FIG. 1 is a block diagram of an exemplary networked environment in which computing devices share data via RDMA;
  • FIG. 2 is a schematic diagram of an exemplary computing device of the present invention
  • FIG. 3 is a schematic diagram of an application scenario of an RDMA memory management method
  • FIG. 5 is a schematic diagram of an application scenario of a memory management method according to an embodiment of the invention.
  • FIG. 6 is a signaling diagram of a memory management method according to an embodiment of the invention.
  • FIG. 7 is an exemplary flowchart of a memory management method according to an embodiment of the invention.
  • FIG. 8 is a schematic diagram showing the logical structure of a memory management device according to an embodiment of the invention.
  • FIG. 9 is a schematic structural diagram of a hardware of a computing device according to an embodiment of the invention.
  • FIG. 1 illustrates an RDMA networking environment 100 in which network 102 is coupled to four computing devices 104.
  • Computing devices 104 use their network 102 connections to perform mutual RDMA transfers.
  • Network 102 can be the Internet, intranets, local area networks (LANs), wide area networks (WLANs), storage area networks (SANs), etc., or a combination of the above.
  • FIG. 1 is only intended to introduce RDMA participants and their interrelationships for the purposes of the following discussion.
  • the depicted RDMA environment 100 is greatly simplified. Since some aspects of RDMA are well known in the art, these aspects, such as authentication schemes and security, are not discussed herein.
  • the complexity involved in setting up and running a successful RDMA environment 100 is well known to those working in the art.
  • the computing device 104 of Figure 1 can be of any architecture.
  • 2 is a block diagram generally showing an exemplary computer system supporting an embodiment of the present invention.
  • the computer system of Figure 2 is merely an example and is not intended to suggest any limitation as to the scope of use or functionality of the embodiments of the invention. Neither should computing device 104 be interpreted as having any dependency or requirement relating to any one or combination of the components shown in FIG. 2.
  • Embodiments of the invention may operate in conjunction with many other general purpose or special purpose computing environments or configurations.
  • computing device 104 typically includes at least one processor 200 and memory 202.
  • Memory 202 can be used by computing device 104 as a memory resource, and can be volatile (such as RAM), non-volatile (such as ROM or flash), or some combination of the two.
  • This most basic configuration is illustrated in Figure 2 by dashed line 204.
  • Computing device 104 can have additional features and functionality.
  • FIG. 2 it may include storage (removable and non-removable) of peripherals including, but not limited to, magnetic disks and magnetic tapes, as well as optical disks and optical tapes.
  • storage is illustrated in FIG. 2 by removable storage 206 and non-removable storage 208.
  • Computer storage media includes both volatile and nonvolatile, removable and non-removable, implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. medium.
  • Memory 202, removable storage 206 and non-removable storage 208 are all examples of computer storage media.
  • Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory, other memory technologies, CD-ROMs, digital versatile discs, other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage, other magnetic storage devices, and Any other medium that can be used to store the required information and be accessible by computing device 104. Any such computer storage media may be part of computing device 104.
  • Computing device 104 may also include a communication channel 210 that allows it to communicate with other devices, including devices on network 102.
  • Communication channel 210 is an example of a communication medium.
  • Communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal or other transport mechanism, such as a carrier wave, and includes any information delivery media.
  • communication media includes optical media, wired media such as wired networks and linear connections, and wireless media such as sound, RF, infrared, and other wireless media.
  • computer readable medium includes both storage media and communication media.
  • Computing device 104 may also have input device 212 such as a touch sensitive display, a hardware keyboard, a mouse, a voice input device, and the like.
  • Output device 214 includes the device itself, such as touch sensitive display screens, speakers, printers, and rendering modules (often referred to as "adapters") used to drive these devices. All of these devices are well known in the art and therefore need not be discussed in detail herein.
  • Computing device 104 has a power source 216.
  • the computing resources of the computing device 104 are separated from the memory resources, and the computing device 104 is divided into computing nodes and memory resources.
  • the memory resources include memory 202 and a memory controller for controlling operations such as data access by memory 202; the computing nodes include other features and functions of computing device 104.
  • the computing node further includes other memory resources of the computing device 104 other than the separated memory resources. The computing node and the separated memory resources are connected through the network 102.
  • the computing resource of the computing device 104 is decoupled from the memory resource, that is, the computing resource is separated from the memory resource, the computing resource exists in the form of a computing resource pool, the memory resource exists in the form of a memory resource pool, and the computing resource pool includes at least one A compute node, the memory resource pool contains at least one memory node.
  • the compute node contains the processor 200 and other components necessary for computation and communication.
  • the memory node contains the memory 202 and other components necessary for storage and communication, such as the access controller.
  • FIG. 3 is a schematic diagram of a logical structure of an application scenario of a remote direct data access RDMA method.
  • the system includes a first computing device and a second computing device, where the first computing device and the second computing device are as shown in FIG.
  • the signaling diagram thereof is as shown in FIG. 4, and the execution steps are:
  • the second computing device sends an RDMA operation request to the first computing device over the network 102.
  • the RDMA operation request carries an RDMA operation type requested by the second computing device to the first computing device, and a memory size required for the RDMA operation.
  • the first computing device performs a memory application in the local memory according to the RDMA operation request.
  • a queue pair is also generated when the memory application is performed, and is bound to a memory area (MR).
  • MR is a general term for the registered memory area to be applied.
  • MR is presented as a virtual address, which is a mapping of physical addresses (page mode or block mode) at the application layer.
  • the QP includes a Send Queue (SQ) and a Receive Queue (RQ).
  • SQ is used for a send operation, storing instructions that cause data to be transferred between a memory device of one computing device and a memory device of another computing resource; RQ is used for receiving operations, saving information about data received from another computing device Where is the instruction.
  • the computing device submits a work request, which is a Work Queue Element (WQE) to be placed in the appropriate work queue.
  • WQE Work Queue Element
  • the channel adapters perform WQE so that they are placed in the work queue.
  • the operating system checks the operations allowed in the registered memory area during the memory access.
  • the requested memory has remote keywords and local keywords, which are used to control the access rights of the memory.
  • the local keywords are used for the local RDMA network card.
  • the RDMA Network Interface Card (RNIC) hardware interface adapter accesses local memory, and the remote key is used by the remote RNIC hardware interface adapter to access system memory.
  • RNIC RDMA Network Interface Card
  • the first computing device sends the requested registration memory area message to the second computing device.
  • the RDMA registration memory area message includes a virtual address (VA) and a memory key (Remote Key, R_KEY).
  • VA virtual address
  • R_KEY Remote Key
  • the virtual address VA represents a virtual address of the storage unit for accepting the RDMA operation
  • the memory key R_KEY is used to represent the right to access the first memory, and is used to perform virtual address to the first memory physics in combination with the virtual real address translation table. The conversion of the address. .
  • the second computing device performs an RDMA operation on the first computing device.
  • an RDMA memory application based on the first computing device 104 and the second computing device 104 can be implemented.
  • the RDMA memory application described in FIG. 4 is performed point-to-point, and is only applicable to a memory application when an RDMA operation is required between two computing devices.
  • the requested memory is limited to the internal of the computing device, that is, the applied memory cannot be multi-crossed.
  • Memory nodes especially in the architecture of computing resources and memory resources decoupling of computing devices, cannot achieve unified management of memory.
  • the computing resources of the computing device are separated from the memory resources, the memory resources exist in the form of a memory resource pool.
  • the memory resource pool contains multiple memory nodes. Different MRs need to be created between the points and multiple points, so that the same process needs to be maintained. MR, and physical memory can not be maximized, resulting in the node memory can not be optimally utilized.
  • FIG. 5 is a schematic diagram of an application scenario of a memory management method according to an embodiment of the present invention.
  • the computing resources of the computing device 104 are separated from the memory resources, and are divided into a computing node 502 and a memory node 506, that is, a computing device.
  • the decoupling of resources and memory resources is no longer physically integrated on a computing device, but provides computing nodes and memory nodes to computing devices in the form of computing resource pools and memory resource pools.
  • Computing nodes 502 and memory nodes 506 pass through the network. 102, PCIE bus or message bus and other forms of connection.
  • the memory resources of the computing device are provided to the computing node 502 in the form of a memory resource pool 510, which includes N memory nodes, where N is a natural number greater than zero.
  • a memory resource pool 510 which includes N memory nodes, where N is a natural number greater than zero.
  • the calculation and the memory are no longer a strongly coupled relationship, the computing resources and the memory resources are divided into different nodes, and the computing node 502 can apply for the resources of the memory resource pool 510 without being limited.
  • a memory node Inside a memory node.
  • the computing node 502 removes the remaining portion of the memory resource for the computing device 104, and the memory resource of the computing node 502 is decoupled from the computing node 502, that is, the memory resource of the computing node 502 is separated from the computing node 502 by the memory resource pool 510.
  • the form provides memory resources to compute node 502.
  • the computing node 502 is a computing device 104, and part of the memory resource and the computing node 502 is decoupled, that is, a portion of the memory resources of the compute node 502 is separated from the compute node 502 and provided to the compute node 502 in the form of a memory resource pool 510.
  • computing node 502 is the node responsible for computing processing operations for computing device 104, including processor 200 and other components necessary for computation and communication.
  • the computing node 502 is a computing resource pool that includes a plurality of processors 200 and other components necessary for computing and communication.
  • the memory controller 504 is a management device for performing unified memory management on the memory node 506 in the memory resource pool 510.
  • the memory controller 504 is responsible for unified management and allocation of N memory nodes 506 inside the memory resource pool 510.
  • the system memory address is divided into a virtual address and a physical address.
  • the user layer sees the virtual address, and the physical address is required when processing on the memory node 506, and the virtual address to physical address conversion of the memory node 506 is completed on the memory controller 504. .
  • the memory controller 504 stores the memory usage of the entire memory resource pool 510. That is, the memory controller 504 knows which memory is used on the N memory nodes 506, and which memory is idle, so that the memory controller 504 can be based on the user. Apply memory length to allocate memory reasonably in the memory node.
  • the memory controller 504 uniformly addresses the N memory nodes in the memory resource pool 510, and the virtual addresses of the N memory nodes in the memory resource pool 510 are uniformly managed by the memory controller 504.
  • the memory controller 508 is deployed on the memory node 506 and is responsible for the access control of the memory node 506 and the instructions of the memory controller 504.
  • the memory access authority control table is set on the memory controller 508.
  • the memory access control table is first searched, and the physical memory is actually operated after the permission is met.
  • the memory controller 504 provides a unified memory resource interface.
  • the signaling diagram is as shown in FIG. 6, and the steps are as follows:
  • the memory controller 504 receives and receives a memory registration request from the computing node 502 through a unified memory resource interface, where the memory registration request carries a size of the registered memory area.
  • the memory application request further includes a process identifier.
  • the memory controller 504 allocates a virtual address to the registered memory area according to the process identification and the size of the registered memory area requested by the memory registration request.
  • the memory registration request further includes a permission identifier, where the permission identifier is used to represent an operation type allowed by the registered memory region.
  • the operation type includes at least one of the following: local read, local write, remote read, remote write, atomic operation, or binding.
  • the memory controller 504 determines, from the plurality of memory nodes 506, M memory nodes 506 that provide physical memory for the registered memory area, and each of the M memory nodes 506 needs to provide The physical memory size, where M is a natural number greater than zero.
  • the memory controller 504 maintains a remaining memory size of each of the plurality of memory nodes 506; the memory controller 504 determines from the plurality of memory nodes 506 to provide the registered memory area.
  • the M memory nodes 506 of the physical memory and the physical memory size that each of the M memory nodes 506 need to provide respectively include: the memory controller 504 is configured according to the plurality of memory nodes 506 maintained by itself.
  • the remaining memory size of each node and the size of the registered memory area determine the physical memory size of the M memory nodes 506 and each of the M memory nodes 506.
  • the memory controller 504 determines, according to the memory space size requested by the memory registration request and the physical memory usage of the N memory nodes 506 in the memory resource pool 510, M memory nodes that provide physical memory for the registered memory area. 506, and a physical memory size provided by each of the M memory nodes 506.
  • the memory controller 504 sends a memory application message to each of the M memory nodes 506, where each memory application message carries the physical memory size that needs to be provided.
  • the memory application message further includes a permission identifier, where the permission identifier is used to represent an operation type allowed by the registered memory region.
  • the type of operation includes at least one of: local read, local write, remote read, remote write, atomic operation, or binding.
  • the memory application message further carries a process identifier
  • the memory controller 508 allocates a physical memory space according to the size of the memory space requested by the received memory application message, and identifies the process identifier. Corresponding to the assigned physical memory address, it is logged to the memory management permission table.
  • the memory controller 508 also creates a QP on the memory node 506 and binds to the allocated physical memory space.
  • the memory controller 504 receives the memory application response message sent from each of the M memory nodes 506, and each memory application response message carries the memory information allocated by the corresponding memory node 506.
  • the memory application response message includes 506 physical address information of a memory allocated for the memory application message.
  • the memory controller 504 allocates a virtual address to the registered memory area according to the size of the registered memory area, and establishes a virtual address of the registered memory area and the allocated memory of the M memory nodes 506.
  • the mapping relationship between physical address information is not limited to the mapping relationship between physical address information.
  • the memory application response message further includes queue pair information, and the queue is associated with the memory allocated by the associated memory node 506 for the memory application message.
  • the memory controller 504 establishes a mapping relationship between the registered memory area and a queue pair QP associated with the memory allocated by the M memory nodes 506 for the registered memory area.
  • the memory controller 504 also generates a queue team QP, which is associated with the registered memory area.
  • the memory controller 504 generates information about the registered memory area according to the application response message of the M memory nodes 506, and sends a memory registration response message to the computing node 502 through the unified memory resource interface, where the memory registration response message is sent. Carrying information about the registered memory area.
  • the memory registration response message includes a mapping relationship between a virtual address of the registered memory area and physical address information of the allocated memory of the M memory nodes 506.
  • the memory registration response message includes virtual address information of the registered memory area.
  • the memory registration response message further includes a memory-associated queue pair QP information allocated by each of the M memory nodes 506 for the registered memory area.
  • the memory registration response message further includes queue queue QP information associated with the registered memory area.
  • the memory controller 504 further generates key information, and sends the key information to the M memory nodes 506, where each memory node 506 of the M memory nodes 506 is received. After the key acknowledgement response message, the key is sent to a computing device requesting the registered memory area, the key information being used to characterize access to the M memory nodes 506.
  • the memory resources are provided to the computing resources in the form of a memory resource pool, and the memory resource pool includes multiple memory nodes, which can implement the memory.
  • the unified management of multiple memory nodes in the resource pool realizes the function of globally managing memory resources, so that the range of registered memory areas can span memory nodes, improving the efficiency of memory utilization, and making memory management more flexible and efficient.
  • FIG. 7 is an exemplary flow diagram of a memory management method 700 in accordance with an embodiment of the present invention.
  • the memory resources of the computing device are separated from the memory resources, the memory resources of the computing device are provided to the computing resources in the form of a memory resource pool, where the memory resource pool includes N memory nodes, where N is a natural number greater than 0.
  • the method 700 implements the function of computing resources to perform RDMA memory registration in a memory resource pool, so that memory registration is no longer limited to a certain memory node.
  • the execution body of method 700 can be an RDMA memory controller of a memory resource pool.
  • the memory controller provides a unified memory resource interface. As shown in FIG. 7, the method 700 includes:
  • the memory controller receives a memory registration request by using the unified memory resource interface, where the memory registration request carries a size of the registered memory area.
  • the memory controller determines, from the plurality of memory nodes, M memory nodes that provide physical memory for the registered memory area, and physical memory sizes that each of the M memory nodes needs to provide respectively.
  • M is a natural number greater than zero.
  • S706 The memory controller sends a memory application message to each of the M memory nodes, where each memory application message carries the physical memory size that needs to be provided.
  • S708 The memory controller receives a memory application response message sent from each of the M memory nodes, where each memory application response message carries the allocated memory information.
  • the memory controller generates information about a registered memory area according to an application response message of the M memory nodes, and sends a memory registration response through the unified memory resource interface.
  • the memory registration response message carries information of the registered memory area. .
  • the memory controller maintains a remaining memory size of each of the plurality of memory nodes; and the memory controller determines, from the plurality of memory nodes, an M that provides physical memory for the registered memory area.
  • the memory node, and the physical memory size that each of the M memory nodes need to provide respectively includes: the memory controller according to the remaining memory size and registration of each of the plurality of memory nodes maintained by the memory controller
  • the size of the memory area determines the M memory nodes and the amount of physical memory that each of the M memory nodes needs to provide.
  • the allocated memory information carried by the memory application response message includes physical address information of the allocated memory.
  • the method 700 further includes: the memory controller is configured according to the size of the registered memory area.
  • the registration memory area allocates a virtual address, and establishes a mapping relationship between the virtual address of the registered memory area and the physical address information of the allocated memory of the M memory nodes.
  • the memory registration response message includes a mapping relationship between a virtual address of the registered memory area and physical address information of the allocated memory of the M memory nodes.
  • the memory registration response message includes virtual address information of the registered memory area.
  • the memory application response message further includes queue pair information, where the queue pair is associated with a memory allocated for the memory request message; the memory registration response message further includes each memory of the M memory nodes.
  • the memory registration request further includes a permission identifier, where the permission identifier is used to represent an operation type allowed by the registration memory area; and the memory application message further includes the permission identifier.
  • the operation type includes at least one of the following: local read, local write, remote read, remote write, atomic operation, or binding.
  • the method 700 further includes: the memory controller generates key information, and sends the key information to the M memory nodes, where each of the M memory nodes is received After the key acknowledgement response message, the key is sent to a computing device that requests the registered memory area, and the key information is used to characterize the access to the M memory nodes. .
  • the memory controller is further configured to generate a queue queue QP, and establish an association relationship between the queue queue QP and the registered memory area; the memory registration response message further includes the queue queue information.
  • the memory application response message further includes a remote memory key (Remote Key, R_KEY), the remote memory key R_KEY is used to characterize the access to the memory application response message, and is used to jointly determine the physical address of the storage unit used by the memory node to receive the operation in conjunction with the virtual address.
  • the memory registration response message further includes each of the M memory nodes being a remote memory key R_KEY corresponding to the registered memory area.
  • the memory application request further includes a process identifier, and the memory controller of the memory resource pool allocates a virtual address to the registered memory area according to the process identifier and the size of the registered memory area requested by the memory registration request.
  • the memory controller of the memory resource pool determines, according to the memory space size requested by the memory registration request and the physical memory usage of the N memory nodes in the memory resource pool, the M memory nodes that provide physical memory for the registered memory area. And the amount of physical memory provided by each of the M memory nodes.
  • the memory resources are provided to the computing resources in the form of a memory resource pool, and the memory resource pool includes multiple memory nodes, which can implement the memory.
  • the unified management of multiple memory nodes in the resource pool realizes the function of globally managing memory resources, so that the range of registered memory areas can span memory nodes, improving the efficiency of memory utilization, and making memory management more flexible and efficient.
  • FIG. 8 is a schematic diagram showing the logical structure of a memory management device 800 according to an embodiment of the invention.
  • the memory resources of the computing device are separated from the memory resources, the memory resources of the computing device are provided to the computing resources in the form of a memory resource pool, where the memory resource pool includes N memory nodes, where N is a natural number greater than 0.
  • the device 800 implements the function of computing resources to perform RDMA memory registration in the memory resource pool, so that the RDMA memory registration is no longer limited to a certain memory node.
  • method 800 includes:
  • the receiving unit 802 is configured to receive, by using the unified memory resource interface, a memory registration request, where the memory registration request carries a size of the registered memory area;
  • the processing unit 804 is configured to determine, from the plurality of memory nodes, M memory nodes that provide physical memory for the registered memory area, and a physical memory size that each of the M memory nodes needs to provide, Where M is a natural number greater than 0;
  • the sending unit 806 is configured to send a memory application message to each of the M memory nodes, where each memory application message carries the required physical memory size;
  • the receiving unit 802 is further configured to receive each memory node from the M memory nodes. a memory application response message sent separately, and each memory application response message carries the allocated memory information;
  • the sending unit 806 is further configured to generate information about the registered memory area according to the application response message of the M memory nodes, and send a memory registration response message by using the unified memory resource interface, where the memory registration response message carries the Register information about the memory area.
  • the processing unit 804 is configured to maintain a remaining memory size of each of the plurality of memory nodes, where the processing unit 804 is configured to determine, from the plurality of memory nodes, physical memory for the registered memory area.
  • the M memory nodes, and the physical memory size that each of the M memory nodes needs to provide respectively includes: the processing unit according to the remaining memory size of each of the plurality of memory nodes maintained by the processing unit Registering a memory area size, determining the M memory nodes, and the physical memory size that each of the M memory nodes needs to provide.
  • the allocated memory information carried by the memory application response message includes physical address information of the allocated memory; the processing unit 804 is further configured to: use the registered memory area according to the size of the registered memory area Allocating a virtual address, and establishing a mapping relationship between the virtual address of the registered memory area and the physical address information of the allocated memory of the M memory nodes.
  • the memory registration response message includes a mapping relationship between a virtual address of the registered memory area and physical address information of the allocated memory of the M memory nodes.
  • the memory registration response message includes virtual address information of the registered memory area.
  • the memory application response message further includes queue pair information, where the queue pair is associated with a memory allocated for the memory request message; the memory registration response message further includes each memory of the M memory nodes.
  • the memory registration request further includes a permission identifier, where the permission identifier is used to represent an operation type allowed by the registration memory area; and the memory application message further includes the permission identifier.
  • the operation type includes at least one of the following: local read, local write, remote read, remote write, atomic operation, or binding.
  • the processing unit 804 is further configured to: generate key information, and send the key information to the M memory nodes, where each memory node of the M memory nodes is received After the key confirmation response message, the key is sent to the computing device applying for the registered memory area, and the key information is used to characterize the access to the M memory nodes.
  • the memory application response message further includes a remote memory key (R_KEY), and the remote memory key R_KEY is used to represent the permission to access the memory application response message, and is used to combine the virtual address together. Determining the physical address of the memory location that the memory node is used to receive RDMA operations.
  • the memory registration response message further includes each of the M memory nodes being a remote memory key R_KEY corresponding to the registered memory area.
  • the processing unit 804 is further configured to generate a queue queue QP, and establish an association relationship between the queue queue QP and the registered memory area; the memory registration response message further includes the queue queue information.
  • the memory application request further includes a process identifier
  • the processing unit 804 allocates a virtual address to the registered memory area according to the process identifier and the size of the registered memory area requested by the memory registration request.
  • the processing unit 804 determines, according to the memory space size of the memory registration request request and the physical memory usage of the N memory nodes in the memory resource pool, M memory nodes that provide physical memory for the registered memory area, and the The amount of physical memory provided by each memory node in the M memory nodes.
  • the memory resources are provided to the computing resources in the form of a memory resource pool, and the memory resource pool includes multiple memory nodes, which can implement the memory.
  • the unified management of multiple memory nodes in the resource pool realizes the function of globally managing memory resources, so that the range of registered memory areas can span memory nodes, improving the efficiency of memory utilization, and making memory management more flexible and efficient.
  • FIG. 9 is a schematic diagram showing the hardware structure of a computing device device 900 according to an embodiment of the invention.
  • computing device 900 includes a processor 902, a memory 904, an input/output interface 906, a communication interface 908, and a bus 910.
  • the processor 902, the memory 904, the input/output interface 906, and the communication interface 908 implement a communication connection with each other through the bus 910.
  • the processor 902 can be a general-purpose central processing unit (CPU), a microprocessor, an application specific integrated circuit (ASIC), or one or more integrated circuits for executing related programs.
  • CPU central processing unit
  • ASIC application specific integrated circuit
  • the memory 904 can be a read only memory (ROM), a static memory device, a dynamic memory device, or a random access memory (RAM).
  • the memory 904 can store the operating system and other applications.
  • the program code for implementing the technical solution provided by the embodiment of the present invention is stored in the memory 904 and executed by the processor 902.
  • the input/output interface 906 is for receiving input data and information, and outputting data such as operation results.
  • Communication interface 908 enables communication between computing device 900 and other devices or communication networks using transceivers such as, but not limited to, transceivers.
  • Bus 910 can include a path for communicating information between various components of computing device 900, such as processor 902, memory 904, input/output interface 906, and communication interface 908.
  • computing device 900 shown in FIG. 9 only shows the processor 902, the memory 904, the input/output interface 906, the communication interface 908, and the bus 910, in a specific implementation, those skilled in the art It should be understood that computing device 900 also includes other devices necessary to achieve proper operation. Also, those skilled in the art will appreciate that computing device 900 may also include hardware devices that implement other additional functions, depending on the particular needs. Moreover, those skilled in the art will appreciate that computing device 900 may also only include the components necessary to implement embodiments of the present invention, and does not necessarily include all of the devices shown in FIG.
  • FIG. 9 and the foregoing description are applicable to various memory management devices and systems provided by the embodiments of the present invention, and are applicable to performing various memory management methods provided by the embodiments of the present invention.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the modules is only a logical function division, and may be implemented in another manner, for example, multiple modules or components may be combined or may be Integrate into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or module, and may be electrical, mechanical or otherwise.
  • the modules described as separate components may or may not be physically separated.
  • the components displayed as modules may or may not be physical modules, that is, may be located in one place, or may be distributed to multiple network modules. You can choose which one according to your actual needs. Some or all of the modules implement the objectives of the solution of the embodiment.
  • each functional module in each embodiment of the present invention may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module.
  • the above integrated modules can be implemented in the form of hardware or in the form of hardware plus software function modules.
  • the above-described integrated module implemented in the form of a software function module can be stored in a computer readable memory medium.
  • the software function module described above resides in a memory medium and includes instructions for causing a computer device (which may be a personal computer, server, or network device, etc.) to perform some of the steps of the methods described in various embodiments of the present invention.
  • the foregoing memory medium includes: a mobile hard disk, a read-only memory (English: Read-Only Memory, ROM for short), a random access memory (English: Random Access Memory, RAM), a magnetic disk or an optical disk, and the like.
  • the media for the memory program code includes: a mobile hard disk, a read-only memory (English: Read-Only Memory, ROM for short), a random access memory (English: Random Access Memory, RAM), a magnetic disk or an optical disk, and the like.
  • the media for the memory program code includes: a mobile hard disk, a read-only memory (English: Read-Only Memory, ROM for short

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Abstract

本发明实施例提供了一种内存管理方法、设备和系统，实现了全局管理内存资源的功能，使注册内存区域的范围可以跨内存节点，提高了内存利用的效率，并使内存管理更加灵活和高效。该方法包括：接收内存注册请求，其中携带要申请的注册内存区域的大小；确定为所述注册内存区域提供物理内存的M个内存节点,以及每个内存节点提供的物理内存大小；向所述M个内存节点中每个内存节点发送内存申请消息；接收来自所述M个内存节点中每个内存节点的内存申请应答消息；发送内存注册应答消息，所述内存注册应答消息携带分配的注册内存区域的信息。

Description

一种内存管理方法、设备和系统 技术领域
本发明实施例涉及计算机领域，尤其涉及一种内存管理方法、设备和系统。
背景技术
随着计算机网络技术的迅猛发展，网络的性能目前已经达到每秒100千兆比特级别，如何充分利用高速网络的特性是我们面对的一个重要问题。远程直接数据存取(Remote Direct Memory Access，简称RDMA)是为了解决网络传输中数据处理的延迟而产生的，RDMA使一台计算设备可以直接将信息传送到另一台计算设备的内存中，消除了外部存储器复制和文本交换操作。这项技术通过减少处理器开销和减少内存的拷贝降低了时延，提高了网络利用率。
RDMA解决了现有以计算设备为单位的数据快速交互,然而随着提高资源利用率的需求越来越受到重视，计算设备的内存资源与计算设备相互分离，形成内存资源池，RDMA方式的数据交互也被从计算设备/计算设备模式的数据交互引申到计算设备与分离内存资源之间的数据交互，由此带来的变化对RDMA带来了新的需求。即当计算设备的内存资源与计算设备分离后，当计算设备向内存资源注册内存区域时，如何实现对内存资源的内存管理。
发明内容
有鉴于此，本发明实施例提供了一种远程直接数据存取内存管理方法、设备和系统，在计算设备与内存资源分离的情况下，实现了内存资源全局管理的功能。
第一方面，本发明实施例提供了一种内存管理方法，内存控制器向外提供统一的内存资源接口，包括：
内存控制器通过所述统一的内存资源接口接收内存注册请求，所述内存注册请求中携带注册内存区域的大小；
所述内存控制器从所述多个内存节点中确定为所述注册内存区域提供物 理内存的M个内存节点，以及所述M个内存节点中每个内存节点分别需要提供的物理内存大小，其中，M为大于0的自然数；
所述内存控制器向所述M个内存节点中每个内存节点分别发送内存申请消息，每个内存申请消息中携带所述需要提供的物理内存大小；
所述内存控制器接收来自所述M个内存节点中每个内存节点分别发送的内存申请应答消息，每个内存申请应答消息中携带分配的内存信息；
所述内存控制器根据所述M个内存节点的申请应答消息生成注册内存区域的信息，并通过所述统一的内存资源接口发送内存注册应答消息，所述内存注册应答消息携带所述注册内存区域的信息。
结合第一方面，在第一种可能的实现方式中，所述内存控制器维护所述多个内存节点中每一个节点的剩余内存大小；
所述内存控制器从所述多个内存节点中确定为所述注册内存区域提供物理内存的M个内存节点，以及所述M个内存节点中每个内存节点分别需要提供的物理内存大小包括：所述内存控制器根据自身维护的所述多个内存节点中每一个节点的剩余内存大小和注册内存区域大小，确定所述M个内存节点，以及所述M个内存节点中每个内存节点需要提供的物理内存大小。
结合第一方面或以上任一项可能的实现方式，在第二种可能的实现方式中，所述内存申请应答消息携带的所述分配的内存信息包含分配的内存的物理地址信息；
所述方法还包括：所述内存控制器根据所述注册内存区域大小，为所述注册内存区域分配虚拟地址，并建立所述注册内存区域的虚拟地址与所述M个内存节点的所述分配的内存的物理地址信息之间的映射关系。
结合第一方面或以上任一项可能的实现方式，在第三种可能的实现方式中，所述内存注册应答消息包含所述注册内存区域的虚拟地址与所述M个内存节点的所述分配的内存的物理地址信息之间的映射关系。
结合第一方面或以上任一项可能的实现方式，在第四种可能的实现方式中，所述内存注册应答消息包含所述注册内存区域的虚拟地址信息。
结合第一方面或以上任一项可能的实现方式，在第五种可能的实现方式中，所述内存申请应答消息还包含队列对信息，所述队列对与为所述内存申请消息分配的内存关联；
所述内存注册应答消息还包含所述M个内存节点中每个内存节点为所 述注册内存区域分配的内存关联的队列对信息。
结合第一方面或以上任一项可能的实现方式，在第六种可能的实现方式中，所述内存注册请求还包含权限标识，所述权限标识用于表征所述注册内存区域允许的操作类型；
所述内存申请消息还包含所述权限标识。
结合第一方面或以上任一项可能的实现方式，在第七种可能的实现方式中，还包括：所述内存控制器生成密钥信息，并将所述密钥信息发送给所述M个内存节点，在收到所述M个内存节点中每个内存节点的密钥确认应答消息后，将所述密钥发送给申请所述注册内存区域的计算装置，所述密钥信息用于表征访问所述M个内存节点的权限。
第二方面，本发明实施例提供了一种内存管理设备，向外提供统一的内存资源接口，包括：处理器、存储器、总线和通信接口；
所述存储器用于存储计算机执行指令，所述处理器与所述存储器通过所述总线连接，当所述计算设备运行时，所述处理器执行所述存储器存储的所述计算机执行指令，以使所述内存管理设备执行执行第一方面或第一方面任一种可能的实现方式的方法。
第三方面，本发明实施例提供了一种内存管理设备，向外提供统一的内存资源接口，向外提供统一的内存资源接口，包括：
接收单元，用于通过所述统一的内存资源接口接收内存注册请求，所述内存注册请求中携带注册内存区域的大小；
处理单元，用于从所述多个内存节点中确定为所述注册内存区域提供物理内存的M个内存节点，以及所述M个内存节点中每个内存节点分别需要提供的物理内存大小，其中，M为大于0的自然数；
发送单元，用于向所述M个内存节点中每个内存节点分别发送内存申请消息，每个内存申请消息中携带所述需要提供的物理内存大小；
所述接收单元还用于接收来自所述M个内存节点中每个内存节点分别发送的内存申请应答消息，每个内存申请应答消息中携带分配的内存信息；
所述发送单元还用于根据所述M个内存节点的申请应答消息生成注册内存区域的信息，并通过所述统一的内存资源接口发送内存注册应答消息，所述内存注册应答消息携带所述注册内存区域的信息。
结合第三方面，在第一种可能的实现方式中，所述处理单元还用于维护 所述多个内存节点中每一个节点的剩余内存大小；
所述处理单元用于从所述多个内存节点中确定为所述注册内存区域提供物理内存的M个内存节点，以及所述M个内存节点中每个内存节点分别需要提供的物理内存大小包括：所述处理单元根据自身维护的所述多个内存节点中每一个节点的剩余内存大小和注册内存区域大小，确定所述M个内存节点，以及所述M个内存节点中每个内存节点需要提供的物理内存大小。
结合第三方面或以上任一项可能的实现方式，在第二种可能的实现方式中，所述内存申请应答消息携带的所述分配的内存信息包含分配的内存的物理地址信息；
所述处理单元还用于：根据所述注册内存区域大小，为所述注册内存区域分配虚拟地址，并建立所述注册内存区域的虚拟地址与所述M个内存节点的所述分配的内存的物理地址信息之间的映射关系。
结合第三方面或以上任一项可能的实现方式，在第三种可能的实现方式中，所述内存注册应答消息包含所述注册内存区域的虚拟地址与所述M个内存节点的所述分配的内存的物理地址信息之间的映射关系。
结合第三方面或以上任一项可能的实现方式，在第四种可能的实现方式中，所述内存注册应答消息包含所述注册内存区域的虚拟地址信息。
结合第三方面或以上任一项可能的实现方式，在第五种可能的实现方式中，所述内存申请应答消息还包含队列对信息，所述队列对与为所述内存申请消息分配的内存关联；
所述内存注册应答消息还包含所述M个内存节点中每个内存节点为所述注册内存区域分配的内存关联的队列对信息。
结合第三方面或以上任一项可能的实现方式，在第六种可能的实现方式中，所述内存注册请求还包含权限标识，所述权限标识用于表征所述注册内存区域允许的操作类型；
所述内存申请消息还包含所述权限标识。
结合第三方面或以上任一项可能的实现方式，在第七种可能的实现方式中，所述处理单元还用于：生成密钥信息，并将所述密钥信息发送给所述M个内存节点，在收到所述M个内存节点中每个内存节点的密钥确认应答消息后，将所述密钥发送给申请所述注册内存区域的计算装置，所述密钥信息用于表征访问所述M个内存节点的权限。
第四方面，本发明实施例提供了一种内存管理系统，内存管理设备向外提供统一的内存资源接口，包含：计算节点，多个内存节点以及以及第三方面或第三方面任一种可能使得实现方式中的所述的内存管理设备，
所述计算节点用于通过所述统一的内存资源接口向所述内存管理设备发送内存注册请求，所述内存注册请求中携带注册内存区域的大小，并通过所述统一的内存资源接口接收来自所述内存管理设备的内存注册应答消息，所述内存注册应答消息携带所述注册内存区域的信息。
所述多个内存节点用于接收所述内存管理设备的内存申请消息，根据所述内存申请消息为所述注册内存区域分配内存，并向所述内存管理设备发送内存申请应答消息。
根据本发明提供的技术方案，当计算设备的计算资源与内存资源解耦后，内存资源以内存资源池的形式提供给计算资源使用，一个内存资源池包含多个内存节点，可以实现对内存资源池内的多个内存节点的统一管理，实现了全局管理RDMA内存资源的功能，使注册内存区域的范围可以跨内存节点，提高了内存利用的效率，并使内存管理更加灵活和高效。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为各计算设备经由RDMA共享数据的示例性联网环境框图；
图2为本发明的示例性计算设备的示意图；
图3为一种RDMA内存管理方法的应用场景示意图；
图4为一种RDMA内存管理方法的信令图；
图5为依据本发明一实施例的内存管理方法的应用场景示意图；
图6为依据本发明一实施例的内存管理方法信令图；
图7为依据本发明一实施例的内存管理方法的示范性流程图；
图8为依据本发明一实施例的内存管理设备的逻辑结构示意图；
图9为依据本发明一实施例的计算设备硬件结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
图1示出了RDMA连网环境100，其中网络102连接了四个计算设备104。计算设备104使用它们的网络102连接来执行相互的RDMA传递。网络102可以是因特网，内联网，局域网(LANs),广域网络(WLANs)，存储区域网络(SANs)等，或者以上网络的组合。
图1仅旨在为以下讨论目的而引入RDMA参与者以及它们的相互关系。因此，所描绘的RDMA环境100被大大地简化。由于RDMA的一些方面在本领域中是公知的，因此这些方面，诸如认证方案和安全等在此不再讨论。在设置和运行成功的RDMA环境100中所涉及的复杂性对于在本领域中工作的人来说都是公知的。
图1的计算设备104可以是任意体系结构的。图2是一般化地示出支持本发明实施例的示例性计算机系统的框图。图2的计算机系统仅是一个例子，并不试图对本发明实施例的使用范围或功能提出任何限定。也不应当将计算设备104解释为具有与图2中所示的组件中的任何一个或其组合有关的任何依赖性或要求。本发明实施例可与许多其他的通用或专用计算环境或配置一起工作。适于与本发明实施例一起使用的公知计算系统、环境和配置的示例包括但不限于，个人计算机、服务器、手持式或膝上型设备、多处理器系统、基于微处理器的系统、机顶盒、可编程消费电器、网络PC、微型计算机、大型计算机、以及包括任意以上系统或设备的分布式计算环境。在其最基本的配置中，计算设备104通常包括至少一个处理器200和存储器202。存储器202可以被计算设备104当做内存资源使用，可以是易失性的(诸如RAM)、非易失性的(诸如ROM或闪存)、或这两者的某种组合。这个最基本的配置在图2中由虚线204例示。计算设备104可以具有外加的特征和功能。例如，它可以包括外设的存储(可移动的和不可移动的)，其包括但不限于，磁盘和磁带以及光盘和光带。这样的外 设存储在图2中由可移动存储206和不可移动存储208例示。计算机存储介质包括易失性和非易失性的，可移动的和不可移动的，在任何方法或技术中实现的用来存储诸如计算机可读指令、数据结构、程序模块或其它数据等信息的介质。存储器202，可移动存储206和不可移动存储208都是计算机存储介质的示例。计算机存储介质包括，但不限于，RAM、ROM、EEPROM、闪存、其他的存储器技术，CD-ROM、数字通用盘、其他的光存储，磁卡带、磁带、磁盘存储、其他的磁存储设备，以及任何其他可以用来存储所需信息并可由计算设备104访问的介质。任何这样的计算机存储介质都可以是计算设备104的一部分。计算设备104还可以包含允许其与其他设备，包括在网络102上的设备，通信的通信信道210。通信信道210是通信介质的示例。通信介质通常在诸如载波等的已调制数据信号或其它传输机制中包含计算机可读指令、数据结构、程序模块、或其他数据，并包括任何信息传递介质。作为示例而非限定，通信介质包括光介质、诸如有线网络和直线连接等的有线介质、诸如声音、RF、红外线和其他无线介质等的无线介质。在此使用的术语"计算机可读介质"包括存储介质和通信介质两者。计算设备104还可以具有诸如触敏式显示屏、硬件键盘、鼠标、语音输入设备等的输入设备212。输出设备214包括设备本身，诸如触敏式显式屏、扬声器、打印机和用来驱动这些设备的呈现模块(常称之为"适配器")。所有这些设备都是本领域公知的，因此在此无需详细讨论。计算设备104具有电源216。
可选的，计算设备104的计算资源与内存资源分离，计算设备104分为计算节点和内存资源。内存资源包括存储器202和存储器控制器，存储器控制器用于控制存储器202的数据存取等操作；计算节点包括计算设备104的其他特征和功能。可选的，计算节点还包括计算设备104的除分离的内存资源以外的其他内存资源。计算节点和分离内存资源之间通过网络102进行连接。
可选的，计算设备104的计算资源与内存资源解耦，即计算资源与内存资源分离，计算资源以计算资源池的形式存在，内存资源以内存资源池的形式存在，计算资源池包含至少一个计算节点，内存资源池包含至少一个内存节点。计算节点包含处理器200以及其他计算与通讯必须的组件， 内存节点包含存储器202以及存取器控制器等其他存储和通讯必须的组件。
图3是远程直接数据存取RDMA方法应用场景的逻辑结构示意图，如图3所示，该系统包括第一计算设备和第二计算设备，其中第一计算设备和第二计算设备为图2所示的计算设备，图中仅示出计算设备的处理器和存储器，其他特征和功能在图3未示出。
当第二计算设备的第二存储器需要向第一计算设备的第一存储器进行RDMA操作时，其信令图如图4所示，执行步骤为：
402：第二计算设备向第一计算设备通过网络102发送RDMA操作请求。
可选的，所述RDMA操作请求中携带第二计算设备向第一计算设备请求的RDMA操作类型，以及RDMA操作需要的内存大小。
404：第一计算设备根据RDMA操作请求在本地内存进行内存申请。
可选的，进行内存申请的时候还生成队列对(Queue Pair,QP)，并与注册内存区域(Memory Region，MR)绑定。MR是所申请的注册内存区域的统称，MR以虚拟地址的方式呈现，它是物理地址(页模式或块模式)在应用层的映射。
QP包括发送队列(Send Queue，SQ)和接收队列(Receive Queue，RQ)。SQ用于发送操作，保存使数据在一个计算设备的内存设备和另一个计算资源的内存设备之间传输的指令；RQ用于接收操作，保存有关将从另一个计算设备接收到的数据放在哪里的指令。计算设备提交工作请求，这是要放置在适当的工作队列中的工作队列元素(Work Queue Element，WQE)。通道适配器执行WQE，以便它们放置在工作队列中。
可选的，操作系统在内存访问期间要对注册内存区域允许的操作进行检查，申请的内存都有远程关键字和本地关键字，用来控制内存的访问权限，本地关键字用于本地RDMA网卡(RDMA Network Interface Card，RNIC)硬件接口适配器访问本地内存，远程关键字用于远程的RNIC硬件接口适配器访问系统内存。
406：第一计算设备将申请的注册内存区域消息发送给第二计算设备。
可选的，RDMA注册内存区域消息中包含虚拟地址(Virtual Address，VA)和内存钥匙(Remote Key，R_KEY)。其中，虚拟地址VA表示第一存储器用于接受RDMA操作的存储单元的虚拟地址，内存钥匙R_KEY用于表征访问第一存储器的权限，且用于结合虚实地址转换表进行虚拟地址到第一存储器物理地址的转换。。
408：第二计算设备对第一计算设备进行RDMA操作。
依据图4所示的RDMA方法，可以实现基于第一计算设备104与第二计算设备104之间的RDMA内存申请。但图4所述的RDMA内存申请是点对点进行的，仅适用于当两个计算设备之间需要进行RDMA操作时的内存申请，所申请的内存仅限于计算设备内部，即申请的内存无法跨多个内存节点，尤其在计算设备的计算资源和内存资源解耦的架构下，无法实现内存的统一管理。当计算设备的计算资源与内存资源分离时，内存资源以内存资源池的形式存在，内存资源池包含多个内存节点，点到多点之间需要创建不同的MR，导致同一进程需要维护多个MR，而且物理内存无法最大化利用，导致节点内存不能最优化利用。
图5为依据本发明一实施例的内存管理方法的应用场景示意图，如图5所示，计算设备104的计算资源与内存资源分离，分为计算节点502和内存节点506，即计算设备的计算资源和内存资源解耦，不再是物理上集成在一个计算设备上，而是以计算资源池和内存资源池的形式向计算设备提供计算节点和内存节点，计算节点502与内存节点506通过网络102、PCIE总线或者消息总线等形式进行连接。计算设备的内存资源以内存资源池510的形式提供给计算节点502，内存资源池510包含N个内存节点，其中N为大于0的自然数。在图5所示的框架中，计算和内存不再是一个强耦合的关系，计算资源和内存资源被划分为不同的节点，计算节点502可以申请内存资源池510的资源，不需要再局限于某个内存节点内部。
可选的，计算节点502为计算设备104除去内存资源的剩余部分，计算节点502的内存资源与计算节点502解耦，即计算节点502的内存资源与计算节点502分离，以内存资源池510的形式向计算节点502提供内存资源。
可选的，计算节点502为计算设备104，其部分内存资源与计算节点 502解耦，即计算节点502的部分内存资源与计算节点502分离，以内存资源池510的形式提供给计算节点502。
可选的，计算节点502为计算设备104负责计算处理操作的节点，包含处理器200以及其他计算与通讯必须的组件。
可选的，计算节点502为一个计算资源池，该计算资源池包含多个处理器200以及其他计算与通讯必须的组件。
其中，内存控制器504为对内存资源池510内的内存节点506进行统一内存管理的管理设备。
可选的，内存控制器504负责内存资源池510内部的N个内存节点506的统一管理和分配。系统内存地址分为虚拟地址和物理地址，用户层看到的是虚拟地址，而在内存节点506上处理时需要物理地址，在内存控制器504上完成内存节点506的虚拟地址到物理地址的转换。
可选的，内存控制器504上保存了整个内存资源池510的内存使用情况，即内存控制器504知道N个内存节点506上哪些内存被使用，哪些内存空闲，这样内存控制器504可以根据用户申请内存长度在内存节点中合理分配内存。
可选的，内存控制器504对内存资源池510内部的N个内存节点进行统一编址，内存资源池510内部的N个内存节点的虚拟地址由内存控制器504统一管理。
可选的，存储器控制器508部署在内存节点506上，负责内存节点506访问权限控制及响应内存控制器504的指令。
可选的，在存储器控制器508上设置内存访问权限控制表，当接收到内存访问指令时，要先到权限控制表中查找，符合权限后才去实际操作物理内存。
内存控制器504向外提供统一的内存资源接口。
可选的，当计算节点502要在内存资源池510进行RDMA内存申请的时候，其信令图如图6所示，其步骤为：
602：内存控制器504通过统一的内存资源接口接收接收来自计算节点502的内存注册请求，所述内存注册请求中携带注册内存区域的大小。
可选的，所述内存申请请求还包含进程标识。内存控制器504根据进程标识和内存注册请求请求的注册内存区域大小为注册内存区域分配虚拟地址。
可选的，所述内存注册请求还包含权限标识，所述权限标识用于表征所述注册内存区域允许的操作类型。
可选的，所述操作类型包含以下至少一种：本地读、本地写、远程读、远程写、原子操作或绑定。
604：内存控制器504从所述多个内存节点506中确定为所述注册内存区域提供物理内存的M个内存节点506，以及所述M个内存节点506中每个内存节点506分别需要提供的物理内存大小，其中，M为大于0的自然数。
可选的，所述内存控制器504维护所述多个内存节点506中每一个节点的剩余内存大小；所述内存控制器504从所述多个内存节点506中确定为所述注册内存区域提供物理内存的M个内存节点506，以及所述M个内存节点506中每个内存节点506分别需要提供的物理内存大小包括：所述内存控制器504根据自身维护的所述多个内存节点506中每一个节点的剩余内存大小和注册内存区域大小，确定所述M个内存节点506，以及所述M个内存节点506中每个内存节点506需要提供的物理内存大小。
可选的，内存控制器504根据内存注册请求请求的内存空间大小、和内存资源池510内的N个内存节点506物理内存使用情况，确定为所述注册内存区域提供物理内存的M个内存节点506，以及所述M个内存节点506中每个内存节点506提供的物理内存大小。
606：内存控制器504向所述M个内存节点506中每个内存节点506分别发送内存申请消息，每个内存申请消息中携带所述需要提供的物理内存大小。
可选的，所述内存申请消息还包含权限标识，所述权限标识用于表征所述注册内存区域允许的操作类型。所述操作类型包含以下至少一种：本地读、本地写、远程读、远程写、原子操作或绑定。
可选的，内存申请消息还携带进程标识，存储器控制器508根据接收到的内存申请消息所申请内存空间大小分配物理内存空间，并把进程标识 和所分配的物理内存地址对应起来，记录到内存管理权限表。
可选的，存储器控制器508还在内存节点506上创建QP，并和分配的物理内存空间进行绑定。
608：内存控制器504接收来自所述M个内存节点506中每个内存节点506分别发送的内存申请应答消息，每个内存申请应答消息中携带对应的内存节点506分配的内存信息。
可选的，所述内存申请应答消息包含506为所述内存申请消息分配的内存的物理地址信息。
可选的，内存控制器504根据所述注册内存区域大小，为所述注册内存区域分配虚拟地址，并建立所述注册内存区域的虚拟地址与所述M个内存节点506的所述分配的内存的物理地址信息之间的映射关系。
可选的，所述内存申请应答消息还包含队列对信息，所述队列对QP与所属的内存节点506为所述内存申请消息分配的内存关联。
可选的，所述内存控制器504建立所述注册内存区域与所述M个内存节点506为所述注册内存区域分配的内存关联的队列对QP之间的映射关系。
可选的，内存控制器504还生成队列队QP，该队列队QP与注册内存区域关联。
610：内存控制器504根据所述M个内存节点506的申请应答消息生成注册内存区域的信息，并通过所述统一的内存资源接口向计算节点502发送内存注册应答消息，所述内存注册应答消息携带所述注册内存区域的信息。
可选的，所述内存注册应答消息包含所述注册内存区域的虚拟地址与所述M个内存节点506的所述分配的内存的物理地址信息之间的映射关系。
可选的，所述内存注册应答消息包含所述注册内存区域的虚拟地址信息。
可选的，所述内存注册应答消息还包含所述M个内存节点506中每个内存节点506为所述注册内存区域分配的内存关联的队列对QP信息。
可选的，所述内存注册应答消息还包含与所述注册内存区域关联的队列队QP信息。
可选的，所述内存控制器504还生成密钥信息，并将所述密钥信息发送给所述M个内存节点506，在收到所述M个内存节点506中每个内存节点506的密钥确认应答消息后，将所述密钥发送给申请所述注册内存区域的计算装置，所述密钥信息用于表征访问所述M个内存节点506的权限。
根据本实施例公开的技术方案，当计算设备的计算资源与内存资源解耦后，内存资源以内存资源池的形式提供给计算资源使用，一个内存资源池包含多个内存节点，可以实现对内存资源池内的多个内存节点的统一管理，实现了全局管理内存资源的功能，使注册内存区域的范围可以跨内存节点，提高了内存利用的效率，并使内存管理更加灵活和高效。
图7为依据本发明一实施例的的内存管理方法700的示范性流程图。当计算设备的计算资源与内存资源分离，计算设备的内存资源以内存资源池的形式提供给计算资源，内存资源池包含N个内存节点，其中N为大于0的自然数。方法700实现了计算资源在内存资源池内进行RDMA内存注册的功能，使内存注册不再局限于某个内存节点内部。方法700的执行主体可以是内存资源池的RDMA内存控制器。内存控制器向外提供统一的内存资源接口，如图7所示，方法700包括：
S702：内存控制器通过所述统一的内存资源接口接收内存注册请求，所述内存注册请求中携带注册内存区域的大小。
S704：所述内存控制器从所述多个内存节点中确定为所述注册内存区域提供物理内存的M个内存节点，以及所述M个内存节点中每个内存节点分别需要提供的物理内存大小，其中，M为大于0的自然数。
S706：所述内存控制器向所述M个内存节点中每个内存节点分别发送内存申请消息，每个内存申请消息中携带所述需要提供的物理内存大小。
S708：所述内存控制器接收来自所述M个内存节点中每个内存节点分别发送的内存申请应答消息，每个内存申请应答消息中携带分配的内存信息。
S710：所述内存控制器根据所述M个内存节点的申请应答消息生成注册内存区域的信息，并通过所述统一的内存资源接口发送内存注册应答消 息，所述内存注册应答消息携带所述注册内存区域的信息。。
可选的，所述内存控制器维护所述多个内存节点中每一个节点的剩余内存大小；所述内存控制器从所述多个内存节点中确定为所述注册内存区域提供物理内存的M个内存节点，以及所述M个内存节点中每个内存节点分别需要提供的物理内存大小包括：所述内存控制器根据自身维护的所述多个内存节点中每一个节点的剩余内存大小和注册内存区域大小，确定所述M个内存节点，以及所述M个内存节点中每个内存节点需要提供的物理内存大小。
可选的，所述内存申请应答消息携带的所述分配的内存信息包含分配的内存的物理地址信息；所述方法700还包括：所述内存控制器根据所述注册内存区域大小，为所述注册内存区域分配虚拟地址，并建立所述注册内存区域的虚拟地址与所述M个内存节点的所述分配的内存的物理地址信息之间的映射关系。
可选的，所述内存注册应答消息包含所述注册内存区域的虚拟地址与所述M个内存节点的所述分配的内存的物理地址信息之间的映射关系。
可选的，所述内存注册应答消息包含所述注册内存区域的虚拟地址信息。
可选的，所述内存申请应答消息还包含队列对信息，所述队列对与为所述内存申请消息分配的内存关联；所述内存注册应答消息还包含所述M个内存节点中每个内存节点为所述注册内存区域分配的内存关联的队列对信息。
可选的，所述内存注册请求还包含权限标识，所述权限标识用于表征所述注册内存区域允许的操作类型；所述内存申请消息还包含所述权限标识。
可选的，所述操作类型包含以下至少一种：本地读、本地写、远程读、远程写、原子操作或绑定。
可选的，方法700还包括：所述内存控制器生成密钥信息，并将所述密钥信息发送给所述M个内存节点，在收到所述M个内存节点中每个内存节点的密钥确认应答消息后，将所述密钥发送给申请所述注册内存区域的计算装置，所述密钥信息用于表征访问所述M个内存节点的权限。。
可选的，所述内存控制器还用于生成队列队QP，并建立该队列队QP与所述注册内存区域之间的关联关系；所述内存注册应答消息还包含该队列队信息。
可选的，所述内存申请应答消息还包含远端内存钥匙(Remote Key， R_KEY)，所述远端内存钥匙R_KEY用于表征访问所述内存申请应答消息的权限，且用于结合虚拟地址共同确定该内存节点用于接收操作的存储单元的物理地址。所述内存注册应答消息还包含所述M个内存节点中每个内存节点为所述注册内存区域对应的远端内存钥匙R_KEY。
可选的，所述内存申请请求还包含进程标识，内存资源池的内存控制器根据进程标识和内存注册请求请求的注册内存区域大小为注册内存区域分配虚拟地址。
可选的，内存资源池的内存控制器根据内存注册请求请求的内存空间大小、和内存资源池内的N个内存节点物理内存使用情况，确定为所述注册内存区域提供物理内存的M个内存节点，以及所述M个内存节点中每个内存节点提供的物理内存大小。
根据本实施例公开的技术方案，当计算设备的计算资源与内存资源解耦后，内存资源以内存资源池的形式提供给计算资源使用，一个内存资源池包含多个内存节点，可以实现对内存资源池内的多个内存节点的统一管理，实现了全局管理内存资源的功能，使注册内存区域的范围可以跨内存节点，提高了内存利用的效率，并使内存管理更加灵活和高效。
图8为依据本发明一实施例的内存管理设备800的逻辑结构示意图。当计算设备的计算资源与内存资源分离，计算设备的内存资源以内存资源池的形式提供给计算资源，内存资源池包含N个内存节点，其中N为大于0的自然数。设备800实现了计算资源在内存资源池内进行RDMA内存注册的功能，使RDMA内存注册不再局限于某个内存节点内部。如图8所示，方法800包括：
接收单元802，用于通过所述统一的内存资源接口接收内存注册请求，所述内存注册请求中携带注册内存区域的大小；
处理单元804，用于从所述多个内存节点中确定为所述注册内存区域提供物理内存的M个内存节点，以及所述M个内存节点中每个内存节点分别需要提供的物理内存大小，其中，M为大于0的自然数；
发送单元806，用于向所述M个内存节点中每个内存节点分别发送内存申请消息，每个内存申请消息中携带所述需要提供的物理内存大小；
所述接收单元802还用于接收来自所述M个内存节点中每个内存节点 分别发送的内存申请应答消息，每个内存申请应答消息中携带分配的内存信息；
所述发送单元806还用于根据所述M个内存节点的申请应答消息生成注册内存区域的信息，并通过所述统一的内存资源接口发送内存注册应答消息，所述内存注册应答消息携带所述注册内存区域的信息。
可选的，所述处理单元804维护所述多个内存节点中每一个节点的剩余内存大小；所述处理单元804用于从所述多个内存节点中确定为所述注册内存区域提供物理内存的M个内存节点，以及所述M个内存节点中每个内存节点分别需要提供的物理内存大小包括：所述处理单元根据自身维护的所述多个内存节点中每一个节点的剩余内存大小和注册内存区域大小，确定所述M个内存节点，以及所述M个内存节点中每个内存节点需要提供的物理内存大小。
可选的，所述内存申请应答消息携带的所述分配的内存信息包含分配的内存的物理地址信息；所述处理单元804还用于：根据所述注册内存区域大小，为所述注册内存区域分配虚拟地址，并建立所述注册内存区域的虚拟地址与所述M个内存节点的所述分配的内存的物理地址信息之间的映射关系。
可选的，所述内存注册应答消息包含所述注册内存区域的虚拟地址与所述M个内存节点的所述分配的内存的物理地址信息之间的映射关系。
可选的，所述内存注册应答消息包含所述注册内存区域的虚拟地址信息。
可选的，所述内存申请应答消息还包含队列对信息，所述队列对与为所述内存申请消息分配的内存关联；所述内存注册应答消息还包含所述M个内存节点中每个内存节点为所述注册内存区域分配的内存关联的队列对信息。
可选的，所述内存注册请求还包含权限标识，所述权限标识用于表征所述注册内存区域允许的操作类型；所述内存申请消息还包含所述权限标识。
可选的，所述操作类型包含以下至少一种：本地读、本地写、远程读、远程写、原子操作或绑定。
可选的，所述处理单元804还用于：生成密钥信息，并将所述密钥信息发送给所述M个内存节点，在收到所述M个内存节点中每个内存节点 的密钥确认应答消息后，将所述密钥发送给申请所述注册内存区域的计算装置，所述密钥信息用于表征访问所述M个内存节点的权限。
可选的，所述内存申请应答消息还包含远端内存钥匙(Remote Key，R_KEY)，所述远端内存钥匙R_KEY用于表征访问所述内存申请应答消息的权限，且用于结合虚拟地址共同确定该内存节点用于接收RDMA操作的存储单元的物理地址。所述内存注册应答消息还包含所述M个内存节点中每个内存节点为所述注册内存区域对应的远端内存钥匙R_KEY。
可选的，所述处理单元804还用于生成队列队QP，并建立该队列队QP与所述注册内存区域之间的关联关系；所述内存注册应答消息还包含该队列队信息。
可选的，所述内存申请请求还包含进程标识，处理单元804根据进程标识和内存注册请求请求的注册内存区域大小为注册内存区域分配虚拟地址。
可选的，处理单元804根据内存注册请求请求的内存空间大小、和内存资源池内的N个内存节点物理内存使用情况，确定为所述注册内存区域提供物理内存的M个内存节点，以及所述M个内存节点中每个内存节点提供的物理内存大小。
根据本实施例公开的技术方案，当计算设备的计算资源与内存资源解耦后，内存资源以内存资源池的形式提供给计算资源使用，一个内存资源池包含多个内存节点，可以实现对内存资源池内的多个内存节点的统一管理，实现了全局管理内存资源的功能，使注册内存区域的范围可以跨内存节点，提高了内存利用的效率，并使内存管理更加灵活和高效。
图9是依据本发明一实施例的计算设备设备900的硬件结构示意图。如图9所示，计算设备900包括处理器902、内存器904、输入/输出接口906、通信接口908和总线910。其中，处理器902、内存器904、输入/输出接口906和通信接口908通过总线910实现彼此之间的通信连接。
处理器902可以采用通用的中央处理器(Central Processing Unit，CPU)，微处理器，应用专用集成电路(Application SQecific Integrated Circuit，ASIC)，或者一个或多个集成电路，用于执行相关程序，以实现本发明实施例所提供的技术方案。
内存器904可以是只读内存器(Read Only Memory，ROM)，静态内存设备，动态内存设备或者随机存取内存器(Random Access Memory，RAM)。内存器904可以内存操作系统和其他应用程序。在通过软件或者固件来实现本发明实施例提供的技术方案时，用于实现本发明实施例提供的技术方案的程序代码保存在内存器904中，并由处理器902来执行。
输入/输出接口906用于接收输入的数据和信息，输出操作结果等数据。
通信接口908使用例如但不限于收发器一类的收发装置，来实现计算设备900与其他设备或通信网络之间的通信。
总线910可包括一通路，在计算设备900各个部件(例如处理器902、内存器904、输入/输出接口906和通信接口908)之间传送信息。
应注意，尽管图9所示的计计算设备900仅仅示出了处理器902、内存器904、输入/输出接口906、通信接口908以及总线910，但是在具体实现过程中，本领域的技术人员应当明白，计算设备900还包含实现正常运行所必须的其他器件。同时，根据具体需要，本领域的技术人员应当明白，计算设备900还可包含实现其他附加功能的硬件器件。此外，本领域的技术人员应当明白，计算设备900也可仅仅包含实现本发明实施例所必须的器件，而不必包含图9中所示的全部器件。
图9所示的硬件结构以及上述描述适用于本发明实施例所提供的各种内存管理设备和系统，适用于执行本发明实施例所提供的各种内存管理方法。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统，设备和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述模块的划分，仅仅为一种逻辑功能划分，实现时可以有另外的划分方式，例如多个模块或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或模块的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的模块可以是或者也可以不是物理上分开的，作为模块显示的部件可以是或者也可以不是物理模块，即可以位于一个地方，或者也可以分布到多个网络模块上。可以根据实际的需要选择其中的 部分或者全部模块来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能模块可以集成在一个处理模块中，也可以是各个模块单独物理存在，也可以两个或两个以上模块集成在一个模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用硬件加软件功能模块的形式实现。
上述以软件功能模块的形式实现的集成的模块，可以内存在一个计算机可读取内存介质中。上述软件功能模块内存在一个内存介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本发明各个实施例所述方法的部分步骤。而前述的内存介质包括：移动硬盘、只读内存器(英文：Read-Only Memory，简称ROM)、随机存取内存器(英文：Random Access Memory，简称RAM)、磁碟或者光盘等各种可以内存程序代码的介质。
最后应说明的是：以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的保护范围。

Claims (18)

  1. 一种内存管理方法，其特征在于，内存控制器向外提供统一的内存资源接口，包括：
    内存控制器通过所述统一的内存资源接口接收内存注册请求，所述内存注册请求中携带注册内存区域的大小；
    所述内存控制器从所述多个内存节点中确定为所述注册内存区域提供物理内存的M个内存节点，以及所述M个内存节点中每个内存节点分别需要提供的物理内存大小，其中，M为大于0的自然数；
    所述内存控制器向所述M个内存节点中每个内存节点分别发送内存申请消息，每个内存申请消息中携带所述需要提供的物理内存大小；
    所述内存控制器接收来自所述M个内存节点中每个内存节点分别发送的内存申请应答消息，每个内存申请应答消息中携带分配的内存信息；
    所述内存控制器根据所述M个内存节点的申请应答消息生成注册内存区域的信息，并通过所述统一的内存资源接口发送内存注册应答消息，所述内存注册应答消息携带所述注册内存区域的信息。
  2. 根据权利要求1所述的方法，其特征在于，所述内存控制器维护所述多个内存节点中每一个节点的剩余内存大小；
    所述内存控制器从所述多个内存节点中确定为所述注册内存区域提供物理内存的M个内存节点，以及所述M个内存节点中每个内存节点分别需要提供的物理内存大小包括：所述内存控制器根据自身维护的所述多个内存节点中每一个节点的剩余内存大小和注册内存区域大小，确定所述M个内存节点，以及所述M个内存节点中每个内存节点需要提供的物理内存大小。
  3. 根据权利要求1或2所述的方法，其特征在于，所述内存申请应答消息携带的所述分配的内存信息包含分配的内存的物理地址信息；
    所述方法还包括：所述内存控制器根据所述注册内存区域大小，为所述注册内存区域分配虚拟地址，并建立所述注册内存区域的虚拟地址与所述M个内存节点的所述分配的内存的物理地址信息之间的映射关系。
  4. 根据权利要求3所述的方法，其特征在于，所述内存注册应答消息包含所述注册内存区域的虚拟地址与所述M个内存节点的所述分配的内存的物理地址信息之间的映射关系。
  5. 根据权利要求3所述的方法，其特征在于，所述内存注册应答消息包含所述注册内存区域的虚拟地址信息。
  6. 根据权利要求4或5所述的方法，其特征在于，所述内存申请应答消息还包含队列对信息，所述队列对与为所述内存申请消息分配的内存关联；
    所述内存注册应答消息还包含所述M个内存节点中每个内存节点为所述注册内存区域分配的内存关联的队列对信息。
  7. 根据权利要求6所述的方法，其特征在于，所述内存注册请求还包含权限标识，所述权限标识用于表征所述注册内存区域允许的操作类型；
    所述内存申请消息还包含所述权限标识。
  8. 根据权利要求1-7任一项所述的方法，其特征在于，还包括：所述内存控制器生成密钥信息，并将所述密钥信息发送给所述M个内存节点，在收到所述M个内存节点中每个内存节点的密钥确认应答消息后，将所述密钥发送给申请所述注册内存区域的计算装置，所述密钥信息用于表征访问所述M个内存节点的权限。
  9. 一种内存管理设备，其特征在于，向外提供统一的内存资源接口，包括：处理器、存储器、总线和通信接口；
    所述存储器用于存储计算机执行指令，所述处理器与所述存储器通过所述总线连接，当所述计算设备运行时，所述处理器执行所述存储器存储的所述计算机执行指令，以使所述内存管理设备执行权利要求1-8任一项所述的方法。
  10. 一种内存管理设备，其特征在于，向外提供统一的内存资源接口，向外提供统一的内存资源接口，包括：
    接收单元，用于通过所述统一的内存资源接口接收内存注册请求，所述内存注册请求中携带注册内存区域的大小；
    处理单元，用于从所述多个内存节点中确定为所述注册内存区域提供物理内存的M个内存节点，以及所述M个内存节点中每个内存节点分别需要提供的物理内存大小，其中，M为大于0的自然数；
    发送单元，用于向所述M个内存节点中每个内存节点分别发送内存申请消息，每个内存申请消息中携带所述需要提供的物理内存大小；
    所述接收单元还用于接收来自所述M个内存节点中每个内存节点分别 发送的内存申请应答消息，每个内存申请应答消息中携带分配的内存信息；
    所述发送单元还用于根据所述M个内存节点的申请应答消息生成注册内存区域的信息，并通过所述统一的内存资源接口发送内存注册应答消息，所述内存注册应答消息携带所述注册内存区域的信息。
  11. 根据权利要求10所述的设备，其特征在于，所述处理单元还用于维护所述多个内存节点中每一个节点的剩余内存大小；
    所述处理单元用于从所述多个内存节点中确定为所述注册内存区域提供物理内存的M个内存节点，以及所述M个内存节点中每个内存节点分别需要提供的物理内存大小包括：所述处理单元根据自身维护的所述多个内存节点中每一个节点的剩余内存大小和注册内存区域大小，确定所述M个内存节点，以及所述M个内存节点中每个内存节点需要提供的物理内存大小。
  12. 根据权利要求10或11所述的设备，其特征在于，所述内存申请应答消息携带的所述分配的内存信息包含分配的内存的物理地址信息；
    所述处理单元还用于：根据所述注册内存区域大小，为所述注册内存区域分配虚拟地址，并建立所述注册内存区域的虚拟地址与所述M个内存节点的所述分配的内存的物理地址信息之间的映射关系。
  13. 根据权利要求12所述的设备，其特征在于，所述内存注册应答消息包含所述注册内存区域的虚拟地址与所述M个内存节点的所述分配的内存的物理地址信息之间的映射关系。
  14. 根据权利要求12所述的设备，其特征在于，所述内存注册应答消息包含所述注册内存区域的虚拟地址信息。
  15. 根据权利要求13或14所述的设备，其特征在于，所述内存申请应答消息还包含队列对信息，所述队列对与为所述内存申请消息分配的内存关联；
    所述内存注册应答消息还包含所述M个内存节点中每个内存节点为所述注册内存区域分配的内存关联的队列对信息。
  16. 根据权利要求15所述的设备，其特征在于，所述内存注册请求还包含权限标识，所述权限标识用于表征所述注册内存区域允许的操作类型；
    所述内存申请消息还包含所述权限标识。
  17. 根据权利要求10-16任一项所述的设备，其特征在于，所述处理单元还用于：生成密钥信息，并将所述密钥信息发送给所述M个内存节点， 在收到所述M个内存节点中每个内存节点的密钥确认应答消息后，将所述密钥发送给申请所述注册内存区域的计算装置，所述密钥信息用于表征访问所述M个内存节点的权限。
  18. 一种内存管理系统，其特征在于，内存管理设备向外提供统一的内存资源接口，包含：计算节点，多个内存节点以及权利要求10-17任一项所述的内存管理设备，
    所述计算节点用于通过所述统一的内存资源接口向所述内存管理设备发送内存注册请求，所述内存注册请求中携带注册内存区域的大小，并通过所述统一的内存资源接口接收来自所述内存管理设备的内存注册应答消息，所述内存注册应答消息携带所述注册内存区域的信息。
    所述多个内存节点用于接收所述内存管理设备的内存申请消息，根据所述内存申请消息为所述注册内存区域分配内存，并向所述内存管理设备发送内存申请应答消息。
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