WO2016162053A1

WO2016162053A1 - Memristor functions based on an orthogonal electrode

Info

Publication number: WO2016162053A1
Application number: PCT/EP2015/057523
Authority: WO
Inventors: Milorad Jovanovic
Original assignee: Hewlett-Packard Development Company, L.P.
Priority date: 2015-04-07
Filing date: 2015-04-07
Publication date: 2016-10-13

Abstract

A memristor function based on an orthogonal electrode is disclosed. One example is a memristor device with a plurality of electrodes (108, 110, 112, 114), including a first group of electrodes (108, 110), a second group of electrodes (112, 114), and an active region. The first group includes at least two electrodes arranged in a first direction, and the second group includes at least one electrode arranged in a second direction orthogonal to the first direction. The active region is bounded by the plurality of electrodes, the active region including a first region (102) with a dopant and a second region (104) without a dopant, wherein a boundary (106) between the first region and the second region is selectively positioned by altering a percentage of the dopant in the first region to control flow of charge carriers in the active region to implement a memristor function, where the altering is based on applying a voltage to a sub-plurality of the plurality of electrodes.

Description

MEMRISTOR FUNCTIONS BASED ON AN ORTHOGONAL ELECTRODE

Background

[0001] Memristors are memory devices that are generally incorporated in a computer's memory. Memristors may be arranged in an electronic circuit to perform functions of a switch or a logic gate.

Brief Description of the Drawings

[0002] Figure 1 A illustrates an example memristor device configured to implement a memristor function of a switch in an off-position.

[0003] Figure 1 B illustrates an example memristor device configured to implement a memristor function of a switch in an on-position.

[0004] Figures 2A and 2B illustrate an example memristor device configured to implement a memristor function of a NOT logic gate.

[0005] Figures 3A - 3D illustrate an example memristor device configured to implement a memristor function of a NAND logic gate.

Detailed Description

[0006] Memristors may switch resistance states at lower voltage levels than signal voltage levels used in transistors. Experimental results suggest that memristor based circuits may employ considerably less voltage when signaling than CMOS circuits. As a result, computing circuits, which traditionally employ many CMOS circuits, may experience substantial energy reduction by implementing memristors to perform the computing circuit's logic if clock speed is held constant.

[0007] In existing applications to computer memory, memristors are generally viewed as a one dimensional element. Accordingly, electrodes in a memristor are typically arranged longitudinally along the length of a memristor. However, a memristor is a three-dimensional object. Existing memristors generally do not utilize added functionalities provided by the third dimension. Although devices and circuitry are known to implement logic with memristors, they may generally require multiple memristors.

[0008] As described herein, the three-dimensional structure of a memristor may be utilized to arrange additional electrodes in a direction orthogonal to the longitudinal direction. In such instances, electrical current may flow not just longitudinally, but also transversally. Accordingly, a variety of different memristor functions, such as, for example, switching, NOT, NAND, and/or other complex logical operations, may be performed using a single memristor device.

[0009] The principles described herein include a single memristor device with a plurality of electrodes organized to form a logic cell. A logic cell is an

arrangement of electrodes that may perform a logical operation. The memristor may be electrically connected to a voltage source, and voltage may be applied to a sub-plurality of the plurality of electrodes.

[0010] As described in various examples herein, a memristor function based on an orthogonal electrode is disclosed. One example is a memristor device with a plurality of electrodes, including a first group of electrodes, a second group of electrodes, and an active region. The first group includes at least two electrodes arranged in a first direction, and the second group includes at least one electrode arranged in a second direction orthogonal to the first direction. The active region is bounded by the plurality of electrodes, the active region including a first region with a dopant and a second region without a dopant, wherein a boundary between the first region and the second region is selectively positioned by altering a percentage of the dopant in the first region to control flow of charge carriers in the active region to implement a memristor function, where the altering is based on applying a voltage to a sub-plurality of the plurality of electrodes. The term "active region" as used herein indicates the doped and undoped regions of the memristor device. Also, the term "bounded" as used herein refers to "being surrounded on a boundary and/or a periphery" and/or "enclosed". For example, the plurality of electrodes may be positioned along the boundary of the active region. In some examples, the plurality of electrodes may be positioned along the boundary of the active region to enclose the active region.

[0011] In the following detailed description, reference is made to the

accompanying drawings which form a part hereof, and in which is shown by way of illustration specific examples in which the disclosure may be practiced. It is to be understood that other examples may be utilized, and structural or logical changes may be made without departing from the scope of the present disclosure. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims. It is to be understood that features of the various examples described herein may be combined, in part or whole, with each other, unless specifically noted otherwise.

[0012] Generally, a memristor, as disclosed herein, may include a plurality of electrodes, with an active region bounded by the plurality of electrodes, the active region including a first region including a dopant and a second region not including a dopant. In some examples, the dopant may include one of an oxygen vacancy, a nitrogen vacancy, a sulfur vacancy, a carbon vacancy, and an anion vacancy. Although the examples described herein will be based on references to an oxygen vacancy, similar principles apply to other vacancies as well.

[0013] Application of a positive voltage to a sub-plurality of the plurality of electrodes, causes the positively charged oxygen vacancies in a ΤΊΟ2 layer to be repelled, moving the vacancies towards the second region not including the dopant, for example, the ΤΊΟ2 layer. As a result, by altering a percentage of the dopant in the first region, the boundary between the first region and the second region may be selectively positioned, causing an increase in the percentage of the conducting ΤΊΟ2 layer, thereby controlling flow of charge carriers in the active region. For example, conductivity of the memristor device may be increased.

[0014] Application of a negative voltage to a second sub-plurality of the plurality of electrodes, causes the positively charged oxygen vacancies in the ΤΊΟ2 layer to be attracted, pulling them out of ΤΊΟ2 layer. As a result, the amount of insulating ΤΊΟ2 is increased, thereby controlling flow of charge carriers in the active region. For example, resistivity of the memristor device may be decreased.

[0015] Generally, as the conductivity of the memristor device is increased, the flow of charge carriers may be directed to an output electrode. In like manner, as the resistivity of the memristor device is increased, the flow of charge carriers through the output electrode may be impeded. Such a combination of positively and negatively charged electrodes may be utilized to perform a memristor function. In some examples, the memristor function may be a switch.

Generally, a switch is a memristor that has two states - an "on" position that facilitates a flow of the charge carriers, and an "off position that impedes a flow of the charge carriers.

[0016] As described herein, the plurality of electrodes may include a first group of electrodes and a second group of electrodes. Generally, the first group may include at least two electrodes arranged in a first direction. For example, the first direction may be a longitudinal direction along the length of the memristor device. Generally, the second group may include at least one electrode arranged in a second direction orthogonal to the first direction. For example, the first direction may be a longitudinal direction with the first group of electrodes generally situated in a planar region, and the second direction may be a direction orthogonal to the planar region, thereby taking advantage of a three- dimensional structure of the memristor device.

[0017] In some examples, the first group may include a first sub-plurality of electrodes arranged along a longitudinal direction of the device, and the second group may include a second sub-plurality of electrodes arranged in a direction orthogonal to the longitudinal direction. As described herein, a memristor function may be implemented by impeding or facilitating a flow of charge carriers in the active region, from a first electrode in the first group to a second electrode in the second group, by selectively applying a voltage to a third sub- plurality of the plurality of electrodes. In some examples, the third sub-plurality of the plurality of electrodes may include electrodes from the first and second groups. In some examples, the applied voltage may be positive and/or negative.

[0018] Figure 1 A illustrates an example memristor device configured to implement a memristor function of a switch in an off-position. The active region may include a first region, illustrated as doped region 102A, and a second region, illustrated as undoped region 104A. The plurality of electrodes may include a first electrode 108A of the first group in contact with the first region, doped region 102A. The plurality of electrodes may include a second electrode 1 10A of the first group in contact with the second region, undoped region 104A. As illustrated, the first electrode 108A and the second electrode 1 10A may be situated opposite each other in a longitudinal direction. Also, as illustrated, a boundary 106A between doped region 102A and undoped region 104A may be generated.

[0019] The plurality of electrodes may include a third electrode 1 12A and a fourth electrode 1 14A, both in the second group. As illustrated, the third electrode 1 12A and the fourth electrode 1 14A may be situated opposite each other in a direction orthogonal to the longitudinal direction in which the first electrode 108A and the second electrode 1 10A are situated. The third electrode 1 12A and the fourth electrode 1 14A are both in contact with the second region, undoped region 104A. Accordingly, a flow of charge carriers from the third electrode 1 12A to the fourth electrode 1 14A may be impeded, indicated by impeded flow 1 16. Such an arrangement may correspond to an "off position for the switch.

[0020] Figure 1 B illustrates an example memristor device configured to implement a memristor function of a switch in an on-position. The active region may include a first region, illustrated as doped region 102B, and a second region, illustrated as undoped region 104B. The plurality of electrodes may include a first electrode 108B of the first group in contact with the first region, doped region 102B. The plurality of electrodes may include a second electrode 1 10B of the first group in contact with the second region, undoped region 104B. As illustrated, the first electrode 108B and the second electrode 1 10B may be situated opposite each other in a longitudinal direction. [0021] The plurality of electrodes may include a third electrode 1 12B and a fourth electrode 1 14B, both in the second group. As illustrated, the third electrode 1 12B and the fourth electrode 1 14B may be situated opposite each other in a direction orthogonal to the longitudinal direction in which the first electrode 108B and the second electrode 1 10B are situated. As a positive voltage is applied to the first electrode 108B, and a negative voltage is applied to the second electrode 1 10B, boundary 106B between doped region 102B and undoped region 104B may be selectively positioned. For example, boundary 106A of Figure 1 A may move to the boundary 106B of Figure 1 B, where the direction of the move is toward the second electrode 1 10B. This may place the third electrode 1 12B and the fourth electrode 1 14B in contact with the first region, doped region 102B. Accordingly, a flow of charge carriers from the third electrode 1 12A to the fourth electrode 1 14A may be facilitated, indicated by flow 1 18. Such an arrangement may correspond to an "on" position for the switch.

[0022] In some examples, the memristor function may be a logic gate. A logic gate is a gate that provides a binary output based on a combination of binary inputs. In implementing a logic gate, the positively charged electrodes may be associated with a binary input value of "1 ", whereas the negatively charged electrodes may be associated with a binary input value of "0". As the flow of charge carriers is facilitated via the output electrode, the output electrode may be associated with a binary output value of "1 ". Likewise, as the flow of charge carriers is impeded via the output electrode, the output electrode may be associated with a binary output value of "0". Selective application of the positive voltage to the sub-plurality of the plurality of electrodes, and application of the negative voltage to the second sub-plurality of the plurality of electrodes, allows various combinations of binary inputs and associated binary outputs to be implemented.

[0023] Figures 2A and 2B illustrate an example memristor device configured to implement a memristor function of a NOT logic gate. With reference to Figure 2A, the active region may include a first region, illustrated as doped region 202A, and a second region, illustrated as undoped region 204A. The plurality of electrodes may include a first electrode 208A of the first group in contact with the first region, doped region 202A. The plurality of electrodes may include a second electrode 21 OA of the first group in contact with the second region, undoped region 204A. As illustrated, the first electrode 208A and the second electrode 21 OA may be situated opposite each other in a longitudinal direction. Also illustrated is a boundary 206A between doped region 202A and undoped region 204A.

[0024] With continued reference to Figure 2A, the plurality of electrodes may include a third electrode 212A of the second group. As illustrated, the third electrode 212A may be situated in a direction orthogonal to the longitudinal direction in which the first electrode 208A and the second electrode 21 OA are situated. The third electrode 212A may be in contact with the second region, undoped region 204A. Accordingly, a flow of charge carriers from the first electrode 208A to the third electrode 212A may be impeded, indicated by impeded flow 214.

[0025] As illustrated in Figure 2A, a positive voltage may be applied to the first electrode 208A and the second electrode 21 OA, thereby maintaining boundary 206A, and maintaining contact between the third electrode 212A and the second region, undoped region 204A. Accordingly, the second electrode 21 OA may be associated with a logical input "A" with a binary input value "1 " corresponding to the positive voltage applied to the second electrode 21 OA. Also, for example, the third electrode 212A may be associated with a logical output "B" with a binary output value "0" corresponding to the impeded flow 214. Accordingly, "A" and "B" are in opposite states, emulating a NOT function. For example, "B", associated with the binary output value "0" is "NOT A", where "A" is associated with the binary input value "1 ".

[0026] With reference to Figure 2B, the active region may include a first region, illustrated as doped region 202B, and a second region, illustrated as undoped region 204B. The plurality of electrodes may include a first electrode 208B of the first group in contact with the first region, doped region 202B. The plurality of electrodes may include a second electrode 210B of the first group in contact with the second region, undoped region 204B. As illustrated, the first electrode 208B and the second electrode 210B may be situated opposite each other in a longitudinal direction. Also illustrated is a boundary 206B between doped region 202B and undoped region 204B.

[0027] With continued reference to Figure 2B, a positive voltage may be applied to the first electrode 208A and a negative voltage may be applied to the second electrode 21 OA to selectively position boundary 206B between doped region 202B and undoped region 204B. For example, boundary 206A of Figure 2A may move to the boundary 206B of Figure 2B, where the direction of the move is toward the second electrode 21 OB. This may place the third electrode 212B in contact with the first region, doped region 202B. Accordingly, a flow of charge carriers from the first electrode 208B to the third electrode 212B may be facilitated, indicated by flow 216.

[0028] With continued reference to Figure 2B, the second electrode 210B may be associated with a logical input "A" with a binary input value "0" corresponding to the negative voltage applied to the second electrode 210B. Also, for example, the third electrode 212B may be associated with a logical output "B" with a binary output value "1 " corresponding to the flow 216. Accordingly, "A" and "B" are in opposite states, emulating a NOT function. For example, "B", associated with the binary output value "1 " is "NOT A", where "A" is associated with the binary input value "0".

[0029] Figures 3A - 3D illustrate an example memristor device configured to implement a memristor function of a NAND logic gate. With reference to Figure 3A, the active region may include a first region, illustrated as doped region 302A, and a second region, illustrated as undoped region 304A. The plurality of electrodes may include a first electrode 308A of the first group in contact with the first region, doped region 302A. The plurality of electrodes may include a second electrode 31 OA and a third electrode 312A of the first group in contact with the second region, undoped region 304A. As illustrated, the first electrode 308A may be situated opposite the second electrode 31 OA and the third electrode 312A, in a longitudinal direction. Also illustrated is a boundary 306A between doped region 302A and undoped region 304A.

[0030] With continued reference to Figure 3A, the plurality of electrodes may include a fourth electrode 314A of the second group. As illustrated, the fourth electrode 314A may be situated in a direction orthogonal to the longitudinal direction in which the first electrode 308A, the second electrode 31 OA, and the third electrode 312A are situated. The fourth electrode 314A may be in contact with the second region, undoped region 304A. Accordingly, a flow of charge carriers from the first electrode 308A to the fourth electrode 314A may be impeded, indicated by impeded flow 316.

[0031] As illustrated in Figure 3A, a positive voltage may be applied to the first electrode 308A, the second electrode 31 OA, and the third electrode 312A, thereby maintaining boundary 306A, and maintaining contact between the fourth electrode 314A and the second region, undoped region 304A. Accordingly, the second electrode 31 OA may be associated with a logical input "A" with a binary input value "1 " corresponding to the positive voltage applied to the second electrode 31 OA. Likewise, the third electrode 312A may be associated with a logical input "B" with a binary input value "1 " corresponding to the positive voltage applied to the third electrode 312A. Also, for example, the fourth electrode 314A may be associated with a logical output "C" with a binary output value "0" corresponding to the impeded flow 316. Accordingly, "A", "B", and "C" emulate an aspect of a NAND function, where C = NAND (A, B).

[0032] With reference to Figure 3B, the active region may include a first region, illustrated as doped region 302B, and a second region, illustrated as undoped region 304B. The plurality of electrodes may include a first electrode 308B of the first group in contact with the first region, doped region 302B. The plurality of electrodes may include a second electrode 310B and a third electrode 312B of the first group in contact with the second region, undoped region 304B. As illustrated, the first electrode 308B may be situated opposite the second electrode 310B and the third electrode 312B, in a longitudinal direction. Also illustrated is a boundary 306B between doped region 302B and undoped region 304 B.

[0033] With continued reference to Figure 3B, the plurality of electrodes may include a fourth electrode 314B of the second group. As illustrated, the fourth electrode 314B may be situated in a direction orthogonal to the longitudinal direction in which the first electrode 308B, the second electrode 310B, and the third electrode 312B are situated. A positive voltage may be applied to the first electrode 308B and the second electrode 31 OB, and a negative voltage may be applied to the third electrode 312B to selectively position boundary 306B between doped region 302B and undoped region 304B. For example, boundary 306A of Figure 3A may move to the boundary 306B of Figure 3B, where the direction of the move is toward the third electrode 312B. This may place the fourth electrode 314B in contact with the first region, doped region 302B.

Accordingly, a flow of charge carriers from the first electrode 308B to the fourth electrode 314B may be facilitated, indicated by flow 318.

[0034] Accordingly, the second electrode 31 OB may be associated with a logical input "A" with a binary input value "1 " corresponding to the positive voltage applied to the second electrode 31 OB. Likewise, the third electrode 312B may be associated with a logical input "B" with a binary input value "0" corresponding to the negative voltage applied to the third electrode 312B. Also, for example, the fourth electrode 314B may be associated with a logical output "C" with a binary output value "1 " corresponding to the flow 318. Accordingly, "A", "B", and "C" emulate another aspect of the NAND function, where C = NAND (A, B).

[0035] With reference to Figure 3C, the active region may include a first region, illustrated as doped region 302C, and a second region, illustrated as undoped region 304C. The plurality of electrodes may include a first electrode 308C of the first group in contact with the first region, doped region 302C. The plurality of electrodes may include a second electrode 310C and a third electrode 312C of the first group in contact with the second region, undoped region 304C. As illustrated, the first electrode 308C may be situated opposite the second electrode 310C and the third electrode 312C, in a longitudinal direction. Also illustrated is a boundary 306C between doped region 302C and undoped region 304C.

[0036] With continued reference to Figure 3C, the plurality of electrodes may include a fourth electrode 314C of the second group. As illustrated, the fourth electrode 314C may be situated in a direction orthogonal to the longitudinal direction in which the first electrode 308C, the second electrode 310C, and the third electrode 312C are situated. A positive voltage may be applied to the first electrode 308C and the third electrode 312C, and a negative voltage may be applied to the second electrode 31 OC to selectively position boundary 306C between doped region 302C and undoped region 304C. For example, boundary 306A of Figure 3A (or boundary 306B of Figure 3B) may move to the boundary 306C of Figure 3C, where the direction of the move is toward the second electrode 31 OC. This may place the fourth electrode 314C in contact with the first region, doped region 302C. Accordingly, a flow of charge carriers from the first electrode 308C to the fourth electrode 314C may be facilitated, indicated by flow 320.

[0037] Accordingly, the second electrode 310C may be associated with a logical input "A" with a binary input value "0" corresponding to the negative voltage applied to the second electrode 310C. Likewise, the third electrode 312C may be associated with a logical input "B" with a binary input value "1 " corresponding to the positive voltage applied to the third electrode 312C. Also, for example, the fourth electrode 314C may be associated with a logical output "C" with a binary output value "1 " corresponding to the flow 320. Accordingly, "A", "B", and "C" emulate another aspect of the NAND function, where C = NAND (A, B).

[0038] With reference to Figure 3D, the active region may include a first region, illustrated as doped region 302D, and a second region, illustrated as undoped region 304D. The plurality of electrodes may include a first electrode 308D of the first group in contact with the first region, doped region 302D. The plurality of electrodes may include a second electrode 310D and a third electrode 312D of the first group in contact with the second region, undoped region 304D. As illustrated, the first electrode 308D may be situated opposite the second electrode 310D and the third electrode 312D, in a longitudinal direction. Also illustrated is a boundary 306D between doped region 302D and undoped region 304 D.

[0039] With continued reference to Figure 3D, the plurality of electrodes may include a fourth electrode 314D of the second group. As illustrated, the fourth electrode 314D may be situated in a direction orthogonal to the longitudinal direction in which the first electrode 308D, the second electrode 310D, and the third electrode 312D are situated. A positive voltage may be applied to the first electrode 308D, and a negative voltage may be applied to the second electrode 310D and the third electrode 312D, to selectively position boundary 306D between doped region 302D and undoped region 304D. For example, boundary 306A of Figure 3A (or boundary 306B of Figure 3B, boundary 306C of Figure 3C) may move to the boundary 306D of Figure 3D, where the direction of the move is toward the second electrode 310D and the third electrode 312D. This may place the fourth electrode 314D in contact with the first region, doped region 302D. Accordingly, a flow of charge carriers from the first electrode 308D to the fourth electrode 314D may be facilitated, indicated by flow 322.

[0040] Accordingly, the second electrode 310D may be associated with a logical input "A" with a binary input value "0" corresponding to the negative voltage applied to the second electrode 310D. Likewise, the third electrode 312D may be associated with a logical input "B" with a binary input value "0" corresponding to the negative voltage applied to the third electrode 312D. Also, for example, the fourth electrode 314D may be associated with a logical output "C" with a binary output value "1 " corresponding to the flow 322. Accordingly, "A", "B", and "C" emulate another aspect of the NAND function, where C = NAND (A, B).

[0041] Examples of the disclosure provide a generalized schema to emulate multiple memristor functions on a single memristor device. The generalized schema takes advantage of the memristor device's three-dimensional structure to position at least one electrode in a direction orthogonal to the longitudinal directional electrodes, as generally found in existing devices.

[0042] Although specific examples have been illustrated and described herein, especially as related to numerical data, the examples illustrate applications to any dataset. Accordingly, there may be a variety of alternate and/or equivalent implementations that may be substituted for the specific examples shown and described without departing from the scope of the present disclosure. For example, a variety of logic gates may be implemented via arrangements described herein. This application is intended to cover any adaptations or variations of the specific examples discussed herein. Therefore, it is intended that this disclosure be limited only by the claims and the equivalents thereof.

Claims

1 . A memristor device comprising:

a plurality of electrodes comprising a first group of electrodes and a second group of electrodes, wherein:

the first group comprises at least two electrodes arranged in a first direction, and

the second group comprises at least one electrode arranged in a second direction orthogonal to the first direction;

an active region bounded by the plurality of electrodes, the active region comprising a first region including a dopant and a second region not including a dopant, wherein a boundary between the first region and the second region is selectively positioned by altering a percentage of the dopant in the first region to control flow of charge carriers in the active region to implement a memristor function, wherein the altering is based on applying a voltage to a sub-plurality of the plurality of electrodes.

2. The device of claim 1 , wherein applying the voltage includes applying a positive voltage to a first sub-plurality of electrodes, and applying a negative voltage to a second sub-plurality of electrodes.

3. The device of claim 1 , wherein the memristor function is a switch.

4. The device of claim 1 , wherein the memristor function is a logic gate.

5. The device of claim 4, wherein the logic gate is one of a NOT gate and a NAN D gate.

6. The device of claim 1 , wherein the dopant comprises one of an oxygen vacancy, a nitrogen vacancy, a sulfur vacancy, a carbon vacancy, and an anion vacancy.

7. A method to implement a memristor function, the method comprising: selective positioning of a boundary between a first region of an active region and a second region of the active region, wherein the first region includes a dopant and the second region does not include the dopant, the selective positioning based on altering a percentage of the dopant in the first region to control a flow of charge carriers in the active region to implement the memristor function, and wherein the active region is bounded by a first group of electrodes and a second group of electrodes, and wherein:

the second group comprises at least one electrode arranged in a second direction orthogonal to the first direction, and

wherein the altering is based on applying a voltage to a sub- plurality of the plurality of electrodes.

8. The method of claim 7, wherein applying the voltage includes applying a positive voltage to a first sub-plurality of electrodes, and applying a negative voltage to a second sub-plurality of electrodes.

9. The method of claim 7, wherein the dopant comprises one of an oxygen vacancy, a nitrogen vacancy, a sulfur vacancy, a carbon vacancy, and an anion vacancy.

10. The method of claim 7, wherein the memory function is a switch, and wherein:

an off position for the switch is implemented by:

a first electrode, of the first group, in contact with the first region, a second electrode, of the first group, placed opposite to the first electrode along the first direction, the second electrode in contact with the second region, and

a third electrode and a fourth electrode, each of the second group, placed opposite to one another along the second direction, the third electrode and the fourth electrode in contact with the second region; and

an on position for the switch is implemented by:

applying a positive voltage to the first electrode and a negative voltage to the second electrode to move the boundary toward the second electrode, thereby placing the third electrode and the fourth electrode in contact with the first region, and facilitating the flow of charge carriers from the third electrode to the fourth electrode.

1 1 .The method of claim 7, wherein the memristor function is a logic gate.

12. The method of claim 1 1 , wherein the logic gate is a NOT gate

implemented by:

a third electrode of the second group in contact with the second region, and wherein:

a positive voltage is applied to the first electrode and a second electrode to impede the flow of charge carriers from the first electrode to the third electrode, and

a positive voltage is applied to the first electrode and a negative voltage is applied to the second electrode to facilitate the flow of charge carriers from the first electrode to the third electrode.

13. The method of claim 1 1 , wherein the logic gate is a NAND gate implemented by:

a first electrode, of the first group, in contact with the first region, a second electrode and a third electrode, of the first group, placed opposite to the first electrode along the first direction, the second electrode and the third electrode in contact with the second region, and a fourth electrode of the second group in contact with the second region, and wherein:

a positive voltage is applied to the first electrode, and the flow of charge carriers from the first electrode to the fourth electrode is impeded or facilitated based on an application of a combination of positive voltage and negative voltage to the second electrode and the third electrode.

14. A memristor device comprising:

the first group comprises a first sub-plurality of electrodes arranged along a longitudinal direction of the device, and

the second group comprises a second sub-plurality of electrodes arranged in a direction orthogonal to the longitudinal direction; an active region bounded by the plurality of electrodes, the active region comprising a first region including a dopant and a second region not including the dopant, and

wherein a memristor function is implemented by impeding or facilitating a flow of charge carriers in the active region, from a first electrode in the first group to a second electrode in the second group, by selectively applying a voltage to a third sub-plurality of the plurality of electrodes.

15. The device of claim 14, wherein the voltage comprises one of a positive voltage and a negative voltage.