WO2016161938A1 - 一种基带处理单元的单板复位方法、装置及设备 - Google Patents

一种基带处理单元的单板复位方法、装置及设备 Download PDF

Info

Publication number
WO2016161938A1
WO2016161938A1 PCT/CN2016/078609 CN2016078609W WO2016161938A1 WO 2016161938 A1 WO2016161938 A1 WO 2016161938A1 CN 2016078609 W CN2016078609 W CN 2016078609W WO 2016161938 A1 WO2016161938 A1 WO 2016161938A1
Authority
WO
WIPO (PCT)
Prior art keywords
reset
board
bbu
instruction
proxy
Prior art date
Application number
PCT/CN2016/078609
Other languages
English (en)
French (fr)
Inventor
任立钢
刘龙新
祁高珍
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Publication of WO2016161938A1 publication Critical patent/WO2016161938A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks

Definitions

  • the present invention relates to the field of network communication technologies, and in particular, to a board reset method, apparatus, and device for a baseband processing unit.
  • the Base Band Unit can communicate with the network management device through the transmission network, and the two BBUs communicate in the form of BBU interconnection.
  • the BBU interconnection refers to physically connecting two BBUs through the BBU interconnection signal line.
  • the interconnection of the two BBUs can be implemented through the interconnection of the internal boards of the two BBUs.
  • the internal single board interconnection can be implemented through physical interconnections. For example, when two BBUs are interconnected, only one BBU can communicate directly with the transport network, and another BBU wants to communicate with the transport network only by means of a BBU that communicates directly with the transport network. Communicate directly with the transport network.
  • Each of the BBUs contains multiple boards.
  • the board inside the BBU is abnormal.
  • the board is reset to eliminate the board abnormalities inside the BBU.
  • the link fault refers to the failure of the physical interconnect line between the two BBUs.
  • the service fault refers to the failure of the BBU network service that depends on another BBU to communicate with the transport network.
  • the above-mentioned self-reset can only perform one-level reset on the main control board in the BBU, and triggers the secondary reset of the interconnect interface board after the primary control board performs the first-level reset.
  • a reset method can only exclude a part of the board abnormalities, and there are a large number of single board differences. Often through such a reset method can not be eliminated.
  • An embodiment of the present invention provides a method, a device, and a device for resetting a single-board processing unit of a baseband processing unit, which are used to solve the problem that an abnormality of an abnormality of an internal board of a BBU that can communicate with a transmission network by another BBU is low.
  • a first aspect of the present invention provides a method for resetting a single-board processing unit.
  • the baseband processing unit BBU and the network management device are connected to each other through a proxy BBU, and the proxy BBU is directly connected to the network management device.
  • the BBU of the communication, the proxy BBU is interconnected with the BBU where the board to be reset is located, and the method includes:
  • the method further includes:
  • the reset identification information being used to indicate whether the first reset instruction is modified
  • the first reset instruction is sent to the BBU where the board to be reset is located through the physical interconnection line.
  • the acquiring the board type and the reset level to be reset includes:
  • Second reset command sent by the network management device, where the second reset command includes: target location information, a board type to be reset, and a reset level, where the target location information is used to obtain the BBU where the board to be reset is located.
  • the method includes:
  • the first reset command is carried in the sCPRI protocol, and is sent to the BBU where the board to be reset is located.
  • the board to be reset includes the main control board or the interconnect interface board.
  • a second aspect of the embodiments of the present invention provides a board resetting apparatus of a baseband processing unit, where the apparatus is applied to a proxy baseband processing unit BBU, and a BBU where a board to be reset is connected to a network management device by the proxy BBU,
  • the proxy BBU is a BBU that communicates directly with the network management device, and the proxy BBU is interconnected with the BBU where the board to be reset is located.
  • the device includes:
  • An acquiring unit configured to acquire the board type and a reset level to be reset
  • An instruction generating unit configured to generate a first reset instruction according to the type of the board to be reset acquired by the acquiring unit and the reset level;
  • the instruction sending unit is configured to send, by the physical interconnecting line, the first reset instruction generated by the instruction generating unit to the BBU where the board to be reset is located, where the first reset instruction is used to indicate the board to be reset The board in which the BBU is located is reset.
  • the device further includes:
  • An information generating unit configured to generate reset identification information, where the reset identification information is used to indicate whether the first reset instruction is modified
  • the instruction sending unit is further configured to: when detecting that the reset identification information generated by the information generating unit indicates that the first reset instruction is not modified, send the first reset instruction through the physical interconnect line The BBU where the board to be reset is located is located.
  • the acquiring unit includes:
  • An instruction receiving subunit configured to receive a second reset instruction sent by the network management device,
  • the second reset command includes: a target location information, a board type to be reset, and a reset level, where the target location information is used to indicate the location of the outbound board of the BBU where the board to be reset is located;
  • the instruction acquisition subunit is configured to acquire the board type to be reset and the reset level from the second reset instruction received by the instruction receiving subunit.
  • the instruction sending unit is used to When the physical interconnection line is a common public radio interface sCPRI link, the first reset instruction is carried in the sCPRI protocol, and the first reset instruction is sent to the to-be-reset board through the sCPRI link. BBU.
  • the board to be reset includes the main control board or the interconnect interface board.
  • a third aspect of the embodiments of the present invention provides a board resetting device of a baseband processing unit, where the device includes a proxy baseband processing unit BBU, and the BBU where the board to be reset is connected to the network management device through the proxy BBU,
  • the proxy BBU is a BBU that communicates directly with the network management device, and the proxy BBU is interconnected with the BBU where the board to be reset is located.
  • the device includes:
  • a memory for storing information including program instructions
  • a processor configured to control execution of the program instruction, specifically, to acquire a board type and a reset level to be reset; and generate a first reset instruction according to the type of the board to be reset and the reset level;
  • the transceiver is configured to send the first reset command obtained by the processor to the BBU where the board to be reset is located through a physical interconnection line;
  • the first reset command is used to indicate that the BBU where the board to be reset is located is reset by the board.
  • the processor is further configured to generate reset identification information, where the reset identification information is used to indicate whether the first reset instruction is modified;
  • the transceiver is further configured to: when detecting the reset identification information, indicating the first reset finger When the command is not modified, the first reset command is sent to the BBU where the board to be reset is located through the physical interconnect line.
  • the transceiver is further configured to receive a second reset command sent by the network management device, where the second reset command includes: target location information, a board type to be reset, and a reset level, where the target location information is used to indicate acquisition. The position of the external board of the BBU where the board to be reset is located.
  • the processor is further configured to acquire the board type to be reset and the reset level from the second reset instruction obtained by the transceiver.
  • the transceiver is further configured to: when the physical interconnection line is a common public radio interface sCPRI link, carry the first reset instruction in an sCPRI protocol, and send the to-reset through the sCPRI link
  • the board is in the BBU.
  • the board to be reset includes the main control board or the interconnect interface board.
  • the board resetting method, device and device of the baseband processing unit provided by the embodiment of the present invention obtain the board type and the reset level to be reset by the proxy BBU, and generate a first reset command according to the two kinds of information, and then pass the proxy.
  • the physical interconnection between the BBU and the BBU where the board to be reset is located is sent to the BBU where the board to be reset is located.
  • the technical solution provided by the embodiment of the present invention is to perform the BBU board reset by using the first reset command, which can solve the problem that the BBU internal board abnormality repair rate is low when the other BBU can communicate with the transmission network.
  • FIG. 1 is a schematic diagram of a method for implementing a single board resetting method for a baseband processing unit according to an embodiment of the present invention. Schematic diagram of the scene;
  • 1-1 is a flowchart of a method for resetting a single board in a baseband processing unit according to an embodiment of the present invention
  • FIG. 2 is a flowchart of a method for resetting a single board in a baseband processing unit according to another embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of an internal structure of a baseband processing unit single board according to another embodiment of the present invention.
  • FIG. 4 is a flowchart of a method for resetting a single board in a baseband processing unit according to another embodiment of the present invention.
  • 4-1 is a schematic diagram of communication between baseband processing units according to another embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a single board resetting device of a baseband processing unit according to another embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a single board resetting device of a baseband processing unit according to another embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a single board resetting device of a baseband processing unit according to another embodiment of the present invention.
  • GSM Global System for Mobile Communications
  • CDMA Code Division Multiple Access
  • TDMA Time Division Multiple Access
  • WCDMA Wideband Code Division Multiple Access
  • FDMA Frequency Division Multiple Access
  • OFDMA Orthogonal Frequency-Division Multiple Access
  • SC-FDMA single carrier FDMA
  • GPRS General Packet Radio Service
  • LTE Long Term Evolution
  • system and “network” are used interchangeably herein.
  • the term “and/or” in this context is merely an association describing the associated object, indicating that there may be three relationships, for example, A and / or B, which may indicate that A exists separately, and both A and B exist, respectively. B these three situations.
  • the character "/" in this article generally indicates that the contextual object is an "or" relationship.
  • the embodiment of the present invention provides a method for resetting a board of a BBU.
  • the application scenario of the method includes at least two physical interconnected BBUs, one transport network, and one network management device.
  • BBUs are respectively recorded as BBU0 and BBU1
  • BBU0 and BBU1 are interconnected through physical interconnections.
  • the BBU1 directly accesses the transmission network to communicate with the network management device through the link of the common common public radio interface (sCPRI) link, and the BBU0 and BBU1 share the transmission interface to the transmission network to communicate with the network management device.
  • sCPRI common common public radio interface
  • the BBU0 can sequentially establish a communication relationship with the network management device through the BBU1 and the transmission network.
  • the external board in the BBU0 is a Universal Inter-Connection Infrastructure Unit (UCIU), which can communicate with the Universal Main Processing and Transmission Unit (UMPT) on the BBU1.
  • the UCIU is an interconnected interface board.
  • the UMPT is a board that integrates the interface interconnection function and the main control function.
  • the BBU1 connects to the transmission network through the UMPT board.
  • the BBU0 further includes: a main control board UMPT, and a base band processor (BBP).
  • BBU1 also includes: BBP.
  • the above-mentioned external board refers to the single connection communication between the BBU and the outside world.
  • the board can be an interconnected interface board or a main control board.
  • the path in which the BBUO communicates with the network management device is: UMPT(BBU0) ⁇ ->UCIU ⁇ ->sCPRI link ⁇ ->UMPT(BBU1) ⁇ -> Transport network ⁇ -> network management equipment; BBU1 and network management equipment to communicate with the path: UMPT (BBU1) ⁇ -> transport network ⁇ -> network management equipment.
  • the board resetting method of the baseband processing unit can perform a board reset on a BBU (represented by BBU0) that can communicate with the transport network by relying on another BBU, and the execution flow can be performed on the BBU0.
  • the board is flexibly reset.
  • the board can be re-communicated with the network management device through the board reset process.
  • the embodiment of the present invention provides a method for resetting a single-board processing unit.
  • the method is performed on a BBU that communicates directly with the transmission network, and is executed on the BBU1 as shown in FIG. As shown in Figure 1-1, the method includes:
  • the board to be reset includes the main control board or the interconnect interface card.
  • the reset level includes a level 1 reset or a level 2 reset.
  • the first reset command is generated according to the type of the board to be reset and the reset level, and the first reset command is sent to the BBU where the board to be reset is located.
  • the first reset command is used to indicate that the BBU where the board to be reset is located is reset by the board.
  • the proxy BBU is the BBU that communicates with the network management device.
  • the proxy BBU is interconnected with the BBU where the board to be reset is located. The method flow shown in FIG. 1 is performed by the proxy BBU.
  • the BBU where the board to be reset is located is BBU0 shown in FIG. 1, and the proxy BBU is BBU1 described in FIG.
  • the board resetting method of the baseband processing unit acquires the board type and the reset level to be reset by the proxy BBU, and generates a first reset instruction according to the two kinds of information, and further passes the proxy BBU and is to be reset.
  • the physical interconnect line between the BBUs on which the board resides sends the first reset command to the BBU where the board to be reset is located. Reset.
  • the BBU board is reset by using the first reset command, which can solve the problem that the abnormal repair rate of the internal board of the BBU where the board to be reset is low is low.
  • Step 1 Receive the second reset command sent by the network management device.
  • the second reset command includes: a target location information, a board type to be reset, and a reset level, and the target location information is used to indicate the location of the outbound board of the BBU where the board to be reset is located.
  • the second reset instruction involved is converted into the first reset instruction described above in the proxy BBU.
  • the first reset command can be sent to the board to be reset through the physical interconnect line. Located in the BBU.
  • the target location information is used to indicate that the BBU where the board to be reset is located is obtained, and the location information is added to the second reset command by the network management device side, and the BBU where the board to be reset is located is located.
  • the BBU1 can communicate with the network management device directly through the transmission network. Therefore, the target location information includes not only the address of the BBU1 but also the interface address of the BBU1 and the BBU0.
  • the second reset command can instruct BBU0 to perform a board reset.
  • Step 2 Obtain the board type and reset level to be reset from the second reset instruction.
  • the method specifically includes:
  • the board resetting method of the baseband processing unit acquires the board type and the reset level to be reset by the proxy BBU, and generates a first reset instruction according to the two types of information. Then, the first reset command is sent to the BBU where the board to be reset is located, and the BBU where the board to be reset is located is reset by the BBU of the board to be reset.
  • the BBU board is reset by using the first reset command, which can solve the problem that the abnormal repair rate of the internal board of the BBU where the board to be reset is low is low.
  • the embodiment of the present invention provides a method for resetting a single-board processing unit, and in combination with the method flow shown in FIG. 2, in an implementation manner of the embodiment of the present invention, the foregoing step 102 is described in detail. That is, in this implementation manner, the implementation process of generating the first reset instruction by the proxy BBU is specifically introduced, which specifically includes:
  • the first reset instruction needs to be used for transmission between the BBUs, and the second reset instruction needs to comply with the sCPR protocol, that is, the board type and the reset level to be reset are added to the sCPRI protocol, and the first reset instruction is generated in the sCPRI protocol.
  • the first reset command is carried in the sCPRI protocol, and thus can be transmitted through the physical interconnect line sCPRI link between the BBUs.
  • the first reset command is carried in the sCPRI protocol, and is sent to the BBU0 through the sCPRI link, and the sCPRI protocol is transmitted in real time between the BBUs, in order to ensure the BBU0.
  • the out-of-board board can identify a protocol carrying a reset command
  • the second reset command can further include: a reset identifier.
  • the reset flag is used to indicate whether the board in the BBU0 needs to be actually reset.
  • the reset flag can be identified by using "0" and "1", and "0" can be set to indicate that the BBU0 does not need to be reset according to the second reset instruction. “1” indicates that BBU0 needs to perform board reset according to the second reset command. In this way, BBU0 can timely and accurately identify whether it is necessary to parse the reset instruction field in the sCPRI protocol.
  • the embodiment of the present invention provides another implementation manner of the single board resetting method of the baseband processing unit.
  • the BBU1 may further generate reset identification information when the second reset instruction is generated, and the reset identification information is applied to Internal to the BBU, the reset identification information is used to indicate whether the generated second reset instruction is modified.
  • the reset identification information indicates that the first reset instruction is not modified, the first reset instruction is sent to the BBU where the board to be reset is located through the physical interconnection line; if the instruction is modified, the modified second reset instruction is still sent to BBU0, BBU0 will be reset by mistake, resulting in waste of resources.
  • a central processing unit CPU
  • FPGA field programmable gate array
  • the CPU of the UMPT (BBU1) receives the second reset command sent by the network management device.
  • the CPU of the UMPT converts the second reset command, and generates a first reset command to be carried in the sCPRI protocol.
  • the first reset command is in accordance with a reset control field in the sCPRI protocol.
  • the CPU generates reset identification information and sends the reset identification information to the FPGA.
  • the reset identification information is in one-to-one correspondence with the first reset command, or may be only a number corresponding. For example, when three reset commands are sent, three reset identifier information are generated correspondingly, but the contents of the three reset identifier information are generated. the same.
  • the steps are performed in the order of steps 2 and 3.
  • the execution order of the steps 2 and 3 is not limited, and the step 3 and the step 2 described above may be performed simultaneously. Or step 3 is performed before step 2.
  • the CPU needs to send the first reset instruction and the reset identification information to the FPGA at the same time, so that the first reset instruction sent this time can be verified by resetting the identification information.
  • the FPGA After receiving the reset identification information, the FPGA detects whether the reset identification information conforms to a predetermined format.
  • the predetermined format may be determined by the CPU in the BBU1 and the FPGA in the BBU1, or determined by the CPU and informed to the FPGA that the reset identification information satisfies the predetermined format, indicating that the first reset instruction is not modified; otherwise , indicating that the first reset instruction has been modified.
  • the reset identification information conforms to the predetermined format, indicating that the first reset command received by the FPGA has not been modified, and then proceeds to step 5 below.
  • the second result the reset identification information does not conform to the predetermined format, indicating that the second reset command received by the FPGA has been modified, and the following step 6 is performed.
  • the FPGA carries the first reset command in the sCPRI protocol, and sends the sCPRI protocol reset control field to the FPGA in the UCIU (BBU0).
  • the FPGA carries the default non-reset information stored locally in the sCPRI protocol, and sends the sCPRI protocol to the FPGA in the UCIU (BBU0).
  • the FPGA in UCIU (BBU0) sends the sCPRI protocol to the CPU in the UCIU for resolution by the CPU in the UCIU.
  • a board resetting method of a baseband processing unit is provided.
  • the foregoing step 103 is described in detail in the implementation manner:
  • the proxy BBU When the proxy BBU sends the first reset command to the BBU where the board to be reset is located, the first reset command is sent from the external board of the proxy BBU to the outbound board of the BBU where the board to be reset is located. .
  • the reset instruction is sent through the physical interconnection line, and the physical interconnection belongs to the physical layer communication between the two BBUs.
  • the transmission of the first reset instruction does not need to consider whether the upper layer communication such as the application layer between the BBUs is normal.
  • the board of the BBU where the board to be reset is faulty is faulty.
  • the reset command is transmitted directly through the physical interconnect line, so that the worker does not need to directly go to the BBU site where the board to be reset is located to perform fault repair, which also greatly saves cost and reduces repair time, which inevitably reduces.
  • the interruption time after the base station fails.
  • a first reset command indicates that a board in the BBU where the board to be reset is located is reset by the board, and the board may be a main control board or an interconnect interface board.
  • the BBU of the board to be reset When the first reset command indicates that the main control board performs the first-level reset, the BBU of the board to be reset performs a level-reset on the main control board, and simultaneously resets the external board of the interface.
  • the BBU of the board to be reset is only for the corresponding board. The corresponding level of reset is performed and the associated reset is no longer performed by itself.
  • the BBU where the board to be reset is not completed after the board is reset according to the type of the board to be reset and/or the reset level included in the first reset instruction.
  • the fault is rectified.
  • the network management device can detect that the BBU where the original board is to be reset is still in the fault state.
  • the first reset command is sent again according to the above procedure, indicating that the BBU of the board to be reset is reset twice until the fault is rectified. until.
  • this specific execution process includes:
  • the network management device detects whether BBU0 and BBU1 are normally connected.
  • the detection of the network management device in this step detects whether the communication link between the BBU0 and the BBU1 and the network management device described above can communicate normally.
  • the UCIU on the BBU0 is the interconnected interface board
  • the UMPT is the main control board (the function of the interconnected interface board).
  • the UMPT on the BBU1 has the functions of the interconnected interface board and the main control board. It can be referred to as a proxy board.
  • the repair of the baseband processing unit involved in this embodiment refers to the BBU0. Repair of UCIU or UMPT.
  • the sCPRI link between the BBU0 and the BBU1 can communicate normally, and the communication link between the BBU1 and the network management device communicates normally, and the UMPT board inside the BBU1 is normal. jobs.
  • step 402 is performed. If the detection result of the foregoing step 401 is normal, the BBU0 and the BBU1 can communicate with the network management device normally. The situation is no longer explained.
  • the network management device displays fault alarm information.
  • the network management device receives a command input by the user through a man-machine language (MML) human-machine interface.
  • MML man-machine language
  • the instruction input by the user is the second reset instruction described above, and the related content description is the same, and the description is not repeated here, and in the subsequent step, the instruction input by the user will be described by the second reset instruction.
  • the network management device transmits the second reset command to the FPGA of the UMPT board of the BBU1 through the transmission network.
  • the transmission of the second reset command in the step is implemented by the transmission path between the BBU 1 and the network management device.
  • the transmission path has been described in the above description of FIG. 1 and will not be repeatedly described herein.
  • the CPU in the UMPT board on the BBU1 implements a conversion between the second reset command and the reset control field.
  • reset control field can be defined in bits (BIT), as defined below:
  • Bit 0 (bit 0): Whether to perform a board reset, including yes or no;
  • Bit 1 The board to be reset, including the interconnect interface card or the main control board.
  • Bit 2 Reset level, including level 1 reset or level 2 reset.
  • the reset control field involved in the embodiment is the first reset command described above, and the bit 0 indicating whether the board reset is performed is the reset identifier.
  • the reset control field is a field in the sCPRI protocol, as shown in Table 1 below, in which part of the sCPRI protocol is described.
  • the CPU in BBU1 generates reset identification information and sends it to the FPGA in BBU1.
  • the reset control field is sent to the FPGA of the UCIU in the BBU0.
  • BBU1 and BBU0 are actually the communication between the BBU0's external board (UCIU) and the FPGA in the outbound board (UMPT) in BBU1.
  • UCIU external board
  • UMPT outbound board
  • the method shown in the figure is used.
  • Figure 4-1 the structure of the external board in BBU0 is The board of the UMPT in the BBU1 shown in FIG. 3 has the same configuration.
  • the FPGA in the UCIU in the BBU0 and the FPGA in the UMPT in the BBU1 are interconnected through the sCPRI link.
  • step 406 and step 407 in this embodiment the related content descriptions in the foregoing steps 3-6 are the same. And when the FPGA detects that the reset identification information does not conform to the preset format, the locally stored default non-reset information is sent to the FPGA in the BBU0. This case will not be described in this embodiment.
  • the reset control field involved in this embodiment is the first reset command described above.
  • the FPGA in the UCIU sends a first reset command to the CPU in the UCIU.
  • the CPU in the UCIU parses the first reset command, obtains the board type and the reset level to be reset included in the first reset command, and performs a board reset.
  • the board to be reset When the board to be reset is the interface of the interconnected interface, the board is reset in the UCIU.
  • the board to be reset is the master board, the parsed reset command is sent to the master through the FPGA in the UCIU.
  • the board is the UMPT involved in this embodiment, and the board is reset on the UMPT.
  • connection modes between the BBUs are various, as long as they are between two boards with interconnected interfaces.
  • the BBU0 and the BBU1 shown in FIG. 1 are still taken as an example, and the UCIU (BBU0) and the UMPT (BBU1) may be connected.
  • Either UMPT (BBU0) and UMPT (BBU1) are connected, or UMPT (BBU1) is interconnected with UMPT (BBU0), no matter which type of interconnection is the same as that shown in Figure 1 above, as long as it is The interconnection is implemented through the sCPRI link, and the specific implementation form is the same regardless of the form of the interconnection, and the description is not repeated here.
  • the network management device can also repair the board fault on the BBU directly connected to it.
  • the network management device can directly send a reset command to the BBU1 to implement the BBU1. After the board is reset, after the BBU1 receives the reset command sent by the network management device, the subsequent execution process is the same as the execution flow after the BBU0 receives the first reset command sent by the BBU1.
  • the reset command is transmitted through the physical interconnection between the BBUs, and then the board in which the board is to be reset is reset.
  • the board in which the board is to be reset is reset.
  • Each interconnection form has a corresponding transmission protocol between the BBUs, and the transmission reset command between the BBUs needs to conform to the transmission protocol between the BBUs.
  • the physical interconnection of the BBUs through the sCPRI link is taken as an example.
  • the corresponding execution process is similar, and is not performed in the embodiment of the present invention. Description.
  • the reset command can be sent to the UMPT (BBU1).
  • BBU1 converts this command, and then the UMPT sends the UCIU (BBU0) through the sCPRI link.
  • the UCIU parses the converted reset command and resets the board through the reset command to eliminate the BBU0 fault and implement BBU0. Communicate again with the network management device.
  • Another embodiment of the present invention provides a single board resetting apparatus for a baseband processing unit.
  • the apparatus is applied to a proxy BBU.
  • the apparatus includes: an obtaining unit 51, an instruction generating unit 52, and an instruction sending unit 53. .
  • the obtaining unit 51 is configured to acquire a board type and a reset level to be reset.
  • the instruction generating unit 52 is configured to generate a first reset instruction according to the board type to be reset and the reset level acquired by the obtaining unit 51.
  • the command sending unit 53 is configured to send the first reset command generated by the command generating unit 52 to the BBU where the board to be reset is located.
  • the first reset command is used to indicate that the BBU where the board to be reset is located is reset by the board.
  • the proxy BBU is the BBU that communicates with the network management device.
  • the proxy BBU is interconnected with the BBU where the board to be reset resides.
  • the apparatus further includes: an information generating unit 54; the obtaining unit 51 includes: an instruction receiver Unit 511, instruction acquisition subunit 512.
  • the information generating unit 54 is configured to generate reset identification information.
  • the reset identification information is used to indicate whether the first reset instruction is modified.
  • the instruction sending unit 53 is further configured to: when it is detected that the reset identification information generated by the information generating unit 54 indicates that the first reset instruction is not modified, send the first reset instruction to the BBU where the board to be reset is located through the physical interconnection line.
  • the obtaining unit 51 includes an instruction receiving subunit 511 and an instruction acquiring subunit 512.
  • the instruction receiving subunit 511 is configured to receive a second reset instruction sent by the network management device.
  • the second reset command includes: a target location information, a board type to be reset, and a reset level, where the target location information is used to indicate the location of the outbound board of the BBU where the board to be reset is located.
  • the instruction acquisition sub-unit 512 is configured to obtain the board type to be reset and the reset level from the second reset instruction received by the instruction receiving sub-unit 511.
  • the instruction sending unit 53 is further configured to be physically interconnected.
  • the line is the sCPRI link
  • the first reset command is carried in the sCPRI protocol, and the first reset command is sent to the BBU where the board to be reset is located through the sCPRI link.
  • the device shown in FIG. 5 and FIG. 6 is used to reset the board in the baseband processing unit, and the type of the board to be reset includes the main control board or the interconnect interface board.
  • FIG. 5 and FIG. 6 can be used to implement the method flow shown in FIG. 1-1 to FIG. 4, and can be applied to the methods shown in FIG. 1-1 and FIG.
  • FIG. 5 and FIG. 6 For the convenience of the description, only the parts related to the embodiments of the present invention are shown. The specific technical details are not disclosed. Please refer to the related content description of the embodiments of the present invention shown in FIG. 1 to FIG.
  • An embodiment of the present invention provides a single board resetting apparatus of a baseband processing unit, where the apparatus is placed in a proxy BBU, and the acquiring unit acquires a board type and a reset level to be reset, and generates an instruction according to the two types of information by the command generating unit.
  • a reset command is sent to the BBU where the board to be reset is located, and the BBU of the board to be reset is instructed by the BBU of the board to be reset by the physical connection line between the proxy BBU and the BBU where the board to be reset is located.
  • the board is reset.
  • the BBU board is reset by using the first reset command, which can solve the problem that the abnormal repair rate of the internal board of the BBU where the board to be reset is low is low.
  • the apparatus includes: a memory 71, a processor 72, a transceiver 73, a memory 71, a processor 72, and a transceiver.
  • 73 is connected via bus 74 to perform data transmission with each other, and this device can be a proxy BBU.
  • the memory 71 may be a read only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM).
  • the memory 71 can store an operating system and other applications.
  • the program code for implementing the technical solution provided by the embodiment of the present invention is stored in the memory 71 and executed by the processor 72 when the technical solution provided by the embodiment of the present invention is implemented by software or firmware.
  • the transceiver 73 is used for the device with other devices or communication networks (such as but not limited to Ethernet, Communication between a Radio Access Network (RAN), a Wireless Local Area Network (WLAN), and the like.
  • RAN Radio Access Network
  • WLAN Wireless Local Area Network
  • the processor 72 can be a general-purpose central processing unit (CPU), a microprocessor, an application specific integrated circuit (ASIC), or one or more integrated circuits for executing related programs.
  • CPU central processing unit
  • ASIC application specific integrated circuit
  • Bus 74 may include a path for communicating information between various components of the device, such as memory 71, transceiver 73, and processor 72.
  • FIG. 7 only shows the memory 71, the processor 72 and the transceiver 73, and the bus 74, in the specific implementation process, those skilled in the art should understand that the device also includes the normal operation. Other devices necessary. At the same time, those skilled in the art will appreciate that hardware devices that implement other functions may also be included, depending on the particular needs.
  • the memory 71 is configured to store information including program instructions.
  • the processor 72 is coupled to the memory 71 and the transceiver 73, respectively, for controlling the execution of the program instruction, specifically for acquiring the board type and the reset level to be reset; and generating the first according to the board type and the reset level to be reset. Reset instruction.
  • the transceiver 73 is configured to send the first reset command obtained by the processor 72 to the BBU where the board to be reset is located.
  • the first reset command is used to indicate that the BBU where the board to be reset is located is reset by the board.
  • the BBU where the board to be reset is connected to the network management device is connected to the BBU, and the proxy BBU is a BBU that communicates with the network management device.
  • the proxy BBU is interconnected with the BBU where the board to be reset is located.
  • the processor 72 is further configured to generate reset identification information.
  • the reset identification information is used to indicate whether the first reset instruction is modified.
  • the transceiver 73 is further configured to: when detecting the reset identification information, indicating that the first reset instruction is not modified The first reset command is sent to the BBU where the board to be reset is located.
  • the transceiver 73 is further configured to receive a second reset instruction sent by the network management device.
  • the second reset command includes: a target location information, a board type to be reset, and a reset level.
  • the target location information is used to indicate the location of the outbound board of the BBU where the board to be reset is located.
  • the processor 72 is further configured to obtain a board type and a reset level to be reset from the second reset instruction obtained by the transceiver 73.
  • the device provided by the present invention is applied to a specific example, that is, when the proxy BBU and the BBU where the board to be reset is located are interconnected through the sCPRI link, that is, the physical interconnect line is the sCPRI link, and the first reset command at this time is used.
  • the transceiver 73 is further configured to carry the first reset command in the sCPRI protocol, and send the first reset command to the BBU where the board to be reset is located through the sCPRI link.
  • the type of the board to be reset includes the main control board or the interconnect interface board.
  • the embodiment of the invention provides a single board resetting device of the baseband processing unit, wherein the processor acquires the type of the board to be reset and the reset level, and generates a first reset instruction according to the two kinds of information, and then the transceiver passes the proxy BBU. And the physical interconnect line between the BBU and the BBU where the board to be reset is located.
  • the first reset command is sent to the BBU where the board to be reset is located.
  • the BBU board is reset by using the first reset command, which can solve the problem that the abnormal repair rate of the internal board of the BBU where the board to be reset is low is low.
  • the disclosed system, apparatus, and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the modules or units is only a logical function division.
  • there may be another division manner for example, multiple units or components may be used. Combinations can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as a standalone product, may be stored in a computer readable storage medium.
  • the technical solution of the present invention which is essential or contributes to the prior art, or all or part of the technical solution, may be embodied in the form of a software product stored in a storage medium.
  • a number of instructions are included to cause a computer device (which may be a personal computer, server, or network device, etc.) or a processor to perform all or part of the steps of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes: a USB flash drive, a mobile hard disk, a read-only memory (ROM), and a random access memory (RAM).
  • Random Access Memory A variety of media that can store program code, such as a disk or a disc.
  • a disk or a disc A variety of media that can store program code, such as a disk or a disc.
  • the above is only a specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of changes or substitutions within the technical scope of the present invention. It should be covered by the scope of the present invention. Therefore, the scope of the invention should be determined by the scope of the appended claims.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Small-Scale Networks (AREA)
  • Debugging And Monitoring (AREA)

Abstract

本发明实施例公开了一种基带处理单元的单板复位方法、装置及设备，涉及网络通信技术领域，解决依靠另一BBU才能与传输网络进行通信的BBU内部单板异常修复率低的问题。具体方案为：获取到待复位单板类型和复位级别，并根据这两种信息生成第一复位指令，进而通过代理BBU和待复位单板所在BBU之间的物理互联线，将该第一复位指令发送给待复位单板所在BBU，以指示待复位单板所在BBU进行单板复位。本发明用于BBU的单板复位流程。

Description

一种基带处理单元的单板复位方法、装置及设备
本申请要求于2015年04月08日提交中国专利局、申请号为201510163306.3、发明名称为“一种基带处理单元的单板复位方法、装置及设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及网络通信技术领域，尤其涉及一种基带处理单元的单板复位方法、装置及设备。
背景技术
目前，基带处理单元(Base Band Unit，BBU)可以通过传输网络与网络管理设备进行通信，而两个BBU会采用BBU互联的形式进行通信。其中，BBU互联是指，将两个BBU通过BBU互联信号线进行物理连接。两个BBU的互联可以通过该两个BBU内部单板的互联实现，而内部单板互联可以通过物理互联线实现。比如，当两个BBU互联时，只会有一个BBU可以直接与传输网络进行通信，而另一个BBU想要与传输网络进行通信就只能借助直接与传输网络进行通信的BBU，其自身是不能直接与传输网络进行通信的。
现有每个BBU内部包含多个单板，在实际通信过程中，BBU内部的单板会出现异常，目前，通过进行单板复位来排除BBU内部的单板异常。比如，当上述的必须借助另一个BBU才能与传输网络通信的BBU单板异常时，只有该BBU同时链路故障和业务故障时，启动自复位流程才能进行该BBU内的单板复位。其中，链路故障指的是，两个BBU之间的物理互联线故障，业务故障指的是，该依赖另一BBU才能与传输网络进行通信的BBU网络业务失败。上述的自复位只能对该BBU内的主控单板进行一级复位，并在主控单板进行一级复位之后触发互联接口单板的二级复位。但是这样的复位方式只能排除一部分单板异常，有极大部分单板异 常通过这样的复位方式仍然无法消除。
发明内容
本发明的实施例提供一种基带处理单元的单板复位方法、装置及设备，用于解决依靠另一BBU才能与传输网络进行通信的BBU内部单板异常修复率低的问题。
为达到上述目的，本发明的实施例采用如下技术方案：
本发明实施例的第一方面，提供一种基带处理单元的单板复位方法，待复位单板所在基带处理单元BBU与网管设备通过代理BBU连接，所述代理BBU为与所述网管设备直接进行通信的BBU，所述代理BBU与所述待复位单板所在BBU互联，所述方法包括：
所述代理BBU获取所述待复位单板类型和复位级别；
根据所述待复位单板类型和所述复位级别生成第一复位指令，并通过物理互联线将所述第一复位指令发送给所述待复位单板所在BBU，所述第一复位指令用于指示所述待复位单板所在BBU进行单板复位。
结合第一方面，在第一方面的第一种可能的实现方式中，所述方法还包括：
生成复位识别信息，所述复位识别信息用于指示所述第一复位指令是否被修改；
当检测到所述复位识别信息指示所述第一复位指令未被修改时，将所述第一复位指令通过所述物理互联线发送给所述待复位单板所在BBU。
结合第一方面或第一方面的第一种可能实现方式，在第一方面的第二种可能实现方式中，所述获取待复位单板类型和复位级别包括：
接收所述网管设备发送的第二复位指令，所述第二复位指令包括:目标位置信息、待复位单板类型、复位级别，所述目标位置信息用于指示获取所述待复位单板所在BBU的外联单板的位置；
从所述第二复位指令中获取所述待复位单板类型和所述复位级别。
结合第一方面、第一方面的第一种可能实现方式、第一方面的第二种 可能实现方式，在第一方面的第三种可能实现方式中，当所述物理互联线为类通用公共无线接口sCPRI链路时，所述方法包括：
将所述第一复位指令携带在sCPRI协议中，通过所述sCPRI链路发送给所述待复位单板所在BBU。
结合第一方面、第一方面的第一种可能实现方式、第一方面的第二种可能实现方式、第一方面的第三种可能实现方式，在第一方面的第四种可能实现方式中，所述待复位单板类型包括主控单板或互联接口单板。
本发明实施例的第二方面，提供一种基带处理单元的单板复位装置，所述装置应用于代理基带处理单元BBU，待复位单板所在BBU与网管设备通过所述代理BBU连接，所述代理BBU为与所述网管设备直接进行通信的BBU，所述代理BBU与所述待复位单板所在BBU互联，所述装置包括：
获取单元，用于获取所述待复位单板类型和复位级别；
指令生成单元，用于根据所述获取单元获取的所述待复位单板类型和所述复位级别生成第一复位指令；
指令发送单元，用于通过物理互联线将所述指令生成单元生成的所述第一复位指令发送给所述待复位单板所在BBU，所述第一复位指令用于指示所述待复位单板所在BBU进行单板复位。
结合第二方面，在第二方面的第一种可能的实现方式中，所述装置还包括：
信息生成单元，用于生成复位识别信息，所述复位识别信息用于指示所述第一复位指令是否被修改；
所述指令发送单元，还用于当检测到所述信息生成单元生成的所述复位识别信息指示所述第一复位指令未被修改时，将所述第一复位指令通过所述物理互联线发送给所述待复位单板所在BBU。
结合第二方面或第二方面的第一种可能实现方式，在第二方面的第二种可能实现方式中，所述获取单元包括：
指令接收子单元，用于接收所述网管设备发送的第二复位指令，所述 第二复位指令包括:目标位置信息、待复位单板类型、复位级别，所述目标位置信息用于指示获取待复位单板所在BBU的外联单板的位置；
指令获取子单元，用于从所述指令接收子单元接收的所述第二复位指令中获取所述待复位单板类型和所述复位级别。
结合第二方面、第二方面的第一种可能实现方式、第二方面的第二种可能实现方式，在第二方面的第三种可能实现方式中，所述指令发送单元，用于当所述物理互联线为类通用公共无线接口sCPRI链路时，将所述第一复位指令携带在sCPRI协议中，通过所述sCPRI链路将所述第一复位指令发送给所述待复位单板所在BBU。
结合第二方面、第二方面的第一种可能实现方式、第二方面的第二种可能实现方式、第二方面的第三种可能实现方式，在第二方面的第四种可能实现方式中，所述待复位单板类型包括主控单板或互联接口单板。
本发明实施例的第三方面，提供一种基带处理单元的单板复位设备，，所述设备包括代理基带处理单元BBU，待复位单板所在BBU与网管设备通过所述代理BBU连接，所述代理BBU为与所述网管设备直接进行通信的BBU，所述代理BBU与所述待复位单板所在BBU互联，所述设备包括：
存储器，用于存储包括程序指令的信息；
处理器，用于控制所述程序指令的执行，具体用于，获取待复位单板类型和复位级别；根据所述待复位单板类型和所述复位级别生成第一复位指令；
所述收发器，用于通过物理互联线将所述处理器得到的所述第一复位指令发送给所述待复位单板所在BBU；
所述第一复位指令用于指示所述待复位单板所在BBU进行单板复位。
结合第三方面，在第三方面的第一种可能的实现方式中，所述处理器，还用于生成复位识别信息，所述复位识别信息用于指示所述第一复位指令是否被修改；
所述收发器，还用于当检测到所述复位识别信息指示所述第一复位指 令未被修改时，将所述第一复位指令通过所述物理互联线发送给所述待复位单板所在BBU。
结合第三方面或第三方面的第一种可能实现方式，在第三方面的第二种可能实现方式中，
所述收发器，还用于接收所述网管设备发送的第二复位指令，所述第二复位指令包括:目标位置信息、待复位单板类型、复位级别，所述目标位置信息用于指示获取待复位单板所在BBU的外联单板的位置；
所述处理器，还用于从所述收发器得到的所述第二复位指令中获取所述待复位单板类型和所述复位级别。
结合第三方面、第三方面的第一种可能实现方式、第三方面的第二种可能实现方式，在第三方面的第三种可能实现方式中，
所述收发器，还用于当所述物理互联线为类通用公共无线接口sCPRI链路时，将所述第一复位指令携带在sCPRI协议中，通过所述sCPRI链路发送给所述待复位单板所在BBU。
结合第三方面、第三方面的第一种可能实现方式、第三方面的第二种可能实现方式、第三方面的第三种可能实现方式，在第三方面的第四种可能实现方式中，所述待复位单板类型包括主控单板或互联接口单板。
本发明实施例提供的一种基带处理单元的单板复位方法、装置及设备，由代理BBU获取到待复位单板类型和复位级别，并根据这两种信息生成第一复位指令，进而通过代理BBU和待复位单板所在BBU之间的物理互联线，将该第一复位指令发送给待复位单板所在BBU，以指示待复位单板所在BBU进行单板复位。与现有技术中，在BBU内部的单板会出现异常时，只是通过主控单板自行复位排除部分单板异常相比。本发明实施例提供的技术方案，是通过第一复位指令进行BBU单板复位，能够解决依靠另一BBU才能与传输网络进行通信的BBU内部单板异常修复率低的问题。
附图说明
图1为本发明实施例提供的一种实施基带处理单元单板复位方法的应 用场景示意图；
图1-1为本发明实施例提供的一种复位基带处理单元中单板的方法流程图；
图2为本发明另一实施例提供的一种复位基带处理单元中单板的方法流程图；
图3为本发明另一实施例提供的一种基带处理单元单板内部结构组成示意图；
图4为本发明另一实施例提供的一种复位基带处理单元中单板的方法流程图；
图4-1为本发明另一实施例提供的一种基带处理单元间的通信示意图；
图5为本发明另一实施例提供的一种基带处理单元单板复位装置的结构组成示意图；
图6为本发明另一实施例提供的一种基带处理单元单板复位装置的结构组成示意图；
图7为本发明另一实施例提供的一种基带处理单元单板复位设备的结构组成示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本文中描述的各种技术可用于各种无线通信系统，例如当前2G，3G通信系统和下一代通信系统，例如全球移动通信系统(GSM，Global System for Mobile communications)，码分多址(CDMA，Code Division Multiple Access)系统，时分多址(TDMA，Time Division Multiple Access)系统， 宽带码分多址(WCDMA，Wideband Code Division Multiple Access Wireless)，频分多址(FDMA，Frequency Division Multiple Addressing)系统，正交频分多址(OFDMA，Orthogonal Frequency-Division Multiple Access)系统，单载波FDMA(SC-FDMA)系统，通用分组无线业务(GPRS，General Packet Radio Service)系统，长期演进(LTE，Long Term Evolution)系统，以及其他此类通信系统。
另外，本文中术语“系统”和“网络”在本文中常被可互换使用。本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
本发明实施例提供了一种BBU的单板复位方法，该方法的应用场景中至少包括：两个物理互联的BBU，一个传输网络、一个网管设备。为了更为清楚地描述上述应用场景，以一个具体的场景实例进行说明，如图1所示，在这一场景实例中，两个BBU分别记为BBU0和BBU1，BBU0和BBU1通过物理互联线互联，比如通过类通用公共无线接口(similar Common Public Radio Interface，sCPRI)链路物理互联，BBU1直接接入传输网络与网管设备进行通信，BBU0和BBU1共享传输接口到传输网络与网管设备进行通信，也就是说，BBU0依次通过BBU1、传输网络才能与网管设备建立通信关系。BBU0中的外联单板为通用互联基础单元(Universal inter-Connection Infrastructure Unit，UCIU)，能够与BBU1上的外联单板通用主处理传输单元(Universal Main Processing and Transmission unit，UMPT)进行通信，UCIU为互联接口单板，UMPT为集成了接口互联功能和主控功能的单板，且BBU1通过UMPT单板连接传输网络。在该图1中，BBU0还包括：主控单板UMPT、基带处理器(Base band Processor，BBP)。BBU1还包括：BBP。
值得说明的是，上述的外联单板是指，BBU与外界进行连接通信的单 板，外联单板可以是互联接口单板或者是主控单板。
结合上述描述，在该附图1所示的实例场景中，BBUO与网管设备进行通信的路径为：UMPT(BBU0)<—>UCIU<—>sCPRI链路<—>UMPT(BBU1)<—>传输网络<—>网管设备；BBU1与网管设备进行通信的路径为：UMPT(BBU1)<—>传输网络<—>网管设备。
本发明实施例提供的基带处理单元的单板复位方法，能够对依赖另一BBU才能与传输网络进行通信的BBU(下述已BBU0表示)进行单板复位，且这一执行流程能够对BBU0上的单板灵活复位。并且，在由于一些单板异常导致BBU0与网管设备通信故障时，还能通过这一单板复位流程，实现BBU0与网管设备的再次通信。
本发明实施例提供了一种基带处理单元的单板复位方法，该方法在直接与传输网络进行通信的BBU上执行，以在上述如图1所示的BBU1上执行为例进行说明，如图1-1所示，该方法包括：
01、获取待复位单板类型和复位级别。
其中，待复位单板类型包括主控单板或互联接口单板，复位级别包括一级复位或二级复位。
02、根据待复位单板类型和复位级别生成第一复位指令，并通过物理互联线将第一复位指令发送给待复位单板所在BBU。
其中，第一复位指令用于指示待复位单板所在BBU进行单板复位。
值得说明的是，待复位单板所在BBU与网管设备通过代理BBU连接，该代理BBU为与网管设备直接进行通信的BBU，代理BBU与待复位单板所在BBU互联，且在上述如图1-1所示的方法流程通过该代理BBU执行，待复位单板所在BBU为图1中示出的BBU0，代理BBU即为图1中描述的BBU1。
本发明实施例提供的一种基带处理单元的单板复位方法，由代理BBU获取到待复位单板类型和复位级别，并根据这两种信息生成第一复位指令，进而通过代理BBU和待复位单板所在BBU之间的物理互联线，将该第一复位指令发送给待复位单板所在BBU，以指示待复位单板所在BBU进行单板 复位。与现有技术中，在BBU内部的单板会出现异常时，只是通过主控单板自行复位排除部分单板异常相比。本发明实施例提供的技术方案，是通过第一复位指令进行BBU单板复位，能够解决待复位单板所在BBU内部单板异常修复率低的问题。
结合上述01所描述方法流程，下述将介绍如何获取待复位单板类型和复位级别，具体包括：
第一步：接收网管设备发送的第二复位指令。
其中，第二复位指令包括:目标位置信息、待复位单板类型、复位级别，且目标位置信息用于指示获取待复位单板所在BBU的外联单板的位置。
在本实现方式中，涉及的第二复位指令在代理BBU中被转换为上述描述的第一复位指令，经过这一转换流程后，使得第一复位指令能够通过物理互联线发送给待复位单板所在BBU。
值得说明的是，在本实施例中目标位置信息用于指示获取待复位单板所在BBU的，而这一位置信息是由网管设备侧添加到第二复位指令进去的，待复位单板所在BBU为BBU0，而能够直接通过传输网络与该网管设备进行通信的是BBU1，所以这一目标位置信息，不仅包括BBU1的地址，还包括BBU1与BBU0互联的接口地址，这样才能使得网管设备发出的第二复位指令能够指示BBU0进行单板复位。
第二步：从第二复位指令中获取待复位单板类型和复位级别。
下述将从接收第二复位指令到生成并发送第一复位指令的过程进行完整描述，如图2所示，这一方法具体包括：
101、接收网管设备发送的第二复位指令。
102、根据第二复位指令中的待复位单板类型和复位级别生成第一复位指令。
103、通过物理互联线将第一复位指令发送给待复位单板所在BBU。
本发明实施例提供的一种基带处理单元的单板复位方法，由代理BBU获取到待复位单板类型和复位级别，并根据这两种信息生成第一复位指令， 进而通过代理BBU和待复位单板所在BBU之间的物理互联线，将该第一复位指令发送给待复位单板所在BBU，以指示待复位单板所在BBU进行单板复位。与现有技术中，在BBU内部的单板会出现异常时，只是通过主控单板自行复位排除部分单板异常相比。本发明实施例提供的技术方案，是通过第一复位指令进行BBU单板复位，能够解决待复位单板所在BBU内部单板异常修复率低的问题。
本发明实施例提供了一种基带处理单元的单板复位方法，结合上述如图2所示的方法流程中，在本发明实施例的一种实现方式中，就上述的步骤102作出详细说明，即在本实现方式中，详细介绍了代理BBU生成第一复位指令的实现流程，具体包括：
第一复位指令需要用于在BBU之间传输，则该第二复位指令需要符合sCPR协议，即将待复位单板类型和复位级别添加到sCPRI协议中，在该sCPRI协议中生成第一复位指令。
也就是说，该第一复位指令是携带在sCPRI协议中，进而才能够通过BBU之间的物理互联线sCPRI链路传输。
值得说明的是，在本实施例的一种可选实现方式中，第一复位指令携带在sCPRI协议中，并通过sCPRI链路发送给BBU0，而sCPRI协议在BBU之间实时传输，为了保证BBU0中的外联单板能够识别出携带复位指令的协议，在该第二复位指令中还可以包括：复位标识。该复位标识用于指示BBU0中的单板是否需要进行实际复位，该复位标识可以使用“0”、“1”标识，且可以设置“0”表示BBU0无需根据第二复位指令进行单板复位，“1”表示BBU0需要根据第二复位指令进行单板复位。这样BBU0就能够及时准确的识别出是否需要对sCPRI协议中的复位指令字段进行解析。
结合本实施例所提供的实现方式，在进行BBU单板复位过程中，只需要依赖BBU之间的物理互联通道的物理层进行通信，不必考虑应用层是否正常工作，即只要两个BBU物理互联线正常，就能够实现对待复位单板所在BBU进行单板复位。
本发明实施例提供了基带处理单元的单板复位方法的另一种实现方式，在本实施例中，BBU1可以在生成第二复位指令时，还可以生成复位识别信息，该复位识别信息作用于代理BBU内部，该复位识别信息用于指示生成的第二复位指令是否被修改。当复位识别信息指示第一复位指令未被修改时，则将第一复位指令通过物理互联线发送给待复位单板所在BBU；如果指令被修改，仍然将被修改后的第二复位指令发送给BBU0，就会出现BBU0误复位,造成资源浪费。
结合图1中所描述的示意场景，如图3所示，在BBU1中的UMPT单板内部，至少存在中央处理器(Central Processing Unit，CPU)和现场可编程门阵列(Field Programmable Gate Array，FPGA)两个模块，FPGA主要负责复位控制信息的传输通信，CPU主要负责复位的操作和执行，而在本实施例中涉及的复位识别信息是在该FPGA与CPU之间进行传递的，具体的实现流程为：
1、UMPT(BBU1)的CPU接收到网管设备发送的第二复位指令。
2、UMPT的CPU对该第二复位指令进行转换，生成第一复位指令携带在sCPRI协议中。
值得说明的是，该第一复位指令为符合sCPRI协议中的一个复位控制字段。
3、CPU生成复位识别信息，并将该复位识别信息发送给FPGA。
其中，复位识别信息与第一复位指令是一一对应，也可以只是个数对应，比如，在发送3个复位指令时，相应的生成3个复位标识信息，但是这3个复位标识信息的内容相同。
值得说明的是，这里描述的是，按照步骤2、3的顺序执行，但是在具体的实现过程中，并不限定该步骤2、3的执行顺序，该步骤3与上述的步骤2可以同时执行，或者步骤3在步骤2之前执行。且在实现过程中，CPU需要将该第一复位指令和复位标识信息同时下发给FPGA，这样才能通过复位识别信息来检验本次发送的第一复位指令。
4、FPGA在接收到复位标识信息之后，检测该复位标识信息是否符合预定格式。
值得说明的是，该预定格式可以是BBU1内的CPU与BBU1内的FPGA协商确定，或者由CPU确定并告知FPGA，复位识别信息满足这一预定格式，则指示第一复位指令未被修改；否则，则表示第一复位指令已经被修改。
进一步的对该复位识别信息的检测结果包括下述两种：
第一种结果：复位识别信息符合预定格式，则表明FPGA接收到的第一复位指令未被修改，则继续执行下述步骤5。
第二种结果：复位识别信息不符合预定格式，则表明FPGA接收到的第二复位指令已经被修改，执行下述步骤6。
5、FPGA将第一复位指令携带在sCPRI协议中，并将sCPRI协议复位控制字段发送UCIU(BBU0)中的FPGA。
6、FPGA将本地存储的默认不复位的信息携带在sCPRI协议中，并将sCPRI协议发送到UCIU(BBU0)中的FPGA。
结合上述步骤3-6的描述，为了确保UMPT(BBU1)中的FPGA发送正确的第二复位指令，所以添加上述复位识别信息。
7、UCIU(BBU0)中的FPGA将sCPRI协议发送给UCIU中的CPU，由UCIU中的CPU进行解析。
本发明实施例的另一种实现方式中提供了一种基带处理单元的单板复位方法，结合上述如图1所示的方法流程中，本实现方式对上述步骤103进行了详细描述：
在代理BBU将第一复位指令发送给待复位单板所在BBU时，具体是将第一复位指令由代理BBU的外联单板通过物理互联线发送给待复位单板所在BBU的外联单板。
在本实现方式中，复位指令通过物理互联线发送，物理互联属于两个BBU之间的物理层通信，这时第一复位指令的传输并不需要考虑BBU之间的应用层等上层通信是否正常，就可以排除待复位单板所在BBU的单板故障， 显著提高了单板故障的修复成功率。而且将复位指令直接通过物理互联线传输，从而就不必要求工作人员直接到待复位单板所在BBU站点，进行故障修复，这样也极大的节约了成本，减少了修复时间，也就必然减少了基站故障后的中断时间。
值得说明的是，在本实施例中，一条第一复位指令指示待复位单板所在BBU中的一个单板进行单板复位，这一单板可以是主控单板或者互联接口单板。
当第一复位指令指示主控单板进行一级复位时，待复位单板所在BBU对该主控单板进行一级复位，并同时自行对接口外联单板进行二级复位。
但是，当第一复位指令指示主控单板进行二级复位，或者第一复位指令指示接口外联单板进行一级复位或者二级复位时，待复位单板所在BBU只针对相应的单板进行相应级别的复位，不再自行进行连带复位。
此外，值得说明的是，本实施例提供的技术方案中，待复位单板所在BBU在根据第一复位指令中包含的待复位单板类型和/或复位级别进行单板复位后，并未完成故障修复，此时网管设备同时能够检测到原待复位单板所在BBU仍然处于故障状态，从而会按照上述流程再次发送第一复位指令，指示待复位单板所在BBU进行二次复位，直到故障排除为止。
为了更为详细的本发明实施例提供的基带处理单元单板复位方法的执行流程，本实施例将介绍完整的复位流程，且以上述附图1所示的应用场景是本实施例技术方案的执行场景为例，如图4所示，这一具体的执行流程包括：
401、网管设备检测BBU0和BBU1是否正常连接。
结合上述附图1所示的连接结构，本步骤中网管设备的检测即检测上述描述的BBU0和BBU1与网管设备之间的通信链路是否能够正常通信。在本实施例中，其中，BBU0上的UCIU为互联接口单板，UMPT为主控单板(同时有互联接口单板的功能)BBU1上UMPT同时具备互联接口单板和主控单板的功能，可称为代理单板，本实施例涉及的对基带处理单元的修复指对BBU0 上的UCIU或UMPT的修复。
值得说明的是，在本实施所提供技术方案的执行过程中，BBU0和BBU1之间的sCPRI链路能够正常通信，且BBU1与网管设备间的通信链路正常通信，BBU1内部的UMPT单板正常工作。
进一步的在检测到BBU0未能与网管设备连接时，执行下述步骤402，而在上述步骤401的检测结果均正常的情况下，说明BBU0和BBU1能够与网管设备正常通信，本实施例对这种情况不再进行说明。
402、网管设备会显示故障告警信息。
403、网管设备通过人机语言(man-machine language，MML)人机接口，接收用户输入的指令。
其中，用户输入的指令即为上述描述的第二复位指令，相关内容描述相同，在此不再重复说明，且在后续步骤中，将通过第二复位指令描述该用户输入的指令。
404、网管设备将第二复位指令通过传输网络传递到BBU1的UMPT单板的FPGA上。
该步骤中的第二复位指令的传输，通过BBU1与网管设备之间的传输路径实现，在上述对附图1介绍时，已经对该传输路径进行了说明，在此不再重复说明。
405、BBU1上的UMPT单板中的CPU实现第二复位指令到复位控制字段之间的转换。
值得说明的是，该复位控制字段可以按位(BIT)定义，具体定义如下：
位0(bit0)：是否进行单板复位，包括是、否；
位1(bit1)：待复位单板类型，包括互联接口单板或主控单板；
位2(bit2)：复位级别，包括一级复位或二级复位。
值得说明的是，上述对复位控制字段定义只是本实施中对复位信息的一种定义形式的举例，对于通过哪一个数位或者通过什么形式表示在本实 施例中不做限定。本实施例中涉及的复位控制字段即上述描述的第一复位指令，表示是否进行单板复位的位0即为上述复位标识。
此外值得说明的是，在本实施例中复位控制字段是sCPRI协议中的一个字段，如下表1所示，在该表中描述了sCPRI协议的部分内容。
表1
Figure PCTCN2016078609-appb-000001
值得说明的是，上述表1描述的内容示出了sCPRI协议的部分内容，在除去上述表格中用加粗字体标明的“复位控制字段”之外，均为该协议的现有内容，在本实施例中不再对相其余部分作出说明，且上述表格中示出的“reserved”位置标示的是保留字段，在这些保留字段的位置均可以添加复位控制字段，但是在上述表格所示的添加位置，该位置所在的行列 为控制BBU之间通信的位置，所以在本处添加能够缩短待复位单板所在BBU中单板的解析时间，从而提高单板复位的效率。
406、BBU1中的CPU生成复位识别信息，并发送给BBU1中的FPGA。
407、当FPGA检测到复位识别信息符合预设格式时，将复位控制字段发送给BBU0中UCIU的FPGA。
值得说明的是，BBU1与BBU0之间实现通信，实际是BBU0的外联单板(UCIU)与BBU1中的外联单板(UMPT)中的FPGA之间进行的通信，在各自单板的FPGA中存在多个接口能够与外界连接，为了更为清楚描述两个外联单板之间的通信关系，用图示的方法进行说明.在附图4-1中，BBU0中外联单板构造与图3中示出的BBU1中的UMPT的单板构造相同，在具体实现过程中，是BBU0中UCIU中的FPGA与BBU1中UMPT中的FPGA通过sCPRI链路进行互联。
此外值得说明的是，本实施例中步骤406和步骤407，上述步骤3-6中相关内容描述对应相同。且当FPGA检测到复位标识信息不符合预设格式时，将本地存储的默认不复位的信息发送给BBU0中的FPGA。本实施例中对这一情况将不再进行说明。
在本实施例中涉及的复位控制字段即为上述描述的第一复位指令。
408、UCIU中的FPGA将第一复位指令发送给UCIU中的CPU。
409、UCIU中的CPU对第一复位指令进行解析，获取到该第一复位指令中包括的待复位单板类型和复位级别，并进行单板复位。
当待复位单板类型为：互联接口单板时，在UCIU中进行单板复位，当待复位单板类型为主控单板时，通过UCIU中的FPGA将解析后的复位指令发送到主控单板即本实施例中涉及的UMPT上，并在UMPT上进行单板复位。
值得说明的是，在实际应用过程中，BBU之间的连接方式是多样的，只要是两个具备互联接口功能的单板之间均可。比如，仍然是以图1中示出的BBU0和BBU1为例说明，可以是UCIU(BBU0)和UMPT(BBU1)进行连接， 或者是UMPT(BBU0)和UMPT(BBU1)进行连接，或者是UMPT(BBU1)与UMPT(BBU0)进行互联，无论是哪一种互联形式与上述附图1中示出的互联形式相同，只要是通过sCPRI链路实现互联，无论是哪种形式的互联其具体实现形式相同，在此不再重复说明。
此外，在具体实现过程中，会出现只有BBU0连接外网的情况，此时通过上述方法能够修复BBU1上的单板故障；还会出现BBU1与BBU0同时连接外部传输网络的情况，此时通过上述方法，可以由BBU0连接的网管设备0修复BBU1上的单板故障，由BBU1连接的网管设备1修复BBU0上的单板故障(也就是上述附图1所示出的情况)。当然的，在实际应用过程中，网管设备也可以修复直接与其连接的BBU上的单板故障，以上述附图1中示出的示例说明，网管设备可以直接将复位指令发送给BBU1,实现BBU1上的单板复位，在BBU1接收到网管设备发送的复位指令后，其后续的执行流程与BBU0接收到BBU1发送的第一复位指令后的执行流程相同，对此不再重复说明。
此外值得说明的是，本发明是通过BBU之间的物理互联线传输复位指令，进而对待复位单板所在BBU进行单板复位。在BBU互联的实际实现过程中，存在多种互联形式，每一种互联形式有相对应的在BBU之间的传输协议，BBU之间传输复位指令需要符合BBU之间的传输协议。在本发明所给出的实施例中以BBU之间通过sCPRI链路进行物理互联为例进行说明，BBU通过其余形式进行物理互联时，相应的执行流程类似，在本发明实施例中不再进行说明。
具体的在BBU之间通过sCPRI链路互联情况下，在本发明实施例所提供方案的具体实现过程中，是在网管设备检测到BBU0故障时后，能够将复位指令发送给UMPT(BBU1)，并在UMPT对这一指令进行转换,而后由UMPT通过sCPRI链路发送给UCIU(BBU0)，最终由UCIU解析转换后的复位指令，并通过复位指令进行单板复位，以排除BBU0故障，实现BBU0与网管设备的再次通信。
本发明另一实施例提供了一种基带处理单元的单板复位装置，该装置应用于代理BBU，如图5所示，这一装置包括：获取单元51、指令生成单元52、指令发送单元53。
获取单元51，用于获取待复位单板类型和复位级别。
指令生成单元52，用于根据获取单元51获取的待复位单板类型和复位级别生成第一复位指令。
指令发送单元53，用于通过物理互联线将指令生成单元52生成的第一复位指令发送给待复位单板所在BBU。
其中，第一复位指令用于指示待复位单板所在BBU进行单板复位。
值得说明的是，待复位单板所在BBU与网管设备通过代理BBU连接，代理BBU为与网管设备直接进行通信的BBU，且代理BBU与待复位单板所在BBU互联。
在本发明另一实施例中，提供了一种基带处理单元的单板复位装置的可能构成方式，如图6所示，该装置还包括：信息生成单元54；获取单元51包括：指令接收子单元511、指令获取子单元512。
信息生成单元54，用于生成复位识别信息。
其中，复位识别信息用于指示第一复位指令是否被修改。
指令发送单元53，还用于当检测到信息生成单元54生成的复位识别信息指示第一复位指令未被修改时，将第一复位指令通过物理互联线发送给待复位单板所在BBU。
获取单元51包括：指令接收子单元511、指令获取子单元512。
指令接收子单元511，用于接收网管设备发送的第二复位指令。
其中，第二复位指令包括:目标位置信息、待复位单板类型、复位级别，该目标位置信息用于指示获取待复位单板所在BBU的外联单板的位置。
指令获取子单元512，用于从指令接收子单元511接收的第二复位指令中获取待复位单板类型和复位级别。
在本发明的另一种实现方式中，指令发送单元53，还用于当物理互联 线为sCPRI链路时，将第一复位指令携带在sCPRI协议中，通过sCPRI链路将所述第一复位指令发送给待复位单板所在BBU。
值得说明的是，该如图5和如图6所示的装置，用于复位基带处理单元中的单板，且待复位单板类型包括主控单板或互联接口单板。
此外，值得说明的是，上述图5、图6所示的装置，可用于实现图1-1至图4所示的方法流程，且能够适用于图1-1和图4-1所示的场景示意图，为了便于说明，仅示出了与本发明实施例相关的部分，具体技术细节未揭示的，请参照图1至图4所示的本发明各实施例的相关内容描述。
本发明实施例提供了一种基带处理单元的单板复位装置，该装置置于代理BBU，由获取单元获取到待复位单板类型和复位级别，并通过指令生成单元根据这两种信息生成第一复位指令，进而由指令发送单元凭借代理BBU和待复位单板所在BBU之间的物理互联线，将该第一复位指令发送给待复位单板所在BBU，以指示待复位单板所在BBU进行单板复位。与现有技术中，在BBU内部的单板会出现异常时，只是通过主控单板自行复位排除部分单板异常相比。本发明实施例提供的技术方案，是通过第一复位指令进行BBU单板复位，能够解决待复位单板所在BBU内部单板异常修复率低的问题。
本发明另一实施例提供了一种基带处理单元的单板复位设备，如图7所示，这一设备包括：存储器71、处理器72、收发器73，存储器71、处理器72和收发器73通过总线74连接，可相互进行数据传输，且这一设备可以为代理BBU。
存储器71可以是只读存储器(Read Only Memory，ROM)，静态存储设备，动态存储设备或者随机存取存储器(Random Access Memory，RAM)。存储器71可以存储操作系统和其他应用程序。在通过软件或者固件来实现本发明实施例提供的技术方案时，用于实现本发明实施例提供的技术方案的程序代码保存在存储器71中，并由处理器72来执行。
收发器73用于装置与其他设备或通信网络(例如但不限于以太网， 无线接入网(Radio Access Network，RAN)，无线局域网(Wireless Local Area Network，WLAN)等)之间的通信。
处理器72可以采用通用的中央处理器(Central Processing Unit，CPU)，微处理器，应用专用集成电路(Application Specific Integrated Circuit，ASIC)，或者一个或多个集成电路，用于执行相关程序，以实现本发明实施例所提供的技术方案。
总线74可包括一通路，在装置各个部件(例如存储器71、收发器73和处理器72)之间传送信息。
应注意，尽管图7所示的硬件仅仅示出了存储器71、处理器72和收发器73以及总线74，但是在具体实现过程中，本领域的技术人员应当明白，该设备还包含实现正常运行所必须的其他器件。同时，根据具体需要，本领域的技术人员应当明白，还可包含实现其他功能的硬件器件。
具体的，图7所示的基站用于实现图5-图6实施例所示的装置时，
存储器71，用于存储包括程序指令的信息。
处理器72，分别与存储器71和收发器73耦合，用于控制所述程序指令的执行，具体用于，获取待复位单板类型和复位级别；根据待复位单板类型和复位级别生成第一复位指令。
收发器73，用于通过物理互联线将处理器72得到的第一复位指令发送给待复位单板所在BBU。
其中，第一复位指令用于指示待复位单板所在BBU进行单板复位。
在本实施例中，待复位单板所在BBU与网管设备通过代理BBU连接，该代理BBU为与网管设备直接进行通信的BBU，且代理BBU与待复位单板所在BBU互联。
在本实施例提供设备的另一种构成形式中，
处理器72，还用于生成复位识别信息。
其中，复位识别信息用于指示第一复位指令是否被修改。
收发器73，还用于当检测到复位识别信息指示第一复位指令未被修改 时，将第一复位指令通过所述物理互联线发送给待复位单板所在BBU。
在本发明提供实施例的另一种实现方式中，收发器73，还用于接收网管设备发送的第二复位指令。
其中，第二复位指令包括:目标位置信息、待复位单板类型、复位级别，这里的目标位置信息用于指示获取待复位单板所在BBU的外联单板的位置。
处理器72，还用于从收发器73得到的第二复位指令中获取待复位单板类型和复位级别。
将本发明提供的设备，应用于一个具体实例中，即当代理BBU和待复位单板所在BBU通过sCPRI链路互联时，即此时物理互联线为sCPRI链路，此时的第一复位指令符合sCPRI协议，则收发器73，还用于将第一复位指令携带在sCPRI协议中，通过sCPRI链路将第一复位指令发送给待复位单板所在BBU。
值得说明的是，在本实施例中，涉及的待复位单板类型包括主控单板或互联接口单板。
此外值得说明的是，上述图7所示的设备，用于执行图1-1至图4所示的方法流程。
本发明实施例提供了一种基带处理单元的单板复位设备，由处理器获取到待复位单板类型和复位级别，并根据这两种信息生成第一复位指令，进而由收发器通过代理BBU和待复位单板所在BBU之间的物理互联线，将该第一复位指令发送给待复位单板所在BBU，以指示待复位单板所在BBU进行单板复位。与现有技术中，在BBU内部的单板会出现异常时，只是通过主控单板自行复位排除部分单板异常相比。本发明实施例提供的技术方案，是通过第一复位指令进行BBU单板复位，能够解决待复位单板所在BBU内部单板异常修复率低的问题。
通过以上的实施方式的描述，所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，仅以上述各功能模块的划分进行举例说明，实 际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将装置的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。上述描述的系统，装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统，装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述模块或单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)或处理器(processor)执行本发明各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM， Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种基带处理单元的单板复位方法，其特征在于，待复位单板所在基带处理单元BBU与网管设备通过代理BBU连接，所述代理BBU为与所述网管设备直接进行通信的BBU，所述代理BBU与所述待复位单板所在BBU互联，所述方法包括：
    所述代理BBU获取所述待复位单板类型和复位级别；
    根据所述待复位单板类型和所述复位级别生成第一复位指令，并通过物理互联线将所述第一复位指令发送给所述待复位单板所在BBU，所述第一复位指令用于指示所述待复位单板所在BBU进行单板复位。
  2. 根据权利要求1所述的方法，其特征在于，所述方法还包括：
    生成复位识别信息，所述复位识别信息用于指示所述第一复位指令是否被修改；
    当检测到所述复位识别信息指示所述第一复位指令未被修改时，将所述第一复位指令通过所述物理互联线发送给所述待复位单板所在BBU。
  3. 根据权利要求1或2所述的方法，其特征在于，所述获取待复位单板类型和复位级别包括：
    接收所述网管设备发送的第二复位指令，所述第二复位指令包括:目标位置信息、待复位单板类型、复位级别，所述目标位置信息用于指示获取所述待复位单板所在BBU的外联单板的位置；
    从所述第二复位指令中获取所述待复位单板类型和所述复位级别。
  4. 根据权利要求3所述的方法，其特征在于，当所述物理互联线为类通用公共无线接口sCPRI链路时，所述方法包括：
    将所述第一复位指令携带在sCPRI协议中，通过所述sCPRI链路发送给所述待复位单板所在BBU。
  5. 根据权利要求4所述的方法，其特征在于，所述待复位单板类型包括主控单板或互联接口单板。
  6. 一种基带处理单元的单板复位装置，其特征在于，所述装置应用 于代理基带处理单元BBU，待复位单板所在BBU与网管设备通过所述代理BBU连接，所述代理BBU为与所述网管设备直接进行通信的BBU，所述代理BBU与所述待复位单板所在BBU互联，所述装置包括：
    获取单元，用于获取所述待复位单板类型和复位级别；
    指令生成单元，用于根据所述获取单元获取的所述待复位单板类型和所述复位级别生成第一复位指令；
    指令发送单元，用于通过物理互联线将所述指令生成单元生成的所述第一复位指令发送给所述待复位单板所在BBU，所述第一复位指令用于指示所述待复位单板所在BBU进行单板复位。
  7. 根据权利要求6所述的装置，其特征在于，所述装置还包括：
    信息生成单元，用于生成复位识别信息，所述复位识别信息用于指示所述第一复位指令是否被修改；
    所述指令发送单元，还用于当检测到所述信息生成单元生成的所述复位识别信息指示所述第一复位指令未被修改时，将所述第一复位指令通过所述物理互联线发送给所述待复位单板所在BBU。
  8. 根据权利要求6或7所述的装置，其特征在于，所述获取单元包括：
    指令接收子单元，用于接收所述网管设备发送的第二复位指令，所述第二复位指令包括:目标位置信息、待复位单板类型、复位级别，所述目标位置信息用于指示获取待复位单板所在BBU的外联单板的位置；
    指令获取子单元，用于从所述指令接收子单元接收的所述第二复位指令中获取所述待复位单板类型和所述复位级别。
  9. 根据权利要求8所述的装置，其特征在于，
    所述指令发送单元，用于当所述物理互联线为类通用公共无线接口sCPRI链路时，将所述第一复位指令携带在sCPRI协议中，通过所述sCPRI链路将所述第一复位指令发送给所述待复位单板所在BBU。
  10. 根据权利要求9所述的装置，其特征在于，所述待复位单板类型 包括主控单板或互联接口单板。
  11. 一种基带处理单元的单板复位设备，其特征在于，所述设备包括代理基带处理单元BBU，待复位单板所在BBU与网管设备通过所述代理BBU连接，所述代理BBU为与所述网管设备直接进行通信的BBU，所述代理BBU与所述待复位单板所在BBU互联，所述设备包括：
    存储器，用于存储包括程序指令的信息；
    处理器，用于控制所述程序指令的执行，具体用于，获取待复位单板类型和复位级别；根据所述待复位单板类型和所述复位级别生成第一复位指令；
    所述收发器，用于通过物理互联线将所述处理器得到的所述第一复位指令发送给所述待复位单板所在BBU；
    所述第一复位指令用于指示所述待复位单板所在BBU进行单板复位。
  12. 根据权利要求11所述的设备，其特征在于，
    所述处理器，还用于生成复位识别信息，所述复位识别信息用于指示所述第一复位指令是否被修改；
    所述收发器，还用于当检测到所述复位识别信息指示所述第一复位指令未被修改时，将所述第一复位指令通过所述物理互联线发送给所述待复位单板所在BBU。
  13. 根据权利要求11或12所述的设备，其特征在于，
    所述收发器，还用于接收所述网管设备发送的第二复位指令，所述第二复位指令包括:目标位置信息、待复位单板类型、复位级别，所述目标位置信息用于指示获取待复位单板所在BBU的外联单板的位置；
    所述处理器，还用于从所述收发器得到的所述第二复位指令中获取所述待复位单板类型和所述复位级别。
  14. 根据权利要求13所述的设备，其特征在于，
    所述收发器，还用于当所述物理互联线为类通用公共无线接口sCPRI链路时，将所述第一复位指令携带在sCPRI协议中，通过所述sCPRI链路 发送给所述待复位单板所在BBU。
  15. 根据权利要求14所述的设备，其特征在于，所述待复位单板类型包括主控单板或互联接口单板。
PCT/CN2016/078609 2015-04-08 2016-04-06 一种基带处理单元的单板复位方法、装置及设备 WO2016161938A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510163306.3 2015-04-08
CN201510163306.3A CN104753723B (zh) 2015-04-08 2015-04-08 一种基带处理单元的单板复位方法、装置及设备

Publications (1)

Publication Number Publication Date
WO2016161938A1 true WO2016161938A1 (zh) 2016-10-13

Family

ID=53592871

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/078609 WO2016161938A1 (zh) 2015-04-08 2016-04-06 一种基带处理单元的单板复位方法、装置及设备

Country Status (2)

Country Link
CN (1) CN104753723B (zh)
WO (1) WO2016161938A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113115478A (zh) * 2021-04-16 2021-07-13 网络通信与安全紫金山实验室 空口数据的获取方法、装置及bbu

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104753723B (zh) * 2015-04-08 2018-04-20 华为技术有限公司 一种基带处理单元的单板复位方法、装置及设备
CN108322324B (zh) * 2017-01-18 2022-05-24 中兴通讯股份有限公司 一种端站复位方法和装置
CN108152746B (zh) * 2017-12-14 2021-05-25 郑州云海信息技术有限公司 一种检测备用电源组电池活性的方法及系统

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101159933A (zh) * 2005-05-19 2008-04-09 华为技术有限公司 分体式基站系统及其组网方法和基带单元
CN101257668A (zh) * 2005-06-23 2008-09-03 华为技术有限公司 一种识别基带单元的方法
CN102970699A (zh) * 2012-11-09 2013-03-13 大唐移动通信设备有限公司 一种故障处理方法及分布式基站
CN103916895A (zh) * 2013-01-06 2014-07-09 中兴通讯股份有限公司 一种基站基带单元保护射频拉远单元功放的方法及系统
CN104753723A (zh) * 2015-04-08 2015-07-01 华为技术有限公司 一种基带处理单元的单板复位方法、装置及设备

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100343816C (zh) * 2004-09-24 2007-10-17 华为技术有限公司 恢复单板软件版本的方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101159933A (zh) * 2005-05-19 2008-04-09 华为技术有限公司 分体式基站系统及其组网方法和基带单元
CN101257668A (zh) * 2005-06-23 2008-09-03 华为技术有限公司 一种识别基带单元的方法
CN102970699A (zh) * 2012-11-09 2013-03-13 大唐移动通信设备有限公司 一种故障处理方法及分布式基站
CN103916895A (zh) * 2013-01-06 2014-07-09 中兴通讯股份有限公司 一种基站基带单元保护射频拉远单元功放的方法及系统
CN104753723A (zh) * 2015-04-08 2015-07-01 华为技术有限公司 一种基带处理单元的单板复位方法、装置及设备

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113115478A (zh) * 2021-04-16 2021-07-13 网络通信与安全紫金山实验室 空口数据的获取方法、装置及bbu
CN113115478B (zh) * 2021-04-16 2022-07-26 网络通信与安全紫金山实验室 空口数据的获取方法、装置及bbu

Also Published As

Publication number Publication date
CN104753723B (zh) 2018-04-20
CN104753723A (zh) 2015-07-01

Similar Documents

Publication Publication Date Title
US9445286B2 (en) Protocol version negotiation method, mobile terminal, base station and communications system
US11019536B2 (en) Communication method and apparatus
WO2016161938A1 (zh) 一种基带处理单元的单板复位方法、装置及设备
US10972362B2 (en) Network service configuration method and network management device
CN106603581B (zh) 支持多种通信协议的测试方法及装置
US10609633B2 (en) Method for triggering registrar protocol interaction, access point, and station
EP3490304A1 (en) Method for identifying access point and hotspot, and related product
JP2017510169A5 (zh)
BR112014024866B1 (pt) Métodos para obter minimização de terminal de dados de testes de unidade, elemento de rede e operação, administração e manutenção
EP3099011A1 (en) Interface management service entity, functional service entity and network element management method
EP3734870A1 (en) Notification method and device for execution of pdcp data recovery
CN104486146A (zh) 一种测试控制台与测试设备之间的通信方法
WO2016086890A1 (zh) 一种检测连通性的方法和装置
US20170134999A1 (en) Method and apparatus for allocating d2d resource in a handover procedure and communication system
EP3306872A1 (en) Method and apparatus for exploring fronthaul topology
CN107484214B (zh) 物联网接入点频点选择方法及装置
US9686128B2 (en) Wireless network adapter and self-configuration method of same
CN111200519B (zh) 数据处理方法、装置、bbu、接入网设备和存储介质
CN112399446A (zh) 边缘网关通信方法、装置、计算机设备和存储介质
US20220052902A1 (en) Method for managing remote device through management device
US20240154874A1 (en) Bare metal detection method and system, and related component
US20150334047A1 (en) Initiator terminal, target terminal, method of interrupting access of initiator terminal, and method of interrupting access of target terminal
CN105049294A (zh) Eaps协议master交换机端口状态切换的自动化测试方法
EP2506614B1 (en) Method, apparatus and computer program product for security configuration coordination during a cell update procedure
US20180331881A1 (en) Embedded Device Identification Information in Packetized Communications

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16776113

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16776113

Country of ref document: EP

Kind code of ref document: A1