WO2016157487A1 - Buzzer sounding device - Google Patents

Buzzer sounding device Download PDF

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Publication number
WO2016157487A1
WO2016157487A1 PCT/JP2015/060399 JP2015060399W WO2016157487A1 WO 2016157487 A1 WO2016157487 A1 WO 2016157487A1 JP 2015060399 W JP2015060399 W JP 2015060399W WO 2016157487 A1 WO2016157487 A1 WO 2016157487A1
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WO
WIPO (PCT)
Prior art keywords
buzzer
voltage signal
transistor
switch circuit
circuit
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Application number
PCT/JP2015/060399
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French (fr)
Japanese (ja)
Inventor
琢磨 青島
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to PCT/JP2015/060399 priority Critical patent/WO2016157487A1/en
Priority to JP2017509099A priority patent/JP6425799B2/en
Publication of WO2016157487A1 publication Critical patent/WO2016157487A1/en

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    • G—PHYSICS
    • G10—MUSICAL INSTRUMENTS; ACOUSTICS
    • G10K—SOUND-PRODUCING DEVICES; METHODS OR DEVICES FOR PROTECTING AGAINST, OR FOR DAMPING, NOISE OR OTHER ACOUSTIC WAVES IN GENERAL; ACOUSTICS NOT OTHERWISE PROVIDED FOR
    • G10K9/00—Devices in which sound is produced by vibrating a diaphragm or analogous element, e.g. fog horns, vehicle hooters or buzzers
    • G10K9/12—Devices in which sound is produced by vibrating a diaphragm or analogous element, e.g. fog horns, vehicle hooters or buzzers electrically operated
    • G10K9/122—Devices in which sound is produced by vibrating a diaphragm or analogous element, e.g. fog horns, vehicle hooters or buzzers electrically operated using piezoelectric driving means

Definitions

  • the present invention relates to a buzzer sounding device that sounds a buzzer formed using a piezoelectric element.
  • a buzzer formed using a piezoelectric element is known. Such a buzzer is mounted on devices including portable communication terminals, home appliances, and OA devices.
  • a device equipped with a buzzer is provided with a buzzer sounding device for sounding the buzzer.
  • the buzzer sounding device is provided with a buzzer sounding circuit connected to the buzzer.
  • Patent Document 1 describes a buzzer sounding circuit in which a plurality of switching transistors are provided and a voltage is applied to the buzzer by individually controlling on / off of the plurality of transistors.
  • Patent Document 2 describes a buzzer sounding circuit that applies a voltage to a buzzer using a push-pull circuit having an inverter IC.
  • the present invention has been made in view of the above, and an object thereof is to obtain a buzzer sounding device capable of maintaining the volume of a buzzer during steady driving and standby.
  • the present invention provides a buzzer formed using a piezoelectric element, a buzzer sounding circuit having a first switch circuit and a second switch circuit connected to the buzzer, A power supply circuit for supplying a voltage having a first voltage value to the common terminal connected to the buzzer sounding circuit during steady driving and supplying a voltage having a second voltage value smaller than the first voltage value during standby;
  • the switch circuit and the second switch circuit For the switch circuit and the second switch circuit, the positive voltage signal of the first voltage value and the positive / negative reference value voltage signal are alternately applied to the buzzer during steady driving, and the positive / negative of the second voltage value is applied to the buzzer during standby.
  • a control circuit for alternately applying either one of the voltage signal and the other voltage signal of the third voltage value smaller than the first voltage value.
  • FIG. 1 The block diagram which shows the circuit of the buzzer ringing apparatus which concerns on Embodiment 1.
  • FIG. The graph which shows the relationship between the voltage value applied to the buzzer which concerns on Embodiment 1, and time at the time of steady driving and standby
  • the block diagram which shows the circuit of the buzzer ringing apparatus which concerns on Embodiment 2.
  • FIG. 1 is a block diagram showing a circuit of a buzzer sounding device 1 according to the first embodiment.
  • the buzzer sounding device 1 includes a power supply circuit 10 that is a power supply source, a control circuit 20 that generates a voltage signal, and a buzzer sounding circuit 30 that sounds a buzzer 40.
  • the buzzer sounding device 1 is mounted on devices including mobile communication terminals, home appliances, and OA devices.
  • the power supply circuit 10 supplies a power supply voltage to the buzzer sounding circuit 30.
  • the power supply circuit 10 may be a power supply of a device on which the buzzer sounding device 1 is mounted.
  • the power supply circuit 10 can supply a power supply voltage by switching to a plurality of voltage values.
  • the plurality of voltage values include a voltage value V1 at the time of steady driving of a device on which the buzzer sounding device 1 is mounted, and a voltage value V2 at the time of standby of the device.
  • the voltage value V2 during standby is smaller than the voltage value V1 during steady driving. By making the voltage value V2 during standby smaller than the voltage value V1 during steady driving, energy saving of the buzzer sounding device 1 can be achieved.
  • the power supply circuit 10 can set the voltage value V1 during steady driving to 12V and the voltage value V2 during standby to 7V, but is not limited thereto.
  • the power supply circuit 10 is connected to a common terminal and a ground terminal. The voltage value of the common terminal is maintained at the voltage value V1 or V2 of the power supply voltage by the power supply circuit 10.
  • the control circuit 20 supplies a voltage signal to the buzzer sounding circuit 30.
  • the control circuit 20 sets the power supply voltage in the power supply circuit 10.
  • the control circuit 20 has a first output port 21 and a second output port 22.
  • the first output port 21 is connected to a first input terminal 31 a described later in the buzzer sounding circuit 30 through an electric resistance 23.
  • the first output port 21 is connected to the power supply circuit 10.
  • the control circuit 20 outputs a low level voltage signal to the first output port 21 during steady driving.
  • the control circuit 20 outputs a high level voltage signal to the first output port 21 during standby.
  • the high level or low level voltage signal is input to the power supply circuit 10 and the buzzer sounding circuit 30.
  • the high level voltage signal is set to a value equal to the voltage value V1 or V2 of the power supply voltage.
  • the second output port 22 is connected to a second input terminal 32a described later in the buzzer sounding circuit 30.
  • the control circuit 20 outputs to the second output port 22 a pulse signal obtained by alternately repeating a high level voltage signal and a low level voltage signal.
  • the control circuit 20 can output a pulse signal having the same frequency as a ringing frequency of a buzzer 40 described later by using a timer terminal of the microcomputer.
  • the buzzer sounding circuit 30 includes a buzzer 40, a first switch circuit 31 and a second switch circuit 32 connected to the buzzer 40, and an inverting circuit 33 connected to the first switch circuit 31 and the second switch circuit 32. is doing.
  • the buzzer 40 is formed using piezoelectric ceramics. The buzzer 40 vibrates and generates a sound wave when a pulse voltage or an AC voltage having the same frequency as the ringing frequency is applied.
  • the buzzer 40 is connected in parallel with the electrical resistor 34.
  • the buzzer 40 is connected between the first switch circuit 31 and the second switch circuit 32.
  • the buzzer 40 will be described assuming that the first switch circuit 31 side is positive and the second switch circuit 32 side is negative, but the same description is possible even if the positive and negative are opposite.
  • the first switch circuit 31 includes a first transistor T1 and a second transistor T2.
  • a PNP bipolar transistor is used as the first transistor T1.
  • the base terminal of the first transistor T1 is connected to the first output port 21 via the first input terminal 31a.
  • the emitter terminal of the first transistor T1 is connected to the common terminal via the electric resistor 35.
  • the collector terminal of the first transistor T1 is connected to the buzzer 40.
  • the connection between the common terminal and the buzzer 40 is turned on when a low level voltage signal is applied to the base terminal, and the connection is turned off when a high level voltage signal is applied. It becomes the state of.
  • An NPN bipolar transistor is used as the second transistor T2.
  • the base terminal of the second transistor T2 is connected to the first output port 21 via the first input terminal 31a.
  • the emitter terminal of the second transistor T2 is connected to the ground terminal.
  • the collector terminal of the second transistor T2 is connected to the buzzer 40. The connection between the buzzer 40 and the ground terminal is turned on when a high level voltage signal is applied to the base terminal of the second transistor T2, and the connection is turned off when a low level voltage signal is applied. It becomes the state of.
  • the second switch circuit 32 includes a third transistor T3 and a fourth transistor T4.
  • a PNP bipolar transistor is used as the third transistor T3.
  • the base terminal of the third transistor T3 is connected to the second output port 22 via the second input terminal 32a.
  • the emitter terminal of the third transistor T3 is connected to the common terminal.
  • the collector terminal of the third transistor T3 is connected to the buzzer 40.
  • the connection between the common terminal and the buzzer 40 is turned on when a low level voltage signal is applied to the base terminal, and the connection is turned off when a high level voltage signal is applied. It becomes the state of.
  • An NPN bipolar transistor is used for the fourth transistor T4.
  • the base terminal of the fourth transistor T4 is connected to the second output port 22 via the second input terminal 32a.
  • the emitter terminal of the fourth transistor T4 is connected to the ground terminal.
  • the collector terminal of the fourth transistor T4 is connected to the buzzer 40.
  • the connection between the buzzer 40 and the ground terminal is turned on when a high level voltage signal is applied to the base terminal, and the connection is turned off when a low level voltage signal is applied. It becomes the state of.
  • the inversion circuit 33 includes a fifth transistor T5, a pull-up resistor 36, and a connection terminal 37.
  • An NPN bipolar transistor is used as the fifth transistor T5.
  • the base terminal of the fifth transistor T5 is connected to the second output port 22 via the second input terminal 32a.
  • the emitter terminal of the fifth transistor T5 is connected to the ground terminal.
  • the collector terminal of the fifth transistor T5 is connected to the connection terminal 37.
  • the pull-up resistor 36 has one end connected to the connection terminal 37 and the other end connected to the common terminal.
  • the connection terminal 37 is connected to the first input terminal 31a.
  • the inverting circuit 33 can input a voltage signal obtained by inverting the high level and the low level to the first input terminal 31a with respect to the voltage signal input to the second input terminal 32a.
  • the electrical resistance value of the pull-up resistor 36 and the electrical resistance value of the electrical resistor 23 described above are the values when the fifth transistor T5 is off and a low level voltage signal is supplied to the first output port 21.
  • the value is set in advance so that a low level voltage signal is input to the 1 input terminal 31a.
  • the control circuit 20 outputs a low level voltage signal to the first output port 21.
  • a low level voltage signal is input to the power supply circuit 10 and the first input terminal 31a by the voltage signal from the control circuit 20.
  • the power supply circuit 10 supplies a voltage having a voltage value V1 corresponding to the steady driving to the common terminal.
  • the control circuit 20 outputs a pulse signal having the same frequency as the ringing frequency of the buzzer 40 to the second output port 22. By the pulse signal from the control circuit 20, a high level voltage signal and a low level voltage signal are alternately input to the second input terminal 32a.
  • the fifth transistor T5 since the high level voltage signal is input to the fifth transistor T5, the fifth transistor T5 is turned on. For this reason, the common terminal and ground terminal of the inverting circuit 33 are connected, and a low-level voltage signal is input to the first input terminal 31a. Therefore, on the first switch circuit 31 side, a low level voltage is input to the base terminals of the first transistor T1 and the second transistor T2. As a result, the first transistor T1 is turned on, and the second transistor T2 is turned off. Therefore, the buzzer 40 and the common terminal of the first switch circuit 31 are electrically connected.
  • the common terminal of the first switch circuit 31, the buzzer 40, and the ground terminal of the second switch circuit 32 are electrically connected.
  • a high level voltage is supplied to the first terminal 40 a of the buzzer 40.
  • a low level voltage is supplied to the second terminal 40 b of the buzzer 40.
  • the voltage of the voltage value V ⁇ b> 1 is applied to the piezoelectric ceramic used for the buzzer 40.
  • the fifth transistor T5 since a low level voltage signal is input to the fifth transistor T5, the fifth transistor T5 is turned off, and the common terminal of the inverting circuit 33 and the first output port 21 are connected to the pull-up resistor 36, the first The input terminal 31a and the electrical resistor 23 are connected.
  • the electrical resistance value of the pull-up resistor 36 and the electrical resistance value of the electrical resistor 23 are set in advance, a low-level voltage signal is input to the first input terminal 31a. Therefore, on the first switch circuit 31 side, a low level voltage is input to the base terminals of the first transistor T1 and the second transistor T2. As a result, the first transistor T1 is turned on, and the second transistor T2 is turned off. Therefore, the buzzer 40 and the common terminal of the first switch circuit 31 are electrically connected.
  • the voltage signal supplied to the first input terminal 31a is fixed at a low level.
  • the common terminal of the first switch circuit 31, the buzzer 40, and the common terminal of the second switch circuit 32 are electrically connected.
  • a high level voltage is supplied to the first terminal 40 a of the buzzer 40.
  • a high level voltage is supplied to the second terminal 40 b of the buzzer 40. For this reason, no voltage is applied to the piezoelectric ceramic used for the buzzer 40.
  • FIG. 2 is a graph showing the relationship between the voltage value applied to the buzzer 40 according to Embodiment 1 and time during steady driving and standby.
  • the left diagram of FIG. 2 shows the relationship between the voltage value and time during steady driving, and the right diagram shows the standby time.
  • the period during which the voltage value V1 is applied to the buzzer 40 and the period during which the reference voltage of 0V is applied to the buzzer 40 are the same as the ringing frequency. Repeated alternately with frequency.
  • the control circuit 20 outputs a high level voltage signal to the first output port 21.
  • a high level voltage signal is input to the power supply circuit 10 and the first input terminal 31a by the voltage signal from the control circuit 20.
  • the power supply circuit 10 supplies a voltage having a voltage value V2 corresponding to the standby time to the common terminal.
  • the control circuit 20 can simultaneously switch the power supply voltage in the power supply circuit 10 and the voltage signal of the first input terminal 31 a via the first output port 21. Further, the control circuit 20 outputs a pulse signal having the same frequency as the ringing frequency of the buzzer 40 to the second output port 22. By this pulse signal, a high level voltage signal and a low level voltage signal are alternately input to the second input terminal 32a.
  • the fifth transistor T5 since the high level voltage signal is input to the fifth transistor T5, the fifth transistor T5 is turned on. For this reason, the common terminal and the ground terminal of the inverting circuit 33 are connected.
  • the first input terminal 31 a is connected to the connection terminal 37, the first output port 21 is electrically connected to the ground terminal via the first input terminal 31 a and the connection terminal 37. Therefore, a low level voltage signal is input to the first input terminal 31a. Therefore, on the first switch circuit 31 side, a low level voltage is input to the base terminals of the first transistor T1 and the second transistor T2. As a result, the first transistor T1 is turned on, and the second transistor T2 is turned off. Therefore, the buzzer 40 and the common terminal of the first switch circuit 31 are electrically connected.
  • the common terminal of the first switch circuit 31, the buzzer 40, and the ground terminal of the second switch circuit 32 are electrically connected.
  • An electrical resistor 35 is provided between the common terminal of the first switch circuit 31 and the buzzer 40.
  • the voltage of the third voltage value V3 which is a voltage drop from the high level voltage value V2 by the electric resistance 35, is supplied to the first terminal 40a of the buzzer 40. Therefore, the third voltage value V3 is equal to or less than the second voltage value V2.
  • a low level voltage is supplied to the second terminal 40 b of the buzzer 40. Therefore, a negative third voltage value V3 is applied to the piezoelectric ceramic used for the buzzer 40.
  • the fifth transistor T5 since the low-level voltage signal is input to the fifth transistor T5, the fifth transistor T5 is turned off, and the common terminal of the inverting circuit 33 and the first input terminal 31a are connected. In this case, since both the first output port 31 side and the inverting circuit 33 side are at a high level voltage, a high level voltage signal is input to the first input terminal 31a. Therefore, on the first switch circuit 31 side, a high level voltage is input to the base terminals of the first transistor T1 and the second transistor T2. As a result, the first transistor T1 is turned on, and the second transistor T2 is turned off. Therefore, the buzzer 40 and the ground terminal of the first switch circuit 31 are electrically connected.
  • the ground terminal of the first switch circuit 31, the buzzer 40, and the common terminal of the second switch circuit 32 are electrically connected.
  • a high level voltage is supplied to the first terminal 40 a of the buzzer 40.
  • a low level voltage is supplied to the second terminal 40 b of the buzzer 40.
  • the voltage of the voltage value V ⁇ b> 2 is applied to the piezoelectric ceramic used for the buzzer 40.
  • FIG. 3 is a graph showing the relationship between the voltage value applied to the conventional buzzer and time during steady driving and standby. As shown in FIG. 3, a pulse signal having a voltage value Va is applied to the buzzer during steady driving, but a pulse signal having a voltage value Vb smaller than the voltage value Va is applied to the buzzer during standby. Thereby, the volume of the buzzer during standby may be smaller than during steady driving.
  • the first embodiment when a pulse signal is supplied to the second switch circuit 32 during steady driving, a low-level voltage signal is supplied to the first switch circuit 31 and the standby switch
  • a low-level voltage signal is supplied to the second switch circuit 32
  • a high-level voltage signal is supplied to the first switch circuit 31 and a high-level voltage signal is supplied to the first switch circuit 31.
  • the volume of the buzzer can be maintained during steady driving and standby.
  • control circuit 20 can simultaneously switch the power supply voltage in the power supply circuit 10 and the voltage signal of the first input terminal 31a via the first output port 21. Therefore, the switching control of the operation between the steady driving and the standby is simplified. Further, according to the first embodiment, even when the power supply voltage cannot be switched instantaneously, the time until the buzzer 40 responds can be shortened.
  • FIG. FIG. 4 is a block diagram illustrating a circuit of the buzzer sounding device 2 according to the second embodiment.
  • the same components as those in the buzzer sounding device 1 according to the first embodiment are denoted by the same reference numerals, and description thereof is omitted or simplified.
  • the buzzer sounding device 2 includes a power supply circuit 10 that is a power supply source, a control circuit 20 that generates a voltage signal, and a buzzer sounding circuit 30 that sounds a buzzer 40. Further, the control circuit 20 includes a switching circuit 50 that switches a voltage signal input to the first input terminal 31a in accordance with the magnitude of the power supply voltage supplied from the power supply circuit 10.
  • the switching circuit 50 includes an electric resistor 51 connected to the common terminal, a Zener diode 52 connected to the electric resistor 51, a sixth transistor T6 connected to the Zener diode 52, and a sixth transistor T6 connected to the sixth transistor T6. 7 transistor T7, a drop resistor 53 connected to the common terminal and the seventh transistor T7, and an output port 54 capable of outputting a voltage signal.
  • the zener diode 52 is turned on and off depending on the power supply voltage. That is, the Zener diode 52 is turned on when the power supply voltage is the voltage value V1 during steady driving, and is turned off when the power supply voltage is the standby voltage value V2.
  • An NPN bipolar transistor is used as the sixth transistor T6.
  • the base terminal of the sixth transistor T6 is connected to the Zener diode 52.
  • the emitter terminal of the sixth transistor T6 is connected to the ground terminal.
  • the collector terminal of the sixth transistor T6 is connected to the base terminal of the seventh transistor T7. In the sixth transistor T6, when a high level voltage signal is applied to the base terminal, the connection between the ground terminal and the base terminal of the seventh transistor T7 is turned on, and a low level voltage signal is applied. The connection is turned off.
  • a PNP bipolar transistor is used as the seventh transistor T7.
  • the base terminal of the seventh transistor T7 is connected to the collector terminal of the sixth transistor T6.
  • the emitter terminal of the seventh transistor T7 is connected to the drop resistor 53.
  • the collector terminal of the seventh transistor T7 is connected to the output port 54.
  • the seventh transistor T7 when a high level voltage signal is applied to the base terminal, the connection between the output port 54, the drop resistor 53 and the common terminal is turned on, and a low level voltage signal is applied. The connection is turned off.
  • the control circuit 20 outputs a low level voltage signal to the first output port 21.
  • a low level voltage signal is input to the power supply circuit 10. With this input, the power supply circuit 10 supplies a voltage having a voltage value V1 corresponding to the steady driving to the common terminal.
  • the voltage of the voltage value V1 is applied to the Zener diode 52 via the common terminal and the electric resistance 51.
  • the Zener diode 52 is turned on, and the common terminal and the base terminal of the sixth transistor T6 are connected. Therefore, a high level voltage signal is applied to the base terminal of the sixth transistor T6, and the sixth transistor T6 is turned on.
  • the ground terminal and the base terminal of the seventh transistor T7 are connected. Therefore, a low level voltage signal is applied to the base terminal of the seventh transistor T7, and the seventh transistor T7 is turned on.
  • the output port 54 is connected to the drop resistor 53 and the common terminal, and a low-level voltage signal is output from the output port 54.
  • the low level voltage signal from the output port 54 is input to the first input terminal 31a.
  • the first The value is set in advance so that a low level voltage signal is input to the input terminal 31a.
  • the voltage signal supplied to the first input terminal 31a is fixed at a low level as in the first embodiment. .
  • control circuit 20 outputs a pulse signal having the same frequency as the ringing frequency of the buzzer 40 to the second output port 22 as in the steady driving of the first embodiment.
  • a pulse signal having the same frequency as the ringing frequency of the buzzer 40 to the second output port 22 as in the steady driving of the first embodiment.
  • the period in which the voltage value V1 is applied to the buzzer 40 and the period in which no voltage is applied to the buzzer 40. are alternately repeated at the same frequency as the ringing frequency.
  • the control circuit 20 outputs a high level voltage signal to the first output port 21.
  • a high level voltage signal is input to the power supply circuit 10.
  • the power supply circuit 10 supplies the voltage of the voltage value V2 corresponding to the standby time to the common terminal.
  • the voltage of the voltage value V2 is applied to the Zener diode 52 via the common terminal and the electric resistance 51.
  • the Zener diode 52 is turned off, and a high level voltage is not applied to the base terminal of the sixth transistor T6. Therefore, the sixth transistor T6 is turned off, and a low level voltage is not applied to the base terminal of the seventh transistor T7. Therefore, the seventh transistor T7 is turned off, and a low level voltage signal is not output from the output port 54.
  • a voltage signal is input from the inverting circuit 33 to the first input terminal 31a.
  • the period during which the negative voltage of the voltage value V3 is applied to the buzzer 40 and the voltage value V2 to the buzzer 40 is alternately repeated at the same frequency as the ringing frequency.
  • the switching circuit 50 inputs a high-level or low-level voltage signal to the first input terminal 31a according to the magnitude of the power supply voltage supplied from the power supply circuit 10. Will be. Thereby, similarly to Embodiment 1, switching of a voltage signal can be speeded up.
  • the configuration described in the above embodiment shows an example of the contents of the present invention, and can be combined with another known technique, and can be combined with other configurations without departing from the gist of the present invention. It is also possible to omit or change the part.

Abstract

The present invention is characterized by comprising: a buzzer 40 that is formed by using a piezoelectric element; a buzzer sounding circuit 30 having a first switch circuit 31 and a second switch circuit 32 connected to the buzzer 40; a power supply circuit 10 that supplies, to a common terminal connected to the buzzer sounding circuit 30, a voltage of a first voltage value V1 during normal driving, and a voltage of a second voltage value V2 smaller than the first voltage value V1 during standby; and a control circuit 20 for causing the first switch circuit 31 and the second switch circuit 32, during normal driving, to alternately apply, to the buzzer 40, a positive voltage signal of the first voltage value V1 and a voltage signal of 0 V which is a positive/negative reference value, and during standby, to alternately apply, to the buzzer 40, one of either a positive or a negative voltage signal of the second voltage value V2 and the other of a positive or a negative voltage signal of a third voltage value V3 smaller than the first voltage value V1.

Description

ブザー鳴動装置Buzzer sounding device
　本発明は、圧電素子を用いて形成されたブザーを鳴動させるブザー鳴動装置に関する。 The present invention relates to a buzzer sounding device that sounds a buzzer formed using a piezoelectric element.
　圧電素子を用いて形成されたブザーが知られている。このようなブザーは、携帯通信端末、家電製品及びＯＡ機器を含む機器に搭載されている。ブザーを搭載する機器には、ブザーを鳴動させるためのブザー鳴動装置が設けられる。ブザー鳴動装置には、ブザーに接続されたブザー鳴動回路が設けられている。 A buzzer formed using a piezoelectric element is known. Such a buzzer is mounted on devices including portable communication terminals, home appliances, and OA devices. A device equipped with a buzzer is provided with a buzzer sounding device for sounding the buzzer. The buzzer sounding device is provided with a buzzer sounding circuit connected to the buzzer.
　特許文献１には、スイッチ用のトランジスタが複数設けられ、複数のトランジスタのオンオフを個別に制御することでブザーに電圧を印加するブザー鳴動回路が記載されている。特許文献２には、インバータＩＣを有するプッシュプル回路を用いてブザーに電圧を印加するブザー鳴動回路が記載されている。 Patent Document 1 describes a buzzer sounding circuit in which a plurality of switching transistors are provided and a voltage is applied to the buzzer by individually controlling on / off of the plurality of transistors. Patent Document 2 describes a buzzer sounding circuit that applies a voltage to a buzzer using a push-pull circuit having an inverter IC.
特開２００７－３３９３９号公報JP 2007-33939 A 特開２０１０－２７７５６２号公報JP 2010-277562 A
　近年、ブザーを搭載する機器においては、定常駆動時の電源電圧よりも待機時の電源電圧の方を低く設定することにより、待機時の消費電力を抑制することが行われている。上記特許文献１及び特許文献２に記載の技術によれば、機器の待機時にブザーを鳴動させる場合、電源電圧が定常駆動時よりも低くなっているため、ブザーの音量が小さくなってしまう可能性がある。 In recent years, in devices equipped with buzzers, standby power consumption has been reduced by setting the standby power supply voltage lower than the steady-state power supply voltage. According to the techniques described in Patent Document 1 and Patent Document 2, when the buzzer is sounded during standby of the device, the power supply voltage is lower than that during steady driving, and thus the volume of the buzzer may be reduced. There is.
　本発明は、上記に鑑みてなされたものであって、定常駆動時及び待機時においてブザーの音量を維持することが可能なブザー鳴動装置を得ることを目的とする。 The present invention has been made in view of the above, and an object thereof is to obtain a buzzer sounding device capable of maintaining the volume of a buzzer during steady driving and standby.
　上述した課題を解決し、目的を達成するために、本発明は、圧電素子を用いて形成されるブザーと、ブザーに接続された第１スイッチ回路及び第２スイッチ回路を有するブザー鳴動回路と、ブザー鳴動回路に接続されるコモン端子に対して定常駆動時には第１電圧値の電圧を供給し、待機時には第１電圧値よりも小さい第２電圧値の電圧を供給する電源供給回路と、第１スイッチ回路及び第２スイッチ回路に対して、定常駆動時にはブザーに第１電圧値の正の電圧信号と正負の基準値の電圧信号とを交互に印加させ、待機時にはブザーに第２電圧値の正負いずれか一方の電圧信号と第１電圧値よりも小さい第３電圧値の正負いずれか他方の電圧信号とを交互に印加させる制御回路とを備えることを特徴とする。 In order to solve the above-described problems and achieve the object, the present invention provides a buzzer formed using a piezoelectric element, a buzzer sounding circuit having a first switch circuit and a second switch circuit connected to the buzzer, A power supply circuit for supplying a voltage having a first voltage value to the common terminal connected to the buzzer sounding circuit during steady driving and supplying a voltage having a second voltage value smaller than the first voltage value during standby; For the switch circuit and the second switch circuit, the positive voltage signal of the first voltage value and the positive / negative reference value voltage signal are alternately applied to the buzzer during steady driving, and the positive / negative of the second voltage value is applied to the buzzer during standby. And a control circuit for alternately applying either one of the voltage signal and the other voltage signal of the third voltage value smaller than the first voltage value.
　本発明によれば、定常駆動時及び待機時においてブザーの音量を維持することが可能であるという効果を奏する。 According to the present invention, there is an effect that it is possible to maintain the volume of the buzzer during steady driving and standby.
実施の形態１に係るブザー鳴動装置の回路を示すブロック図The block diagram which shows the circuit of the buzzer ringing apparatus which concerns on Embodiment 1. FIG. 定常駆動時及び待機時において、実施の形態１に係るブザーに印加される電圧値と時間との関係を示すグラフThe graph which shows the relationship between the voltage value applied to the buzzer which concerns on Embodiment 1, and time at the time of steady driving and standby 定常駆動時及び待機時において、従来のブザーに印加される電圧値と時間との関係を示すグラフA graph showing the relationship between the voltage value applied to a conventional buzzer and time during steady driving and standby 実施の形態２に係るブザー鳴動装置の回路を示すブロック図The block diagram which shows the circuit of the buzzer ringing apparatus which concerns on Embodiment 2. FIG.
　以下、本発明の実施の形態に係るブザー鳴動装置を図面に基づいて詳細に説明する。なお、以下の実施の形態により発明が限定されるものではない。また、下記実施形態における構成要素には、当業者が置換可能かつ容易なもの、あるいは実質的に同一のものが含まれる。 Hereinafter, a buzzer sounding device according to an embodiment of the present invention will be described in detail with reference to the drawings. The invention is not limited to the following embodiments. In addition, constituent elements in the following embodiments include those that can be easily replaced by those skilled in the art or those that are substantially the same.
実施の形態１．
　図１は、実施の形態１に係るブザー鳴動装置１の回路を示すブロック図である。図１に示すように、ブザー鳴動装置１は、電源の供給元である電源供給回路１０と、電圧信号を生成する制御回路２０と、ブザー４０を鳴動させるブザー鳴動回路３０とを備えている。ブザー鳴動装置１は、携帯通信端末、家電製品及びＯＡ機器を含む機器に搭載される。 Embodiment 1 FIG.
FIG. 1 is a block diagram showing a circuit of a buzzer sounding device 1 according to the first embodiment. As shown in FIG. 1, the buzzer sounding device 1 includes a power supply circuit 10 that is a power supply source, a control circuit 20 that generates a voltage signal, and a buzzer sounding circuit 30 that sounds a buzzer 40. The buzzer sounding device 1 is mounted on devices including mobile communication terminals, home appliances, and OA devices.
　電源供給回路１０は、ブザー鳴動回路３０に電源電圧を供給する。電源供給回路１０には、ブザー鳴動装置１が搭載される機器の電源が用いられてもよい。電源供給回路１０は、複数の電圧値に切り替えて電源電圧を供給可能である。複数の電圧値には、ブザー鳴動装置１を搭載する機器の定常駆動時における電圧値Ｖ１と、当該機器の待機時における電圧値Ｖ２とが含まれる。待機時における電圧値Ｖ２は、定常駆動時における電圧値Ｖ１よりも小さい値となる。待機時における電圧値Ｖ２を定常駆動時における電圧値Ｖ１よりも小さくすることにより、ブザー鳴動装置１の省エネルギー化を図ることができる。電源供給回路１０は、定常駆動時の電圧値Ｖ１を１２Ｖとし、待機時の電圧値Ｖ２を７Ｖとすることができるが、これに限定するものではない。電源供給回路１０は、コモン端子及びグランド端子に接続される。コモン端子の電圧値は、電源供給回路１０により、電源電圧の電圧値Ｖ１又はＶ２に維持される。 The power supply circuit 10 supplies a power supply voltage to the buzzer sounding circuit 30. The power supply circuit 10 may be a power supply of a device on which the buzzer sounding device 1 is mounted. The power supply circuit 10 can supply a power supply voltage by switching to a plurality of voltage values. The plurality of voltage values include a voltage value V1 at the time of steady driving of a device on which the buzzer sounding device 1 is mounted, and a voltage value V2 at the time of standby of the device. The voltage value V2 during standby is smaller than the voltage value V1 during steady driving. By making the voltage value V2 during standby smaller than the voltage value V1 during steady driving, energy saving of the buzzer sounding device 1 can be achieved. The power supply circuit 10 can set the voltage value V1 during steady driving to 12V and the voltage value V2 during standby to 7V, but is not limited thereto. The power supply circuit 10 is connected to a common terminal and a ground terminal. The voltage value of the common terminal is maintained at the voltage value V1 or V2 of the power supply voltage by the power supply circuit 10.
　制御回路２０は、ブザー鳴動回路３０に電圧信号を供給する。制御回路２０は、電源供給回路１０における電源電圧を設定する。 The control circuit 20 supplies a voltage signal to the buzzer sounding circuit 30. The control circuit 20 sets the power supply voltage in the power supply circuit 10.
　また、制御回路２０は、第１出力ポート２１及び第２出力ポート２２を有する。第１出力ポート２１は、電気抵抗２３を介して、ブザー鳴動回路３０のうち後述する第１入力端子３１ａに接続されている。また、第１出力ポート２１は、電源供給回路１０に接続される。制御回路２０は、定常駆動時には第１出力ポート２１に対して、ローレベルの電圧信号を出力する。制御回路２０は、待機時には第１出力ポート２１に対して、ハイレベルの電圧信号を出力する。当該ハイレベル又はローレベルの電圧信号は、電源供給回路１０及びブザー鳴動回路３０に入力される。ハイレベルの電圧信号は、電源電圧の電圧値Ｖ１又はＶ２に等しい値とする。 The control circuit 20 has a first output port 21 and a second output port 22. The first output port 21 is connected to a first input terminal 31 a described later in the buzzer sounding circuit 30 through an electric resistance 23. The first output port 21 is connected to the power supply circuit 10. The control circuit 20 outputs a low level voltage signal to the first output port 21 during steady driving. The control circuit 20 outputs a high level voltage signal to the first output port 21 during standby. The high level or low level voltage signal is input to the power supply circuit 10 and the buzzer sounding circuit 30. The high level voltage signal is set to a value equal to the voltage value V1 or V2 of the power supply voltage.
　第２出力ポート２２は、ブザー鳴動回路３０のうち後述する第２入力端子３２ａに接続されている。制御回路２０は、第２出力ポート２２に、ハイレベルの電圧信号とローレベルの電圧信号とを交互に繰り返したパルス信号を出力する。制御回路２０は、マイコンのタイマー端子を用いることで、後述するブザー４０の鳴動周波数と同一周波数のパルス信号を出力可能である。 The second output port 22 is connected to a second input terminal 32a described later in the buzzer sounding circuit 30. The control circuit 20 outputs to the second output port 22 a pulse signal obtained by alternately repeating a high level voltage signal and a low level voltage signal. The control circuit 20 can output a pulse signal having the same frequency as a ringing frequency of a buzzer 40 described later by using a timer terminal of the microcomputer.
　ブザー鳴動回路３０は、ブザー４０と、ブザー４０に接続された第１スイッチ回路３１及び第２スイッチ回路３２と、第１スイッチ回路３１及び第２スイッチ回路３２に接続された反転回路３３とを有している。ブザー４０は、圧電セラミックスを用いて形成される。ブザー４０は、鳴動周波数と同一周波数のパルス電圧又は交流電圧が印加された場合に、振動して音波を発生する。ブザー４０は、電気抵抗３４と並列に接続されている。ブザー４０は、第１スイッチ回路３１と第２スイッチ回路３２との間に接続されている。以下、ブザー４０では、第１スイッチ回路３１側を正、第２スイッチ回路３２側を負として説明するが、正負が逆であっても同様の説明が可能である。 The buzzer sounding circuit 30 includes a buzzer 40, a first switch circuit 31 and a second switch circuit 32 connected to the buzzer 40, and an inverting circuit 33 connected to the first switch circuit 31 and the second switch circuit 32. is doing. The buzzer 40 is formed using piezoelectric ceramics. The buzzer 40 vibrates and generates a sound wave when a pulse voltage or an AC voltage having the same frequency as the ringing frequency is applied. The buzzer 40 is connected in parallel with the electrical resistor 34. The buzzer 40 is connected between the first switch circuit 31 and the second switch circuit 32. Hereinafter, the buzzer 40 will be described assuming that the first switch circuit 31 side is positive and the second switch circuit 32 side is negative, but the same description is possible even if the positive and negative are opposite.
　第１スイッチ回路３１は、第１トランジスタＴ１及び第２トランジスタＴ２を有する。第１トランジスタＴ１には、ＰＮＰ型のバイポーラトランジスタが用いられる。第１トランジスタＴ１のベース端子は、第１入力端子３１ａを介して第１出力ポート２１に接続されている。第１トランジスタＴ１のエミッタ端子は、電気抵抗３５を介してコモン端子に接続されている。第１トランジスタＴ１のコレクタ端子は、ブザー４０に接続されている。第１トランジスタＴ１は、ベース端子にローレベルの電圧信号が印加された場合にはコモン端子とブザー４０との接続がオンの状態となり、ハイレベルの電圧信号が印加された場合には接続がオフの状態となる。 The first switch circuit 31 includes a first transistor T1 and a second transistor T2. A PNP bipolar transistor is used as the first transistor T1. The base terminal of the first transistor T1 is connected to the first output port 21 via the first input terminal 31a. The emitter terminal of the first transistor T1 is connected to the common terminal via the electric resistor 35. The collector terminal of the first transistor T1 is connected to the buzzer 40. In the first transistor T1, the connection between the common terminal and the buzzer 40 is turned on when a low level voltage signal is applied to the base terminal, and the connection is turned off when a high level voltage signal is applied. It becomes the state of.
　第２トランジスタＴ２には、ＮＰＮ型のバイポーラトランジスタが用いられる。第２トランジスタＴ２のベース端子は、第１入力端子３１ａを介して第１出力ポート２１に接続されている。第２トランジスタＴ２のエミッタ端子は、グランド端子に接続されている。第２トランジスタＴ２のコレクタ端子は、ブザー４０に接続されている。第２トランジスタＴ２は、ベース端子にハイレベルの電圧信号が印加された場合にはブザー４０とグランド端子との接続がオンの状態となり、ローレベルの電圧信号が印加された場合には接続がオフの状態となる。 An NPN bipolar transistor is used as the second transistor T2. The base terminal of the second transistor T2 is connected to the first output port 21 via the first input terminal 31a. The emitter terminal of the second transistor T2 is connected to the ground terminal. The collector terminal of the second transistor T2 is connected to the buzzer 40. The connection between the buzzer 40 and the ground terminal is turned on when a high level voltage signal is applied to the base terminal of the second transistor T2, and the connection is turned off when a low level voltage signal is applied. It becomes the state of.
　第２スイッチ回路３２は、第３トランジスタＴ３及び第４トランジスタＴ４を有する。第３トランジスタＴ３には、ＰＮＰ型のバイポーラトランジスタが用いられる。第３トランジスタＴ３のベース端子は、第２入力端子３２ａを介して第２出力ポート２２に接続されている。第３トランジスタＴ３のエミッタ端子は、コモン端子に接続されている。第３トランジスタＴ３のコレクタ端子は、ブザー４０に接続されている。第３トランジスタＴ３は、ベース端子にローレベルの電圧信号が印加された場合にはコモン端子とブザー４０との接続がオンの状態となり、ハイレベルの電圧信号が印加された場合には接続がオフの状態となる。 The second switch circuit 32 includes a third transistor T3 and a fourth transistor T4. A PNP bipolar transistor is used as the third transistor T3. The base terminal of the third transistor T3 is connected to the second output port 22 via the second input terminal 32a. The emitter terminal of the third transistor T3 is connected to the common terminal. The collector terminal of the third transistor T3 is connected to the buzzer 40. In the third transistor T3, the connection between the common terminal and the buzzer 40 is turned on when a low level voltage signal is applied to the base terminal, and the connection is turned off when a high level voltage signal is applied. It becomes the state of.
　第４トランジスタＴ４には、ＮＰＮ型のバイポーラトランジスタが用いられる。第４トランジスタＴ４のベース端子は、第２入力端子３２ａを介して第２出力ポート２２に接続されている。第４トランジスタＴ４のエミッタ端子は、グランド端子に接続されている。第４トランジスタＴ４のコレクタ端子は、ブザー４０に接続されている。第４トランジスタＴ４は、ベース端子にハイレベルの電圧信号が印加された場合にはブザー４０とグランド端子との接続がオンの状態となり、ローレベルの電圧信号が印加された場合には接続がオフの状態となる。 An NPN bipolar transistor is used for the fourth transistor T4. The base terminal of the fourth transistor T4 is connected to the second output port 22 via the second input terminal 32a. The emitter terminal of the fourth transistor T4 is connected to the ground terminal. The collector terminal of the fourth transistor T4 is connected to the buzzer 40. In the fourth transistor T4, the connection between the buzzer 40 and the ground terminal is turned on when a high level voltage signal is applied to the base terminal, and the connection is turned off when a low level voltage signal is applied. It becomes the state of.
　反転回路３３は、第５トランジスタＴ５と、プルアップ抵抗３６と、接続端子３７とを有する。第５トランジスタＴ５には、ＮＰＮ型のバイポーラトランジスタが用いられる。第５トランジスタＴ５のベース端子は、第２入力端子３２ａを介して第２出力ポート２２に接続されている。第５トランジスタＴ５のエミッタ端子は、グランド端子に接続されている。第５トランジスタＴ５のコレクタ端子は、接続端子３７に接続されている。第５トランジスタＴ５は、ベース端子にハイレベルの電圧信号が印加された場合にはコモン端子とグランド端子との接続がオンの状態となり、ローレベルの電圧信号が印加された場合には接続がオフの状態となる。プルアップ抵抗３６は、一端が接続端子３７に接続され、他端がコモン端子に接続されている。また、接続端子３７は、第１入力端子３１ａに接続されている。 The inversion circuit 33 includes a fifth transistor T5, a pull-up resistor 36, and a connection terminal 37. An NPN bipolar transistor is used as the fifth transistor T5. The base terminal of the fifth transistor T5 is connected to the second output port 22 via the second input terminal 32a. The emitter terminal of the fifth transistor T5 is connected to the ground terminal. The collector terminal of the fifth transistor T5 is connected to the connection terminal 37. In the fifth transistor T5, the connection between the common terminal and the ground terminal is turned on when a high-level voltage signal is applied to the base terminal, and the connection is turned off when a low-level voltage signal is applied. It becomes the state of. The pull-up resistor 36 has one end connected to the connection terminal 37 and the other end connected to the common terminal. The connection terminal 37 is connected to the first input terminal 31a.
　第２入力端子３２ａにハイレベルの電圧信号が入力された場合、第５トランジスタＴ５のベース端子にはハイレベルの電圧信号が入力される。このため、第５トランジスタＴ５がオンの状態となり、反転回路３３のコモン端子からグランド端子までが電気的に接続される。したがって、第１入力端子３１ａには、グランド端子の電圧信号であるローレベルの電圧信号が入力される。 When a high level voltage signal is input to the second input terminal 32a, a high level voltage signal is input to the base terminal of the fifth transistor T5. For this reason, the fifth transistor T5 is turned on, and the common terminal to the ground terminal of the inverting circuit 33 are electrically connected. Therefore, a low level voltage signal that is a voltage signal of the ground terminal is input to the first input terminal 31a.
　一方、第２入力端子３２ａにローレベルの電圧信号が入力された場合、第５トランジスタＴ５のベース端子にはローレベルの電圧信号が入力される。このため、第５トランジスタＴ５がオフのままであり、反転回路３３のコモン端子はプルアップ抵抗３６及び接続端子３７を介して第１入力端子３１ａに接続される。したがって、第１入力端子３１ａには、コモン端子の電圧信号であるハイレベルの電圧信号が入力される。このように、反転回路３３は、第２入力端子３２ａに入力される電圧信号に対してハイレベルとローレベルとを反転させた電圧信号を第１入力端子３１ａに入力可能である。 On the other hand, when a low level voltage signal is input to the second input terminal 32a, a low level voltage signal is input to the base terminal of the fifth transistor T5. For this reason, the fifth transistor T5 remains off, and the common terminal of the inverting circuit 33 is connected to the first input terminal 31a via the pull-up resistor 36 and the connection terminal 37. Therefore, a high level voltage signal that is a voltage signal of the common terminal is input to the first input terminal 31a. Thus, the inverting circuit 33 can input a voltage signal obtained by inverting the high level and the low level to the first input terminal 31a with respect to the voltage signal input to the second input terminal 32a.
　なお、プルアップ抵抗３６の電気抵抗値及び上記の電気抵抗２３の電気抵抗値は、第５トランジスタＴ５がオフの場合かつ第１出力ポート２１にローレベルの電圧信号が供給される場合に、第１入力端子３１ａにローレベルの電圧信号が入力される値に予め設定されている。 Note that the electrical resistance value of the pull-up resistor 36 and the electrical resistance value of the electrical resistor 23 described above are the values when the fifth transistor T5 is off and a low level voltage signal is supplied to the first output port 21. The value is set in advance so that a low level voltage signal is input to the 1 input terminal 31a.
　次に、ブザー鳴動装置１の動作を説明する。ブザーを搭載する機器においては、定常駆動時の電源電圧よりも待機時の電源電圧の方を低く設定することにより、待機時の消費電力を抑制することが行われている。そこで、まず定常駆動時の動作を説明する。定常駆動時において、制御回路２０は、第１出力ポート２１にローレベルの電圧信号を出力する。制御回路２０からの電圧信号により、電源供給回路１０及び第１入力端子３１ａには、ローレベルの電圧信号が入力される。電源供給回路１０は、定常駆動時に対応する電圧値Ｖ１の電圧をコモン端子に供給する。また、制御回路２０は、ブザー４０の鳴動周波数と同一周波数のパルス信号を第２出力ポート２２に出力する。制御回路２０からのパルス信号により、第２入力端子３２ａには、ハイレベルの電圧信号とローレベルの電圧信号とが交互に入力される。 Next, the operation of the buzzer sounding device 1 will be described. In a device equipped with a buzzer, standby power consumption is suppressed by setting the standby power supply voltage lower than the power supply voltage during steady driving. First, the operation during steady driving will be described. During steady driving, the control circuit 20 outputs a low level voltage signal to the first output port 21. A low level voltage signal is input to the power supply circuit 10 and the first input terminal 31a by the voltage signal from the control circuit 20. The power supply circuit 10 supplies a voltage having a voltage value V1 corresponding to the steady driving to the common terminal. Further, the control circuit 20 outputs a pulse signal having the same frequency as the ringing frequency of the buzzer 40 to the second output port 22. By the pulse signal from the control circuit 20, a high level voltage signal and a low level voltage signal are alternately input to the second input terminal 32a.
　第２入力端子３２ａにハイレベルの電圧信号が入力された場合、第２スイッチ回路３２側では、第３トランジスタＴ３及び第４トランジスタＴ４のベース端子にはハイレベルの電圧信号が入力される。これにより、第３トランジスタＴ３はオフの状態となり、第４トランジスタＴ４はオンの状態となる。よって、ブザー４０と第２スイッチ回路３２のグランド端子とが電気的に接続される。 When a high level voltage signal is input to the second input terminal 32a, a high level voltage signal is input to the base terminals of the third transistor T3 and the fourth transistor T4 on the second switch circuit 32 side. As a result, the third transistor T3 is turned off, and the fourth transistor T4 is turned on. Therefore, the buzzer 40 and the ground terminal of the second switch circuit 32 are electrically connected.
　また、第５トランジスタＴ５にハイレベルの電圧信号が入力されるため、第５トランジスタＴ５がオンの状態となる。このため、反転回路３３のコモン端子とグランド端子とが接続され、第１入力端子３１ａにはローレベルの電圧信号が入力される。したがって、第１スイッチ回路３１側では、第１トランジスタＴ１及び第２トランジスタＴ２のベース端子にはローレベルの電圧が入力される。これにより、第１トランジスタＴ１はオンの状態となり、第２トランジスタＴ２はオフの状態となる。よって、ブザー４０と第１スイッチ回路３１のコモン端子とが電気的に接続される。 Further, since the high level voltage signal is input to the fifth transistor T5, the fifth transistor T5 is turned on. For this reason, the common terminal and ground terminal of the inverting circuit 33 are connected, and a low-level voltage signal is input to the first input terminal 31a. Therefore, on the first switch circuit 31 side, a low level voltage is input to the base terminals of the first transistor T1 and the second transistor T2. As a result, the first transistor T1 is turned on, and the second transistor T2 is turned off. Therefore, the buzzer 40 and the common terminal of the first switch circuit 31 are electrically connected.
　したがって、第１スイッチ回路３１のコモン端子と、ブザー４０と、第２スイッチ回路３２のグランド端子とが電気的に接続される。ブザー４０の第１端子４０ａには、ハイレベルの電圧が供給される。ブザー４０の第２端子４０ｂには、ローレベルの電圧が供給される。このため、ブザー４０に用いられる圧電セラミックスに対して電圧値Ｖ１の電圧が印加される。 Therefore, the common terminal of the first switch circuit 31, the buzzer 40, and the ground terminal of the second switch circuit 32 are electrically connected. A high level voltage is supplied to the first terminal 40 a of the buzzer 40. A low level voltage is supplied to the second terminal 40 b of the buzzer 40. For this reason, the voltage of the voltage value V <b> 1 is applied to the piezoelectric ceramic used for the buzzer 40.
　一方、第２入力端子３２ａにローレベルの電圧信号が入力された場合、第２スイッチ回路３２側では、第３トランジスタＴ３及び第４トランジスタＴ４のベース端子にはローレベルの電圧信号が入力される。これにより、第３トランジスタＴ３はオンの状態となり、第４トランジスタＴ４はオフの状態となる。したがって、ブザー４０と第２スイッチ回路３２のコモン端子とが電気的に接続される。 On the other hand, when a low level voltage signal is input to the second input terminal 32a, a low level voltage signal is input to the base terminals of the third transistor T3 and the fourth transistor T4 on the second switch circuit 32 side. . As a result, the third transistor T3 is turned on, and the fourth transistor T4 is turned off. Therefore, the buzzer 40 and the common terminal of the second switch circuit 32 are electrically connected.
　また、第５トランジスタＴ５にはローレベルの電圧信号が入力されるため、第５トランジスタＴ５がオフの状態となり、反転回路３３のコモン端子と第１出力ポート２１とがプルアップ抵抗３６、第１入力端子３１ａ及び電気抵抗２３を介して接続される。ここで、プルアップ抵抗３６の電気抵抗値と電気抵抗２３の電気抵抗値とが予め設定されているため、第１入力端子３１ａにはローレベルの電圧信号が入力される。したがって、第１スイッチ回路３１側では、第１トランジスタＴ１及び第２トランジスタＴ２のベース端子にはローレベルの電圧が入力される。これにより、第１トランジスタＴ１はオンの状態となり、第２トランジスタＴ２はオフの状態となる。よって、ブザー４０と第１スイッチ回路３１のコモン端子とが電気的に接続される。このように、第１出力ポート２１にローレベルの電気信号が供給される場合には、第１入力端子３１ａに供給される電圧信号がローレベルに固定されることになる。 Further, since a low level voltage signal is input to the fifth transistor T5, the fifth transistor T5 is turned off, and the common terminal of the inverting circuit 33 and the first output port 21 are connected to the pull-up resistor 36, the first The input terminal 31a and the electrical resistor 23 are connected. Here, since the electrical resistance value of the pull-up resistor 36 and the electrical resistance value of the electrical resistor 23 are set in advance, a low-level voltage signal is input to the first input terminal 31a. Therefore, on the first switch circuit 31 side, a low level voltage is input to the base terminals of the first transistor T1 and the second transistor T2. As a result, the first transistor T1 is turned on, and the second transistor T2 is turned off. Therefore, the buzzer 40 and the common terminal of the first switch circuit 31 are electrically connected. Thus, when a low-level electrical signal is supplied to the first output port 21, the voltage signal supplied to the first input terminal 31a is fixed at a low level.
　したがって、第１スイッチ回路３１のコモン端子と、ブザー４０と、第２スイッチ回路３２のコモン端子とが電気的に接続される。ブザー４０の第１端子４０ａには、ハイレベルの電圧が供給される。ブザー４０の第２端子４０ｂには、ハイレベルの電圧が供給される。このため、ブザー４０に用いられる圧電セラミックスに対して電圧は印加されない。 Therefore, the common terminal of the first switch circuit 31, the buzzer 40, and the common terminal of the second switch circuit 32 are electrically connected. A high level voltage is supplied to the first terminal 40 a of the buzzer 40. A high level voltage is supplied to the second terminal 40 b of the buzzer 40. For this reason, no voltage is applied to the piezoelectric ceramic used for the buzzer 40.
　図２は、定常駆動時及び待機時において、実施の形態１に係るブザー４０に印加される電圧値と時間との関係を示すグラフである。図２の左側の図が定常駆動時、右側の図が待機時における電圧値と時間との関係を示している。図２の左側のグラフに示すように、定常駆動時には、ブザー４０に電圧値Ｖ１が印加される期間と、ブザー４０に基準値である０Ｖの電圧が印加される期間とが鳴動周波数と同一の周波数で交互に繰り返される。 FIG. 2 is a graph showing the relationship between the voltage value applied to the buzzer 40 according to Embodiment 1 and time during steady driving and standby. The left diagram of FIG. 2 shows the relationship between the voltage value and time during steady driving, and the right diagram shows the standby time. As shown in the graph on the left side of FIG. 2, during steady driving, the period during which the voltage value V1 is applied to the buzzer 40 and the period during which the reference voltage of 0V is applied to the buzzer 40 are the same as the ringing frequency. Repeated alternately with frequency.
　続いて、待機時の動作を説明する。待機時において、制御回路２０は、第１出力ポート２１にハイレベルの電圧信号を出力する。制御回路２０からの電圧信号により、電源供給回路１０及び第１入力端子３１ａには、ハイレベルの電圧信号が入力される。電源供給回路１０は、待機時に対応する電圧値Ｖ２の電圧をコモン端子に供給する。このように、制御回路２０は、第１出力ポート２１を介して、電源供給回路１０における電源電圧の切り替えと、第１入力端子３１ａの電圧信号の切り替えとを同時に行うことができる。また、制御回路２０は、ブザー４０の鳴動周波数と同一周波数のパルス信号を第２出力ポート２２に出力する。このパルス信号により、第２入力端子３２ａには、ハイレベルの電圧信号とローレベルの電圧信号とが交互に入力される。 Next, the operation during standby will be described. During standby, the control circuit 20 outputs a high level voltage signal to the first output port 21. A high level voltage signal is input to the power supply circuit 10 and the first input terminal 31a by the voltage signal from the control circuit 20. The power supply circuit 10 supplies a voltage having a voltage value V2 corresponding to the standby time to the common terminal. As described above, the control circuit 20 can simultaneously switch the power supply voltage in the power supply circuit 10 and the voltage signal of the first input terminal 31 a via the first output port 21. Further, the control circuit 20 outputs a pulse signal having the same frequency as the ringing frequency of the buzzer 40 to the second output port 22. By this pulse signal, a high level voltage signal and a low level voltage signal are alternately input to the second input terminal 32a.
　第２入力端子３２ａにハイレベルの電圧信号が入力された場合、第２スイッチ回路３２側では、第３トランジスタＴ３及び第４トランジスタＴ４のベース端子にはハイレベルの電圧信号が入力される。これにより、第３トランジスタＴ３はオフの状態となり、第４トランジスタＴ４はオンの状態となる。よって、ブザー４０と第２スイッチ回路３２のグランド端子とが電気的に接続される。 When a high level voltage signal is input to the second input terminal 32a, a high level voltage signal is input to the base terminals of the third transistor T3 and the fourth transistor T4 on the second switch circuit 32 side. As a result, the third transistor T3 is turned off, and the fourth transistor T4 is turned on. Therefore, the buzzer 40 and the ground terminal of the second switch circuit 32 are electrically connected.
　また、第５トランジスタＴ５にハイレベルの電圧信号が入力されるため、第５トランジスタＴ５がオンの状態となる。このため、反転回路３３のコモン端子とグランド端子とが接続される。このとき、第１入力端子３１ａが接続端子３７に接続されているため、第１出力ポート２１は、第１入力端子３１ａ、接続端子３７を介してグランド端子に電気的に接続される。このため、第１入力端子３１ａにはローレベルの電圧信号が入力される。したがって、第１スイッチ回路３１側では、第１トランジスタＴ１及び第２トランジスタＴ２のベース端子にはローレベルの電圧が入力される。これにより、第１トランジスタＴ１はオンの状態となり、第２トランジスタＴ２はオフの状態となる。よって、ブザー４０と第１スイッチ回路３１のコモン端子とが電気的に接続される。 Further, since the high level voltage signal is input to the fifth transistor T5, the fifth transistor T5 is turned on. For this reason, the common terminal and the ground terminal of the inverting circuit 33 are connected. At this time, since the first input terminal 31 a is connected to the connection terminal 37, the first output port 21 is electrically connected to the ground terminal via the first input terminal 31 a and the connection terminal 37. Therefore, a low level voltage signal is input to the first input terminal 31a. Therefore, on the first switch circuit 31 side, a low level voltage is input to the base terminals of the first transistor T1 and the second transistor T2. As a result, the first transistor T1 is turned on, and the second transistor T2 is turned off. Therefore, the buzzer 40 and the common terminal of the first switch circuit 31 are electrically connected.
　したがって、第１スイッチ回路３１のコモン端子と、ブザー４０と、第２スイッチ回路３２のグランド端子とが電気的に接続される。第１スイッチ回路３１のコモン端子とブザー４０との間には、電気抵抗３５が設けられる。このため、ハイレベルの電圧値Ｖ２から電気抵抗３５によって電圧降下された第３電圧値Ｖ３の電圧がブザー４０の第１端子４０ａに供給される。したがって、第３電圧値Ｖ３は、第２電圧値Ｖ２の値以下となる。ブザー４０の第２端子４０ｂには、ローレベルの電圧が供給される。このため、ブザー４０に用いられる圧電セラミックスに対して負の第３電圧値Ｖ３の電圧が印加される。 Therefore, the common terminal of the first switch circuit 31, the buzzer 40, and the ground terminal of the second switch circuit 32 are electrically connected. An electrical resistor 35 is provided between the common terminal of the first switch circuit 31 and the buzzer 40. For this reason, the voltage of the third voltage value V3, which is a voltage drop from the high level voltage value V2 by the electric resistance 35, is supplied to the first terminal 40a of the buzzer 40. Therefore, the third voltage value V3 is equal to or less than the second voltage value V2. A low level voltage is supplied to the second terminal 40 b of the buzzer 40. Therefore, a negative third voltage value V3 is applied to the piezoelectric ceramic used for the buzzer 40.
　一方、第２入力端子３２ａにローレベルの電圧信号が入力された場合、第２スイッチ回路３２側では、第３トランジスタＴ３及び第４トランジスタＴ４のベース端子にはローレベルの電圧信号が入力される。これにより、第３トランジスタＴ３はオンの状態となり、第４トランジスタＴ４はオフの状態となる。したがって、ブザー４０と第２スイッチ回路３２のコモン端子とが電気的に接続される。 On the other hand, when a low level voltage signal is input to the second input terminal 32a, a low level voltage signal is input to the base terminals of the third transistor T3 and the fourth transistor T4 on the second switch circuit 32 side. . As a result, the third transistor T3 is turned on, and the fourth transistor T4 is turned off. Therefore, the buzzer 40 and the common terminal of the second switch circuit 32 are electrically connected.
　また、第５トランジスタＴ５にはローレベルの電圧信号が入力されるため、第５トランジスタＴ５がオフの状態となり、反転回路３３のコモン端子と第１入力端子３１ａとが接続される。この場合、第１出力ポート３１側及び反転回路３３側がいずれもハイレベルの電圧であるため、第１入力端子３１ａには、ハイレベルの電圧信号が入力される。したがって、第１スイッチ回路３１側では、第１トランジスタＴ１及び第２トランジスタＴ２のベース端子にはハイレベルの電圧が入力される。これにより、第１トランジスタＴ１はオンの状態となり、第２トランジスタＴ２はオフの状態となる。よって、ブザー４０と第１スイッチ回路３１のグランド端子とが電気的に接続される。 Further, since the low-level voltage signal is input to the fifth transistor T5, the fifth transistor T5 is turned off, and the common terminal of the inverting circuit 33 and the first input terminal 31a are connected. In this case, since both the first output port 31 side and the inverting circuit 33 side are at a high level voltage, a high level voltage signal is input to the first input terminal 31a. Therefore, on the first switch circuit 31 side, a high level voltage is input to the base terminals of the first transistor T1 and the second transistor T2. As a result, the first transistor T1 is turned on, and the second transistor T2 is turned off. Therefore, the buzzer 40 and the ground terminal of the first switch circuit 31 are electrically connected.
　したがって、第１スイッチ回路３１のグランド端子と、ブザー４０と、第２スイッチ回路３２のコモン端子とが電気的に接続される。ブザー４０の第１端子４０ａには、ハイレベルの電圧が供給される。ブザー４０の第２端子４０ｂには、ローレベルの電圧が供給される。このため、ブザー４０に用いられる圧電セラミックスに対して電圧値Ｖ２の電圧が印加される。 Therefore, the ground terminal of the first switch circuit 31, the buzzer 40, and the common terminal of the second switch circuit 32 are electrically connected. A high level voltage is supplied to the first terminal 40 a of the buzzer 40. A low level voltage is supplied to the second terminal 40 b of the buzzer 40. For this reason, the voltage of the voltage value V <b> 2 is applied to the piezoelectric ceramic used for the buzzer 40.
　よって、待機時には、図２の右側のグラフに示すように、ブザー４０に電圧値Ｖ３の負の電圧が印加される期間と、ブザー４０に電圧値Ｖ２の正の電圧が印加される期間とが鳴動周波数と同一の周波数で交互に繰り返される。このため、ブザー４０に印加されるパルス電圧の最大値と最小値との差が、電圧値Ｖ２と電圧値Ｖ３とを合わせた電圧値Ｖ４となる。ここで、電気抵抗３５の電気抵抗値を調整することにより、電圧値Ｖ３の値を調整することができる。この場合、電圧値Ｖ１と電圧値Ｖ４とを等しくすることができる。これにより、待機時においても、定常駆動時と同一の電圧をブザー４０に印加することができる。 Therefore, at the time of standby, as shown in the graph on the right side of FIG. 2, there are a period in which a negative voltage having a voltage value V3 is applied to the buzzer 40 and a period in which a positive voltage having a voltage value V2 is applied to the buzzer 40. Repeated alternately at the same frequency as the ringing frequency. For this reason, the difference between the maximum value and the minimum value of the pulse voltage applied to the buzzer 40 is a voltage value V4 that is a combination of the voltage value V2 and the voltage value V3. Here, by adjusting the electric resistance value of the electric resistor 35, the value of the voltage value V3 can be adjusted. In this case, the voltage value V1 and the voltage value V4 can be made equal. Thus, the same voltage as that during steady driving can be applied to the buzzer 40 even during standby.
　従来のブザー鳴動装置では、機器の待機時にブザーを鳴動させる場合、電源電圧が定常駆動時よりも低くなっているため、ブザーの音量が小さくなってしまう可能性がある。図３は、定常駆動時及び待機時において、従来のブザーに印加される電圧値と時間との関係を示すグラフである。図３に示すように、定常駆動時には電圧値Ｖａのパルス信号がブザーに印加されているが、待機時には電圧値Ｖａよりも小さい電圧値Ｖｂのパルス信号がブザーに印加される。これにより、待機時のブザーの音量は、定常駆動時よりも小さくなる可能性がある。 In the conventional buzzer sounding device, when the buzzer is sounded when the apparatus is on standby, the power supply voltage is lower than that during steady driving, so the volume of the buzzer may be reduced. FIG. 3 is a graph showing the relationship between the voltage value applied to the conventional buzzer and time during steady driving and standby. As shown in FIG. 3, a pulse signal having a voltage value Va is applied to the buzzer during steady driving, but a pulse signal having a voltage value Vb smaller than the voltage value Va is applied to the buzzer during standby. Thereby, the volume of the buzzer during standby may be smaller than during steady driving.
　これに対して、実施の形態１によれば、定常駆動時においては第２スイッチ回路３２にパルス信号が供給される場合には第１スイッチ回路３１にローレベルの電圧信号を供給し、待機時おいては第２スイッチ回路３２にパルス信号のうちローレベルの電圧信号が供給される場合には第１スイッチ回路３１にハイレベルの電圧信号を供給すると共にパルス信号のうちハイレベルの電圧信号が供給される場合には第１スイッチ回路３１にローレベルの電圧信号を供給するため、定常駆動時及び待機時においてブザーの音量を維持することが可能となる。 On the other hand, according to the first embodiment, when a pulse signal is supplied to the second switch circuit 32 during steady driving, a low-level voltage signal is supplied to the first switch circuit 31 and the standby switch In this case, when a low-level voltage signal is supplied to the second switch circuit 32, a high-level voltage signal is supplied to the first switch circuit 31 and a high-level voltage signal is supplied to the first switch circuit 31. When supplied, since a low level voltage signal is supplied to the first switch circuit 31, the volume of the buzzer can be maintained during steady driving and standby.
　また、実施の形態１によれば、制御回路２０が第１出力ポート２１を介して、電源供給回路１０における電源電圧の切り替えと、第１入力端子３１ａの電圧信号の切り替えとを同時に行うことができるため、定常駆動時と待機時との動作の切り替え制御が単純化される。また、実施の形態１によれば、電源電圧を瞬時に切り替えることができない回路であっても、ブザー４０の応答までの時間を短縮化することができる。 Further, according to the first embodiment, the control circuit 20 can simultaneously switch the power supply voltage in the power supply circuit 10 and the voltage signal of the first input terminal 31a via the first output port 21. Therefore, the switching control of the operation between the steady driving and the standby is simplified. Further, according to the first embodiment, even when the power supply voltage cannot be switched instantaneously, the time until the buzzer 40 responds can be shortened.
実施の形態２．
　図４は、実施の形態２に係るブザー鳴動装置２の回路を示すブロック図である。実施の形態２では、実施の形態１に係るブザー鳴動装置１と同一の構成要素には同一の符号を付すこととし、説明を省略又は簡略化する。 Embodiment 2. FIG.
FIG. 4 is a block diagram illustrating a circuit of the buzzer sounding device 2 according to the second embodiment. In the second embodiment, the same components as those in the buzzer sounding device 1 according to the first embodiment are denoted by the same reference numerals, and description thereof is omitted or simplified.
　図４に示すように、ブザー鳴動装置２は、電源の供給元である電源供給回路１０と、電圧信号を生成する制御回路２０と、ブザー４０を鳴動させるブザー鳴動回路３０とを備えている。また、制御回路２０は、電源供給回路１０から供給される電源電圧の大きさに応じて第１入力端子３１ａに入力する電圧信号を切り替える切替回路５０を有している。 As shown in FIG. 4, the buzzer sounding device 2 includes a power supply circuit 10 that is a power supply source, a control circuit 20 that generates a voltage signal, and a buzzer sounding circuit 30 that sounds a buzzer 40. Further, the control circuit 20 includes a switching circuit 50 that switches a voltage signal input to the first input terminal 31a in accordance with the magnitude of the power supply voltage supplied from the power supply circuit 10.
　切替回路５０は、コモン端子に接続された電気抵抗５１と、電気抵抗５１に接続されたツェナーダイオード５２と、ツェナーダイオード５２に接続された第６トランジスタＴ６と、第６トランジスタＴ６に接続された第７トランジスタＴ７と、コモン端子と第７トランジスタＴ７とに接続されたドロップ抵抗５３と、電圧信号を出力可能な出力ポート５４とを有している。 The switching circuit 50 includes an electric resistor 51 connected to the common terminal, a Zener diode 52 connected to the electric resistor 51, a sixth transistor T6 connected to the Zener diode 52, and a sixth transistor T6 connected to the sixth transistor T6. 7 transistor T7, a drop resistor 53 connected to the common terminal and the seventh transistor T7, and an output port 54 capable of outputting a voltage signal.
　ツェナーダイオード５２は、電源電圧によってオン及びオフが変化する。つまり、ツェナーダイオード５２は、電源電圧が定常駆動時の電圧値Ｖ１である場合にオンとなり、電源電圧が待機時の電圧値Ｖ２である場合にオフとなる。 The zener diode 52 is turned on and off depending on the power supply voltage. That is, the Zener diode 52 is turned on when the power supply voltage is the voltage value V1 during steady driving, and is turned off when the power supply voltage is the standby voltage value V2.
　第６トランジスタＴ６には、ＮＰＮ型のバイポーラトランジスタが用いられる。第６トランジスタＴ６のベース端子は、ツェナーダイオード５２に接続されている。第６トランジスタＴ６のエミッタ端子は、グランド端子に接続されている。第６トランジスタＴ６のコレクタ端子は、第７トランジスタＴ７のベース端子に接続されている。第６トランジスタＴ６は、ベース端子にハイレベルの電圧信号が印加された場合にはグランド端子と第７トランジスタＴ７のベース端子との接続がオンの状態となり、ローレベルの電圧信号が印加された場合には接続がオフの状態となる。 An NPN bipolar transistor is used as the sixth transistor T6. The base terminal of the sixth transistor T6 is connected to the Zener diode 52. The emitter terminal of the sixth transistor T6 is connected to the ground terminal. The collector terminal of the sixth transistor T6 is connected to the base terminal of the seventh transistor T7. In the sixth transistor T6, when a high level voltage signal is applied to the base terminal, the connection between the ground terminal and the base terminal of the seventh transistor T7 is turned on, and a low level voltage signal is applied. The connection is turned off.
　第７トランジスタＴ７には、ＰＮＰ型のバイポーラトランジスタが用いられる。第７トランジスタＴ７のベース端子は、第６トランジスタＴ６のコレクタ端子に接続されている。第７トランジスタＴ７のエミッタ端子は、ドロップ抵抗５３に接続されている。第７トランジスタＴ７のコレクタ端子は、出力ポート５４に接続されている。第７トランジスタＴ７は、ベース端子にハイレベルの電圧信号が印加された場合には出力ポート５４とドロップ抵抗５３及びコモン端子との接続がオンの状態となり、ローレベルの電圧信号が印加された場合には接続がオフの状態となる。 A PNP bipolar transistor is used as the seventh transistor T7. The base terminal of the seventh transistor T7 is connected to the collector terminal of the sixth transistor T6. The emitter terminal of the seventh transistor T7 is connected to the drop resistor 53. The collector terminal of the seventh transistor T7 is connected to the output port 54. In the seventh transistor T7, when a high level voltage signal is applied to the base terminal, the connection between the output port 54, the drop resistor 53 and the common terminal is turned on, and a low level voltage signal is applied. The connection is turned off.
　次に、ブザー鳴動装置２の動作を説明する。まず定常駆動時の動作を説明する。定常駆動時において、制御回路２０は、第１出力ポート２１にローレベルの電圧信号を出力する。電源供給回路１０には、ローレベルの電圧信号が入力される。この入力により、電源供給回路１０は、定常駆動時に対応する電圧値Ｖ１の電圧をコモン端子に供給する。 Next, the operation of the buzzer sounding device 2 will be described. First, the operation during steady driving will be described. During steady driving, the control circuit 20 outputs a low level voltage signal to the first output port 21. A low level voltage signal is input to the power supply circuit 10. With this input, the power supply circuit 10 supplies a voltage having a voltage value V1 corresponding to the steady driving to the common terminal.
　このとき、切替回路５０では、コモン端子及び電気抵抗５１を介してツェナーダイオード５２に電圧値Ｖ１の電圧が印加される。これにより、ツェナーダイオード５２がオンの状態となり、コモン端子と第６トランジスタＴ６のベース端子とが接続される。よって、第６トランジスタＴ６のベース端子にはハイレベルの電圧信号が印加され、第６トランジスタＴ６がオンの状態となる。これにより、グランド端子と第７トランジスタＴ７のベース端子とが接続される。よって、第７トランジスタＴ７のベース端子にはローレベルの電圧信号が印加され、第７トランジスタＴ７がオンの状態となる。これにより、出力ポート５４とドロップ抵抗５３及びコモン端子とが接続され、出力ポート５４からはローレベルの電圧信号が出力される。よって、第１入力端子３１ａには、出力ポート５４からのローレベルの電圧信号が入力される。ここで、プルアップ抵抗３６の電気抵抗値及び上記のドロップ抵抗５３の電気抵抗値について、第５トランジスタＴ５がオフの場合かつ出力ポート５４にローレベルの電圧信号が供給される場合に、第１入力端子３１ａにローレベルの電圧信号が入力される値に予め設定しておく。これにより、第１出力ポート２１にローレベルの電気信号が供給される場合に、実施の形態１と同様に、第１入力端子３１ａに供給される電圧信号がローレベルに固定されることになる。 At this time, in the switching circuit 50, the voltage of the voltage value V1 is applied to the Zener diode 52 via the common terminal and the electric resistance 51. As a result, the Zener diode 52 is turned on, and the common terminal and the base terminal of the sixth transistor T6 are connected. Therefore, a high level voltage signal is applied to the base terminal of the sixth transistor T6, and the sixth transistor T6 is turned on. As a result, the ground terminal and the base terminal of the seventh transistor T7 are connected. Therefore, a low level voltage signal is applied to the base terminal of the seventh transistor T7, and the seventh transistor T7 is turned on. As a result, the output port 54 is connected to the drop resistor 53 and the common terminal, and a low-level voltage signal is output from the output port 54. Therefore, the low level voltage signal from the output port 54 is input to the first input terminal 31a. Here, regarding the electrical resistance value of the pull-up resistor 36 and the electrical resistance value of the drop resistor 53 described above, when the fifth transistor T5 is off and the low level voltage signal is supplied to the output port 54, the first The value is set in advance so that a low level voltage signal is input to the input terminal 31a. As a result, when a low-level electrical signal is supplied to the first output port 21, the voltage signal supplied to the first input terminal 31a is fixed at a low level as in the first embodiment. .
　また、制御回路２０は、実施の形態１の定常駆動時と同様に、ブザー４０の鳴動周波数と同一周波数のパルス信号を第２出力ポート２２に出力する。このパルス信号により、第２入力端子３２ａには、ハイレベルの電圧信号とローレベルの電圧信号とが交互に入力される。 Also, the control circuit 20 outputs a pulse signal having the same frequency as the ringing frequency of the buzzer 40 to the second output port 22 as in the steady driving of the first embodiment. By this pulse signal, a high level voltage signal and a low level voltage signal are alternately input to the second input terminal 32a.
　よって、定常駆動時には、実施の形態１の定常駆動時と同様に、図２の左側のグラフに示すように、ブザー４０に電圧値Ｖ１が印加される期間と、ブザー４０に電圧が印加されない期間とが鳴動周波数と同一の周波数で交互に繰り返される。 Therefore, during steady driving, as in the steady driving of the first embodiment, as shown in the left graph of FIG. 2, the period in which the voltage value V1 is applied to the buzzer 40 and the period in which no voltage is applied to the buzzer 40. Are alternately repeated at the same frequency as the ringing frequency.
　続いて、待機時の動作を説明する。待機時において、制御回路２０は、第１出力ポート２１にハイレベルの電圧信号を出力する。電源供給回路１０には、ハイレベルの電圧信号が入力される。電圧信号の入力により、電源供給回路１０は、待機時に対応する電圧値Ｖ２の電圧をコモン端子に供給する。 Next, the operation during standby will be described. During standby, the control circuit 20 outputs a high level voltage signal to the first output port 21. A high level voltage signal is input to the power supply circuit 10. In response to the input of the voltage signal, the power supply circuit 10 supplies the voltage of the voltage value V2 corresponding to the standby time to the common terminal.
　このとき、切替回路５０では、コモン端子及び電気抵抗５１を介してツェナーダイオード５２に電圧値Ｖ２の電圧が印加される。これにより、ツェナーダイオード５２がオフの状態となり、第６トランジスタＴ６のベース端子にはハイレベルの電圧が印加されない状態となる。よって、第６トランジスタＴ６がオフの状態となり、第７トランジスタＴ７のベース端子にはローレベルの電圧が印加されない状態となる。このため、第７トランジスタＴ７がオフの状態となり、出力ポート５４からはローレベルの電圧信号が出力されない状態となる。この場合、第１入力端子３１ａには、反転回路３３から電圧信号が入力される。 At this time, in the switching circuit 50, the voltage of the voltage value V2 is applied to the Zener diode 52 via the common terminal and the electric resistance 51. As a result, the Zener diode 52 is turned off, and a high level voltage is not applied to the base terminal of the sixth transistor T6. Therefore, the sixth transistor T6 is turned off, and a low level voltage is not applied to the base terminal of the seventh transistor T7. Therefore, the seventh transistor T7 is turned off, and a low level voltage signal is not output from the output port 54. In this case, a voltage signal is input from the inverting circuit 33 to the first input terminal 31a.
　第２入力端子３２ａにハイレベルの電圧信号が入力された場合、第５トランジスタＴ５にハイレベルの電圧信号が入力される。このため、第５トランジスタＴ５がオンの状態となり、反転回路３３のコモン端子とグランド端子とが接続される。このため、第１入力端子３１ａにはローレベルの電圧信号が入力される。したがって、第１スイッチ回路３１側では、第１トランジスタＴ１及び第２トランジスタＴ２のベース端子にはローレベルの電圧が入力される。これにより、第１トランジスタＴ１はオンの状態となり、第２トランジスタＴ２はオフの状態となる。よって、ブザー４０と第１スイッチ回路３１のコモン端子とが電気的に接続される。 When a high level voltage signal is input to the second input terminal 32a, a high level voltage signal is input to the fifth transistor T5. Therefore, the fifth transistor T5 is turned on, and the common terminal and the ground terminal of the inverting circuit 33 are connected. Therefore, a low level voltage signal is input to the first input terminal 31a. Therefore, on the first switch circuit 31 side, a low level voltage is input to the base terminals of the first transistor T1 and the second transistor T2. As a result, the first transistor T1 is turned on, and the second transistor T2 is turned off. Therefore, the buzzer 40 and the common terminal of the first switch circuit 31 are electrically connected.
　また、第２入力端子３２ａにローレベルの電圧信号が入力された場合、第５トランジスタＴ５にはローレベルの電圧信号が入力される。このため、第５トランジスタＴ５がオフの状態となり、反転回路３３のコモン端子と第１入力端子３１ａとが接続される。したがって、第１スイッチ回路３１側では、第１トランジスタＴ１及び第２トランジスタＴ２のベース端子にはハイレベルの電圧が入力される。これにより、第１トランジスタＴ１はオンの状態となり、第２トランジスタＴ２はオフの状態となる。よって、ブザー４０と第１スイッチ回路３１のグランド端子とが電気的に接続される。 Further, when a low level voltage signal is input to the second input terminal 32a, a low level voltage signal is input to the fifth transistor T5. For this reason, the fifth transistor T5 is turned off, and the common terminal of the inverting circuit 33 and the first input terminal 31a are connected. Therefore, on the first switch circuit 31 side, a high level voltage is input to the base terminals of the first transistor T1 and the second transistor T2. As a result, the first transistor T1 is turned on, and the second transistor T2 is turned off. Therefore, the buzzer 40 and the ground terminal of the first switch circuit 31 are electrically connected.
　よって、待機時には、実施の形態１の待機時と同様に、図２の右側のグラフに示すように、ブザー４０に電圧値Ｖ３の負の電圧が印加される期間と、ブザー４０に電圧値Ｖ２の正の電圧が印加される期間とが鳴動周波数と同一の周波数で交互に繰り返される。 Therefore, at the time of standby, similarly to the standby at the time of the first embodiment, as shown in the graph on the right side of FIG. 2, the period during which the negative voltage of the voltage value V3 is applied to the buzzer 40 and the voltage value V2 to the buzzer 40. The period during which the positive voltage is applied is alternately repeated at the same frequency as the ringing frequency.
　このように、実施の形態２によれば、切替回路５０により、電源供給回路１０から供給される電源電圧の大きさに応じて、第１入力端子３１ａにハイレベル又はローレベルの電圧信号が入力されることになる。これにより、実施の形態１と同様に、電圧信号の切り替えを迅速化することができる。 As described above, according to the second embodiment, the switching circuit 50 inputs a high-level or low-level voltage signal to the first input terminal 31a according to the magnitude of the power supply voltage supplied from the power supply circuit 10. Will be. Thereby, similarly to Embodiment 1, switching of a voltage signal can be speeded up.
　以上の実施の形態に示した構成は、本発明の内容の一例を示すものであり、別の公知の技術と組み合わせることも可能であるし、本発明の要旨を逸脱しない範囲で、構成の一部を省略、変更することも可能である。 The configuration described in the above embodiment shows an example of the contents of the present invention, and can be combined with another known technique, and can be combined with other configurations without departing from the gist of the present invention. It is also possible to omit or change the part.
　Ｔ１　第１トランジスタ、Ｔ２　第２トランジスタ、Ｖ１，Ｖ２，Ｖ３，Ｖ４，Ｖａ，Ｖｂ　電圧値、Ｔ３　第３トランジスタ、Ｔ４　第４トランジスタ、Ｔ５　第５トランジスタ、Ｔ６　第６トランジスタ、Ｔ７　第７トランジスタ、１，２　ブザー鳴動装置、１０　電源供給回路、２０　制御回路、２１　第１出力ポート、２２　第２出力ポート、２３，３４，３５，５１　電気抵抗、５３　ドロップ抵抗、３０　ブザー鳴動回路、３１　第１スイッチ回路、３１ａ　第１入力端子、３２　第２スイッチ回路、３２ａ　第２入力端子、３３　反転回路、３６　プルアップ抵抗、３７　接続端子、４０　ブザー、４０ａ　第１端子、４０ｂ　第２端子、５０　切替回路、５２　ツェナーダイオード、５４　出力ポート。 T1 1st transistor, T2 2nd transistor, V1, V2, V3, V4, Va, Vb voltage value, T3 3rd transistor, T4 4th transistor, T5 5th transistor, T6 6th transistor, T7 7th transistor, 1 , 2 buzzer sounding device, 10 power supply circuit, 20 control circuit, 21 first output port, 22 second output port, 23, 34, 35, 51 electrical resistance, 53 drop resistance, 30 buzzer sounding circuit, 31 first switch Circuit, 31a first input terminal, 32 second switch circuit, 32a second input terminal, 33 inverting circuit, 36 pull-up resistor, 37 connection terminal, 40 buzzer, 40a first terminal, 40b second terminal, 50 switching circuit, 52 Zener diode, 54 output port.

Claims (8)

  1. 　圧電素子を用いて形成されるブザーと、
    　前記ブザーに接続された第１スイッチ回路及び第２スイッチ回路を有するブザー鳴動回路と、
    　前記ブザー鳴動回路に接続されるコモン端子に対して定常駆動時には第１電圧値の電圧を供給し、待機時には前記第１電圧値よりも小さい第２電圧値の電圧を供給する電源供給回路と、
    　前記第１スイッチ回路及び前記第２スイッチ回路に対して、前記定常駆動時には前記ブザーに前記第１電圧値の正の電圧信号と正負の基準値の電圧信号とを交互に印加させ、前記待機時には前記ブザーに前記第２電圧値の正負いずれか一方の電圧信号と前記第１電圧値よりも小さい第３電圧値の正負いずれか他方の電圧信号とを交互に印加させる制御回路と
    　を備えることを特徴とするブザー鳴動装置。     A buzzer formed using a piezoelectric element;
    A buzzer sounding circuit having a first switch circuit and a second switch circuit connected to the buzzer;
    A power supply circuit that supplies a voltage having a first voltage value to the common terminal connected to the buzzer sounding circuit during steady driving and supplies a voltage having a second voltage value smaller than the first voltage value during standby;
    For the first switch circuit and the second switch circuit, a positive voltage signal of the first voltage value and a voltage signal of a positive / negative reference value are alternately applied to the buzzer during the steady driving, and during the standby time A control circuit for alternately applying either the positive or negative voltage signal of the second voltage value and the positive or negative voltage signal of the third voltage value smaller than the first voltage value to the buzzer. A buzzer sounding device.
  2. 　前記第３電圧値は、前記第２電圧値との和が前記第１電圧値に等しくなる値である
    　ことを特徴とする請求項１に記載のブザー鳴動装置。     The buzzer sounding device according to claim 1, wherein the third voltage value is a value such that a sum of the third voltage value and the second voltage value is equal to the first voltage value.
  3. 　前記第１スイッチ回路は、ハイレベルの電圧信号が供給された場合には前記ブザーとグランド端子とを接続し、ローレベルの電圧信号が供給された場合には前記ブザーとコモン端子とを接続し、
    　前記第２スイッチ回路は、前記ハイレベルの電圧信号が供給された場合には前記ブザーと前記コモン端子とを接続し、前記ローレベルの電圧信号が供給された場合には前記ブザーと前記コモン端子とを接続し、
    　前記制御回路は、前記第１スイッチ回路に対して前記定常駆動時には前記電源供給回路及び前記第１スイッチ回路に対して前記ローレベルの電圧信号を供給すると共に前記待機時には前記ハイレベルの電圧信号を供給し、前記第２スイッチ回路に対しては前記定常駆動時及び前記待機時に前記ハイレベルの電圧信号と前記ローレベルの電圧信号とが交互に繰り返されるパルス信号を供給する
    　ことを特徴とする請求項１又は請求項２に記載のブザー鳴動装置。     The first switch circuit connects the buzzer and the ground terminal when a high level voltage signal is supplied, and connects the buzzer and the common terminal when a low level voltage signal is supplied. ,
    The second switch circuit connects the buzzer and the common terminal when the high level voltage signal is supplied, and the buzzer and the common terminal when the low level voltage signal is supplied. And connect
    The control circuit supplies the low-level voltage signal to the power supply circuit and the first switch circuit during the steady driving to the first switch circuit, and the high-level voltage signal during the standby. And supplying the second switch circuit with a pulse signal in which the high-level voltage signal and the low-level voltage signal are alternately repeated during the steady driving and the standby. The buzzer sounding device according to claim 1 or 2.
  4. 　前記制御回路は、前記定常駆動時においては前記第２スイッチ回路に前記パルス信号が供給される場合に前記第１スイッチ回路に前記ローレベルの電圧信号を供給し、前記待機時おいては前記第２スイッチ回路に前記パルス信号のうち前記ローレベルの電圧信号が供給される場合に前記第１スイッチ回路にハイレベルの電圧信号を供給すると共に前記パルス信号のうち前記ハイレベルの電圧信号が供給される場合に前記第１スイッチ回路にローレベルの電圧信号を供給する
    　ことを特徴とする請求項３に記載のブザー鳴動装置。     The control circuit supplies the low-level voltage signal to the first switch circuit when the pulse signal is supplied to the second switch circuit during the steady driving, and the first signal during the standby time. When the low-level voltage signal of the pulse signal is supplied to the two-switch circuit, the high-level voltage signal is supplied to the first switch circuit and the high-level voltage signal of the pulse signal is supplied. The buzzer sounding device according to claim 3, wherein a low-level voltage signal is supplied to the first switch circuit.
  5. 　前記第１スイッチ回路は、前記ブザーと前記コモン端子との間に接続され前記ローレベルの電圧信号が供給された場合に前記第３電圧値を調整する電気抵抗を有する
    　ことを特徴とする請求項４に記載のブザー鳴動装置。     The first switch circuit has an electric resistance that is connected between the buzzer and the common terminal and adjusts the third voltage value when the low-level voltage signal is supplied. 4. The buzzer sounding device according to 4.
  6. 　前記第１スイッチ回路は、前記コモン端子に接続されＰＮＰトランジスタからなる第１トランジスタと、前記第１トランジスタに直列に接続されると共に前記グランド端子に接続されＮＰＮトランジスタからなる第２トランジスタとを有し、
    　前記第２スイッチ回路は、前記コモン端子に接続されＰＮＰトランジスタからなる第３トランジスタと、前記第３トランジスタに直列に接続されると共に前記グランド端子に接続されＮＰＮトランジスタからなる第４トランジスタとを有する
    　ことを特徴とする請求項３から請求項５のうちいずれか一項に記載のブザー鳴動装置。     The first switch circuit includes a first transistor connected to the common terminal and made of a PNP transistor, and a second transistor connected in series to the first transistor and connected to the ground terminal and made of an NPN transistor. ,
    The second switch circuit includes a third transistor connected to the common terminal and made of a PNP transistor, and a fourth transistor connected in series to the third transistor and connected to the ground terminal and made of an NPN transistor. The buzzer sounding device according to any one of claims 3 to 5, wherein:
  7. 　前記制御回路は、前記電源供給回路から供給される電圧の大きさに応じて前記第１スイッチ回路に入力する電圧信号を切り替える切替回路を有する
    　ことを特徴とする請求項３から請求項６のうちいずれか一項に記載のブザー鳴動装置。     The control circuit includes a switching circuit that switches a voltage signal input to the first switch circuit in accordance with a magnitude of a voltage supplied from the power supply circuit. The buzzer sounding device according to any one of the above.
  8. 　前記切替回路は、ツェナー電圧値が前記第１電圧値と前記第２電圧値との間の値であるツェナーダイオードを有する
    　ことを特徴とする請求項７に記載のブザー鳴動装置。     The buzzer sounding device according to claim 7, wherein the switching circuit includes a Zener diode whose Zener voltage value is a value between the first voltage value and the second voltage value.
PCT/JP2015/060399 2015-04-01 2015-04-01 Buzzer sounding device WO2016157487A1 (en)

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JPH07253786A (en) * 1994-03-16 1995-10-03 Tec Corp Driving device for piezoelectric buzzer
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