WO2016155085A1 - 节点连接芯片通讯电路及数据通讯方法 - Google Patents

节点连接芯片通讯电路及数据通讯方法 Download PDF

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Publication number
WO2016155085A1
WO2016155085A1 PCT/CN2015/078559 CN2015078559W WO2016155085A1 WO 2016155085 A1 WO2016155085 A1 WO 2016155085A1 CN 2015078559 W CN2015078559 W CN 2015078559W WO 2016155085 A1 WO2016155085 A1 WO 2016155085A1
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WO
WIPO (PCT)
Prior art keywords
chip
data
node
node connection
connection chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2015/078559
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English (en)
French (fr)
Inventor
张贯京
陈兴明
葛新科
张少鹏
方静芳
普拉纽克•克里斯基捏
古列莎⋅艾琳娜
波达别特⋅伊万
高伟明
梁昊原
梁艳妮
周荣
徐之艳
周亮
肖应芬
郑慧华
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Qianhai AnyCheck Information Technology Co Ltd
E Techno Information Technologies Co Ltd
Bio Tech Academy China Co Ltd
Shenzhen Gongchuang Science and Technology Development Co Ltd
Original Assignee
Shenzhen Qianhai AnyCheck Information Technology Co Ltd
E Techno Information Technologies Co Ltd
Bio Tech Academy China Co Ltd
Shenzhen Gongchuang Science and Technology Development Co Ltd
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Publication date
Application filed by Shenzhen Qianhai AnyCheck Information Technology Co Ltd, E Techno Information Technologies Co Ltd, Bio Tech Academy China Co Ltd, Shenzhen Gongchuang Science and Technology Development Co Ltd filed Critical Shenzhen Qianhai AnyCheck Information Technology Co Ltd
Publication of WO2016155085A1 publication Critical patent/WO2016155085A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure

Definitions

  • the present invention relates to the field of electronic information technology, and in particular, to a node connection chip communication circuit and a data communication method.
  • the existing node network detection system based on the node network usually places the loop circuit in the area to be tested. When a link of the loop circuit is destroyed, the node detection system based on the node network can obtain the information that has been destroyed. However, the loop circuit does not provide detailed information about the broken link. With the development of technology, in order to distinguish the damaged parts of the area to be tested, each part is designed with a separate circuit, but still has the disadvantages that are difficult to overcome - only part of which is destroyed and applied to textile clothing Monitoring textile damage is very limited because the technology does not allow the creation of high-density loops.
  • subnets that include many detection loops connected to the local microcontroller and send local status information to the host processor through the local microcontroller, but a large number of subnets means that the data transmission bus is too wide and the data processing speed is high. slow.
  • the main object of the present invention is to provide a node connection chip communication circuit and a data communication method, and transmit detailed node connection chip information through a node connection chip data communication circuit to quickly provide detailed node information for the node network.
  • the present invention provides a node connection chip communication circuit
  • the node connection chip communication circuit includes a first node connection chip and a second node connection chip, and the first node connection chip and the second node Connecting a chip signal connection and performing data communication
  • the node connection chip includes a microprocessor and a data port connected to the microprocessor signal
  • the data port includes a switching unit, a receiving unit, and a sending unit
  • the data port is
  • the microprocessor is connected by a power input end, a receiving data end, a receiving data ground end, a selecting end, a power output end, a transmitting data end, and a transmitting data ground end signal
  • the receiving data end includes receiving data input end and receiving data
  • the sending data end includes a sending data input end and a sending data output end;
  • the microprocessor of the first node connection chip controls the selection end of the first node connection chip to be connected to the power output end of the first node connection chip, the first node connection chip is a main chip, and the The data port sending unit of the first node connection chip is valid; the microprocessor of the second node connection chip controls the selection end of the second node connection chip to be connected with the receiving data end of the second node connection chip, The second node connection chip is a slave chip, and the data port receiving unit of the second node connection chip is valid.
  • the receiving unit and the switching unit are connected by a receiving input port and a receiving output port, and the receiving unit and the microprocessor pass the power input end, the receiving data end, and Receiving data ground signal connection;
  • the sending unit and the switching unit are connected by a signal of a transmitting input port and a transmitting output port, and the transmitting unit and the microprocessor are connected by the power output end, the transmitting data end, and the transmitting data ground end signal;
  • the switching unit is connected to the microprocessor through a selection end signal, and the processor controls the switching unit to communicate with the receiving unit through the selection terminal, or controls the switching unit to communicate with the sending unit;
  • the switching unit performs data communication with the outside world through the signal input end and the signal output end.
  • a first capacitor is disposed between the power output end of the first node connection chip and the data transmission end, and the first node is connected between the transmit input port of the chip and the transmit data end.
  • a first resistor is disposed between the transmit data output end of the first node connection chip and the transmit output port, and the first switch is disposed between the transmit data input end and the transmit input port of the first node connection chip
  • a second capacitor is disposed between the power input end of the second node connection chip and the receiving data ground, and a second resistor is disposed between the receiving input port of the second node connection chip and the receiving data ground end
  • a second inverter is disposed between the receiving data output end of the second node connection chip and the receiving output port
  • the second switching tube is disposed between the receiving data input end and the receiving input port of the second node connecting chip.
  • the present invention also provides a node connection chip data communication method, and the node connection chip data communication method includes the following steps:
  • the microprocessor of the first node connection chip controls the selection end of the first node connection chip to be connected to the power output end of the first node connection chip, and the first node connection chip is set as the main chip, and The transmitting unit that connects the data port of the first node to the chip is valid;
  • the microprocessor of the second node connection chip controls the selection end of the second node connection chip to be connected with the receiving data end of the second node connection chip, and the second node connection chip is set as a slave chip, and The receiving unit of the second node connecting the chip data port is valid;
  • the step S3 includes:
  • the data port of the first node connection chip sends data to the data port of the second node connection chip, and the data port of the second node connection chip receives the data sent by the data port of the first node connection chip.
  • S32 The data port of the second node connection chip sends data to the data port of the first node connection chip, and the data port of the first node connection chip receives data sent by the data port of the second node connection chip.
  • the step S31 includes:
  • the first node is connected to the microcontroller of the chip, and the transmit data output end is connected to the transmit data ground end signal;
  • S312 The power output end of the first node connection chip charges the first capacitor and the second capacitor via the first capacitor, the second capacitor, the first resistor, and the second resistor;
  • the first node is connected to the microcontroller of the chip to control the transmit data output end and the power output end signal connection;
  • S315 The second capacitor is discharged through the second resistor, and the second switch tube controls the receiving unit of the second node connected to the chip data port to receive the signal.
  • the step S32 includes:
  • the second node is connected to the microcontroller of the chip to control the receiving data output end and the receiving data ground end signal connection;
  • S322 The power input end of the second node connection chip charges the first capacitor and the second capacitor via the first capacitor, the second capacitor, the first resistor, and the second resistor;
  • the second node is connected to the microcontroller of the chip to control the receiving data output end and the power input end signal connection;
  • S325 The first capacitor is discharged through the first resistor, and the first switch tube controls the transmitting unit of the first node connected to the chip data port to receive the signal.
  • the embodiment of the present invention controls the transmitting unit or the receiving unit of the data port to be effective by the microcontroller connected to the chip, thereby connecting the first node connecting chip and the second node connecting chip.
  • the main chip and the slave chip are respectively set to provide a data communication link for the neighbor node connection chip, and the detailed node connection chip information is transmitted through the node connection chip data communication circuit to quickly provide detailed node information for the node network.
  • FIG. 1 is a block diagram showing a connection of a preferred embodiment of a node connection chip communication circuit of the present invention
  • FIG. 2 is a schematic structural diagram of a circuit of a first preferred embodiment of a node connection chip according to the present invention
  • FIG. 3 is a schematic diagram showing a connection structure of a node-connected chip communication circuit according to a preferred embodiment of the present invention
  • FIG. 4 is a schematic structural diagram of a partial circuit of a node-connected chip communication circuit according to a preferred embodiment of the present invention.
  • FIG. 5 is a schematic flow chart of a method for data communication of a node connection chip according to the present invention.
  • the main object of the present invention is to provide a node connection chip communication circuit and a data communication method, and transmit detailed node connection chip information through a node connection chip data communication circuit to quickly provide detailed node information for the node network.
  • the present invention provides a node connection chip communication circuit.
  • FIG. 1 is a block diagram showing a connection structure of a node connection chip communication circuit according to the present invention.
  • the node connection chip communication circuit includes a first node connection chip 01 and a second node connection chip 02, and the first node The connection chip 01 is connected to the second node connection chip 02 for signal communication and data communication; specifically, referring to FIG. 2, FIG. 2 is a schematic diagram showing the circuit structure of the first preferred embodiment of the invention node connection chip, the node connection chip A microprocessor 1 and a data port 2 connected to the microprocessor 1 are provided.
  • the data port 2 includes a switching unit 21, a receiving unit 22 and a transmitting unit 23, and the data port 2 and the microprocessor 1 Receiving, by the power input end, the receiving data end, the receiving data ground end, the selecting end, the power output end, the transmitting data end, and the transmitting data ground end signal connection;
  • the receiving data end comprises receiving data input end and receiving data output end,
  • the transmitting data end includes a transmitting data input end and a transmitting data output end;
  • the microprocessor 1 is a microprocessing unit having data processing and storage functions for processing and storing data transmitted and received through the data port 2.
  • the data port 2 is configured to receive data sent by the outside world and send data that the node connection chip needs to send.
  • the data port 2 includes a switching unit 21, a receiving unit 22 and a transmitting unit 23, and the switching unit 21 is configured to control the receiving unit 22 and the transmitting unit 23 to be effective under the control of the microprocessor 1, ie
  • the data port 2 is configured to receive data sent by the outside world or data used to send the node connection chip.
  • the external environment refers to data communication between the first node connection chip 01 and the second node connection chip 02.
  • FIG. 3 is a schematic diagram showing a connection structure of a node-connected chip communication circuit according to a preferred embodiment of the present invention.
  • the microprocessor of the first node connection chip 01 controls the selection end of the first node connection chip 01 to be connected to the power output end of the first node connection chip 01, and the first node connects the chip 01 to the main chip. And the data port sending unit of the first node connection chip 01 is valid; the microprocessor of the second node connection chip 02 controls the selection end of the second node connection chip 02 and the second node connection chip 02
  • the receiving data terminal is connected, the second node connecting chip 02 is a slave chip, and the data port receiving unit of the second node connecting chip 02 is valid.
  • the first node connection chip can be set as the slave chip and the second node connection chip can be set as the master chip in the same manner.
  • the transmitting unit or the receiving unit of the data port is controlled by the microcontroller connected to the chip, so that the first node connecting chip and the second node connecting chip are respectively set as the master chip and the slave chip, and the neighbor node is connected to the chip.
  • the data communication link is provided, and the detailed node connection chip information is transmitted through the node connection chip data communication circuit to quickly provide detailed node information for the node network.
  • the first node connection chip 01 and the second node connection chip 02 of FIG. 3 exemplify the circuit structure of the second preferred embodiment of the node connection chip of the present invention.
  • the receiving unit 22 and the switching unit 21 are connected by a receiving input port and a receiving output port, and the receiving unit 22 and the microprocessor 1 receive data through the power input terminal.
  • the sending unit 23 and the switching unit 21 are connected by a transmitting input port and a transmitting output port signal, and the sending unit 23 and the microprocessor 1 pass the power output end, the transmitting data end, and the transmitting data ground end signal. connection;
  • the switching unit 21 is connected to the microprocessor 1 by a selection terminal signal, and the microprocessor 1 controls the switching unit 21 to communicate with the receiving unit 22 through the selection terminal, or controls the switching unit 21
  • the communication unit 23 is in communication with the transmitting unit 23; the switching unit 21 performs data communication with the outside world through the signal input end and the signal output end.
  • the process of the node connection chip transmitting and receiving data of the present invention is as follows: when the node connection chip needs to send data to the neighbor node, the microprocessor 1 controls the switching unit 21 and the sending unit 23 through the selection terminal. The data is transmitted through the transmission input port and the transmission output port of the transmitting unit 23, and finally transmitted through the signal output end of the switching unit to complete the transmission of data. The power output and the transmit data ground are used to provide power to the transmitting unit.
  • the microprocessor 1 controls the switching unit 21 to communicate with the receiving unit 22 via the selection terminal via the signal input end of the switching unit 21, And a receiving input port to which the switching unit 21 is connected to the receiving unit 22, and a receiving data terminal connected to the receiving unit 22 are transmitted to the microprocessor 1 to complete reception of data.
  • FIG. 4 is a schematic structural diagram showing a partial circuit of a node-connected chip communication circuit according to a preferred embodiment of the present invention.
  • the intermediate line is used as a demarcation point.
  • the Tranceiver is the transmitting unit of the first node connecting chip according to the present invention, which is located on the left side in the schematic diagram, and the Receiver in the figure is the second node in the present invention.
  • the receiving unit of the chip is located on the right side in the present diagram.
  • the first node is connected to a power output of the chip (Power A first capacitor C1 is disposed between the output node and the GND of the transmission data (left side), and the first node is connected to the transmission input port (left side) of the chip (In) and the data transmission end (left side) a first resistor R1 is disposed between GND, and the first node is connected to the transmit data output end of the chip (on the left side)
  • the first inverter is set between the output and the output output port (left side) Out (+), and in FIG.
  • the switching transistor Q2 and Q3 are combined to form an inverter, that is, when the data output end is transmitted (left side )Data When output is high, the output output port (left side) Out (+) is low level, and the inverter designed by the switch tube combination can reduce data interference when sending the data input terminal (left side) Data When output is high, Q2 is turned on, and the output output port (left side) Out (+) is low, and vice versa.
  • the first node is connected to the transmit data input end of the chip (on the left side)
  • the first switch Q1 is set between input and the input input port (left side) In(-), when the data input end (left side) is sent When the input is high, the switch Q1 is turned on, and the data is transmitted to the left In(-) to reduce data interference; the second node is connected to the power input terminal of the chip.
  • a second capacitor C2 is disposed between the input and the receiving data ground (right side) GND, and the second node is connected to the chip receiving input port (on the right side) In (+) and the receiving data ground end (on the right side)
  • a second resistor R2 is disposed between GND, the second resistor R2 is connected in series with the second capacitor C2, and the second node is connected to the receiving data output end (right side) of the chip.
  • a second inverter is provided between Output and the output output port (on the right) Out(-), and in FIG. 4, a combination of switching transistors Q4 and Q5 constitutes an inverter, that is, when receiving the output port (on the right side) When Out(-) is high, the data output (right side) is received.
  • Output is low level, the inverter designed by the switch tube combination can reduce data interference.
  • Q5 When the output output port (on the right side) is high (out), Q5 is turned on, and the data output end (right side) is received. Output is low and vice versa.
  • the second node is connected to the receiving data input end (on the right side) of the chip
  • the second switch Q6 is set between the input and the receiving input port (on the right) In (+), when receiving the data input (right side) Data When the input is high, the switch Q6 is turned on, and the data is transmitted to the right In(+) to reduce data interference.
  • the embodiment of the present invention describes the working principle of the node-connected chip data communication circuit through the schematic diagram of the partial circuit structure of the preferred embodiment.
  • the data communication process is simple and can reduce signal interference, and improves the working efficiency of the node-connected chip data communication circuit.
  • the present invention also provides a node connection chip data communication method.
  • FIG. 5 is a schematic flow chart of a preferred embodiment of a data connection method for a node connection chip according to the present invention.
  • the node connection chip data communication method includes the following steps:
  • the microprocessor of the first node connection chip controls the selection end of the first node connection chip to be connected to the power output end of the first node connection chip, and the first node connection chip is set as the main chip, and The transmitting unit that connects the data port of the first node to the chip is valid;
  • the microprocessor of the second node connection chip controls the selection end of the second node connection chip to be connected with the receiving data end of the second node connection chip, and the second node connection chip is set as a slave chip, and The receiving unit of the second node connecting the chip data port is valid;
  • the process of data communication between the node connection chip and the other node connection chip of the present invention is as follows: when the node connection chip needs to send data to other node connection chips, the node 1 connects the chip microprocessor 1 through the station.
  • the selection terminal controls the switching unit 21 to communicate with the sending unit 23, and the data is transmitted through the transmitting input port and the transmitting output port of the sending unit 23 through the transmitting data end, and finally transmitted through the signal output end of the switching unit, The transmission of data.
  • the power output and the transmit data ground are used to provide power to the transmitting unit.
  • the microprocessor 1 controls the switching unit 21 to communicate with the receiving unit 22 via the selection terminal via the signal input end of the switching unit 21, And a receiving input port to which the switching unit 21 is connected to the receiving unit 22, and a receiving data terminal connected to the receiving unit 22 are transmitted to the microprocessor 1 to complete reception of data.
  • the transmitting unit or the receiving unit of the data port is controlled by the microcontroller connected to the chip, so that the first node connecting chip and the second node connecting chip are respectively set as the master chip and the slave chip, and the neighbor node is connected to the chip.
  • the data communication link is provided, and the detailed node connection chip information is transmitted through the node connection chip data communication circuit to quickly provide detailed node information for the node network.
  • the step S3 includes:
  • the data port of the first node connection chip sends data to the data port of the second node connection chip, and the data port of the second node connection chip receives the data sent by the data port of the first node connection chip.
  • step S31 includes:
  • the first node is connected to the microcontroller of the chip, and the transmit data output end is connected to the transmit data ground end signal;
  • the first node is connected to the microcontroller of the chip to control the data output end (left side) Data.
  • Output is connected to the GND signal of the transmitting data terminal (left side), that is, the data output end (left side) Data Output is low, because the first node is connected to the transmit data output of the chip (Data).
  • the first inverter is set between the output and the output output port (on the left), and the inverter Q2 and Q3 are combined to form an inverter in Fig. 4. Therefore, the output port is transmitted (left side ) Out (+) is high.
  • S312 The power output end of the first node connection chip charges the first capacitor and the second capacitor via the first capacitor, the second capacitor, the first resistor, and the second resistor;
  • the first node when the output output port (left side) Out (+) is at a high level, the first node is connected to the power output terminal of the chip.
  • the output charges the first capacitor C1 and the second capacitor C2 via the first capacitor C1, the second capacitor C2, the first resistor R1, and the second resistor R2.
  • This process can be understood as the process in which the first node connection chip sends data to the second node connection chip.
  • the process can also be understood as the process in which the first node connection chip supplies power to the second node connection chip;
  • the data of the first node connecting the chip is sent to the receiving node of the data port of the second node connecting chip through the transmitting unit Tanceiver of the first node connecting the chip data port.
  • Unit Receiver Unit Receiver
  • the first node is connected to the microcontroller of the chip to control the transmit data output end and the power output end signal connection;
  • the first node is connected to the chip of the microcontroller to control the data output end (left side) of the Data output and the power output (Power) Output) signal connection, that is, the data output of the transmit data output (left side) is high, because the first node is connected to the transmit data output end of the chip (Data).
  • the first inverter is set between output and the output output port (on the left), and the inverter is combined with the switch Q2 and Q3 to form an inverter, that is, when the data output is transmitted.
  • the output output port (left side) Out (+) is low level, and the inverter designed by the switch tube combination can reduce data interference, that is, when transmitting the data input terminal (Data When output) is high, Q2 is on, and the output output port (on the left) is low (Out).
  • S315 The second capacitor is discharged through the second resistor, and the second switch tube controls the receiving unit of the second node connected to the chip data port to receive the signal.
  • step S3 further includes:
  • S32 The data port of the second node connection chip sends data to the data port of the first node connection chip, and the data port of the first node connection chip receives data sent by the data port of the second node connection chip.
  • step S32 includes:
  • the second node is connected to the microcontroller of the chip to control the receiving data output end and the receiving data ground end signal connection;
  • the second node is connected to the microcontroller of the chip to control the data output end (on the right side).
  • Output is connected to the GND signal of the receiving data (right side), that is, the receiving data output (right side) Data Output is low, because the first node is connected to the receiving data output of the chip (Data The first inverter is set between the output) and the receive output port (on the right) Out (+).
  • the switch Q4 and Q5 are combined to form an inverter. Therefore, the output port is received (the right side) ) Out (+) is high.
  • S322 The power input end of the second node connection chip charges the first capacitor and the second capacitor via the first capacitor, the second capacitor, the first resistor, and the second resistor;
  • the second node when the output output port (on the right side) Out (+) is at a high level, the second node is connected to the power input terminal of the chip.
  • the input charges the first capacitor C1 and the second capacitor C2 via the first capacitor C1, the second capacitor C2, the first resistor R1, and the second resistor R2.
  • This process can be understood as a process in which the second node connection chip receives data for the first node connection chip, and can also be understood as a process in which the second node connection chip supplies power to the first node connection chip;
  • the data of the second node connection chip is sent to the first node connection chip data port through the transmission unit Tanceiver of the second node connection chip data port.
  • Unit Receiver Unit Receiver
  • the second node is connected to the microcontroller of the chip to control the receiving data output end and the power input end signal connection;
  • the second node is connected to the chip of the microcontroller to control the data output end (on the right side) of the Data output and the power input end (Power Input) signal connection, that is, the data output of the receiving data output (right side) is high level, because the second node is connected to the receiving data output end of the chip (Data The first inverter is set between the output) and the receive output port (on the right) Out (+).
  • the switch Q4 and Q5 are combined to form an inverter, that is, when receiving the data output (right side) )Data When output is high, the output output port (on the right side) Out (+) is low level, and the inverter designed by the switch tube combination can reduce data interference, that is, when receiving the data input terminal (Data When output) is high, Q2 is on, and the output output port (on the right) is low (Out).
  • S325 The first capacitor is discharged through the first resistor, and the first switch tube controls the transmitting unit of the first node connected to the chip data port to receive the signal.

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Abstract

一种节点连接芯片通讯电路，包括第一节点连接芯片（01）和第二节点连接芯片（02），所述第一节点连接芯片（01）与所述第二节点连接芯片（02）信号连接且进行数据通讯。通过节点连接芯片的微处理器（1）控制数据端口（2）的发送单元（23）或者接收单元（22）有效，从而将第一节点连接芯片（01）和第二节点连接芯片（02）分别设置为主芯片和从芯片，为邻居节点连接芯片提供数据通讯链路，通过节点连接芯片数据通讯电路传输详细的节点连接芯片信息，为节点网络快速提供详细的节点信息。

Description

节点连接芯片通讯电路及数据通讯方法
技术领域
本发明涉及电子信息技术领域，尤其涉及一种节点连接芯片通讯电路及数据通讯方法。
背景技术
现有的基于节点网络的节点检测系统通常的做法是将环路电路放置在待测区域，当环路电路一个链路被毁坏时，基于节点网络的节点检测系统能够获取到已经损毁的信息，但环路电路不能提供关于毁坏链路的详细信息。随着技术的发展，为了区别待测区域的毁坏部分，每个部分设计了单独的回路，但仍然具有很难克服的缺点-只能识别其中的一部分被毁坏，且将其应用于纺织衣物中监测纺织物的损毁情况时非常受限，因为本技术不允许创建的高密度环路。因此，出现了包括很多与本地微控制器连接的检测环路并通过本地微控制器发送本地状态信息至主处理器的子网，但大量子网意味着数据传输总线要求太宽，数据处理速度慢。
基于此，有必要设计一种节点连接芯片通讯电路及数据通讯方法，通过节点连接芯片数据通讯电路传输详细的节点连接芯片信息，为节点网络快速提供详细的节点信息。
发明内容
本发明的主要目的在于提供一种节点连接芯片通讯电路及数据通讯方法，通过节点连接芯片数据通讯电路传输详细的节点连接芯片信息，为节点网络快速提供详细的节点信息。
为实现上述目的，本发明提供了一种节点连接芯片通讯电路，所述节点连接芯片通讯电路包括第一节点连接芯片和第二节点连接芯片，所述第一节点连接芯片与所述第二节点连接芯片信号连接且进行数据通讯；所述节点连接芯片包括微处理器以及与所述微处理器信号连接的数据端口，所述数据端口包括切换单元、接收单元和发送单元，所述数据端口与所述微处理器通过电源输入端、接收数据端、接收数据地端、选择端、电源输出端、发送数据端、发送数据地端信号连接；所述接收数据端包括接收数据输入端和接收数据输出端，所述发送数据端包括发送数据输入端和发送数据输出端；
所述第一节点连接芯片的微处理器控制所述第一节点连接芯片的选择端与所述第一节点连接芯片的电源输出端连接，所述第一节点连接芯片为主芯片，且所述第一节点连接芯片的数据端口发送单元有效；所述第二节点连接芯片的微处理器控制所述第二节点连接芯片的选择端与所述第二节点连接芯片的接收数据地端连接，所述第二节点连接芯片为从芯片，且所述第二节点连接芯片的数据端口接收单元有效。
在其中一个实施例中，所述接收单元与所述切换单元通过接收输入端口和接收输出端口信号连接，所述接收单元与所述微处理器之间通过所述电源输入端、接收数据端和接收数据地端信号连接；
所述发送单元与所述切换单元通过发送输入端口和发送输出端口信号连接，所述发送单元与所述微处理器之间通过所述电源输出端、发送数据端、发送数据地端信号连接；
所述切换单元与所述微处理器通过选择端信号连接，所述处理器通过所述选择端控制所述切换单元与所述接收单元连通，或控制所述切换单元与所述发送单元连通；所述切换单元通过所述信号输入端和所述信号输出端与外界进行数据通讯。
在其中一个实施例中，所述第一节点连接芯片的电源输出端与发送数据地端之间设置第一电容，所述第一节点连接芯片的发送输入端口与发送数据地端之间设置第一电阻，所述第一节点连接芯片的发送数据输出端与发送输出端口之间设置第一反相器，所述第一节点连接芯片的发送数据输入端与发送输入端口之间设置第一开关管；所述第二节点连接芯片的电源输入端与接收数据地端之间设置第二电容，所述第二节点连接芯片的接收输入端口与接收数据地端之间设置第二电阻，所述第二节点连接芯片的接收数据输出端与接收输出端口之间设置第二反相器，所述第二节点连接芯片的接收数据输入端与接收输入端口之间设置第二开关管。
为实现上述目的，本发明还提供了一种节点连接芯片数据通讯方法，所述节点连接芯片数据通讯方法包括如下步骤：
S1：第一节点连接芯片的微处理器控制所述第一节点连接芯片的选择端与所述第一节点连接芯片的电源输出端连接，设置所述第一节点连接芯片为主芯片，且所述第一节点连接芯片数据端口的发送单元有效；
S2：第二节点连接芯片的微处理器控制所述第二节点连接芯片的选择端与所述第二节点连接芯片的接收数据地端连接，设置所述第二节点连接芯片为从芯片，且所述第二节点连接芯片数据端口的接收单元有效；
S3：所述第一节点连接芯片的数据端口与所述第二节点连接芯片的数据端口数据通讯。
在其中一个实施例中，所述步骤S3包括：
S31：所述第一节点连接芯片的数据端口向所述第二节点连接芯片的数据端口发送数据，所述第二节点连接芯片的数据端口接收所述第一节点连接芯片的数据端口发送的数据；
S32：所述第二节点连接芯片的数据端口向所述第一节点连接芯片的数据端口发送数据，第一节点连接芯片的数据端口接收所述第二节点连接芯片的数据端口发送的数据。
在其中一个实施例中，所述步骤S31包括：
S311：第一节点连接芯片的微控制器控制发送数据输出端与发送数据地端信号连接；
S312：第一节点连接芯片的电源输出端经由第一电容、第二电容、第一电阻以及第二电阻，为第一电容和第二电容充电；
S313：充电结束后，第一节点连接芯片的数据经第一节点连接芯片数据端口的发送单元发送至第二节点连接芯片数据端口的接收单元；
S314：第一节点连接芯片的微控制器控制发送数据输出端与电源输出端信号连接；
S315：第二电容通过第二电阻放电，第二开关管控制第二节点连接芯片数据端口的接收单元接收信号。
在其中一个实施例中，所述步骤S32包括：
S321：第二节点连接芯片的微控制器控制接收数据输出端与接收数据地端信号连接；
S322：第二节点连接芯片的电源输入端经由第一电容、第二电容、第一电阻以及第二电阻，为第一电容和第二电容充电；
S323：充电结束后，第二节点连接芯片的数据经第二节点连接芯片数据端口的接收单元发送至第一节点连接芯片数据端口的发送单元；
S324：第二节点连接芯片的微控制器控制接收数据输出端与电源输入端信号连接；
S325：第一电容通过第一电阻放电，第一开关管控制第一节点连接芯片数据端口的发送单元接收信号。
本发明采用上述技术方案，带来的技术效果为：本发明实施例通过节点连接芯片的微控制器控制数据端口的发送单元或者接收单元有效，从而将第一节点连接芯片和第二节点连接芯片分别设置为主芯片和从芯片，为邻居节点连接芯片提供数据通讯链路，通过节点连接芯片数据通讯电路传输详细的节点连接芯片信息，为节点网络快速提供详细的节点信息。
附图说明
图1为本发明节点连接芯片通讯电路较佳实施例连接框图；
图2为本发明节点连接芯片第一较佳实施例电路结构示意图；
图3为本发明节点连接芯片通讯电路较佳实施例连接结构示意图；
图4为本发明节点连接芯片通讯电路较佳实施例局部电路结构示意图；
图5为本发明节点连接芯片数据通讯方法较佳实施例流程示意图。
本发明目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
本发明的主要目的在于提供一种节点连接芯片通讯电路及数据通讯方法，通过节点连接芯片数据通讯电路传输详细的节点连接芯片信息，为节点网络快速提供详细的节点信息。
为实现上述目的，本发明提供了一种节点连接芯片通讯电路。
参照图1，图1所示为本发明节点连接芯片通讯电路较佳实施例连接框图，所述节点连接芯片通讯电路包括第一节点连接芯片01和第二节点连接芯片02，所述第一节点连接芯片01与所述第二节点连接芯片02信号连接且进行数据通讯；具体地，参照图2，图2所示为发明节点连接芯片第一较佳实施例电路结构示意图，所述节点连接芯片包括微处理器1以及与所述微处理器1信号连接的数据端口2，所述数据端口2包括切换单元21、接收单元22和发送单元23，所述数据端口2与所述微处理器1通过电源输入端、接收数据端、接收数据地端、选择端、电源输出端、发送数据端、发送数据地端信号连接；所述接收数据端包括接收数据输入端和接收数据输出端，所述发送数据端包括发送数据输入端和发送数据输出端；
所述微处理器1为具有数据处理和存储功能的微处理单元，所述微处理器1用于处理和存储通过所述数据端口2发送和接收的数据。所述数据端口2用于接收外界发送的数据以及发送所述节点连接芯片需要发送的数据。所述数据端口2包括切换单元21、接收单元22和发送单元23，所述切换单元21用于在所述微处理器1的控制下控制所述接收单元22和所述发送单元23有效，即在不同的情况下，所述数据端口2用于接收外界发送的数据或用于发送所述节点连接芯片需要发送的数据。在本发明实施例中，所谓外界是指第一节点连接芯片01和第二节点连接芯片02之间进行数据通讯。
参照图3，图3所示为本发明节点连接芯片通讯电路较佳实施例连接结构示意图。所述第一节点连接芯片01的微处理器控制所述第一节点连接芯片01的选择端与所述第一节点连接芯片01的电源输出端连接，所述第一节点连接芯片01为主芯片，且所述第一节点连接芯片01的数据端口发送单元有效；所述第二节点连接芯片02的微处理器控制所述第二节点连接芯片02的选择端与所述第二节点连接芯片02的接收数据地端连接，所述第二节点连接芯片02为从芯片，且所述第二节点连接芯片02的数据端口接收单元有效。有必要说明的是，也可以通过同样的方式将第一节点连接芯片设置为从芯片、将第二节点连接芯片设置为主芯片。
本发明实施例通过节点连接芯片的微控制器控制数据端口的发送单元或者接收单元有效，从而将第一节点连接芯片和第二节点连接芯片分别设置为主芯片和从芯片，为邻居节点连接芯片提供数据通讯链路，通过节点连接芯片数据通讯电路传输详细的节点连接芯片信息，为节点网络快速提供详细的节点信息。
参照图3，图3中第一节点连接芯片01和第二节点连接芯片02体现了本发明节点连接芯片第二较佳实施例电路结构示意图。在其中一个实施例中，所述接收单元22与所述切换单元21通过接收输入端口和接收输出端口信号连接，所述接收单元22与所述微处理器1通过所述电源输入端、接收数据端和接收数据地端信号连接；
所述发送单元23与所述切换单元21通过发送输入端口和发送输出端口信号连接，所述发送单元23与所述微处理器1通过所述电源输出端、发送数据端、发送数据地端信号连接；
所述切换单元21与所述微处理器1通过选择端信号连接，所述微处理器1通过所述选择端控制所述切换单元21与所述接收单元22连通，或控制所述切换单元21与所述发送单元23连通；所述切换单元21通过所述信号输入端和所述信号输出端与外界进行数据通讯。
本发明节点连接芯片发送和接收数据的过程如下：当所述节点连接芯片需要向邻居节点发送数据时，所述微处理器1通过所述选择端控制所述切换单元21与所述发送单元23连通，数据通过所述发送数据端经由所述发送单元23的发送输入端口和发送输出端口，最后通过切换单元的信号输出端发送，完成数据的发送。所述电源输出端和所述发送数据地端用于为所述发送单元提供电源。当所述节点连接芯片需要从邻居节点接收数据时，所述微处理器1通过所述选择端控制所述切换单元21与所述接收单元22连通数据经由所述切换单元21的信号输入端，以及切换单元21与所述接收单元22连接的接收输入端口，以及所述接收单元22连接的接收数据端传输至所述微处理器1，完成数据的接收。
参照图4，图4所示为本发明节点连接芯片通讯电路较佳实施例局部电路结构示意图。如图4所示，以中间Line为分界点，图中Tranceiver为本发明所述第一节点连接芯片的发送单元，其在本示意图中位于左侧，图中Receiver为本发明所述第二节点连接芯片的接收单元，其在本示意图中位于右侧，后续阐述Tranceiver中的信号端时若与Receiver标号相同，则以左侧和右侧来区别描述。在图4中，所述第一节点连接芯片的电源输出端（Power output）与发送数据地端（左侧的）GND之间设置第一电容C1，所述第一节点连接芯片的发送输入端口（左侧的）In（-）与发送数据地端（左侧的）GND之间设置第一电阻R1，所述第一节点连接芯片的发送数据输出端（左侧的）Data output与发送输出端口（左侧的）Out（+）之间设置第一反相器，在图4中由开关管Q2和Q3组合构成一个反相器，即当发送数据输出端（左侧的）Data output为高电平时，发送输出端口（左侧的）Out（+）为低电平，由开关管组合设计的反相器能够减少数据干扰，当发送数据输入端（左侧的）Data output为高电平时Q2打开，发送输出端口（左侧的）Out（+）才为低电平，反之亦然。同时，在所述第一节点连接芯片的发送数据输入端（左侧的）Data input与发送输入端口（左侧的）In（-）之间设置第一开关管Q1，当发送数据输入端（左侧的）Data Input为高电平时开关管Q1打开，才将数据传输至左侧的In（-），减少数据干扰；所述第二节点连接芯片的电源输入端Power Input与接收数据地端（右侧的）GND之间设置第二电容C2，所述第二节点连接芯片的接收输入端口（右侧的）In（+）与接收数据地端（右侧的）GND之间设置第二电阻R2，所述第二电阻R2与所述第二电容C2串联，所述第二节点连接芯片的接收数据输出端（右侧的）Data Output与接收输出端口（右侧的）Out（-）之间设置第二反相器，在图4中由开关管Q4和Q5组合构成一个反相器，即当接收输出端口（右侧的）Out（-）为高电平时，接收数据输出端（右侧的）Data output为低电平，由开关管组合设计的反相器能够减少数据干扰，当当接收输出端口（右侧的）Out（-）为高电平时Q5打开，接收数据输出端（右侧的）Data output才为低电平，反之亦然。所述第二节点连接芯片的接收数据输入端（右侧的）Data input与接收输入端口（右侧的）In（+）之间设置第二开关管Q6，当接收数据输入端（右侧的）Data input为高电平时开关管Q6打开，才将数据传输至右侧的In（+），减少数据干扰。
在此仅仅描述了本发明节点连接芯片通讯电路较佳实施例局部电路结构示意图及其工作原理，在本领域领会该局部电路结构示意图及其工作原理的情况下，对此做出的任何改进均为本发明的发明构思，在此不一一列举。
本发明实施例通过较佳实施例局部电路结构示意图描述了节点连接芯片数据通讯电路的工作原理，数据通讯过程简洁且能够减少信号干扰，提高了节点连接芯片数据通讯电路的工作效率。
为实现上述目的，本发明还提供了一种节点连接芯片数据通讯方法。
参照图5，图5所示为本发明节点连接芯片数据通讯方法较佳实施例流程示意图。所述节点连接芯片数据通讯方法包括如下步骤：
S1：第一节点连接芯片的微处理器控制所述第一节点连接芯片的选择端与所述第一节点连接芯片的电源输出端连接，设置所述第一节点连接芯片为主芯片，且所述第一节点连接芯片数据端口的发送单元有效；
S2：第二节点连接芯片的微处理器控制所述第二节点连接芯片的选择端与所述第二节点连接芯片的接收数据地端连接，设置所述第二节点连接芯片为从芯片，且所述第二节点连接芯片数据端口的接收单元有效；
S3：所述第一节点连接芯片的数据端口与所述第二节点连接芯片的数据端口数据通讯。
结合图3所示，本发明节点连接芯片和其他节点连接芯片数据通讯的过程如下：当所述节点连接芯片需要向其他节点连接芯片发送数据时，所述节点连接芯片的微处理器1通过所述选择端控制所述切换单元21与所述发送单元23连通，数据通过所述发送数据端经由所述发送单元23的发送输入端口和发送输出端口，最后通过切换单元的信号输出端发送，完成数据的发送。所述电源输出端和所述发送数据地端用于为所述发送单元提供电源。当所述节点连接芯片需要从邻居节点接收数据时，所述微处理器1通过所述选择端控制所述切换单元21与所述接收单元22连通数据经由所述切换单元21的信号输入端，以及切换单元21与所述接收单元22连接的接收输入端口，以及所述接收单元22连接的接收数据端传输至所述微处理器1，完成数据的接收。
本发明实施例通过节点连接芯片的微控制器控制数据端口的发送单元或者接收单元有效，从而将第一节点连接芯片和第二节点连接芯片分别设置为主芯片和从芯片，为邻居节点连接芯片提供数据通讯链路，通过节点连接芯片数据通讯电路传输详细的节点连接芯片信息，为节点网络快速提供详细的节点信息。
具体地，在其中一个实施例中，所述步骤S3包括：
S31：所述第一节点连接芯片的数据端口向所述第二节点连接芯片的数据端口发送数据，所述第二节点连接芯片的数据端口接收所述第一节点连接芯片的数据端口发送的数据；
进一步地，结合图4所示的局部电路结构示意图，所述步骤S31包括：
S311：第一节点连接芯片的微控制器控制发送数据输出端与发送数据地端信号连接；
具体地，结合图4所示，第一节点连接芯片的微控制器控制发送数据输出端（左侧的）Data output与发送数据地端（左侧的）GND信号连接，即发送数据输出端（左侧的）Data output为低电平，由于所述第一节点连接芯片的发送数据输出端（Data output）与发送输出端口（左侧的）Out（+）之间设置第一反相器，在图4中由开关管Q2和Q3组合构成一个反相器，因此，发送输出端口（左侧的）Out（+）为高电平。
S312：第一节点连接芯片的电源输出端经由第一电容、第二电容、第一电阻以及第二电阻，为第一电容和第二电容充电；
具体地，当发送输出端口（左侧的）Out（+）为高电平时，第一节点连接芯片的电源输出端Power output经由第一电容C1、第二电容C2、第一电阻R1以及第二电阻R2，为第一电容C1和第二电容C2充电。此过程可以理解为第一节点连接芯片为第二节点连接芯片发送数据的过程也可以理解为第一节点连接芯片为第二节点连接芯片提供电源的过程；
S313：充电结束后，第一节点连接芯片的数据经第一节点连接芯片数据端口的发送单元发送至第二节点连接芯片数据端口的接收单元；
具体地，当第一电容C1和第二电容C2的已经达到饱和电压时，第一节点连接芯片的数据经第一节点连接芯片数据端口的发送单元Tanceiver发送至第二节点连接芯片数据端口的接收单元Receiver。
S314：第一节点连接芯片的微控制器控制发送数据输出端与电源输出端信号连接；
具体地，第一节点连接芯片的微控制器控制发送数据输出端（左侧的）Data output与电源输出端（Power output）信号连接，即发送数据输出端（左侧的）Data output为高电平，由于所述第一节点连接芯片的发送数据输出端（Data output）与发送输出端口（左侧的）Out（+）之间设置第一反相器，在图4中由开关管Q2和Q3组合构成一个反相器，即当发送数据输出端（Data output）为高电平时，发送输出端口（左侧的）Out（+）为低电平，由开关管组合设计的反相器能够减少数据干扰，即当发送数据输入端（Data output）为高电平时Q2打开，发送输出端口（左侧的）Out（+）才为低电平。
S315：第二电容通过第二电阻放电，第二开关管控制第二节点连接芯片数据端口的接收单元接收信号。
具体地，当发送输出端口（左侧的）Out（+）为低电平时，第二电容C2通过第二电阻R2放电，第二开关管Q6打开，控制第二节点连接芯片数据端口的接收单元的（右侧的）Data input接收信号。至此完成了所述第一节点连接芯片的数据端口向所述第二节点连接芯片的数据端口发送数据，所述第二节点连接芯片的数据端口接收所述第一节点连接芯片的数据端口发送的数据。
在其中一个实施例中，所述步骤S3还包括：
S32：所述第二节点连接芯片的数据端口向所述第一节点连接芯片的数据端口发送数据，第一节点连接芯片的数据端口接收所述第二节点连接芯片的数据端口发送的数据。
进一步地，在其中一个实施例中，所述步骤S32包括：
S321：第二节点连接芯片的微控制器控制接收数据输出端与接收数据地端信号连接；
具体地，结合图4所示，第二节点连接芯片的微控制器控制接收数据输出端（右侧的）Data output与接收数据地端（右侧的）GND信号连接，即接收数据输出端（右侧的）Data output为低电平，由于所述第一节点连接芯片的接收数据输出端（Data output）与接收输出端口（右侧的）Out（+）之间设置第一反相器，在图4中由开关管Q4和Q5组合构成一个反相器，因此，接收输出端口（右侧的）Out（+）为高电平。
S322：第二节点连接芯片的电源输入端经由第一电容、第二电容、第一电阻以及第二电阻，为第一电容和第二电容充电；
具体地，当接收输出端口（右侧的）Out（+）为高电平时，第二节点连接芯片的电源输入端Power input经由第一电容C1、第二电容C2、第一电阻R1以及第二电阻R2，为第一电容C1和第二电容C2充电。此过程可以理解为第二节点连接芯片为第一节点连接芯片接收数据的过程也可以理解为第二节点连接芯片为第一节点连接芯片提供电源的过程；
S323：充电结束后，第二节点连接芯片的数据经第二节点连接芯片数据端口的接收单元发送至第一节点连接芯片数据端口的发送单元；
具体地，当第一电容C1和第二电容C2的已经达到饱和电压时，第二节点连接芯片的数据经第二节点连接芯片数据端口的发送单元Tanceiver发送至第一节点连接芯片数据端口的接收单元Receiver。
S324：第二节点连接芯片的微控制器控制接收数据输出端与电源输入端信号连接；
具体地，第二节点连接芯片的微控制器控制接收数据输出端（右侧的）Data output与电源输入端（Power input）信号连接，即接收数据输出端（右侧的）Data output为高电平，由于所述第二节点连接芯片的接收数据输出端（Data output）与接收输出端口（右侧的）Out（+）之间设置第一反相器，在图4中由开关管Q4和Q5组合构成一个反相器，即当接收数据输出端（右侧的）Data output为高电平时，接收输出端口（右侧的）Out（+）为低电平，由开关管组合设计的反相器能够减少数据干扰，即当接收数据输入端（Data output）为高电平时Q2打开，接收输出端口（右侧的）Out（+）才为低电平。
S325：第一电容通过第一电阻放电，第一开关管控制第一节点连接芯片数据端口的发送单元接收信号。
具体地，当接收输出端口（右侧的）Out（+）为低电平时，第一电容C1通过第一电阻R1放电，第一开关管Q1打开，控制第一节点连接芯片数据端口的接收单元的（左侧的）Data input接收信号。至此完成了所述第二节点连接芯片的数据端口向所述第一节点连接芯片的数据端口发送数据，所述第一节点连接芯片的数据端口接收所述第二节点连接芯片的数据端口发送的数据。
以上仅为本发明的优选实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (8)

  1. 一种节点连接芯片通讯电路，其特征在于，所述节点连接芯片通讯电路包括第一节点连接芯片和第二节点连接芯片，所述第一节点连接芯片与所述第二节点连接芯片信号连接且进行数据通讯；所述节点连接芯片包括微处理器以及与所述微处理器信号连接的数据端口，所述数据端口包括切换单元、接收单元和发送单元，所述数据端口与所述微处理器通过电源输入端、接收数据端、接收数据地端、选择端、电源输出端、发送数据端、发送数据地端信号连接；所述接收数据端包括接收数据输入端和接收数据输出端，所述发送数据端包括发送数据输入端和发送数据输出端；
    所述第一节点连接芯片的微处理器控制所述第一节点连接芯片的选择端与所述第一节点连接芯片的电源输出端连接，所述第一节点连接芯片为主芯片，且所述第一节点连接芯片的数据端口发送单元有效；所述第二节点连接芯片的微处理器控制所述第二节点连接芯片的选择端与所述第二节点连接芯片的接收数据地端连接，所述第二节点连接芯片为从芯片，且所述第二节点连接芯片的数据端口接收单元有效。
  2. 如权利要求1所述的节点连接芯片通讯电路，其特征在于，所述接收单元与所述切换单元通过接收输入端口和接收输出端口信号连接，所述接收单元与所述微处理器之间通过所述电源输入端、接收数据端和接收数据地端信号连接；
    所述发送单元与所述切换单元通过发送输入端口和发送输出端口信号连接，所述发送单元与所述微处理器之间通过所述电源输出端、发送数据端、发送数据地端信号连接；
    所述切换单元与所述微处理器通过选择端信号连接，所述处理器通过所述选择端控制所述切换单元与所述接收单元连通，或控制所述切换单元与所述发送单元连通；所述切换单元通过所述信号输入端和所述信号输出端与外界进行数据通讯。
  3. 如权利要求2所述的节点连接芯片通讯电路，其特征在于，所述第一节点连接芯片的电源输出端与发送数据地端之间设置第一电容，所述第一节点连接芯片的发送输入端口与发送数据地端之间设置第一电阻，所述第一节点连接芯片的发送数据输出端与发送输出端口之间设置第一反相器，所述第一节点连接芯片的发送数据输入端与发送输入端口之间设置第一开关管；所述第二节点连接芯片的电源输入端与接收数据地端之间设置第二电容，所述第二节点连接芯片的接收输入端口与接收数据地端之间设置第二电阻，所述第二节点连接芯片的接收数据输出端与接收输出端口之间设置第二反相器，所述第二节点连接芯片的接收数据输入端与接收输入端口之间设置第二开关管。
  4. 一种节点连接芯片数据通讯方法，其特征在于，所述节点连接芯片数据通讯方法包括如下步骤：
    S1：第一节点连接芯片的微处理器控制所述第一节点连接芯片的选择端与所述第一节点连接芯片的电源输出端连接，设置所述第一节点连接芯片为主芯片，且所述第一节点连接芯片数据端口的发送单元有效；
    S2：第二节点连接芯片的微处理器控制所述第二节点连接芯片的选择端与所述第二节点连接芯片的接收数据地端连接，设置所述第二节点连接芯片为从芯片，且所述第二节点连接芯片数据端口的接收单元有效；
    S3：所述第一节点连接芯片的数据端口与所述第二节点连接芯片的数据端口数据通讯。
  5. 如权利要求4所述的节点连接芯片数据通讯方法，其特征在于，所述步骤S3包括：
    S31：所述第一节点连接芯片的数据端口向所述第二节点连接芯片的数据端口发送数据，所述第二节点连接芯片的数据端口接收所述第一节点连接芯片的数据端口发送的数据；
    S32：所述第二节点连接芯片的数据端口向所述第一节点连接芯片的数据端口发送数据，第一节点连接芯片的数据端口接收所述第二节点连接芯片的数据端口发送的数据。
  6. 如权利要求5所述的节点连接芯片数据通讯方法，其特征在于，所述步骤S31包括：
    S311：第一节点连接芯片的微控制器控制发送数据输出端与发送数据地端信号连接；
    S312：第一节点连接芯片的电源输出端经由第一电容、第二电容、第一电阻以及第二电阻，为第一电容和第二电容充电；
    S313：充电结束后，第一节点连接芯片的数据经第一节点连接芯片数据端口的发送单元发送至第二节点连接芯片数据端口的接收单元；
    S314：第一节点连接芯片的微控制器控制发送数据输出端与电源输出端信号连接；
    S315：第二电容通过第二电阻放电，第二开关管控制第二节点连接芯片数据端口的接收单元接收信号。
  7. 如权利要求5所述的节点连接芯片数据通讯方法，其特征在于，所述步骤S32包括：
    S321：第二节点连接芯片的微控制器控制接收数据输出端与接收数据地端信号连接；
    S322：第二节点连接芯片的电源输入端经由第一电容、第二电容、第一电阻以及第二电阻，为第一电容和第二电容充电；
    S323：充电结束后，第二节点连接芯片的数据经第二节点连接芯片数据端口的接收单元发送至第一节点连接芯片数据端口的发送单元；
    S324：第二节点连接芯片的微控制器控制接收数据输出端与电源输入端信号连接；
    S325：第一电容通过第一电阻放电，第一开关管控制第一节点连接芯片数据端口的发送单元接收信号。
  8. 如权利要求6所述的节点连接芯片数据通讯方法，其特征在于，所述步骤S32包括：
    S321：第二节点连接芯片的微控制器控制接收数据输出端与接收数据地端信号连接；
    S322：第二节点连接芯片的电源输入端经由第一电容、第二电容、第一电阻以及第二电阻，为第一电容和第二电容充电；
    S323：充电结束后，第二节点连接芯片的数据经第二节点连接芯片数据端口的接收单元发送至第一节点连接芯片数据端口的发送单元；
    S324：第二节点连接芯片的微控制器控制接收数据输出端与电源输入端信号连接；
    S325：第一电容通过第一电阻放电，第一开关管控制第一节点连接芯片数据端口的发送单元接收信号。
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