WO2016141800A1 - 数据写入控制装置及方法 - Google Patents

数据写入控制装置及方法 Download PDF

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Publication number
WO2016141800A1
WO2016141800A1 PCT/CN2016/074045 CN2016074045W WO2016141800A1 WO 2016141800 A1 WO2016141800 A1 WO 2016141800A1 CN 2016074045 W CN2016074045 W CN 2016074045W WO 2016141800 A1 WO2016141800 A1 WO 2016141800A1
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write
mode
data
control device
processor
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PCT/CN2016/074045
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English (en)
French (fr)
Inventor
李和和
刘勇攀
赵庆行
罗嵘
杨华中
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华为技术有限公司
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Priority to EP16761027.8A priority Critical patent/EP3258367B1/en
Publication of WO2016141800A1 publication Critical patent/WO2016141800A1/zh
Priority to US15/696,416 priority patent/US10275353B2/en
Priority to US16/371,391 priority patent/US10929292B2/en

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Definitions

  • the present invention relates to the field of data write control technology, and in particular, to a data write control apparatus and method.
  • Non-volatile SRAM A storage structure that includes both SRAM and NVM.
  • the electronic device uses SRAM for data storage in the working mode. After the electronic device is powered down, the NV-SRAM can back up the data to the NVM unit. in.
  • the non-volatile SRAM requires a large on-chip storage capacitor to power up the data for backup, which introduces a large chip area overhead and cost. If a smaller on-chip storage capacitor is used, the backup will fail due to insufficient power. After the backup fails, it can only fall back to the last successful backup point, and returning to the last successful backup point will cause a certain performance overhead, affecting the execution progress of the program.
  • Embodiments of the present invention provide a data write control apparatus and method for improving program execution efficiency of a write apparatus and method by converting two different write modes.
  • a first aspect of the embodiments of the present invention provides a data write control apparatus, including a primary memory, a secondary storage, and a processor, the primary storage including a volatile storage unit, and the secondary storage is a nonvolatile storage a data writing mode of the data writing control device, including a write-back mode and a write-through mode, in which the processor writes the received data into the primary memory, In the write-through mode, the processor writes the received data into the primary memory and the secondary storage;
  • the processor detects the number of dirty blocks in the first memory, when the number of the dirty blocks reaches a first preset threshold, Predicting the execution progress of the program run by the processor in a dangerous time period in two write modes, respectively, when predicting execution of the program run by the processor in the dangerous time period in the write-through mode The progress is greater than the execution progress of the program run by the processor in the write-back mode during the dangerous time period, converting the current data write mode to the write-through mode;
  • the primary memory further includes a nonvolatile storage unit, and the data in the volatile storage unit is backed up after the data write control device is powered off
  • the first preset threshold is a maximum number of dirty blocks that the first memory can support for backup.
  • the calculation formula of the progress of the execution of the write control device program when the write back mode is predicted is:
  • k is the execution progress of the program run by the processor in the unit time in the write-back mode
  • L is the preset length of the dangerous time period
  • t s is reached by the number of the dirty blocks
  • the first preset threshold is time zero, and the power supply time is recently started. The average power supply time of the control device is written to the previously counted data.
  • k' is the execution progress of the program run by the processor in the unit time in the write-through mode.
  • the second preset threshold is the first preset threshold minus one.
  • a second aspect of the embodiments of the present invention provides a data write control method applied to a data write control apparatus, where the data write control apparatus includes a primary memory, a secondary memory, and a processor, the primary memory Included as a volatile memory unit, the secondary memory is a nonvolatile memory unit, and the data write mode of the data write control device includes a write mode and a write-through mode, in which the processor writes the received data into the primary memory, and in the write-through mode, the processor receives the received data Writing into the primary memory and the secondary storage, the method comprising:
  • the processor detects the number of dirty blocks in the first memory when the write control device is in the write-back mode
  • the primary memory further includes a nonvolatile storage unit, and the data in the volatile storage unit is backed up after the data write control device is powered off
  • the first preset threshold is a maximum number of dirty blocks that the first memory can support for backup.
  • the calculation formula of the progress of the execution of the write control device program when the write back mode is predicted is:
  • L is the preset length of the dangerous time period
  • t s is reached by the number of the dirty blocks
  • the first preset threshold is time zero.
  • the second preset threshold is the first preset threshold minus one.
  • the data writing control device and method of the embodiment of the present invention can detect the number of dirty blocks in the volatile storage unit when the data writing mode of the data writing control device is the write-back mode, and the number of dirty blocks.
  • a predetermined threshold is reached, determining whether to convert the data writing control device to the write-through mode according to a preset condition, and when the data writing control device is switched to the write-through mode by reaching a preset condition, continuing Detecting the number of dirty blocks, when the number of dirty blocks is less than a second predetermined threshold, converting the data writing mode of the data writing control device to the write-back mode, thus providing a data writing control device Program execution performance.
  • FIG. 1 is a structural diagram of a data writing apparatus according to a first embodiment of the present invention.
  • FIG. 2 is a schematic diagram of replacement of two data writing modes of the data writing device.
  • FIG. 3 is a flow chart of a data writing method provided by the second embodiment.
  • the technical solution provided by the embodiments of the present invention is mainly applied to a memory having a nonvolatile memory unit and a volatile memory unit, such as a nonvolatile static random access memory (NV-SRAM).
  • NV-SRAM nonvolatile static random access memory
  • the memory can be powered by the backup power on the memory to back up the data in the volatile memory unit to the non-volatile memory unit.
  • the present invention is described by taking an NV-SRAM as an example in the following embodiments, but it should be noted that the memory to which the present invention is applied is not limited to the NV-SRAM, and other memories having the same structure are also included in the present invention. Within the scope of the disclosure.
  • the volatile memory unit in the NV-SRAM is a static random access memory (SRAM), the nonvolatile memory unit is a phase-change random access memory (PCM), and the standby power source is an on-chip storage capacitor.
  • SRAM static random access memory
  • PCM phase-change random access memory
  • the first embodiment provides a data write control device 10.
  • the data write control device 10 includes a primary memory 11, a secondary memory 12, and a processor 13, and the primary memory 11 includes a volatile storage unit 111 and a nonvolatile storage unit 112.
  • the secondary storage 12 is a non-volatile storage unit.
  • the write control device 10 includes two data write modes, a write-back mode and a write-through mode.
  • the write-back mode writes data in the received data write request into the primary memory.
  • the through-write writes the data in the received data write request to the primary memory 11 and the secondary storage 12 simultaneously.
  • the primary memory 11 is a nonvolatile static random access memory (NV-SRAM), and the volatile storage unit 111 is a static random access memory (SRAM).
  • the nonvolatile memory unit 112 is a phase-change random access memory (PCM). After the data write control device 10 is powered off, it can be given by the backup power source 113 on the primary memory 11.
  • the primary memory 11 is provided Electrically, the data in the volatile memory unit 111 is backed up to the non-volatile memory unit 112.
  • the write-back mode is that when the processor 13 receives the data write command, the data is directly written into the memory block 113 of the volatile memory unit 111, and the data written in the volatile memory unit 111 is written.
  • the secondary memory 12 is written only when it is required to be replaced by the volatile storage unit 111.
  • the memory block 113 is written into the memory block 113 of the volatile memory unit 111, and the memory block 113 not written to the secondary memory 12 is a dirty block, and each memory block 113 has a dirty block flag for identifying Whether the storage block 113 is a dirty block. Since the volatile memory unit 111 has a relatively fast data read/write speed, when the data write control device 10 adopts the write back mode, it has a faster program processing progress.
  • the data write control device 10 when the data write control device 10 is powered off, the data of all the dirty blocks in the volatile storage unit 12 needs to be completely backed up to the nonvolatile storage unit 112, but since the power of the backup power source 113 is valid, When the number of dirty blocks exceeds the number of dirty blocks that the backup power supply 113 can support, the backup will fail. When the backup fails, the program needs to fall back to the point of the last successful backup, which will cause a large Performance overhead, affecting the progress of program execution.
  • the write-through mode is that when the processor 13 receives the data write command, the data is written into the memory block 113 of the volatile memory unit 111, and is also written into the secondary memory 12, so that There will be dirty blocks. Therefore, the backup failure does not occur, but since the nonvolatile storage unit 112 has a relatively slow read/write speed of data, when the data write control device 10 adopts the write-write mode, The write-back mode has a slower program processing progress.
  • the data writing control device 10 provided in this embodiment can be converted in two data writing modes to improve the overall program processing progress.
  • the processor 13 detects the number of dirty blocks in the first memory 11, when the number of the dirty blocks reaches a first preset threshold, Or predicting the execution progress of the program in the two write modes when the number of the dirty blocks reaches the first preset threshold, and the execution progress of the program in the predicted write-write mode is greater than the execution progress of the program in the write-back mode Converting the current data write mode to the write-through mode;
  • the processor 13 detects the number of dirty blocks, and when the number of the dirty blocks reaches a second preset threshold, the current data is written. The in mode is converted to the write back mode.
  • the first preset threshold is the maximum number of dirty blocks that the first memory 11 can support for backup.
  • the current data write mode is converted to the write-through mode.
  • the execution progress of the program in the two write modes is predicted, and the prediction is performed at this time.
  • the execution progress of the program starts with the number of dirty blocks reaching the first preset threshold, and the execution progress of the program within the dangerous time period L when the number of dirty blocks is less than the first preset threshold.
  • the data writing control device 10 in this embodiment is generally a specific detecting device, such as a sensor for measuring the health of a human body in a wearable device, so generally only one specific program is run, and the program is run.
  • the dangerous time period L at which the number of dirty blocks reaches and is greater than the first predetermined threshold is also substantially constant, so for a particular procedure, the dangerous time period L can be obtained in advance.
  • the execution progress of the program in this embodiment is expressed by the percentage of progress. Since the data writing control device 10 is running a specific program, the total number of instructions of the program is constant, and the program can be calculated according to the formula (1). schedule:
  • N executed (t) is the number of instruction execution has completed
  • N total is the total number of instructions. If the time overhead due to pipeline stalls is ignored, it can be approximated that G(t) is linearly increasing.
  • the curve C1 is the progress curve of the program when the write-back mode is adopted
  • the curve C2 is the progress curve of the program when the write-once mode is adopted.
  • the data writing control device 10 uses the write-back mode to write data, and starts detecting the number of dirty blocks, when the number of dirty blocks reaches the first preset threshold. At the time of the value, the preset dangerous time period L is acquired, and the progress of the program processing of the two write modes in the event segment L is predicted.
  • the power-down probability of the data writing control device 10 is calculated, and in practice, power-down occurs in different situations. For example, if the data writing control device 10 uses a solar-powered system, passive power-down occurs when the sun is blocked, the sun angle changes, the weather changes, and the like. This feature is reflected in the power supply characteristics, that is, the memoryless time of the power supply, that is, the length of each power supply is directly unrelated. Therefore, the power supply time can be modeled by an exponential distribution:
  • f(t on ) is the probability density of the length of the power supply, It is the expectation of the length of the power supply.
  • k is the program progress per unit time when the write-back mode is used
  • k' is the program progress per unit time when the write-once mode is used.
  • the backup will fail. After the backup fails, the backup will be rolled back. As shown in Figure 2, if the power failure occurs at time Te, the backup will fail. , the program needs to fall back to the program progress at the time Ts when the power supply starts. If the starting point of the dangerous time period L, that is, the switching point P is the time zero point, the program progress of the return is:
  • Te ⁇ L indicates that power failure occurred during the dangerous time period L
  • Te>L indicates that no power failure occurred during the dangerous time period L, and the program does not need to be retracted.
  • the data writing mode of the data writing control device 10 is switched to the write-through mode.
  • the processor 13 switches the data write mode of the data write control device 10 to the write-through mode.
  • the second preset threshold is preferably the first preset threshold minus one. In this way, the data can be quickly written to the control device 10 into the write-back mode.
  • different second preset thresholds may also be set according to specific settings.
  • the second embodiment provides a data writing method applied to the data writing device provided by the first embodiment. As shown in FIG. 3, it is a flowchart of the data writing method.
  • Step S301 when the write control device is in the write-back mode, the processor detects the number of dirty blocks in the first memory
  • Step S302 when the number of the dirty blocks reaches the first preset threshold, respectively predicting the execution progress of the program run by the processor in a dangerous time period in the two writing modes;
  • Step S303 when it is predicted that the execution schedule of the program run by the processor in the dangerous write period in the write-through mode is greater than the program run by the processor in the write-back mode in the dangerous time period
  • the current data write mode is converted to the write-through mode
  • Step S304 when the write control device is in the write-through mode, detecting the number of dirty blocks, and when the number of the dirty blocks reaches a second preset threshold, converting the current data write mode For the write back mode.
  • the primary memory further includes a nonvolatile storage unit, and after the data write control device is powered off, the data in the volatile storage unit is backed up to the nonvolatile storage unit.
  • the first preset threshold is a maximum number of dirty blocks that the first memory can support for backup.
  • the calculation formula of the progress of the program execution of the write control device when the write-back mode is predicted is:
  • L is the preset length of the dangerous time period
  • t s is reached by the number of the dirty blocks
  • the first preset threshold is time zero.
  • the data is written to the control device for power-off time.
  • the average power supply time of the control device is written to the previously counted data.
  • k' is the execution progress of the program run by the processor in the unit time in the write-through mode.
  • the second preset threshold is the first preset threshold minus one.
  • the program may be stored in a computer readable storage medium, and the storage medium may include: ROM, RAM, disk or CD.

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Abstract

一种数据写入控制装置及方法，当所述写入控制装置处于所述回写模式时，所述处理器侦测所述第一存储器中脏块的数量，当所述脏块的数量达到第一预设阈值时，分别预测在两种写入模式下，所述处理器所运行程序在一危险时间段内的执行进度，当预测在通写模式下所述处理器所运行程序在所述危险时间段内的执行进度大于在所述回写模式下所述处理器所运行程序在所述危险时间段内的执行进度时，将当前的数据写入模式转换为通写模式；当所述写入控制装置处于所述通写模式时，侦测所述脏块数量，当所述脏块的数量降至第二预设阈值时，则将当前的数据写入模式转换为所述回写模式。

Description

数据写入控制装置及方法 技术领域
本发明涉及数据写入控制技术领域，特别涉及数据写入控制装置及方法。
背景技术
非易失SRAM(NV-SRAM)一种同时包括SRAM和NVM的存储结构，电子装置在工作模式下采用SRAM进行数据的存储，在电子装置掉电后，NV-SRAM能够将数据备份到NVM单元中。然而，在电子装置掉电后，非易失SRAM需要一个较大的片上储能电容供电以进行数据的备份，该电容会引入较大的芯片面积开销和成本开销。如果采用较小的片上储能电容，则由于电能不足，会引起备份失败。在备份失败后只能回退到上一次成功备份点，而回到上一次成功备份点会造成一定的性能开销，影响程序的执行进度。
发明内容
本发明实施例提供数据写入控制装置及方法，通过两种不同写入模式的转换，提高写入装置及方法的程序执行效率。
本发明实施例的第一方面提供一种数据写入控制装置，包括一级存储器、二级存储器及处理器，所述一级存储器包括易失存储单元，所述二级存储器为非易失存储单元，所述数据写入控制装置的数据写入模式包括回写模式及通写模式，在所述回写模式下，所述处理器将接收到的数据写入所述一级存储器中，在所述通写模式下，所述处理器将接收到的数据写入所述一级存储器及所述二级存储器中；
当所述写入控制装置处于所述回写模式时，所述处理器侦测所述第一存储器中脏块的数量，当所述脏块的数量达到第一预设阈值时， 分别预测在两种写入模式下，所述处理器所运行程序在一危险时间段内的执行进度，当预测在通写模式下所述处理器所运行程序在所述危险时间段内的执行进度大于在所述回写模式下所述处理器所运行程序在所述危险时间段内的执行进度时，将当前的数据写入模式转换为通写模式；
当所述写入控制装置处于所述通写模式时，侦测所述脏块数量，当所述脏块的数量降至第二预设阈值时，则将当前的数据写入模式转换为所述回写模式。
进一步地，在本发明实施例的第一方面中，所述一级存储器还包括非易失存储单元，在所述数据写入控制装置掉电后，所述易失存储单元中的数据被备份至所述非易失存储单元中，所述第一预设阈值为所述第一存储器可支持备份的脏块的最大数量。
进一步地，在本发明实施例的第一方面中，所预测采用回写模式时写入控制装置程序执行的进度的计算公式为：
Figure PCTCN2016074045-appb-000001
其中，k为在回写模式下，所述处理器所运行程序在单位时间内的执行进度，L为预设的所述危险时间段的长度，ts为若以所述脏块的数量达到所述第一预设阈值时为时间零点，最近开始供电时间，
Figure PCTCN2016074045-appb-000002
为预先统计的所述数据写入控制装置的平均供电时间。
所预测采用通写模式时写入控制装置程序执行的进度的计算公式为：
E(G’)＝k’L
其中，k‘为在通写模式下，所述处理器所运行程序在单位时间内的执行进度。
进一步地，在本发明实施例的第一方面中，所述第二预设阈值为所述第一预设阈值减一。
本发明实施例的第二方面提供一种应用于一数据写入控制装置的数据写入控制方法，所述数据写入控制装置包括一级存储器、二级存储器及处理器，所述一级存储器包括易失存储单元，所述二级存储器为非易失存储单元，所述数据写入控制装置的数据写入模式包括回 写模式及通写模式，在所述回写模式下，所述处理器将接收到的数据写入所述一级存储器中，在所述通写模式下，所述处理器将接收到的数据写入所述一级存储器及所述二级存储器中，所述方法包括：
当所述写入控制装置处于所述回写模式时，所述处理器侦测所述第一存储器中脏块的数量；
当所述脏块的数量达到第一预设阈值时，分别预测在两种写入模式下，所述处理器所运行程序在一危险时间段内的执行进度；
当预测在通写模式下所述处理器所运行程序在所述危险时间段内的执行进度大于在所述回写模式下所述处理器所运行程序在所述危险时间段内的执行进度时，将当前的数据写入模式转换为通写模式；
当所述写入控制装置处于所述通写模式时，侦测所述脏块数量，当所述脏块的数量降至第二预设阈值时，则将当前的数据写入模式转换为所述回写模式。
进一步地，在本发明实施例的第二方面中，所述一级存储器还包括非易失存储单元，在所述数据写入控制装置掉电后，所述易失存储单元中的数据被备份至所述非易失存储单元中，所述第一预设阈值为所述第一存储器可支持备份的脏块的最大数量。
进一步地，在本发明实施例的第二方面中，所预测采用回写模式时写入控制装置程序执行的进度的计算公式为：
Figure PCTCN2016074045-appb-000003
其中，k为在回写模式下，所述处理器所运行程序在单位时间内的执行进度，L为预设的所述危险时间段的长度，ts为若以所述脏块的数量达到所述第一预设阈值时为时间零点，在危险时间段内，所述数据写入控制装置开始供电的时间，
Figure PCTCN2016074045-appb-000004
为预先统计的所述数据写入控制装置的平均供电时间。
所预测采用通写模式时写入控制装置程序执行的进度的计算公式为：
E(G’)＝k’L
其中，k‘为在通写模式下，所述处理器所运行程序在单位时间 内的执行进度。
进一步地，在本发明实施例的第二方面中，所述第二预设阈值为所述第一预设阈值减一。
可见本发明实施例的数据写入控制装置及方法，在所述数据写入控制装置的数据写入模式为回写模式时，侦测易失存储单元中脏块的数量，当脏块的数量达到一预设阈值时，根据预设的条件确定是否将所述数据写入控制装置转换至通写模式，当达到预设的条件将所述数据写入控制装置转换至通写模式时，继续侦测脏块的数量吗，当脏块的数量小于第二预设阈值时，再将所述数据写入控制装置的数据写入模式转换为回写模式，如此，可提供数据写入控制装置的程序执行性能。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本发明第一实施例所提供的数据写入装置的结构图。
图2为所述数据写入装置两种数据写入模式进行装换的示意图。
图3为第二实施例所提供的数据写入方法的流程图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例所提供的技术方案主要应用于同时具有非易失存储单元与易失存储单元的存储器，如非易失静态随机存储器(Nonvolatile Static Random Access Memory,NV-SRAM)，在使用这种结构的存储器作为内存的电子装置掉电后，可通过存储器上的备用电源给存储器供电，以将易失存储单元中的数据备份至非易失存储单元中。为了方便描述，在以下实施例中以NV-SRAM为例对本发明进行说明，但需要说明的是，本发明所应用的存储器并不限于NV-SRAM，其他具有相同结构的存储器也包含在本发明所揭露的范围内。
NV-SRAM中的易失存储单元为静态随机存储器(Static Random Access Memory，SRAM)，非易失存储单元为相变存储器(Phase-change Random Access memory,PCM)，备用电源为片上储能电容。
下面将通过不同的实施例对本发明所提供的技术方案从不同的方面进行描述。
第一实施例
第一实施例提供一种数据写入控制装置10。所述数据写入控制装置10包括一级存储器11、二级存储器12及处理器13，所述一级存储器11包括易失存储单元111及非易失存储单元112。所述二级存储器12为非易失存储单元。
所述写入控制装置10包括两种数据写入模式，即回写模式及通写模式。所述回写(write-back)模式为将接收到的数据写入请求中的数据写入所述一级存储器中。所述通写模式(through-write)将接收到的数据写入请求中的数据同时写入所述一级存储器11及二级存储器12中。
本实施例中，所述一级存储器11为非易失静态随机存储器(Nonvolatile Static Random Access Memory,NV-SRAM)，所述易失存储单元111为静态随机存储器(Static Random Access Memory，SRAM)，所述非易失存储单元112为相变存储器(Phase-change Random Access memory,PCM)，在所述数据写入控制装置10掉电后，可通过所述一级存储器11上的备用电源113给所述一级存储器11供 电，以将所述易失存储单元111中的数据备份至非易失存储单元112中。
所述回写模式为在处理器13接收到数据写入指令时，将数据直接写入所述易失存储单元111的存储块113中，被写入所述易失存储单元111中的数据，只有在需要被替换出所述易失存储单元111时，才写入所述二级存储器12。被写入所述易失存储单元111的存储块113中，而未被写入所述二级存储器12的存储块113为脏块，每个存储块113有个脏块标记，用来标识所述存储块113否为脏块。由于所述易失存储单元111具有比较快的数据读写速度，所以当所述数据写入控制装置10采用回写模式时，具有更快的程序处理进度。但当所述数据写入控制装置10掉电时，所述易失存储单元12中的所有脏块的数据需要全部备份至所述非易失存储单元112，但由于备用电源113的电能有效，当脏块的数量超过备用电源113所能支持备份的脏块的数量时，就会造成备份失败，当备份失败时，程序就需要回退到上一次成功备份的点，这样就会造成大的性能开销，影响程序执行的进度。
所述通写模式为所述处理器13接收到数据写入指令时，将数据写入所述易失存储单元111的存储块113的同时，还写入所述二级存储器12，这样就不会有脏块的产生。从而不会发生备份失败的情况，但是，由于所述非易失存储单元112具有对数据的读写的速度比较慢，所以当所述数据写入控制装置10采用通写模式时，相对于所述回写模式，具有比较慢的程序处理进度。
所以为了提高所述数据写入控制装置10的性能，本实施例提供的数据写入控制装置10可在两种数据写入模式下转换，提升整体的程序处理进度。
当所述写入控制装置10处于所述回写模式时，所述处理器13侦测所述第一存储器11中脏块的数量，当所述脏块的数量达到第一预设阈值时，或者当所述脏块的数量达到第一预设阈值时，预测两种写入模式下程序的执行进度，当所预测的通写模式下程序的执行进度大于所述回写模式下程序的执行进度时，将当前的数据写入模式转换为通写模式；
当所述写入控制装置10处于所述通写模式时，所述处理器13侦测所述脏块数量，当所述脏块的数量达到第二预设阈值时，则将当前的数据写入模式转换为回写模式。
所述第一预设阈值即为所述第一存储器11可支持备份的脏块的最大数量。
本实施例中，在一种实现方式中，当所述处理器13所侦测的所述脏块的数量达到所述第一预设阈值时，即将当前的数据写入模式转换为通写模式。
在另外一种实现方式中，当所述处理器13所侦测的所述脏块的数量达到所述第一预设阈值时，预测两种写入模式下程序的执行进度，此时所预测的程序的执行进度为所述脏块的数量达到所述第一预设阈值开始，到所述脏块的数量小于所述第一预设阈值的危险时间段L内程序的执行进度。
本实施例中的数据写入控制装置10一般为一种特定的检测装置，如穿戴式设备中用于测量人体健康状况的感应器等，所以一般只运行一个特定的程序，而所运行程序的脏块数量达到且大于所述第一预设阈值的危险时间段L也基本上是不变的，所以对于特定程序而言，所述危险时间段L可以预先得到。
本实施中程序的执行进度用进度百分比表示，由于所述数据写入控制装置10运行的是特定程序，所以程序的总指令数时一定的，则根据公式(1)可以计算出程序被执行的进度：
Figure PCTCN2016074045-appb-000005
其中，Nexecuted(t)是已经执行完成的指令数量，Ntotal是总指令数量。如果忽略由于流水线停顿造成的时间开销，可以近似认为G(t)是线性增长的。
首先，计算在危险时间段L内采用回写模式时，程序的进度。
如图2所示，曲线C1为采用回写模式时，程序的进度曲线，曲线C2为采用通写模式时，程序的进度曲线。
在程序开始运行后，所述数据写入控制装置10采用回写模式进行数据的写入，并开始侦测脏块的数量，当脏块的数量达到第一预设阈 值时，获取预设的危险时间段L，并预测在所述事件段L内两种写入模式的程序处理的进度。
当脏块的数量达到第一预设阈值时，没有将回写模式转换至通写模式时，所执行程序的处理进度的计算过程为：
首先，计算所述数据写入控制装置10的掉电概率，由于实际当中，掉电会在不同的情形下发生。比如，若所述数据写入控制装置10使用的是太阳能供电的系统，在太阳被遮挡的情况下、太阳角度变化、天气变化等情况下都会发生被动掉电。这种特征体现在供电特点上即供电时间的无记忆性，即每次的供电时间长度直接无关联。所以，可以用指数分布对供电时间建模：
Figure PCTCN2016074045-appb-000006
其中，f(ton)是供电时间长度的概率密度，
Figure PCTCN2016074045-appb-000007
是供电时间长度的期望。
然后，计算在危险时间段L内发生掉电的概率是:
Figure PCTCN2016074045-appb-000008
对于一段连续的供电时间t，采用两种策略的计算进度百分比分别为：
G(t)＝kt
G‘(t)＝k’t
其中，k为采用回写模式时，单位时间内的程序进度，k’为采用通写模式时，单位时间内的程序进度。
若在危险时间段L内发生了掉电，即会发生备份失败，在备份失败后，则会发生备份的回退，如图2所示，若在时间Te处发生掉电，会发生备份失败，则程序需要回退到本次供电开始的时刻Ts处的程序进度。如果以危险时间段L的起始点，即转换点P为时间零点，则退回的程序进度为：
Figure PCTCN2016074045-appb-000009
其中，Te<L表示在危险时间段L内发生了掉电，而Te>L表示在危险时间段L内未发生掉电，则程序无需回退。
如此，在危险时间段L内，若在转换点不将写策略切换至通写策略，则实际的计算进度百分比G-R的期望为：
Figure PCTCN2016074045-appb-000010
而如果脏块数量达到所述第一预设值时，即在所述转换点将所述数据写入模式转换为通写模式，则
则实际的计算进度百分比G-R的期望为：
E(G')＝k'L   (7)
则只有当E(G-R)<E(G’)的时候，才切换至通写策略，即：
Figure PCTCN2016074045-appb-000011
对公式(8)变形可得：
Figure PCTCN2016074045-appb-000012
即满足上面的公式时，将所述数据写入控制装置10的数据写入模式切换至通写模式。
进入通写模式后，脏块的数量不再增加，但由于新数据的写入，原来的脏块的数据被替换写入所述第二存储器12，这样脏块的数量就会减少，在脏块的数量减少到所述第二预设值时，则所述处理器13将所述数据写入控制装置10的数据写入模式切换至通写模式。
由于所述回写模式的程序执行性能比较高，所以所述第二预设阈值优选为所述第一预设阈值减一。如此，可快速的使所述数据写入控制装置10进入回写模式。当然在其他实施例中，也可根据具体设置不同的第二预设阈值。
第二实施例
第二实施例提供一种应用于第一实施例所提供的所述数据写入装置的数据写入方法。如图3所示，为所述数据写入方法的流程图。
步骤S301，当所述写入控制装置处于所述回写模式时，所述处理器侦测所述第一存储器中脏块的数量；
步骤S302，当所述脏块的数量达到第一预设阈值时，分别预测在两种写入模式下，所述处理器所运行程序在一危险时间段内的执行进度；
步骤S303，当预测在通写模式下所述处理器所运行程序在所述危险时间段内的执行进度大于在所述回写模式下所述处理器所运行程序在所述危险时间段内的执行进度时，将当前的数据写入模式转换为通写模式；
步骤S304，当所述写入控制装置处于所述通写模式时，侦测所述脏块数量，当所述脏块的数量达到第二预设阈值时，则将当前的数据写入模式转换为所述回写模式。
本实施例中，所述一级存储器还包括非易失存储单元，在所述数据写入控制装置掉电后，所述易失存储单元中的数据被备份至所述非易失存储单元中，所述第一预设阈值为所述第一存储器可支持备份的脏块的最大数量。
本实施例中，所预测采用回写模式时写入控制装置程序执行的进度的计算公式为：
Figure PCTCN2016074045-appb-000013
其中，k为在回写模式下，所述处理器所运行程序在单位时间内的执行进度，L为预设的所述危险时间段的长度，ts为若以所述脏块的数量达到所述第一预设阈值时为时间零点，在危险时间段内，所述数据写入控制装置掉电的时间，
Figure PCTCN2016074045-appb-000014
为预先统计的所述数据写入控制装置的平均供电时间。
所预测采用通写模式时写入控制装置程序执行的进度的计算公式为：
E(G’)＝k’L
其中，k‘为在通写模式下，所述处理器所运行程序在单位时间内的执行进度。
本实施例中，所述第二预设阈值为所述第一预设阈值减一。
本领域普通技术人员可以理解上述实施例的各种方法中的全部或部分步骤是可以通过程序来指令相关的硬件来完成，该程序可以存储于一计算机可读存储介质中，存储介质可以包括：ROM、RAM、磁盘或光盘等。
以上对本发明实施例所提供的数据写入装置及方法进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想；同时，对于本领域的一般技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。

Claims (8)

  1. 一种数据写入控制装置，包括一级存储器、二级存储器及处理器，所述一级存储器包括易失存储单元，所述二级存储器为非易失存储单元，所述数据写入控制装置的数据写入模式包括回写模式及通写模式，在所述回写模式下，所述处理器将接收到的数据写入所述一级存储器中，在所述通写模式下，所述处理器将接收到的数据写入所述一级存储器及所述二级存储器中；
    当所述写入控制装置处于所述回写模式时，所述处理器侦测所述第一存储器中脏块的数量，当所述脏块的数量达到第一预设阈值时，分别预测在两种写入模式下，所述处理器所运行程序在一危险时间段内的执行进度，当预测在通写模式下所述处理器所运行程序在所述危险时间段内的执行进度大于在所述回写模式下所述处理器所运行程序在所述危险时间段内的执行进度时，将当前的数据写入模式转换为通写模式；
    当所述写入控制装置处于所述通写模式时，侦测所述脏块数量，当所述脏块的数量降至第二预设阈值时，则将当前的数据写入模式转换为所述回写模式。
  2. 如权利要求1所述的数据写入控制装置，其特征在于，所述一级存储器还包括非易失存储单元，在所述数据写入控制装置掉电后，所述易失存储单元中的数据被备份至所述非易失存储单元中，所述第一预设阈值为所述第一存储器可支持备份的脏块的最大数量。
  3. 如权利要求1所述的数据写入控制装置，其特征在于，所预测采用回写模式时，在所述危险时间段内，所述写入控制装置所执行程序进度的计算公式为：
    Figure PCTCN2016074045-appb-100001
    其中，k为在回写模式下，所述处理器所运行程序在单位时间内的执行进度，L为预设的所述危险时间段的长度，ts为若以所述脏块的数量达到所述第一预设阈值时为时间零点，最近开始供电的时刻，1/λ为预先统计的所述数据写入控制装置的平均供电时间。
    所预测采用通写模式时写入控制装置程序执行的进度的计算公式为：
    E(G’)＝k’L
    其中，k‘为在通写模式下，所述处理器所运行程序在单位时间内的执行进度。
  4. 如权利要求1所述的数据写入控制装置，其特征在于，所述第二预设阈值为所述第一预设阈值减一。
  5. 一种应用于数据写入控制装置的数据写入控制方法，所述数据写入控制装置包括一级存储器、二级存储器及处理器，所述一级存储器包括易失存储单元，所述二级存储器为非易失存储单元，所述数据写入控制装置的数据写入模式包括回写模式及通写模式，在所述回写模式下，所述处理器将接收到的数据写入所述一级存储器中，在所述通写模式下，所述处理器将接收到的数据写入所述一级存储器及所述二级存储器中，所述方法包括：
    当所述写入控制装置处于所述回写模式时，所述处理器侦测所述第一存储器中脏块的数量；
    当所述脏块的数量达到第一预设阈值时，分别预测在两种写入模式下，所述处理器所运行程序在一危险时间段内的执行进度；
    当预测在通写模式下所述处理器所运行程序在所述危险时间段内的执行进度大于在所述回写模式下所述处理器所运行程序在所述危险时间段内的执行进度时，将当前的数据写入模式转换为通写模式；
    当所述写入控制装置处于所述通写模式时，侦测所述脏块数量，当所述脏块的数量降至第二预设阈值时，则将当前的数据写入模式转换为所述回写模式。
  6. 如权利要求5所述的数据写入控制方法，其特征在于，所述一级存储器还包括非易失存储单元，在所述数据写入控制装置掉电后，所述易失存储单元中的数据被备份至所述非易失存储单元中，所述第一预设阈值为所述第一存储器可支持备份的脏块的最大数量。
  7. 如权利要求5所述的数据写入控制方法，其特征在于，所预测采用回写模式时写入控制装置程序执行的进度的计算公式为：
    Figure PCTCN2016074045-appb-100002
    其中，k为在回写模式下，所述处理器所运行程序在单位时间内的执行进度，L为预设的所述危险时间段的长度，ts为若以所述脏块的数量达到所述第一预设阈值时为时间零点，在危险时间段内，所述数据写入控制装置掉电前开始供电的时间，1/λ为预先统计的所述数据写入控制装置的平均供电时间。
    所预测采用通写模式时写入控制装置程序执行的进度的计算公式为：
    E(G’)＝k’L
    其中，k‘为在通写模式下，所述处理器所运行程序在单位时间内的执行进度。
  8. 如权利要求5所述的数据写入控制方法，其特征在于，所述第二预设阈值为所述第一预设阈值减一。
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