WO2016140596A1 - Dispositif de chiffrement de données (et variantes), système sur puce l'utilisant (et variantes) - Google Patents

Dispositif de chiffrement de données (et variantes), système sur puce l'utilisant (et variantes) Download PDF

Info

Publication number
WO2016140596A1
WO2016140596A1 PCT/RU2016/000123 RU2016000123W WO2016140596A1 WO 2016140596 A1 WO2016140596 A1 WO 2016140596A1 RU 2016000123 W RU2016000123 W RU 2016000123W WO 2016140596 A1 WO2016140596 A1 WO 2016140596A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
memory
encryption
encryption device
internal
Prior art date
Application number
PCT/RU2016/000123
Other languages
English (en)
Russian (ru)
Inventor
Владимир Леонидович ГНАТЮК
Павел Николаевич ОСИПЕНКО
Константин КРАСИК
Константин Львович ГУРИН
Григорий Юрьевич ХРЕНОВ
Алексей Юрьевич СТАРИКОВСКИЙ
Арсений Александрович ВИТКОВСКИЙ
Владимир Алексеевич ЛУКЬЯНОВ
Сергей Николаевич ШИМКО
Original Assignee
Открытое Акционерное Общество "Байкал Электроникс"
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Открытое Акционерное Общество "Байкал Электроникс" filed Critical Открытое Акционерное Общество "Байкал Электроникс"
Priority to EA201700121A priority Critical patent/EA201700121A1/ru
Publication of WO2016140596A1 publication Critical patent/WO2016140596A1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/60—Protecting data
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols

Definitions

  • the invention relates to data encryption devices that can be used as part of computing systems, for example, in systems on a chip (SoC) for encrypting data coming from the Internet, from hard drives or from other information storages.
  • SoC systems on a chip
  • the invention is known by the patent of the Russian Federation 2412479
  • a) at the hardware level it does not support the execution of individual encryption algorithms such as: simple replacement mode, gamming and gamming modes with feedback, as well as the mode of generating an insert (these modes are provided, for example, GOST 28147-89), b) it has a single mode of operation: reading data from memory, encrypting and writing the result to the internal register of the central processor or the built-in cache memory;
  • the claimed solution is a data encryption device (2 options), implemented as an integrated circuit with functional modules, and SoC using it (2 options).
  • the encryption device works in the following cryptographic conversion modes, namely: in the simple replacement mode, in the gamming and gamming modes with feedback, in the replacement mode with engagement, as well as in the mode of generating an insert. These modes can be used to implement a symmetrical block encoder that uses technology to replace open data with other elements according to certain rules (for example, in accordance with GOST 28147-89).
  • encryption we mean the process of cryptographic conversion (either encryption or decryption) of data occurring in the encryption device.
  • the symmetry property means using the same secret key for encryption and decryption. The difference is only in the sequence of application of the various components of the key during encryption and decryption. This sequence is determined algorithmically and does not change.
  • These algorithms implement the block type of encryption, which means that the array of encrypted data is divided into blocks of the same size. The processing of each block is carried out similarly to each other.
  • Data can be sent to the encryption device (7) from any available information storage in a format that satisfies the requirements for the algorithms implemented in the claimed invention, for example, in blocks of 64 bits each, from (external to the encryption device) memory (6) (for example, serial RAM) connected via a standard interface. After graduation The encryption device (7) sends the crypto-converted data back to the memory (6) (for the recipient, for example, in serial RAM), which is connected via a standard interface.
  • the purpose of creating an encryption device is to increase the speed of cryptographic data conversion processes using the simple replacement mode, gamma and gamma modes with feedback, replace mode with engagement, and the mode of generating an insert. Improving the performance of cryptographic data conversion processes (encryption acceleration) is achieved through the use of separate computing devices that process streaming data directly from external memory in relation to the encryption device as part of the encryption device, and not by using specialized software that uses the resources of the central processor, especially if This encryption device is used as part of SoC.
  • the encryption acceleration in the claimed encryption device (7) is achieved due to the following factors:
  • the encryption device provides data encryption without the direct involvement of the central processor, thereby freeing its resources for other operations.
  • the central processor when using the claimed encryption device (7) as part of the SoC, plays the role of a system arbiter when the device is turned on and off, controls interruptions and is responsible for managing its operating modes. Autonomous operation of the encryption device (7) from the central processor is ensured by the controller (4) integrated in the SoC, which provides direct access to the memory.
  • Data for encryption and encryption results can be transferred (see Fig. 1, 2) between the internal switching unit (3), the direct memory access controller (4) and the computing device (8) or devices (8), (9) depending on the adopted configuration of the encryption device (7) via internal buses (12), (13), (14), (15), (16) in packets consisting of frames.
  • the frame size corresponds to the size of the block of processed data (for example, 64 bits), its size remains unchanged during operation.
  • the frames from the packet are also transmitted to computing devices by the stream, ensuring the uninterrupted operation of the encryption process.
  • the internal switching unit (3) is capable of simultaneously transmitting data in both directions: to the controller (4) of direct access to and from the memory. Data can be accumulated in the controller's built-in repositories (4) to eliminate delays that may occur when working with external memory.
  • one encryption device may be included in the encryption device (7) module (8) (Fig. 1, 5) or two independent computing modules
  • the computing module (8) is used to implement the basic encryption cycle in accordance with the selected mode of operation, if only one is present in the encryption device (7), while it is used sequentially both to calculate the result of encryption of the data block and to calculate the insert (Fig. . fifteen).
  • the computing module (8) is used to implement the basic encryption cycle in accordance with the selected mode of operation, if only one is present in the encryption device (7), while it is used sequentially both to calculate the result of encryption of the data block and to calculate the insert (Fig. . fifteen).
  • both the result of encrypting the data block using the base cycle module (8) and the result of generating the self-insert using the module (9) of generating the self-insert (II) are calculated (Fig. 2, 6).
  • the use of a separate computing unit (9) for generating an imitation insert can further improve the performance of the entire encryption device (7) due to the fact that the main computing module (8), in this case, is used only for the encryption process.
  • the encryption algorithms supported in the claimed device contain the requirement of recursive block processing of the data array, in other words, the encryption of the next block requires the result of processing the previous one.
  • the total execution time of the encryption process increases in direct proportion to the amount of encrypted data.
  • the claimed encryption device (7) allows not only to reduce the encryption time, but also to reduce the cost of software resources of the SoC, in which it can be used, in particular, to isolate secret crypto attacks keys used in the process of data encryption and stored, usually in RAM, on a common basis. Private keys in this case are stored in the internal registers (18) of the encryption device (7), which do not allow the reading of their contents by software.
  • SoC working using the device (7) described in this application in 2 versions, can significantly reduce the execution time of the encryption process in comparison with known computing systems in which the data encryption process is carried out by software using the resources of the central microprocessor.
  • the processing of each data block requires the execution of a small subroutine that loads the data, performs the necessary calculations, and records the result of the crypto conversion.
  • the claimed SoC (1) (2 options), which includes the claimed encryption device (in 2 versions), is a system on a chip (SoC) with the possibility of using internal memory (6) with respect to the SoC (which is part of the SoC) (according to the first option - Fig. 1, 5) or external memory (6) with respect to the SoC (connected to the SoC via the standard interface according to the second option - Fig. 2, 6) (for example, as a memory, serial RAM can be used in both cases.
  • SoC includes:
  • - a general purpose central processing unit (2) that can execute programs; - encryption device (7), thanks to which data can be encrypted and decrypted;
  • FIG. 3 is a diagram of the operation of the encryption device (7) of the present invention.
  • FIG. 4 description of the simple replacement mode with engagement during encryption (a) and decryption (b).
  • the claimed device for encrypting (7) data according to algorithms, simple replacement, simple replacement with engagement, gamming and gamming with feedback, as well as calculating an insert includes a direct memory access controller (4) (6), which provides data for encryption from memory external to the encryption device (6) (e.g., serial RAM), which can be used in the particular case of the invention considered in two ways below, but without limiting it only to the cases considered by the used memory) to the encryption device (7) and encrypted or decrypted data from the encryption device (7) back to the memory (6) (for example, serial RAM, which can be either external to the SoC, or enter the SoC), a computing module (8) that provides data encryption in accordance with the selected mode of operation, a module for calculating the self-insert (9) (this module is not used in the encryption device (7) according to the first embodiment), as well as control registers that store information necessary for the encryption register, (17) (for example, 512-bit), into which the substitution table is loaded, register (18) (for example, 256
  • the above devices are interconnected as shown in FIG. 1, 5 (for the first embodiment of the encryption device (7)) and in FIG. 2, 6 (for the second embodiment of the encryption device (7)).
  • a controller (4) for direct memory access which simultaneously processes requests for reading / writing data from / to memory
  • a well-known (1P) solution from Synopsys or other equipment can be used, the main requirement for which is the possibility of simultaneous operation of the channel reading data from the memory (6) (for example, internal or external serial RAM) to the encryption device (7) and the channel for writing crypto-converted data from the encryption device (7) back to the memory (6) (for example, serial RAM).
  • the address-data bus (14) can be used, for example, satisfying the ANV (Advanced High-performance Bus) standard.
  • an address-data bus (15) can be used that satisfies, for example, the ANV (Advanced High-performance Bus) standard.
  • Computing module (8) has the ability to implement algorithms that provide the implementation of simple replacement mode, gamma mode and gamma mode with feedback provided, for example, GOST 28147-89.
  • the computing (8) module is supplemented with equipment for addition modulo 2 (operation ⁇ - “exclusive OR”).
  • This mode is different from the simple replacement mode that is described, for example, in GOST 28147-89, in that each subsequent data block, before starting processing, is “hooked” with the result obtained by processing the previous data block by adding modulo 2, as shown in FIG. four.
  • the encryption device (7) according to the second embodiment is supplemented by a computing module (9), which has the ability to parallelly implement the algorithm for generating an insert (provided, for example, GOST 28147-89).
  • the encryption device includes a control unit (21), which is implemented as a state machine, which is in a state of waiting for a command to be transferred, which transfers the encryption device (7) to one of the operating modes.
  • a control unit (21) which is implemented as a state machine, which is in a state of waiting for a command to be transferred, which transfers the encryption device (7) to one of the operating modes.
  • the encryption process begins.
  • the central processor (2) puts the encryption device (7) back into standby mode.
  • the control unit (21) also generates control and status signals necessary for the operation of the encryption device (7). At least the following types of signals are generated:
  • control unit (a) (21) signals that control the writing and reading of data to / from the control unit (a) (21), satisfying, for example, the ARV standard (Advanced Peripheral Bus).
  • ARV standard Advanced Peripheral Bus
  • the address-data bus (14) can be used, for example, satisfying the ANV standard.
  • the address-data bus (15) can be used, for example, satisfying the ANV standard.
  • Computing modules (8), (9) are connected to the registers (17), (18), (19), (20) and the control unit (21) for one or bidirectional data buses, for example, 64 bits wide.
  • the encryption device (7) may not contain a computing device dedicated only to calculate the insert (9), as shown in FIG. one .
  • Part of the encryption algorithms implemented in the claimed invention of the device (7) does not require the calculation of an insert, therefore, such an implementation may be the best option.
  • the encryption device (7) (Fig. 1) can be switched to the mode accompanied by the calculation of the insert, and its calculation will be performed in the computing device (8) after the end of the main encryption process.
  • the control unit (21) redirects the corresponding operands to the computing device (8).
  • the result of computing the insert regardless of the configuration of the encryption device (7), is stored in the data register (20).
  • the operation algorithm of the data encryption device (7) is presented in general form in FIG. 3.
  • the encryption device (7) is in the standby mode of the arrival of control commands.
  • condition-1 is checked as to whether updating the replacement table in the register (17) is used, which is used for encryption in accordance with the standard GOST 28147-89.
  • the control unit (21) can store the standard value of the replacement table. If “Yes”, then the table is loaded, if “No”, then condition-2 is further checked as to whether the encryption key needs to be loaded into the register (18). In the general case, the same key can be used for several data blocks and its updating is not required. If “Yes”, then the key is loaded, if “No”, then condition-3 is checked further as to whether it is necessary to load the initialization clock vector into register (19), which is used only in part of the operating modes provided for by the standard GOST 28147-89.
  • condition-4 is checked further on whether loading the initialization vector of the insertion code into register (20), which is used only in part of the operating modes, is required standard GOST 28147-89. If “Yes”, then the insert vector is loaded, if “No”, then the encryption working mode is set further.
  • condition-5 is checked as to whether the operation mode with direct memory access is set.
  • the central processor (2) performs programming of the controller (4) with at least an address in memory from where the data for encryption must be downloaded, addresses in memory at which crypto-converted data must be saved, and the size of the data array for encryption. Then, as data is received from the memory, they arrive in blocks in a computing device (8) or device (8), (9), depending on the operating mode and configuration of the encryption device (7). After encryption, the data is transferred back to memory at a known address. Then, condition-6 is checked as to whether the block just processed is the last in the data array. If “Yes”, then the encryption device finishes its operation and waits for a command from the central processor (2), which puts the encryption device (7) into standby mode, if “No”, then the next data block is processed as described above.
  • the encryption device (7) If the mode is set without direct access to the memory, then the encryption device (7) expects the central processor (2) to download the data block for encryption, according to the set operation mode. At the end of the encryption, the encryption device (7) expects a command from the central processor (2) to read crypto-converted data. After reading the result, the device is put into standby mode.
  • IP information exchange
  • Synopsys can be used as an internal switching unit (3) and as a memory controller (5).
  • Data exchange between the central processor and the rest of the SoC nodes is carried out through the internal switching unit using the address-data bus, for example, satisfying the Advanced extensible Interface (AXI) standard.
  • AXI Advanced extensible Interface
  • the functioning of the SoC (1) is carried out by programming the central processor (2), which can be used, for example, the microprocessor system MIPS P-5600 from Imagination Technologies, and the commands from which are transmitted via the configuration interface (1 1), which includes , at least, bus address, data and control bus of transmitted information.
  • the control signals are sent to the controller (4) direct access to the memory and to the control unit (21) of the encryption device (7).
  • the controller (4) for direct access to the memory is programmed, setting the addresses for which it is necessary to take data for encryption from the memory ( 6) (for example, external or part of the SN serial RAM) and return (save, send) back to the memory (6) data crypto-converted by the encryption device (7), and the rules for generating interrupts at the end of the transfer are also programmed and data to / from the memory (6).
  • the encryption result is accumulated in the control unit (21) of the encryption device (7) and, depending on the selected operating mode, is sent back to the memory (6) (for example, an external or sequential SoC component) RAM) through the controller (4) direct access to the memory, or stored in the control unit (21), waiting for a request to "read" from the central processor (2), when using an encryption device as part of a computing system.
  • the result of the development of the insert is also read on request from the central processor (2) from the corresponding register (20).
  • the configuration bus (11) of the address data for controlling the operation of the encryption device for example, satisfying the ARV standard.
  • the address-data bus (12) can be used, for example, satisfying the AXI standard.
  • the address-data bus (13), for example, satisfying the AXI standard can be used.
  • the address-data bus (14) can be used, for example, which satisfies the ANV standard.
  • an address-data bus (15) can be used, for example, satisfying the ANV standard. Data from the memory is transferred to the memory controller (5) and back via the standard interface.
  • the address-data bus (16) for example, satisfying the AXI standard, can be used.
  • the data for encryption can either be received in streaming form directly from the memory (6) (for example, serial RAM) through the direct memory access controller (4), or received as a single data block by command CPU (2). In the latter case, the result of the crypto conversion becomes available to the central processor for reading through the internal switching unit.
  • preliminary programming the controller (4) indicating the address at which data is located in memory (6) (in external or part of the SoC serial RAM), the addresses at which crypto-converted data should be stored (sent) back to memory (6), as well as the size of the data for crypto conversion.
  • preliminary programming of the controller (4) is not required.
  • the first embodiment of the encryption device shown in FIG. 1 we obtain the first version of SoC
  • the second version of the encryption device shown in FIG. 2 we obtain the second version of SoC.
  • the functioning of the SoC in both cases is carried out similarly, with the exception of the encryption processes occurring in the encryption device (7).
  • the second version of SoC is preferable to use to speed up the encryption process in the modes accompanied by the calculation of the self-insert using the encryption unit (9) of the encryption device (7), which allows it to be computed in parallel with the main encryption process occurring in the computing unit (8).
  • an external serial RAM for example, SRAM, DDR, DDR2, DDR3, etc.
  • TLS Transport Layer Security — a cryptographic protocol that provides secure data transfer between nodes on the Internet.
  • the invention can also be widely applied in SoCs, controllers that encrypt data coming from the Internet or on hard drives.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Theoretical Computer Science (AREA)
  • General Health & Medical Sciences (AREA)
  • Health & Medical Sciences (AREA)
  • Bioethics (AREA)
  • Signal Processing (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Storage Device Security (AREA)

Abstract

Le groupe d'inventions concerne le domaine de la micro-électronique et des équipements informatiques et peut être utilisée dans des systèmes informatiques à haut rendement pour réduire le temps nécessaire au chiffrement des flux de données grâce à l'utilisation d'un dispositif spécialisé de chiffrement de données. Le dispositif de chiffrement comprend un contrôleur à accès direct à la mémoire assurant le chargement de l'ensemble de données depuis la mémoire pour chiffrer les données et sauvegarder dans la mémoire les données transformées par traitement cryptographique, une unité de calcul capable de chiffrer les données selon un algorithme choisi, des registres de données pour stocker les données des tables de substitution, des registres de données pour stocker les clés de chiffrement, des registres pour stocker les vecteurs d'envoi synchronisé et d'insertion d'imitation ainsi qu'une unité de commande. Ce dispositif peut être intégré aux systèmes monopuce dans lesquels les données à chiffrer peuvent arriver directement depuis une mémoire externe (hors puce) ou interne (sur puce).
PCT/RU2016/000123 2015-03-04 2016-03-04 Dispositif de chiffrement de données (et variantes), système sur puce l'utilisant (et variantes) WO2016140596A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EA201700121A EA201700121A1 (ru) 2015-03-04 2016-03-04 Устройство шифрования данных (варианты), система на кристалле с его использованием (варианты)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
RU2015107429 2015-03-04
RU2015107429/08A RU2585988C1 (ru) 2015-03-04 2015-03-04 Устройство шифрования данных (варианты), система на кристалле с его использованием (варианты)

Publications (1)

Publication Number Publication Date
WO2016140596A1 true WO2016140596A1 (fr) 2016-09-09

Family

ID=56115223

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/RU2016/000123 WO2016140596A1 (fr) 2015-03-04 2016-03-04 Dispositif de chiffrement de données (et variantes), système sur puce l'utilisant (et variantes)

Country Status (3)

Country Link
EA (1) EA201700121A1 (fr)
RU (1) RU2585988C1 (fr)
WO (1) WO2016140596A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
HUE16774544T1 (hu) 2016-07-29 2020-02-28 Permanent Privacy Ltd Biztonságos titkosításhoz kapcsolódó alkalmazások
RU2765406C1 (ru) * 2020-05-14 2022-01-28 Акционерное общество "Научно-производственный центр автоматики и приборостроения имени академика Н.А. Пилюгина" (АО "НПЦАП") Устройство симметричного шифрования данных с использованием алгоритма строгой аутентификации

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2287222C1 (ru) * 2005-05-20 2006-11-10 Государственное унитарное предприятие г. Москвы Научно-производственный центр "СПУРТ" Способ формирования синхропосылки криптографического алгоритма в системах связи с обеспечением имитозащищенности и конфиденциальности передаваемых сообщений
US7783037B1 (en) * 2004-09-20 2010-08-24 Globalfoundries Inc. Multi-gigabit per second computing of the rijndael inverse cipher

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2140709C1 (ru) * 1997-12-16 1999-10-27 Молдовян Александр Андреевич Способ криптографического преобразования блоков цифровых данных
DE102004004799B4 (de) * 2004-01-30 2010-02-18 Advanced Micro Devices, Inc., Sunnyvale Hardware/Software-Partitionierung für verschlüsselte WLAN-Verbindungen
DE102004014435A1 (de) * 2004-03-24 2005-11-17 Siemens Ag Anordnung mit einem integrierten Schaltkreis
US8130946B2 (en) * 2007-03-20 2012-03-06 Michael De Mare Iterative symmetric key ciphers with keyed S-boxes using modular exponentiation
US8964554B2 (en) * 2012-06-07 2015-02-24 Broadcom Corporation Tunnel acceleration for wireless access points

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7783037B1 (en) * 2004-09-20 2010-08-24 Globalfoundries Inc. Multi-gigabit per second computing of the rijndael inverse cipher
RU2287222C1 (ru) * 2005-05-20 2006-11-10 Государственное унитарное предприятие г. Москвы Научно-производственный центр "СПУРТ" Способ формирования синхропосылки криптографического алгоритма в системах связи с обеспечением имитозащищенности и конфиденциальности передаваемых сообщений

Also Published As

Publication number Publication date
RU2585988C1 (ru) 2016-06-10
EA201700121A1 (ru) 2017-10-31

Similar Documents

Publication Publication Date Title
US8069279B2 (en) Data flow control within and between DMA channels
US9954681B2 (en) Systems and methods for data encryption
US7496695B2 (en) Unified DMA
US7548997B2 (en) Functional DMA performing operation on DMA data and writing result of operation
US7707477B2 (en) Checksum calculation
US7512743B2 (en) Using shared memory with an execute-in-place processor and a co-processor
KR20150143708A (ko) 스토리지 디바이스 보조 인라인 암호화 및 암호해독
EP2232363A2 (fr) Co-processeur pour traitement de données de flux
JP2008500638A (ja) 暗号化オペレーションをサポートする複数のレジスタを備えたデータムーバコントローラ
EP3803672B1 (fr) Moteur cryptographique matériel à mémoire efficace
US20140173275A1 (en) Securing data transmissions between processor packages
WO2014177905A1 (fr) Dispositif possédant un module de sécurité
US8271805B2 (en) Methods and apparatus for providing a secure buffer
WO2016140596A1 (fr) Dispositif de chiffrement de données (et variantes), système sur puce l'utilisant (et variantes)
JP4960456B2 (ja) 単一および多重ａｅｓ動作をサポートする二重モードａｅｓインプリメンテーション
EA041824B1 (ru) Устройство шифрования данных (варианты), система на кристалле с его использованием (варианты)
US8380137B2 (en) Circuit, process, and use of a memory for transmitting and/or receiving in a radio network

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16759207

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 201700121

Country of ref document: EA

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16759207

Country of ref document: EP

Kind code of ref document: A1