WO2016137437A1

WO2016137437A1 - Determining a state of a memristor cell

Info

Publication number: WO2016137437A1
Application number: PCT/US2015/017242
Authority: WO
Inventors: Yoocharn Jeon
Original assignee: Hewlett Packard Enterprise Development LP
Current assignee: Hewlett Packard Enterprise Development LP
Priority date: 2015-02-24
Filing date: 2015-02-24
Publication date: 2016-09-01
Anticipated expiration: 2017-08-24

Abstract

A disclosed example method involves, at a first time, biasing the selected control line to a first voltage, biasing a second one of control lines in an array to a second voltage, biasing the selected signal line to a third voltage to cause a sneak current through the second one of the control lines in the array, the third voltage different from the second voltage, and sampling and holding, via a subtraction circuit, the sneak current through the selected signal line. The disclosed example method also involves, at a second time after the first time, biasing the selected control line to a fourth voltage to cause a read current through the selected signal line, and measuring, via a sense circuit, the read current after the sneak current is removed from the selected signal line via the subtraction circuit.

Description

DETERMINING A STATE OF A MEMRISTOR CELL

BACKGROUND

[0001] Non-volatile random access memory, such as flash memory and resistive random-access memory (RRAM), retain information when power is not supplied to the memory. Memristor-based RRAM exploits the property of a memristor that the resistance of the memristor depends on the magnitude and direction of the charge that last flowed through it.

BRIEF DESCRIPTION OF THE DRAWINGS

[0002] FIG. 1 illustrates an example system to determine a state of a selected memristor cell.

[0003] FIGS. 2A and 2B illustrate an example hardware circuit that may be used to implement the example system of FIG. 1 to determine the state of the selected memristor cell.

[0004] FIGS. 3A and 3B illustrate another example hardware circuit that may be used to implement the example system of FIG. 1 to determine the state of the selected memristor cell.

[0005] FIG. 4 depicts an example graph showing current and voltage characteristics defining the states of a memristor cell.

[0006] FIG. 5A depicts an example graph showing read current and sneak current of the example system of FIG. 1 and the example hardware circuit(s) of FIGS. 2A, 2B and/or 3A, 3B when the selected memristor cell is in a high resistance state and a low resistance state.

[0007] FIG. 5B depicts an example graph showing read current after subtracting a sneak current of the example system of FIG. 1 and the example hardware circuit(s) of FIGS. 2A, 2B and/or 3A, 3B when the selected memristor cell is in a high resistance state and a low resistance state.

[0008] FIG. 6 depicts a flowchart of an example process that may be used to implement the example system of FIG. 1 and the example hardware circuit(s) of FIGS. 2A, 2B and/or 3A, 3B to determine a state of a selected memristor cell.

[0009] FIG. 7 depicts a flowchart of an example process that may be used to implement the example system of FIG. 1 and the example hardware circuit(s) of FIGS. 2A, 2B and/or 3A, 3B to determine a state of a selected memristor cell.

[0010] FIG. 8 depicts a flowchart of another example process that may be used to implement the example system FIG. 1 and the example hardware circuit(s) of FIGS. 2A, 2B and/or 3A, 3B to determine a state of a selected memristor cell.

[0011] FIG. 9 depicts a flowchart of an example process that may be used to implement the example system of FIG. 1 and the example hardware circuit(s) of FIGS. 2A, 2B and/or 3A, 3B to subtract a sneak current from a signal line of a selected memristor cell.

[0012] FIG. 10 is an example processor system incorporating the example system of FIGS. 1 , 2A, 2B, 3A, and/or 3B.

DETAILED DESCRIPTION

[0013] Example apparatus, methods, and articles of manufacture disclosed herein may be used to determine a state of a memristor cell. A memristor is a passive electrical component having electrical properties that can be used to store information through changing its resistance. The resistance of a memristor cell is a configurable characteristic indicative of the state of the memristor cell, and thus, the information stored in the memristor cell. The resistance of the memristor cell is configurable by applying different electrical currents or voltages across the memristor cell depending on the information (e.g., a binary value of zero or one) to be stored in the memristor cell. For example, the resistance of the memristor can be configured/changed based on the magnitude and direction of the current or voltage that is provided through the memristor cell. Additionally, a memristor cell is a non-volatile component because the memristor cell does not require power to maintain its state (e.g., its resistance). A change in electric potential (e.g., voltage) across two electrodes of a memristor cell changes the resistance of the memristor cell (sometimes referred to as "writing"). To measure a state (e.g., resistance) of the memristor cell, a current or voltage is applied across the memristor cell (sometimes referred to herein as "reading") without changing the resistance characteristics of the memristor cell. Voltages used to change the resistance of the memristor cell are selected to define two states of the memristor cell indicative of binary logic values (e.g., one or zero), namely a high resistance state (H RS) and a low resistance state (LRS). In the HRS, the memristor cell has a relatively higher resistance than when in the LRS so that a read current (l_R) through the memristor cell can be measured to differentiate between the HRS and the LRS.

[0014] A crossbar array includes a first group of conductive parallel paths (e.g., control lines) and a second group of conductive parallel paths (e.g., signal lines) that intersect the first group of conductive parallel paths. A memristor array is a crossbar array with resistive elements (e.g., memristor cells) between the control lines and the signal lines. A memristor cell is selected to be read by applying a select voltage (V_s) to the control line of the memristor cell and a read voltage (V_R) to a corresponding signal line that is also in circuit with the memristor cell to form a read current (l_R) that flows across the selected memristor cell. The resulting read current (l_R) is measured on the signal line to determine the resistance, and thus, the state of the memristor cell (e.g., using Ohm's Law R=Vll). Because other memristor cells are on the same signal line as the selected memristor cell, undesirable current (e.g., sneak current) may leak through the other memristor cells. The sneak current (Is) through the unselected memristor cells on a signal line may obscure the state of the selected memristor cell. For example, if the sneak current (l_s) is sufficiently large enough, a memristor cell in the HRS may be mistakenly read as in the LRS (e.g., due to the measured current being inversely proportional to resistance). As used herein, a read current (l_R) is electrical current on a signal line that is attributable to a selected memristor cell. As used herein, a sneak current (l_s) is current on a signal line that is attributable to unselected memristor cells on the same signal line as a selected memristor cell. As used herein, a total current (l_T) is current on a signal line that is an aggregation of the sneak current (l_s) and the read current (l_R).

[0015] FIG. 1 illustrates an example system 100 to determine the state (e.g., HRS or LRS) of a selected memristor cell 1 02. The example memristor cell 102 is incorporated into a memristor array 1 04. In some examples, the memristor array 104 is a crossbar array of control lines and signals lines across which voltages are applied to select memristor cells for reading and/or writing. The example memristor cell 102 is at an intersection of a control line and a signal line in the memristor array 104. The example memristor cell 102 is in circuit with an example subtraction circuit 106. In some examples, separate subtraction circuits 106 are provided for respective signal lines in the memristor array 1 04. The example subtraction circuit 1 06 subtracts sneak currents (l_s) from the signal line of the selected memristor cell 102 corresponding to current produced by memristor cells that share the same signal line with the selected memristor cell 102. The subtraction circuit 106 is in circuit with a corresponding sensing circuit 108 that subtracts a sneak current (l_s) that flows through the memristor cell 102 to facilitate measuring a read current (l_R) flowing through the memristor cell 102 which may be used to determine the state of the memristor cell 102.

[0016] In the illustrated example, when a memristor cell 1 02 is read (e.g., the state of the memristor cell is determined), a total current (l_T) flows from the corresponding signal line of the memristor array 104 to the subtraction circuit 106. The total current (l_T) is an aggregation of the read current (l_R) attributable to current from the selected memristor cell 102 and the sneak current (l_s) attributable to memristor cells on the same signal line. The example subtraction circuit 106 is configured to remove or subtract the sneak current (l_s) from the total current (l_T) before measuring the read current (l_R) corresponding to the selected memristor cell 102. After the example subtraction circuit 106 removes the sneak current (l_s), the example sensing circuit 108 facilitates determining (e.g., measuring directly or indirectly) the read current (l_R). In the illustrated examples, the read current (I R) is indicative of the state of the selected memristor cell 102. For example, a relatively low read current (l_R) corresponds to a relatively high resistance (e.g., HRS) due to the inverse relationship between current and resistance defined by Ohm's Law. As such, the selected memristor cell 102 is in the HRS when the read current (IR) is relatively low.

[0017] In the illustrated example, a controller 1 10 is in circuit with the memristor array 104, the subtraction circuit 106, and the sensing circuit 108. The example controller 1 1 0 has hardware logic to select memristor(s) 102 in the memristor array 104. For example, the controller 1 10 applies voltages to the control lines and the signal lines of the memristor array 104. In the illustrated example, the controller 1 10 controls switch elements in the subtraction circuit 106 and/or the sensing circuit 1 08 (e.g., switch elements 206, 216 of FIGS. 2A and 2B). The example controller 1 1 0 determines the state (e.g., HRS or LRS) of the selected memristor cell(s) 102 based on read currents (l_R). In some examples, the controller 1 1 0 determines data value(s) (e.g., a logical one or a logical zero) based on the state(s) of the selected memristor cell(s) 102.

[0018] While an example manner of implementing example system 100 is illustrated in FIG. 1 , one or more of the elements, processes and/or devices illustrated in FIG. 1 may be combined, divided, re-arranged, omitted, eliminated and/or implemented in any other way. Further, the example selected memristor cell 102, the example memristor array 104, the example subtraction circuit 106, the example sensing circuit 108, the example controller 1 1 0, and/or more generally the example system 100 of FIG. 1 may be implemented by hardware, software, firmware and/or any combination of hardware, software and/or firmware. Thus, for example, any of the example selected memristor cell 1 02, the example memristor array 1 04, the example subtraction circuit 1 06, the example sensing circuit 108,the example controller 1 10, and/or more generally the example system 1 00 of FIG. 1 could be implemented by one or more analog or digital circuit(s), logic circuits, programmable processor(s), application specific integrated circuit(s) (ASIC(s)), programmable logic device(s) (PLD(s)) and/or field programmable logic device(s) (FPLD(s)). When reading any of the apparatus or system claims of this patent to cover a purely software and/or firmware implementation, at least one of the example selected memristor cell 102, the example memristor array 104, the example subtraction circuit 1 06, the example sensing circuit 108, the example controller 1 1 0, and/or more generally the example system 1 00 of FIG. 1 is/are hereby expressly defined to include a tangible computer readable storage device or storage disk such as a memory, a digital versatile disk (DVD), a compact disk (CD), a Blu-ray disk, etc. storing the software and/or firmware. Further still, the example system 100 may include one or more elements, processes and/or devices in addition to, or instead of, those illustrated in FIG.1 , and/or may include more than one of any or all of the illustrated elements, processes and devices.

[0019] FIGS. 2A and 2B illustrate an example hardware circuit configuration that may be implemented in connection with the example system 100 of FIG. 1 to determine the state (e.g., LRS or HRS) of the selected memristor cell (e.g., the memristor cell 1 02 of FIG. 1 ). The example memristor array 1 04 includes example control lines 200a-200d on a first plane and example signal lines 202a-202d on a second plane. Memristor cells 102, 203 of the memristor array 1 04 connect to corresponding ones of the control lines 200a-200d and corresponding ones of the signal lines 202a-202d. In a memristor cell, the direction of the current through the memristor cell depends on the electric potential differences (e.g., voltages) between a corresponding one of the control lines 200a-200d and a corresponding one of the signal lines 202a-202d. Additionally, the magnitude of the current through the memristor cell depends on the magnitude of the electric potential difference between a corresponding one of the control lines 200a-200d and a corresponding one of the signal lines 202a-202d, and the state (e.g., resistance) of the memristor cell. For example, when the memristor cell 102 is in the LRS, the current through the memristor cell 102 will be high relative to when the memristor cell 1 02 is in the HRS.

[0020] In the illustrated example of FIGS. 2A and 2B, the subtraction circuit 106 includes an example subtraction transistor 204, an example subtraction switch element 206, and an example hold capacitor 208. In the illustrated example, a source 204s of the subtraction transistor 204 is in circuit with ground 210. In the illustrated example, a drain 204d of the subtraction transistor 204 is in circuit with the memristor cell 102 to be measured (e.g., via a signal line 200d). In the illustrated example, a first terminal of the example subtraction switch element 206 is in circuit with the drain 204d of the example subtraction transistor 204. A first terminal of the example hold capacitor 208 is in circuit with a second terminal of the example subtraction switch element 206 and a gate 204g of the example subtraction transistor 204. In the illustrated example, a second terminal of the hold capacitor 208 is in circuit with the ground 21 0. In some examples, the subtraction switch element 206 is a metal oxide (MOS) device (e.g., a MOS transistor, etc.) or a thin-film device (e.g., a thin-film transistor (TFT), etc.). In the illustrated example, the subtraction transistor 204 operates in a saturation operating region when the selected memristor cell 1 02 is measured.

[0021 ] In the illustrated example of FIGS. 2A and 2B, the sensing circuit 108 includes an example first sense transistor 212, an example second sense transistor 214, an example sense switch element 21 6, and an example reference current source 218 (I REF)- In the illustrated examples, the source 212s of the first sense transistor 212 is in circuit with ground 210. A source 214s of the example second sense transistor 214 is in circuit with the ground 210. A gate 214g of the example second sense transistor 214 is in circuit with a gate 21 2g of the example first sense transistor 212. A first terminal of the example sense switch element 216 is in circuit with a drain 204d of the example subtraction transistor 204 of the subtraction circuit 1 06. A second terminal of the example sense switch element 216 is in circuit with the drain 212d of the example first sense transistor 212, the example gate 212g of the first sense transistor 212, and the gate 214g of the example second sense transistor 214. In some examples, the sensing switch element 216 is a metal oxide (MOS) device (e.g., a MOS transistor, etc.) or a thin-film device (e.g., a thin-film transistor (TFT), etc.). In the illustrated example, the reference current source 21 8 is in circuit with a drain 214d of the second sense transistor 214. In some examples, a voltage measurement to determine the state of the memristor cell 102 is performed (e.g., by the controller 1 10) at the drain 214d of the second sense transistor 214 as shown by measurement point 220. Correlating the voltage measurement with the state of the memristor cell 102 is disclosed below in connection with FIGS. 4, 5A, and 5B below.

[0022] FIG. 2A illustrates the example system 100 at a time t=0 when the memristor array 104 is in a sneak current sample mode (e.g., the memristor cell 102 to be read is half-selected). At time t=0, example subtraction switch element 206 enables a conductive path between the memristor cell 102 and the hold capacitor 208, and example sensing switch element 216 disables a conductive path between the memristor cell 1 02 and the sense transistors 212, 214. In the illustrated example of FIG. 2A, the control lines 200a-200d of the memristor array 1 04 are set to a half-select voltage (V_Hs)- In some examples, the half- select voltage (V_Hs) is half of the voltage used to select a memristor cell 102 on the control line (e.g., a select voltage (V_s)). The example signal lines 202a-202c that are not in circuit with the memristor cell 102 to be read are set to the half- select voltage (V_Hs)- The example signal line 202d corresponding to the memristor cell 102 to be read is set to the read voltage (V_R). In some examples, a clamping circuit is used to maintain the read voltage (V_R) throughout the read cycle. In some examples, the half-select voltage (V_Hs) is greater than the read voltage (V_R). Such applying of the half-select voltage (V_Hs) to the control lines 200a-200c causes a sneak current (l_s) to flow through the half-selected memristor cells 203 that are not to be read. The resultant sneak current (l_s) increases the total current (l_T) that flows on the signal line 202d of the memristor cell 102 to be read.

[0023] In the illustrated example of FIG. 2A, when the subtraction switch element 206 enables a conductive path from the memristor cell 102 to the hold capacitor 208 in the subtraction circuit 106, the example hold capacitor 208 accumulates a charge until a voltage (V_c) on the gate of the example

subtraction transistor 204 reaches a target bias voltage (V_TB) to cause the subtraction transistor 204 to divert the sneak current (l_s) through its drain 204d as a drain current of the subtraction transistor 204. When the sneak current (l_s) flows through the subtraction transistor 204, the sneak current (l_s) no longer is available to increase the voltage across the hold capacitor 208. The target bias voltage (V_TB) is the voltage applied to the gate 204g of the subtraction transistor 204 at which the sneak current (l_s) flows through the subtraction transistor 204. In the illustrated example, the target bias voltage (V_TB) is based on the magnitude of the sneak current (l_s). When the example subtraction switch element 206 does not provide the example conductive path (e.g., at time t=1 ) between the memristor cell 102 and the hold capacitor 208, the hold capacitor 208 continues to provide the target bias voltage (V_TB) to a gate 204g of the subtraction transistor 204. In some examples, the target bias voltage (V_TB) depends on the characteristics (e.g., oxide thickness, gate voltage/drain current relationship, temperature, etc.) of the example subtraction transistor 204. In the illustrated example, the subtraction transistor 204 is selected so that at the target bias voltage (V_TB), the subtraction transistor 204 operates in its saturation region (e.g., the magnitude of the sneak current (l_s) is within the saturation region of the subtraction transistor 204).

[0024] FIG. 2B illustrates the example system 100 at a time t=1

(occurring after time t=0) when the memristor array 104 is in a read mode (e.g., the memristor cell 102 to be read is selected). At time t=1 , the memristor array 104 changes modes. For example, in FIG. 2B the control line 200d

corresponding to the memristor cell 102 to be read is set to a select voltage (V_s), which causes a read current (l_R) to flow on the corresponding signal line 202d. A sneak current (l_s) described above also flows through the signal line 202d from the memristor cells 203 on the signal line 202d that are half-selected (e.g., are held at the half-select voltage (V_Hs)), and the signal line 202d is clamped to the read voltage (V_R). At time t=1 , a conductive path between the memristor cell 102 and the sense transistors 21 2, 214 is enabled by the sense switch element 216. Additionally, in the illustrated example, a conductive path between the memristor cell 102 and the hold capacitor 208 is disabled by the subtraction switch element 206. In the illustrated example of FIG. 2B, the hold capacitor 208 holds the target bias voltage (V_TB) on the gate 204g of the subtraction transistor 204. As a result, the current through the subtraction transistor 204 (e.g., the drain current) remains equal to the sneak current (l_s) because the subtraction transistor 204 is held in the saturation region by the target bias voltage (V_TB) established at time t=0. As such, the sneak current (l_s) is subtracted from the total current (l_T) resulting in the read current (l_R) flowing through the first sense transistor 212. The read current (l_R) is measured as a difference between the sneak current (l_s) and a total current (l_T).

[0025] In the illustrated example of FIG. 2B, the first sense transistor 212 and the second sense transistor 214 are connected to one another to form a current mirror. That is, the drain currents of both the first sense transistor 212 and the second sense transistor 214 are equal to the read current (l_R). The example second sense transistor 214 causes the read current (l_R) to be subtracted from the reference current (I _REF) supplied by the example reference current source 21 8. A measurement indicative of the state of the memristor cell 102 is taken at the example measurement point 220 (e.g., by the controller 1 1 0). In some examples, the controller 1 10 includes an analog-to-digital converter (ADC) that is connected to the measurement point 220 to convert a measured voltage to a digital value for further processing (e.g., to determine the state of the memristor cell 102). In some examples, the controller 1 10 includes a comparator circuit in circuit with the measurement point 220. Such a comparator may be configured to include one or more thresholds set to output a Boolean value (e.g., a voltage threshold representing a logical one value, or a voltage threshold representing a logical zero value) depending on whether a difference between the read current (l_R) and the reference current (I _REF) indicates that the memristor cell 102 is in the HRS (e.g., the read current (l_R) is relatively low) or the LRS (e.g., the read current (l_R) is relatively high). For example, when the read current (l_R) is relatively high, the comparator circuit may output a voltage indicating a logical zero value.

[0026] FIGS. 3A and 3B illustrate another example hardware circuit configuration that may be implemented in connection with the example system 100 of FIG. 1 to determine the state (e.g., LRS or HRS) of the selected memristor cell (e.g., the memristor cell 1 02 of FIG. 1 ). The example memristor array 1 04 includes example control lines 200a-200d on a first plane and example signal lines 202a-202d on a second plane. Memristor cells of the memristor array 104 connect to corresponding ones of the control lines 200a- 200d and corresponding ones of the signal lines 202a-202d. In a memristor cell, the direction of the current through the memristor cell depends on the electric potential differences (e.g., voltages) between a corresponding one of the control lines 200a-200d and a corresponding one of the signal lines 202a-202d.

Additionally, the magnitude of the current through the memristor cell depends on the magnitude of the electric potential difference between a corresponding one of the control lines 200a-200d and a corresponding one of the signal lines 202a- 202d, and the state (e.g., resistance) of the memristor cell. For example, when the memristor cell 102 is in the LRS, the current through the memristor cell 1 02 will be high relative to when the memristor cell 102 is in the HRS.

[0027] In the illustrated example of FIGS. 3A and 3B, the subtraction circuit 106 includes an example subtraction transistor 204, an example subtraction switch element 206, an example hold capacitor 208, an example charge capacitor 300, and an example operation amplifier (op-amp) 302. In the illustrated example, a non-inverted input (+) of the op-amp 302 is in circuit with a terminal of the example charge capacitor 300, the control line 202d of the selected memristor cell 102, the drain 204d of the subtraction transistor 204, and a first terminal of the sense switch element 21 6. In the illustrated example, the select voltage (V_s) is applied to the inverted input (-) of the example op-amp 302. An output of the example op-amp 302 is in circuit with a first terminal of subtraction switch element 206. In the illustrated example, the subtraction switch element is a three-element switch that provides conductive paths either between the output of the op-amp 302 and a portion of the subtraction circuit 106 or between the output of the op-amp 302 and the sense circuit 108. A second terminal of the example charge capacitor 300, a second terminal of the example hold capacitor 208, and a drain 204d of the example subtraction transistor 204 are in circuit with the ground 201 . In the illustrated example, a gate 204g of the subtraction transistor 204 and a first terminal of the hold capacitor 208 are in circuit with a second terminal of the subtraction switch element 206.

[0028] In the illustrated example, the subtraction circuit 106 includes a precharge transistor 304. In such example, a drain of the precharge transistor 304 is in circuit with the inverted input (-) of the op-amp 302, and a source of the precharge transistor 304 is in circuit with the non-inverted input (+) of the op- amp 302, a terminal of the example charge capacitor 300, the control line 202d of the selected memristor cell 102, the drain 204d of the subtraction transistor 204, and a first terminal of the sense switch element 216. In the illustrated example, the controller 1 10 applies a voltage to a gate of the precharge transistor 304 to enable a conductive path between the select voltage (V_s) and the terminal of the charge capacitor 300 to precharge the charge capacitor 300 so that when the memristor cell 102 is selected (or half-selected), the charging time of the charge capacitor 300 is reduced (e.g., because the sense node voltage (V_SN) on the charge capacitor 300 is equal to the select voltage (V_S)).

[0029] In the illustrated example of FIGS. 3A and 3B, the sensing circuit 108 includes an example first sense transistor 212, an example second sense transistor 214, an example sense switch element 21 6, and an example reference current source 218 (I REF)- In the illustrated example, the source 21 2s of the first sense transistor 212 and a source 214s of the second sense transistor 214 are in circuit with ground 210. A gate 214g of the example second sense transistor 214 is in circuit with a gate 212g of the example first sense transistor 212 and a third terminal of the subtraction switch element 206. A second terminal of the example sense switch element 216 is in circuit with the drain 212d of the example first sense transistor 21 2. In the illustrated example, the reference current source 218 is in circuit with a drain 214d of the second sense transistor 214. In some examples, a voltage measurement to determine the state of the memristor cell 102 is performed (e.g., by the controller 1 10) at the drain 214d of the second sense transistor 214 as shown by measurement point 220. Correlating the voltage measurement with the state of the memristor cell 102 is disclosed below in connection with FIGS. 4, 5A, and 5B.

[0030] FIG. 3A illustrates the example system 100 at a time t=0 when the memristor array 104 is in a sneak current sample mode (e.g., the memristor cell 102 to be read is half-selected). At time t=0, example subtraction switch element 206 enables a conductive path between the output of the example op-amp 302 and the example hold capacitor 208, and the example sensing switch element 216 disables a conductive path between the selected memristor cell 102 and the drain 212d of the example first sense transistor 212. In the illustrated example of FIG. 3A, the control lines 200a-200d of the memristor array 1 04 are set to a half-select voltage (V_Hs)- The example signal lines 202a-202c that are not in circuit with the memristor cell 102 to be read are set to the half-select voltage (V_Hs)- The example signal line 202d that has the memristor cell 1 02 to be read is set to the read voltage (V_R). Such applying of the half-select voltage (V_Hs) to the signal line 202d causes a sneak current (l_s) to develop through the half-selected memristor cells 203 that are not to be read.

[0031 ] In the illustrated example, the op amp 302 controls the voltage applied to the gate 204g of the subtraction transistor 204 to regulate the voltage (e.g., the sense node voltage (V_SN) at the drain 204d of the of subtraction transistor 204 to the sense voltage (V_s). When the voltage applied to the gate 204g of the example subtraction transistor 204 by the op amp 302 stabilizes, a current substantially equal to the sneak current (IS) flows from the drain 204d to the source 204s of the example subtraction transistor 204. The stabilized voltage is held by the example hold capacitor 208. The sense node voltage (V_SN) is applied to the non-inverting input (+) of the op-amp 302. When the sense node voltage (V_SN) is greater than the select voltage (V_S), the op-amp 302 supplies a higher charge voltage (V_c) to the gate 204g of the subtraction transistor 204 and the hold capacitor 208. As a result, the hold capacitor 208 charges to the higher charge voltage (V_c) and the subtraction transistor 204 diverts more of the sneak current (l_s) through its drain 204d as a drain current. In the illustrated example, when more of the sneak current (l_s) is diverted through the subtraction transistor 204, the sense node voltage (V_SN) returns to the sense voltage (V_s). A portion of the sneak current (l_s) that is not diverted through the subtraction transistor 204 supplies charge to the charge capacitor 300. This cycle continues until substantially all of the sneak current (l_s) is diverted through the subtraction transistor 204. The hold capacitor 208 holds the voltage on the gate 204g of the subtraction transistor 204 when the subtraction switch element 306 disables the conductive path between the op-amp 302 and the subtraction transistor 204 (e.g., at time t=1 ). . [0032] FIG. 3B illustrates the example system 100 at a time t=1

(occurring after time t=0) when the memristor array 104 is in a read mode (e.g., the memristor cell 102 to be read is selected). At time t=1 , the memristor array 104 changes modes. For example, in FIG. 3B the control line 200d

corresponding to the memristor cell 102 to be read is set to a select voltage (V_s), which causes a read current (l_R) to flow on the corresponding signal line 202d. A sneak current (l_s) described above also flows on the signal line 202d from the memristor cells 203 on the signal line 202d that are half-selected (e.g., are held at the half-select voltage (V_Hs))- At time t=1 , a conductive path between the memristor cell 102 and the sense transistors 21 2 is enabled by the sense switch element 216, and a conductive path between the output of the op-amp 302 and the gates 212g, 214g of the sense transistors 212, 214 is enabled by the subtraction switch element 206. In the illustrated example of FIG. 3B, because the hold capacitor 208 holds the charge voltage (V_c) on the gate 204g of the subtraction transistor 204, a current equal to the sneak current (l_s) flows through the subtraction transistor 204 (e.g., as the drain current) to ground 210. As such, the sneak current (l_s) is subtracted from the total current (l_T) resulting in the read current (l_R) flowing through the first sense transistor 212. The read current (l_R) is measured as a difference between the sneak current (l_s) and a total current (l_T).

[0033] In the illustrated example of FIG. 3B, the first sense transistor 212 and the second sense transistor 214 are connected to one another to form a current mirror. That is, the drain currents of both the first sense transistor 212 and the second sense transistor 214 are equal to the read current (l_R). The example second sense transistor 214 causes the read current (l_R) to be subtracted from the reference current (I _REF) supplied by the example reference current source 21 8. A measurement indicative of the state of the memristor cell 102 is taken at the example measurement point 220 (e.g., by the controller 1 1 0). In some examples, the controller 1 10 includes a comparator circuit in circuit with the measurement point 220. In such examples, the comparator circuit may be configured to have one or more thresholds set to output a Boolean value (e.g., a voltage threshold representing a logical one value, or a voltage threshold representing a logical zero value) depending on whether a difference between the read current (l_R) and the reference current (I REF) indicates that the memristor cell 102 is in the HRS (e.g., the read current (l_R) is relatively low) or the LRS (e.g., the read current (l_R) is relatively high). For example, when the read current ( I R) is relatively high, the comparator circuit may output a voltage indicating a logical zero value.

[0034] FIG. 4 depicts an example graph 400 of read current (l_R) relative to voltage which is indicative of the states (e.g., a HRS or LRS, a logical one or a logical zero, etc.) of a memristor cell (e.g., the selected memristor cell 102 of FIGS. 1 , 2A, 2B, 3A, and 3B). In the illustrated example, when the half-select voltage (V_Hs) is applied to the control lines 200a-c and the read voltage (V_R) is applied to the signal line 202d (FIGS. 2A, 2B, 3A, and 3B), the read current (l_R) is substantially zero. When the read voltage (V_R) is applied to the signal line 202d and the select voltage (V_s) is applied to the control line 200d (FIGS. 2A, 2B), the read current (l_R) flows through the selected memristor cell 1 02. The magnitude of the read current (l_R) is based on the state of the selected memristor cell 102. For example, when the memristor cell 102 is in a LRS, the read current (l_R) will be relatively high compared to when the memristor cell 102 is in a HRS. A greater difference (ΔΙ) between read current (l_R) flowing through the selected memristor cell 1 02 in the HRS and the read current (l_R) flowing through the selected memristor cell 102 in the LRS creates a greater tolerance for measurement error. In the illustrated example, the difference (ΔΙ) between the read current (l_R) flowing through the selected memristor cell 102 in the HRS and the read current (l_R) flowing through the selected memristor cell 102 in the LRS is based on the resistance of the memristor cell 102 in the HRS, the resistance of the memristor cell 102 in the LRS, the select voltage (V_s), and the read voltage (V_R).

[0035] FIG. 5A depicts an example graph 500 of the read current (l_R) and the sneak current (l_s) when the selected memristor cell 102 (FIGS. 1 , 2A, 2B, 3A, and 3B) is in a HRS and a LRS when there are many control lines (e.g., the control line 200a-200c of FIGS. 2A, 2B, 3A, and 3B) in the memristor array 104 (FIGS. 1 , 2A, 2B, 3A, and 3B) and the total sneak current (l_s) from the many control lines are significantly large. The magnitude of the total sneak current (l_s) varies depending on the operation temperature of the memristor array 104 and the fabrication process conditions of the memristor array 1 04. In the illustrated example, the magnitude of the variation in the sneak current (Al_s) is sufficiently large to obscure the read current (l_R) used to determine the state of the memristor cell 102 to be measured. For example, because only the total current (l_T) can be measured on the signal line 200d of the selected memristor cell 102, there is no way to distinguish between a memristor cell 102 in the LRS with a low sneak current and a memristor cell 1 02 is in HRS with a high sneak current.

[0036] FIG. 5B depicts an example graph 502 of the read current (l_R) after subtracting the sneak current (l_s) from a total current (l_T) flowing through a signal line 202d (FIGS. 2A and 2B) corresponding to the selected memristor cell 102 when the selected memristor cell is in a HRS and a LRS. In the illustrated example, detection regions 504 are areas along the current measurements where there is a detectable difference between the read current (l_R) of the selected memristor cell 102 in the HRS and the read current (l_R) of the selected memristor cell 102 in the LRS even with variations in the resistance values in the LRS and HRS. For example, while two different memristor cells may have difference resistance values in the HRS, the detection regions 504 are large enough to determine the state of the memristor despite the variation. In some examples, the select voltage (V_s) and/or the read voltage (V_R) are selected so that measurements of the read current (l_R)) fall within the detection regions 504.

[0037] Flowcharts representative processes for implementing the system 100 of FIG. 1 and the example hardware circuit(s) of FIGS. 2A, 2B and/or 3A, 3B are shown in FIGS. 6, 7, 8, and 9. In some examples, the processes or portions thereof are machine readable instructions including a program for execution by a processor such as the processor 1 012 shown in the example processor platform 1000 discussed below in connection with FIG. 10 and/or by a controller, such as the example controller 1 10 of FIGS. 1 , 2A, 2B, 3A, and 3B. The programs may be embodied in software stored on a tangible computer readable storage medium such as a CD-ROM, a floppy disk, a hard drive, a digital versatile disk (DVD), a Blu-ray disk, or a memory associated with the processor 1012, but the entire program and/or parts thereof could alternatively be executed by a device other than the processor 1012 and/or embodied in firmware or dedicated hardware. In some examples, the processes are hardware logic including dedicated hardware of the controller 1 10. Further, although the example processes are described with reference to the flowchart illustrated in FIGS. 6, 7, 8, and 9, many other methods of implementing the example system 100 may alternatively be used. For example, the order of execution of the blocks may be changed, and/or some of the blocks described may be changed, eliminated, or combined.

[0038] As mentioned above, the example processes of FIGS. 6, 7, 8, and 9 may be implemented using coded instructions (e.g., computer and/or machine readable instructions) stored on a tangible computer readable storage medium such as a hard disk drive, a flash memory, a read-only memory (ROM), a compact disk (CD), a digital versatile disk (DVD), a cache, a random-access memory (RAM) and/or any other storage device or storage disk in which information is stored for any duration (e.g., for extended time periods, permanently, for brief instances, for temporarily buffering, and/or for caching of the information). As used herein, the term tangible computer readable storage medium is expressly defined to include any type of computer readable storage device and/or storage disk and to exclude propagating signals and to exclude transmission media. As used herein, "tangible computer readable storage medium" and "tangible machine readable storage medium" are used

interchangeably. Additionally or alternatively, the example processes of FIGS. 6, 7, 8, and 9 may be implemented using coded instructions (e.g., computer and/or machine readable instructions) stored on a non-transitory computer and/or machine readable medium such as a hard disk drive, a flash memory, a read-only memory, a compact disk, a digital versatile disk, a cache, a random- access memory and/or any other storage device or storage disk in which information is stored for any duration (e.g., for extended time periods, permanently, for brief instances, for temporarily buffering, and/or for caching of the information). As used herein, the term non-transitory computer readable medium is expressly defined to include any type of computer readable storage device and/or storage disk and to exclude propagating signals and to exclude transmission media. As used herein, when the phrase "at least" is used as the transition term in a preamble of a claim, it is open-ended in the same manner as the term "comprising" is open ended.

[0039] FIG. 6 depicts a flow diagram representative of an example process 600 that may be used to implement the example system 100 of FIG. 1 , and the example hardware circuit(s) of FIGS. 2A, 2B and/or 3A, 3B to determine a state (e.g., HRS or LRS) of a memristor cell 102 (FIGS. 1 , 2A, 2B, 3A, and 3B) to be read. The example process is shown in connection with two phases, namely a subtraction phase 602 and a sensing phase 604. The subtraction phase 602 of the illustrated example is used to calibrate the subtraction circuit 106 (FIGS. 1 , 2A, 2B, 3A, and 3B) to remove the sneak current (l_s) from a selected signal line (e.g., the signal line 202d of FIGS. 2A, 2B, 3A, and 3B) based on the magnitude of the sneak current (l_s). The sensing phase 604 of the illustrated example is used to determine the magnitude of the read current (l_R) through the signal line 202d after the sneak current (l_s) has be removed by the subtraction circuit 106.

[0040] Initially, at block 606 during the subtraction phase 602, the example controller 1 1 0 (FIGS. 1 , 2A, 2B, 3A, and 3B) biases a selected control line (e.g., the control line 200d of FIGS. 2A, 2B, 3A, and 3B) corresponding to the memristor cell 102 in an array of control lines and signal lines (e.g., the memristor array 104 of FIGS. 1 , 2A, 2B, 3A, and 3B) with a first voltage (e.g. the half-select voltage (V_HS) of FIGS. 2A and 3A, zero volts, etc.). At block 608, the example controller 1 1 0 biases one or more second one(s) of the control lines (e.g., the control lines 200a-200c of FIGS. 2A, 2B, 3A, and 3B) in the array of control lines and signal lines to a second voltage (e.g., the half-select voltage (VHS) of FIGS. 2A, 2B, 3A and 3B). At block 610, the example controller 1 10 biases the selected signal line corresponding to the memristor cell 1 02 in the array of control lines and signal lines to a third voltage (e.g., the read voltage (V_R) of FIGS. 2A, 2B, 3A, and 3B) to cause a sneak current (l_s) through the one or more second one(s) of the control lines 200a-200d and onto the selected signal line 202d. In the illustrated example, the controller 1 10 biases the second one(s) 202a-202c of the control lines in the array of control lines and signal lines to a different voltage than the controller 1 10 biases the selected signal line 202d. At block 612, the example subtraction circuit 106 (FIGS. 1 , 2A, 2B, 3A, and 3B) samples and holds the sneak current (l_s) through the selected signal line 202d. To sample the sneak current (l_s), the example subtraction circuit 106 biases a transistor (e.g., the subtraction transistor 204 of FIGS. 2A, 2B, 3A, and 3B), based on the magnitude of the sneak current (l_s), to allow a current substantially equal to the sneak current (l_s) to flow through the transistor.

Examples to sample the sneak current (l_s) are described in detail above in connection with FIGS. 2A and 3A. To hold the sneak current (Is), the example subtraction circuit 106 maintains a bias voltage on the transistor via a capacitor (e.g., the hold capacitor 208 of FIGS. 2A, 2B, 3A, and 3B) so that the sneak current (IS) flows through the transistor during the sensing phase 604.

Examples to hold the sneak current (l_s) are described in detail above in connection with FIGS. 2A and 3A.

[0041] During the sensing phase 604 at block 614, the example controller 1 1 0 biases the selected control line 200d to a fourth voltage (e.g., the select voltage (V_s) of FIGS. 2B and 3B) to cause a read current (l_R) through the selected signal line 202d. At block 616, the controller 1 10 measures the read current (l_R) after the sneak current (l_s) is removed from the selected signal line 202d (e.g., by the subtraction circuit 106). At block 618, the example controller 1 1 0 determines the state of the example memristor 102 based on the measured read current (l_R). Examples to determine the state of the memristor 102 are described in detail above in connection with FIGS. 2B and 3B. At block 620, the example controller 1 1 0 determines whether a state of another memristor cell 102 is to be read. If a state of another memristor cell 1 02 is to be read, control returns to block 606. Otherwise, if a state of another memristor cell is not to be read, the example process 600 ends.

[0042] FIG. 7 depicts a flow diagram representative of an example process 700 that may be used to implement the example system 100 of FIG. 1 , and the example hardware circuit(s) of FIGS. 2A, 2B and/or 3A, 3B to determine a state (e.g., HRS or LRS) of a memristor cell 102 (FIGS. 1 , 2A, 2B, 3A, and 3B) to be read. Initially, at block 702, the example controller 1 10 (FIGS. 1 , 2A, 2B, 3A, and 3B) half-selects the memristor cells (e.g., the memristor cells 203 of FIGS. 2A, 2B, 3A, and 3B) on the same control line 200d as the memristor cell 102 to be read. For example, the controller 1 10 half-selects the memristor cells 203 of the memristor array 104 by applying a half-select voltage (V_Hs) to control lines (e.g., the control lines 200a-200c of FIGS. 2A, 2B, 3A, and 3B)

corresponding to the memristor cells 203 and a read voltage (V_R) to a corresponding signal line (e.g., the signal line 202d of FIGS. 2A, 2B, 3A, and 3B) of the memristor cell 1 02 as described above in connection with FIGS. 2A and 3A. In some examples, the half-select voltage (V_Hs) is applied to the control line 200d of the memristor cell 1 02. Alternatively, in some examples, the read voltage (V_R) is applied to the control line 200d of the memristor cell 102. At block 704, the example subtraction circuit 106 (FIGS. 1 , 2A, 2B, 3A, and 3B) determines the sneak current (l_s) corresponding to the signal line 202d of the memristor cell 102 to be read. For example, the subtraction circuit 1 06 determines the sneak current (l_s) by applying a target bias voltage to the gate 204g of the subtraction transistor 204 (FIGS. 2A, 2B, 3A, and 3B) as described in detail above in connection with FIG. 2A. At block 706, the example controller 1 1 0 selects the memristor cell 102 to be read. For example, the controller 1 10 applies a select voltage (V_s) to the control line 200d corresponding to the memristor cell 102 as described in detail above in connection with FIGS. 2B and 3B. At block 708, the example subtraction circuit 1 06 subtracts the sneak current (l_s) from the total current (l_T) on the signal line 202d.

[0043] At block 710, the example controller 1 10 determines the state (e.g., HRS or LRS) of the memristor cell 102 to be read. Examples to determine the state of the memristor cell 102 to be read are described in detail above in connection with FIGS. 2B and 3B. At block 712, the example controller 1 10 determines whether a state of another memristor cell is to be read. If a state of another memristor cell 102, 203 is to be read, control returns to block 704. Otherwise, if a state of another memristor cell 102, 203 is not to be read, the example process 700 ends. [0044] FIG. 8 depicts an example process 800 that may be used to implement the example system 100 of FIG. 1 , and the example hardware circuit(s) of FIGS. 2A, 2B and/or 3A, 3B to determine a state (e.g., the HRS or the LRS) of a memristor cell 102 (FIGS. 1 , 2A, 2B, 3A, and 3B) to be read. Initially, at block 802, the example controller 1 10 (FIGS. 1 , 2A, 2B, 3A, and 3B) disables a conductive path between the memristor cell 102 and the sensing circuit 108. For example, the sensing circuit 108 can disable the conductive path by creating an open circuit using the sense switch element 216 of FIGS. 2A, 2B, 3A, and 3B. At block 804, the example controller 1 10 (FIGS. 1 , 2A, 2B, 3A, and 3B) applies a half-select voltage (V_Hs) to control lines (e.g., the control lines 200a-200d of FIGS. 1 , 2A, 2B, 3A, and 3B) and signal lines (e.g., the signal lines 202a-202c of FIGS. 1 , 2A, 2B, 3A, and 3B) of the example memristor array 104. At block 806, the example memristor array 1 04 applies a read voltage (V_R) to the signal line 202d of the memristor cell 102 to be read. At block 808, the example subtraction circuit 106 (FIGS. 1 , 2A, 2B, 3A, and 3B) enables a conductive path between the memristor cell 102 and the subtraction circuit 106. For example, the subtraction circuit 1 06 can enable the conductive path by creating a closed circuit using the subtraction switch element 206 of FIGS. 2A, 2B, 3A, and 3B. At block 810, the example subtraction circuit 106 waits until the sneak current (l_s) flowing through the subtraction transistor 206 (FIGS. 2A, 2B, 3A, and 3B) stabilizes. In some examples, the example subtraction circuit 106 waits until the sense node voltage (V_SN) stabilizes when the sneak current (l_s) flows through the subtraction transistor 206. In some examples, the subtraction circuit 106 may wait a set period of time calculated to allow the voltage applied to the gate 204g of the subtraction transistor to stabilize.

[0045] At block 812, the example subtraction circuit 106 disables the conductive path between the memristor cell 102 and the hold capacitor 208. For example, the subtraction circuit 106 can disable the conductive path by creating an open circuit using the subtraction switch element 206. At block 814, the example controller 1 1 0 applies a select voltage (V_s) to the control line 200d of the memristor cell 102 to be read. At block 816, the example sensing circuit 1 08 enables the conductive path between the memristor cell 102 and the sensing circuit 108. For example, the sensing circuit 108 can enable the conductive path by creating a closed circuit using the sense switch element 216. At block 818, the example controller 1 10 determines the state of the memristor cell 102 to be read. For example, the controller 1 10 may include a comparator circuit that compares a voltage at measurement point 220 caused by the read current (l_R) to a threshold. In such examples, the controller 1 1 0 may determine that the memristor cell 102 is in the LRS if the voltage caused by the read current (l_R) does not satisfy (e.g., is below) the threshold, and that the memristor cell 102 is in the HRS if the voltage caused by the read current (l_R) satisfies (e.g., is above) the threshold. At block 820, the controller 1 10 determines if the state of another memristor cell is to be determined. If a state of another memristor cell is to be determined, control returns to block 802. Otherwise, if a state of another memristor cell is not to be determined, the process 800 ends.

[0046] FIG. 9 depicts a flow diagram representative of an example process 900 that can be executed to implement the example system 100 of FIG. 1 , and the example hardware circuit(s) of FIGS. 2A, 2B and/or 3A, 3B to determine a state (e.g., the HRS or the LRS) of a memristor cell 102 to be read. Initially, at block 902, the example subtraction circuit 1 06 (FIGS. 1 , 2A, 2B, 3A and 3B) enables a conductive path between the memristor cell 102 and the subtraction circuit 106. For example, the subtraction circuit 106 can enable the conductive path by creating a closed circuit using the subtraction switch element 206 of FIGS. 2A, 2B, 3A, and 3B. At block 904, the example subtraction circuit 106 charges a capacitor (e.g. the hold capacitor 208 of FIGS. 2A, 2B, 3A, and 3B) to provide a bias voltage to a gate of a subtraction transistor (e.g., the gate 204g of the subtraction transistor 204 of FIGS. 2A, 2B, 3A and 3B). The example bias voltage is a voltage sufficient to allow the sneak current (l_s) to flow through the subtraction transistor 204 when the bias voltage is applied to the gate 204 of the subtraction transistor 204. For example, a sneak current (l_s) flows though the conductive path between the signal line (e.g., the signal line 202d of FIG. 2A) corresponding to the memristor 102 and the subtraction circuit 106 enabled at block 902 and causes a charge to accumulate on the hold capacitor 208. [0047] At block 906, the example subtraction circuit 106 waits until the bias voltage supplied by the example hold capacitor 208 stabilizes and allows the sneak current (Is) to flow from the drain 204d to the source 204s of the subtraction transistor 204. The example bias voltage supplied by the hold capacitor 208 substantially equalizes over time because, for example, the op amp 302 (FIGS. 3A and 3B) controls the gate voltage of the subtraction transistor 204 to make the transistor 204 flow the same current as the sneak current (l_s) by maintaining the sense node voltage (V_SN) at 204d.. When the bias voltage supplied by the example hold capacitor 208 substantially stabilizes, control advances to block 908. At block 908, the example controller 1 1 0 disables the conductive path between the signal line 202d and the hold capacitor 208. At block 910, the example controller 1 10 enables a conductive path between the memristor cell 1 02 and the sensing circuit 108. For example, the sensing circuit 108 can enable the conductive path by creating a closed circuit using the sense switch element 216. At block 912, the example controller 1 1 0 determines a magnitude of the read current (l_R) to determine the state (e.g., HRS or LRS) of the memristor cell 102. The read current (IR) is the difference between the sneak current (l_s) and the total current (l_T) on the signal line 202d of the memristor cell 1 02. The example process 900 then ends.

[0048] FIG. 10 is a block diagram of an example processor platform 1000 structured to incorporate the example system 100 of FIG. 1 . The processor platform 1000 can be, for example, a server, a personal computer, a mobile device (e.g., a cell phone, a smart phone, a tablet such as an iPad™), a personal digital assistant (PDA), an Internet appliance, a DVD player, a CD player, a digital video recorder, a Blu-ray player, a gaming console, a personal video recorder, a set top box, or any other type of computing device.

[0049] The processor platform 1000 of the illustrated example includes a processor 1012. The processor 1012 of the illustrated example is hardware. For example, the processor 1012 can be implemented by one or more integrated circuits, logic circuits, microprocessors or controllers from any desired family or manufacturer. [0050] The processor 1012 of the illustrated example includes a local memory 1013 (e.g., a cache). The processor 1012 of the illustrated example is in communication with a main memory including a random access memory 1014 and a read-only memory 101 6 via a bus 1 01 8. The random access memory 1014 may be implemented by the system 100 of FIG. 1 . The example random access memory 1014 includes the memristor array(s) 104, the subtraction circuit(s) 106, and the sensing circuit(s) 108. In the illustrated example, the random access memory 1 014 includes the controller 1 10. In some examples, the controller 1 10 is structured to include hardware (e.g., passive and/or active circuit elements, etc.) to implement the processes of FIGS. 6, 7, 8, and 9. The controller 1 10 may be implemented using discrete components, integrated circuits (e.g., via very large-scale integration (VSLI)), application-specific integrated circuits (ASICs), etc. The read-only memory 1016 may be

implemented by flash memory and/or any other desired type of memory device. Access to the main memory 1014, 1016 is controlled by a memory controller.

[0051] The processor platform 1000 of the illustrated example also includes an interface circuit 1020. The interface circuit 1 020 may be

implemented by any type of interface standard, such as an Ethernet interface, a universal serial bus (USB), and/or a PCI express interface.

[0052] In the illustrated example, one or more input devices 1022 are connected to the interface circuit 1020. The input device(s) 1022 permit(s) a user to enter data and commands into the processor 1012. The input device(s) can be implemented by, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, a button, a mouse, a touchscreen, a track-pad, a trackball, isopoint and/or a voice recognition system.

[0053] One or more output devices 1024 are also connected to the interface circuit 1020 of the illustrated example. The output devices 1024 can be implemented, for example, by display devices (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display, a cathode ray tube display (CRT), a touchscreen, a tactile output device, a printer and/or speakers). The interface circuit 1 020 of the illustrated example, thus, typically includes a graphics driver card, a graphics driver chip or a graphics driver processor.

[0054] The interface circuit 1020 of the illustrated example also includes a communication device such as a transmitter, a receiver, a transceiver, a modem and/or network interface card to facilitate exchange of data with external machines (e.g., computing devices of any kind) via a network 1 026 (e.g., an Ethernet connection, a digital subscriber line (DSL), a telephone line, coaxial cable, a cellular telephone system, etc.).

[0055] The processor platform 1000 of the illustrated example also includes one or more mass storage devices 1028 for storing software and/or data. Examples of such mass storage devices 1028 include floppy disk drives, hard drive disks, compact disk drives, Blu-ray disk drives, RAID systems, and digital versatile disk (DVD) drives.

[0056] In some examples, coded instructions 1032 may be stored in the mass storage device 1 028, in the volatile memory 1014, in the non-volatile memory 1016, and/or on a removable tangible computer readable storage medium such as a CD or DVD. The coded instructions 1032 may be used to cause the controller 1 10 to perform one or more of the operations of the example processes described above in connection with FIGS. 6, 7, 8, and 9.

[0057] Although certain example methods, apparatus and articles of manufacture have been disclosed herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all methods, apparatus and articles of manufacture fairly falling within the scope of the claims of this patent.

Claims

What Is Claimed Is:

1 . A method of determining a state of a memristor cell in circuit with a selected control line and a selected signal line in an array of control lines and signal lines, the method comprising:

at a first time:

biasing the selected control line to a first voltage;

biasing a second one of the control lines in the array to a second voltage;

biasing the selected signal line to a third voltage to cause a sneak current through the second one of the control lines in the array, the third voltage different from the second voltage;

sampling and holding, via a subtraction circuit, the sneak current through the selected signal line;

at a second time after the first time:

biasing the selected control line to a fourth voltage to cause a read current through the selected signal line; and

measuring, via a sense circuit, the read current after the sneak current is removed from the selected signal line via the subtraction circuit.

2. A method as defined in claim 1 , wherein sampling and holding the sneak current through the selected signal line includes using the sneak current to provide a charge to a hold capacitor, the hold capacitor to provide a hold voltage to cause the sneak current to flow though a transistor during the second time.

3. A method as defined in claim 2, wherein the charge on the hold capacitor enables a conductive path from a drain of a transistor to a source of the transistor to allow the sneak current to flow through the transistor at the second time.

4. A method as defined in claim 1 , wherein the read current is indicative of a datum stored in the memristor cell.

5. A method as defined in claim 1 , wherein the first voltage is equal to the third voltage.

6. A method as defined in claim 5, wherein the forth voltage is twice the third voltage.

7. A circuit to measure a first resistive memory element, the circuit comprising: a capacitor to provide a bias voltage to a gate of a first transistor, the first transistor to remove a first current on a signal line corresponding to the first resistive memory element when a crossbar array of resistive memory elements is in a first state;

a first switch element to provide a conductive path to facilitate charging the capacitor until the bias voltage causes a drain current of the first transistor to substantially equal the first current and the capacitor to continue to provide the bias voltage to a gate of the first transistor when the first switch element is not providing the conductive path; and

a sensing circuit to, when the crossbar array is in a second state, measure a read current from the first resistive memory element after the subtraction circuit removes the first current from a total current based on the bias voltage at the capacitor.

8. A circuit as defined in claim 7, wherein the bias voltage is a gate-source voltage of the first transistor that enables the sneak current to flow from a drain of the first transistor to a source of the first transistor.

9. A circuit as defined in claim 7, wherein the first current provides charge to the capacitor until the capacitor reaches the bias voltage.

10. A circuit as defined in claim 7, wherein the first state includes a read voltage on the signal line and a half-select voltage on a corresponding control line, and wherein the second state includes the read voltage on the signal line and a select voltage on the corresponding control line.

1 1 . A circuit as defined in claim 7, wherein the read current is indicative of a datum stored in the memristor cell.

12. A circuit to measure a state of a resistive memory element, comprising: a first transistor having in circuit with ground, and a drain of the first transistor being in circuit with the resistive memory element to be measured; a first switch element having a first terminal in circuit with the drain of the first transistor;

a capacitor having a first terminal in circuit with a second terminal of the first switch element and a gate of the first transistor, and a second terminal of the capacitor being in circuit with the ground; and

a second transistor having a source in circuit with the ground;

a third transistor having a source in circuit with the ground, and a gate of the third transistor being in circuit with a gate of the second transistor;

a second switch element having a first in circuit with a drain of the first transistor, and a second terminal of the second switch element being in circuit with the drain of the second transistor, the gate of the second transistor, and the gate of the third transistor; and

a reference current source in circuit with a drain of the third transistor, the measurement of the state of the resistive memory element to be performed at the drain of the third transistor.

13. A circuit as defined in claim 1 2, wherein the first transistor, the first switch element, and the capacitor form a subtraction circuit, and the second transistor, the third transistor, the second switch element, and the reference current source form a sensing circuit.

14. A circuit as defined in claim 1 2, wherein the first transistor operates in a linear operating region when the resistive memory element is measured.

15. A circuit as defined in claim 1 2, wherein the measurement of the state of the resistive memory element is a difference between a reference current from the reference current source and a read current of the memristor cell.