WO2016133518A1 - Enabling advanced error correction control on subset of memory controllers - Google Patents

Enabling advanced error correction control on subset of memory controllers Download PDF

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Publication number
WO2016133518A1
WO2016133518A1 PCT/US2015/016575 US2015016575W WO2016133518A1 WO 2016133518 A1 WO2016133518 A1 WO 2016133518A1 US 2015016575 W US2015016575 W US 2015016575W WO 2016133518 A1 WO2016133518 A1 WO 2016133518A1
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WO
WIPO (PCT)
Prior art keywords
memory
indicators
subset
memory devices
erased
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Application number
PCT/US2015/016575
Other languages
French (fr)
Inventor
David R. SOPER
Subramanian Ramesh
James Tilley
Original Assignee
Hewlett Packard Enterprise Development Lp
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Application filed by Hewlett Packard Enterprise Development Lp filed Critical Hewlett Packard Enterprise Development Lp
Priority to PCT/US2015/016575 priority Critical patent/WO2016133518A1/en
Publication of WO2016133518A1 publication Critical patent/WO2016133518A1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3037—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a memory, e.g. virtual memory, cache

Definitions

  • a memory module may include many memory devices. Error correction logic may be used to correct errors detected in the memory devices.
  • Memory modules may include spare memory devices so that when a memory device malfunctions, a spare memory device may be used instead of the malfunctioning memor device.
  • FIG. 1 is a block diagram of an example system for selectively enabling advanced error correction control on memory controllers
  • FIG. 2 is a block diagram of an example system for retaining error information across system reboots
  • FIG. 3 is a block diagram of an example device that includes a machine-readable storage medium encoded with instructions to enable selective transmission of a signal for advanced error correction control to memory controllers;
  • FIG. 4 is a block diagram of an example device that includes a machine-readable storage medium encoded with instructions to enable erasure of memory devices during boot time;
  • FIG. 5 is a flowchart of an example method for selectively enabling advanced error correction control on memory controllers.
  • FIG, 6 is a flowchart of an example method for using error information during boot time.
  • Large memory systems may implement various mechanisms for resiliency to memory errors. Such mechanisms may involve more memory devices in the storing of data, slowing down the rate at which data may be obtained from the memory devices and decreasing system performance. In addition, such mechanisms are often enabled indiscriminately on all memory controllers in a memory system, even on memor controllers coupled to error-free memory devices, and may not be enabled without a user input. In light of the above, the present disclosure provides for selective and automatic enablement of error correction mechanisms, allowing optimization of both performance and memory resiliency.
  • FIG. 1 is a block diagram of an example system 100 for selectively enabling advanced error correction control on memory controllers.
  • System 100 may be implemented, for example, in an electronic user device (e.g., notebook computer, desktop computer, workstation, tablet computing device, mobile phone, or electronic book reader) or in a server.
  • system 100 includes memory modules 102a « 102b, 102c, 102d, 102e, and 102f; memory controllers 104a, 104b, and 104c; monitoring module 106; and configuration module 108.
  • the terms “include”, “have”, and “comprise” are interchangeable and should be understood to have the same meaning.
  • a module may include a set of instructions encoded on a machine- readable storage medium and executable by a processor, in addition or as an alternative, a module may include a hardware device comprising electronic circuitry for implementing the functionality described videovv.
  • Each of memor modules 102a-f may be an in-line memory module, such as a single in-line memory module ⁇ SIMM ⁇ or a dual in-line memory module (DIMM), or any memory module suitable for mounting memory integrated circuits (ICs).
  • Each of memory controllers 104a-c may control access to and correct errors detected in the memory modules to which it is coupled, and may transmit commands to and send/receive data from such memory modules.
  • Memory controilers 104a-c may foe implemented, for example, in digital circuitry,
  • Each of memory controllers 104a-c may be communicatively coupled to a respective subset of memor modules 102a-f.
  • memory controller 104a may be communicatively coupled to memory modules 102a-b
  • memory controller 104b may be communicatively coupled to memory modules 102c-d
  • memory controller 104c may be communicatively coupled to memory modules 1G2e-f
  • system 100 may include more or fewer memory modules and/or memory controllers than are shown in FIG. 1, that different memory controllers may b communicatively coupled to different numbers of memory modules, and that the concepts described herein may be applicable to systems having any number of memory modules and memory controllers.
  • Monitoring module 108 may track permanent errors detected in memory modules 102a-f.
  • the term "permanent error” should be understood to refer to an error, in a memory location, that cannot be corrected by circuitry that changes the logic state of the memory location.
  • monitoring module 106 may store addresses or parts of addresses of memory locations in which a permanent error has been detected.
  • Configuration module 108 may identify, based on the tracked permanent errors, a subset of memor controllers 104a-c. Each memory controller in the subset may be communicatively coupled to a memory module, of memory modules 102a ⁇ f, on which a permanent error has been detected. For example, permanent errors may be detected in memory modules 102a and 102f, in which case configuration module 108 may identify memory controllers 104a and 104c as the subset of memory controllers.
  • Configuration module 108 may transmit, to the identified subset of memory controllers, a signal to enable an advanced error correction control (AECC) mode.
  • AECC mode as used herein with respect to a memory controller, should be understood to refer to a capability of the memory controller to detect and correct multiple errors on a memory module to which the memory controller is communicatively coupled, tn some implementations, the AECC mode may be double-device data correction (DDDC).
  • DDDC double-device data correction
  • Other examples of AECC modes include, but are not limited to, Chipkill, Extended ECC, and Chipspare.
  • Memory controllers, of memory controllers 10 a-c, that are not in the identified subset do not receive the signal and do not have the AECC mode enabled.
  • the signal to enable an AECC mode may be transmitted to memory controllers 104a and 104c but not to memory controller 104b.
  • memory controllers 104a and 104c may have an AECC mode enabled, and memory controller 104b may not have the AECC mode enabled.
  • FIG. 2 is a block diagram of an example system 200 for retaining error information across system reboots.
  • System 200 may be implemented, for example, in an electronic user device (e.g., notebook computer, desktop computer, workstation, tablet computing device, mobile phone, or electronic book reader) or in a server.
  • system 200 includes memory modules 202a, 202b, 202c, 202d, 202e, and 202f; memory controllers 204a, 204b, and 204c; monitoring module 208; and configuration module 208.
  • a module may include a set of instructions encoded on a machine-readable storage medium and executable by a processor, in addition or as an alternative, a module may include a hardware device comprising electronic circuitr for implementing the functionality described below.
  • Memory modules 2Q2a ⁇ f and memory controllers 204a-c of FIG. 2 may be analogous to (e.g., have functions and/or components similar to) memory modules 102a-f and memory controllers 1G4a-c, respectively, of FIG. 1.
  • each of memory modules 202a-f may include a plurality of memory devices.
  • memory modules 202a-f may include dynamic random-access memory (DRAM) devices and/or memristor memory devices.
  • DRAM dynamic random-access memory
  • Monitoring module 206 may maintain a table 214 of indicators of memory devices in which a permanent error has been detected.
  • table 214 may include a memory device number of, and/or an address segment common to ail memory addresses in, a memory device in which a permanent error has been detected.
  • table 214 may be stored in non-volatile memory (MVfVI) 212.
  • NVM 212 may be, for exampie, a solid-state drive (SSD), hard disk drive (HDD), or memristor memory.
  • Monitoring module 208 may identify, based on the indicators of memory devices in which a permanent error has been detected, a first subset of memor controllers 204a-c, each memory controller in the first subset being communicatively coupled to a memory module, of memory modules 202a-f, on which a permanent error has been detected.
  • monitoring module 208 may transmit to configuration module 208, during boot time after a system reboot, the indicators of memory devices in which a permanent error has been detected.
  • Configuration module 208 may transmit, to the first subset of memory controllers 2Q4a-c, a signal to enable an AECC mode.
  • the AECC mode may be, for example, DDDC, Chipkill, Extended ECC, or Chipspare.
  • Memory controllers, of memory controllers 204a-c, that are not in the first subset do not receive the signal and do not have the AECC mode enabled, as discussed above with respect to FIG, 1 ,
  • configuration module 208 may transmit the signal to the first subset during boot time after a system reboot. Thus, permanent errors may be detected during runtime, and an AECC mode may be enabled on the appropriate memory controllers during the system's next boot time,
  • monitoring moduie 206 may store, in table 214, indicators of memory devices that have been erased, and may transmit to configuration moduie 208, during boot time after a system reboot, the indicators of memory devices that have been erased.
  • An indicator of a memory device that has been erased may include, for example, a memory device number of, and/or an address segment common to all memory addresses in, a memory device that has been erased.
  • the term "erase” or "erasure” should be understood to refer to ignoring and/or correcting data read from the memory device.
  • a memory device ma be erased, for example, when the memory device is known to be defective (e.g., permanent errors have been detected in the memory device).
  • Configuration module 208 may identify, based on the indicators of memory devices that have been erased, a second subset of memory controllers 204a-c, Memory controllers in the second subset may be communicatively coupled to memory modules, of memory modules 2Q2a-f, having memory devices corresponding to the indicators of memory devices that have been erased. Configuration module 208 may instruct the second subset to erase the memory devices corresponding to the indicators of memory devices that have been erased.
  • erasure information may be retained across system reboots, and memory devices erased during runtime may automatically be erased after the next reboot, without expending system resources to rediscover which devices have permanent errors and should be erased, in addition, obtaining erasure information prior to runtime may ai!ow a memory controller to avoid accessing multiple defective memory devices at the same time during runtime.
  • monitoring module 206 may be implemented in management processor 210.
  • Management processor 210 may use an application programming interface (API) to transmit, to configuration moduie 208, tie indicators of memory devices in which a permanent error has been detected and the indicators of memory devices that have been erased. Such indicators may be transmitted, for example, during boot time after a system reboot.
  • API application programming interface
  • monitoring module 208 may delete from table 214, after a service event, the indicators of memory devices in which a permanent error has been detected and the indicators of memory devices that have been erased.
  • a service event may include repairing or replacing memory modules o which a permanent error has been detected.
  • all memor modules may be free of permanent errors, and thus aii entries in table 214 may be deleted and all memory controllers may be set to operate without an AECC mode enabled.
  • FIG. 3 is a block diagram of an example device 300 that includes a machine-readable storage medium encoded with instructions to enable selective transmission of a signai for advanced error correction control to memory controiiers.
  • Device 300 may be implemented, for example, in an electronic user device (e.g., notebook computer, desktop computer, workstation, tablet computing device, mobile phone, or eiectronic book reader) or in a server, in FIG, 3, device 300 includes processor 302 and machine-readable storage medium 304.
  • Processor 302 may include a central processing unit (CPU), microprocessor (e.g., semiconductor-based microprocessor), and/or other hardware device suitable for retrieval and/or execution of instructions stored in machine-readable storage medium 304.
  • processor 302 may fetch, decode, and/ or execute instructions 306 and 308 to enable selective transmission of a signal for advanced error correction control to memory controiiers, as described below.
  • processor 302 may include an electronic circuit comprising a number of electronic components for performing the functionality of instructions 308 and/or 308.
  • Machine-readable storage medium 304 may be any suitable electronic, magnetic, optical , or other physical storage device that contains or stores executable instructions.
  • machine-readable storage medium 304 may include, for example, a random-access memory (RAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), a storage device, an optical disc, and the like, in some implementations, machine-readable storage medium 304 may include a non-transitory storage medium, where the term "non-transitory" does not encompass transitory propagating signals.
  • machine- readable storage medium 30 may be encoded with a set of executable instructions 308 and 308,
  • Instructions 306 may identify, based on indicators of permanent errors detected in a plurality of memory modules, a subset of a plurality of memory controllers.
  • the indicators of permanent errors may inciude, for example, addresses or parts of addresses of memory locations in which a permanent error has been detected.
  • Each of the plurality of memory controllers ⁇ e.g., memory controllers 1G4a ⁇ c or 204a ⁇ c) may be communicatively coupled to a respective subset of the plurality of memory modules.
  • the plurality of memory modules e.g., memory modules 102a-f or 202a-f
  • Each memory controller in the identified subset may be communicatively coupled to a memory module, of the plurality of memor modules, on which a permanent error has been detected,
  • each of the plurality of memor modules may include a plurality of memory devices, and the indicators of permanent errors detected in the plurality of memory modules may include indicators of memory devices in which a permanent error has been detected.
  • An indicator of a memory device in which a permanent error has been detected may include, for example, a memory device number of, and/or an address segment common to all memory addresses in, a memory device in which a permanent error has been detected.
  • the indicators of memory devices in which a permanent error has been detected may be received via an API
  • instructions 308 may transmit, to the identified subset, a signa! to enable an AECC mode.
  • the AECC mode may be, for example, DDDC, Chipkii!, Extended ECC, or Chipspare.
  • Memory controllers, of the plurality of memory controllers, that are not in the identified subset do not receive the signal and do not have the AECC mode enabled, as discussed above with respect to FIG, 1
  • the signai may be transmitted to t e identified subset during boot time after a system reboot.
  • FIG. 4 is a block diagram of an example device 400 that includes a machine-readabie storage medium encoded with instructions to enable erasure of memory devices during boot time.
  • Device 400 may be implemented, for example, in an electronic user device (e.g., notebook computer, desktop computer, workstation, tablet computing device, mobile phone, or electronic book reader) or in a server, in FIG. 4, device 400 includes processor 402 and machine- readabie storage medium 404.
  • processor 402 may include a CPU, microprocessor (e.g., semiconductor-based microprocessor), and/or other hardware device suitable for retrieval and/or execution of instructions stored in machine-readabie storage medium 404.
  • Processor 402 may fetch, decode, and/ or execute instructions 408, 408, 410, 412, 414, and 416 to enable erasure of memory devices during boot time, as described beiow.
  • processor 402 may include an electronic circuit comprising a number of electronic components for performing the functionality of instructions 408, 408, 410, 412, 414, and/or 416.
  • machine-readable storage medium 404 may be any suitable physical storage device that stores executable instaictions.
  • Instructions 406 and 408 on machine-readabie storage medium 404 may be analogous to instructions 306 and 308, respectively, on machine-readabie storage medium 304.
  • instructions 406 may identify, based on indicators of permanent errors detected in a plurality of memory modules, a first subset of a piuraiity of memory controllers, as discussed above with respect to - 0 -
  • Each of the plurality of memory modules may include a plurality of memory devices, and the indicators of permanent errors detected in the plurality of memory modules may include indicators of memory devices in which a permanent error has been detected, instructions 410 may receive, after a system reboot, the indicators of memory devices in which a permanent error has been detected. Such indicators may be received, for example, via an API. In some implementations, the indicators of memory devices in which a permanent error has been detected may be stored in a table, as discussed above with respect to FiG. 2.
  • instructions 412 may receive via an APi, during boot time after a system reboot, indicators of memory devices that have been erased.
  • An indicator of a memory device that has been erased may include, for example, a memory device number of, and/or an address segment common to aSi memor addresses in, a memory devsce that has been erased.
  • the indicators of memory devices that have been erased may be stored in a table, as discussed above with respect to FiG. 2,
  • instructions 414 may identify, based on the indicators of memory devices that have been erased, a second subset of the plurality of memory controllers. Memory controllers in the second subset may be communicatively coupied to memory modules, of the plurality of memory modules, having memory devices corresponding to the indicators of memory devices that have been erased. Instructions 416 may transmit commands to the second subset to erase the memory devices corresponding to the indicators of memory devices that have been erased, as discussed above with respect to FIG. 2,
  • FiG. 5 is a flowchart of an example method 500 for selectively enabling advanced error correction control on memory controllers. Although execution of method 500 is described below with reference to processor 302 of FIG. 3, it should be understood that execution of method 500 may be performed by other suitabl devices, such as processor 402 of FIG. 4. Method 500 may be implemented in the form of executable instructions stored on a machine-readable storage medium and/or in the form of electronic circuitry.
  • Method 500 may start in block 502, where processor 302 may receive indicators of permanent errors detected in a plurality of memory modules, in some implementations, each of the plurality of memory modules may include a plurality of memory devices, and the indicators of permanent errors detected in the plurality of memory modules may include indicators of memory devices in which a permanent error has been detected.
  • processor 302 may identify, based on the indicators of permanent errors detected in the plurality of memory modules, a subset of a plurality of memory controllers.
  • Each of the plurality of memory controllers may be communicatively coupled to a respective subset of the plurality of memory modules.
  • Each memory controller in the identified subset of memor controllers may be communicatively coupled to a memory module, of the plurality of memory modules, on which a permanent error has been detected.
  • processor 302 may transmit, to the identified subset of memory controllers, a signal to enable an AECC mode.
  • the AECC mode may be, for example, DDDC, ChipkiiS, Extended ECC, or Chipspare.
  • the signal may be transmitted to the identified subset of memory controllers during boot time after a system reboot. Thus, permanent errors may be detected during runtime, and an AECC mode may be enabled on the appropriate memor controllers during the system's next boot time,
  • FIG. 6 is a flowchart of an example method 800 for using error information during boot time.
  • execution of method 600 is described below with reference to processor 402 of FIG. 4, it should be understood that execution of method 800 may be performed by other suitable devices, such as processor 302 of FIG, 3. Some blocks of method 600 may be performed in parallel with and/or after method 500.
  • Method 600 may be implemented in the form of executable instructions stored on a machine-readable storage medium and/or in the form of electronic circuitry.
  • Method 800 may start in block 802, where processor 402 may receive, during boot time after a system reboot, indicators of memory devices that have been erased.
  • the memory devices may be among a plurality of memory devices on a plurality of memory modules. Each of a plurality of memory controllers may be communicatively coupled to a respective subset of the plurality of memory modules.
  • processor 402 may determine for each of the plurality of memory controllers, during boot time after the system reboot, and based on the indicators of memory devices that have been erased, whether any memory modules, of the respective subset of the plurality of memory modules communicatively coupled to the respective memory controller, have a memory device corresponding to any of the indicators of memory devices that have been erased. If, in block 804, processor 402 determines that no memory modules have any memory devices corresponding to any of the indicators of memory devices that hav been erased, method 600 may proceed to block 608, where system runtime may commence.
  • method 800 may proceed to block 808, where processor 402 may transmit, during boot time after the system reboot, to memory controllers determined to be communicatively coupled to memory modules having a memory device corresponding to any of the indicators of memory devices that have been erased, commands to erase the memory devices corresponding to the indicators of memory devices that have been erased.
  • processor 402 may transmit, during boot time after the system reboot, to memory controllers determined to be communicatively coupled to memory modules having a memory device corresponding to any of the indicators of memory devices that have been erased, commands to erase the memory devices corresponding to the indicators of memory devices that have been erased.
  • erasure information may be retained across system reboots, and memory devices erased during runtime may automatically be erased after the next reboot.
  • obtaining erasure information prior to runtime may allow a memory controller to avoid accessing multiple defective memory devices at the same time during runtime,
  • An AECC mode may be automatically enabled on memory controllers coupled to defective memory devices, and disabled on memory controllers coupled to error-free memory devices, allowing optimization of both performance and memory resiliency without external user input.

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Abstract

Example implementations relate to selective enablement of advanced error correction control. In example implementations, a first subset of a plurality of memory controllers may be identified based on indicators of permanent errors detected in a plurality of memory modules. Each of the plurality of memory controllers may be communicatively coupled to a respective subset of the plurality of memory modules. Each memory controller in the first subset may be communicatively coupled to a memory module, of the plurality of memory modules, on which a permanent error has been detected. A signal may be transmitted to the first subset to enable an advanced error correction control (AECC) mode. Memory controllers, of the plurality of memory controllers, that are not in the first subset do not receive the signal and do not have the AECC mode enabled.

Description

ENABLING ADVANCED ERRO CORRECTION CONTROL ON SUBSET OF
MEMORY CONTROLLERS
BACKGROUND
[0001] A memory module may include many memory devices. Error correction logic may be used to correct errors detected in the memory devices. Memory modules may include spare memory devices so that when a memory device malfunctions, a spare memory device may be used instead of the malfunctioning memor device.
BR!EF DESCRIPTION OF THE DRAWINGS
[0002] The following detailed description references the drawings, wherein:
[0003] FIG. 1 is a block diagram of an example system for selectively enabling advanced error correction control on memory controllers;
[0004] FIG. 2 is a block diagram of an example system for retaining error information across system reboots;
[0005] FIG. 3 is a block diagram of an example device that includes a machine-readable storage medium encoded with instructions to enable selective transmission of a signal for advanced error correction control to memory controllers;
[0006] FIG. 4 is a block diagram of an example device that includes a machine-readable storage medium encoded with instructions to enable erasure of memory devices during boot time;
[0007] FIG. 5 is a flowchart of an example method for selectively enabling advanced error correction control on memory controllers; and
[0008] FIG, 6 is a flowchart of an example method for using error information during boot time.
DETAILED DESCRIPTION
[0009] Large memory systems may implement various mechanisms for resiliency to memory errors. Such mechanisms may involve more memory devices in the storing of data, slowing down the rate at which data may be obtained from the memory devices and decreasing system performance. In addition, such mechanisms are often enabled indiscriminately on all memory controllers in a memory system, even on memor controllers coupled to error-free memory devices, and may not be enabled without a user input. In light of the above, the present disclosure provides for selective and automatic enablement of error correction mechanisms, allowing optimization of both performance and memory resiliency.
[0010] Referring now to the figures, FIG, 1 is a block diagram of an example system 100 for selectively enabling advanced error correction control on memory controllers. System 100 may be implemented, for example, in an electronic user device (e.g., notebook computer, desktop computer, workstation, tablet computing device, mobile phone, or electronic book reader) or in a server. In FIG. 1 , system 100 includes memory modules 102a« 102b, 102c, 102d, 102e, and 102f; memory controllers 104a, 104b, and 104c; monitoring module 106; and configuration module 108. As used herein, the terms "include", "have", and "comprise" are interchangeable and should be understood to have the same meaning. A module may include a set of instructions encoded on a machine- readable storage medium and executable by a processor, in addition or as an alternative, a module may include a hardware device comprising electronic circuitry for implementing the functionality described beiovv.
[0011] Each of memor modules 102a-f may be an in-line memory module, such as a single in-line memory module {SIMM} or a dual in-line memory module (DIMM), or any memory module suitable for mounting memory integrated circuits (ICs). Each of memory controllers 104a-c may control access to and correct errors detected in the memory modules to which it is coupled, and may transmit commands to and send/receive data from such memory modules. Memory controilers 104a-c may foe implemented, for example, in digital circuitry,
[0012] Each of memory controllers 104a-c may be communicatively coupled to a respective subset of memor modules 102a-f. For example, memory controller 104a may be communicatively coupled to memory modules 102a-b, memory controller 104b may be communicatively coupled to memory modules 102c-d, and memory controller 104c may be communicatively coupled to memory modules 1G2e-f, It should be understood that system 100 may include more or fewer memory modules and/or memory controllers than are shown in FIG. 1, that different memory controllers may b communicatively coupled to different numbers of memory modules, and that the concepts described herein may be applicable to systems having any number of memory modules and memory controllers.
[00 3] Monitoring module 108 may track permanent errors detected in memory modules 102a-f. As used herein, the term "permanent error" should be understood to refer to an error, in a memory location, that cannot be corrected by circuitry that changes the logic state of the memory location. In some implementations, monitoring module 106 may store addresses or parts of addresses of memory locations in which a permanent error has been detected.
[0014] Configuration module 108 may identify, based on the tracked permanent errors, a subset of memor controllers 104a-c. Each memory controller in the subset may be communicatively coupled to a memory module, of memory modules 102a~f, on which a permanent error has been detected. For example, permanent errors may be detected in memory modules 102a and 102f, in which case configuration module 108 may identify memory controllers 104a and 104c as the subset of memory controllers.
[0015] Configuration module 108 may transmit, to the identified subset of memory controllers, a signal to enable an advanced error correction control (AECC) mode. The term "AECC mode", as used herein with respect to a memory controller, should be understood to refer to a capability of the memory controller to detect and correct multiple errors on a memory module to which the memory controller is communicatively coupled, tn some implementations, the AECC mode may be double-device data correction (DDDC). Other examples of AECC modes include, but are not limited to, Chipkill, Extended ECC, and Chipspare.
[0016] Memory controllers, of memory controllers 10 a-c, that are not in the identified subset do not receive the signal and do not have the AECC mode enabled. Continuing with the above exampie, the signal to enable an AECC mode may be transmitted to memory controllers 104a and 104c but not to memory controller 104b. Thus, memory controllers 104a and 104c may have an AECC mode enabled, and memory controller 104b may not have the AECC mode enabled. By selectivel enabling an AECC mode based on where permanent errors have been detected, memory resiliency may be automatically improved where needed, without soliciting user input, and memory unaffected by permanent errors may continue to operate at maximum performance level.
[0017] FIG. 2 is a block diagram of an example system 200 for retaining error information across system reboots. System 200 may be implemented, for example, in an electronic user device (e.g., notebook computer, desktop computer, workstation, tablet computing device, mobile phone, or electronic book reader) or in a server. In FIG. 2, system 200 includes memory modules 202a, 202b, 202c, 202d, 202e, and 202f; memory controllers 204a, 204b, and 204c; monitoring module 208; and configuration module 208. A module may include a set of instructions encoded on a machine-readable storage medium and executable by a processor, in addition or as an alternative, a module may include a hardware device comprising electronic circuitr for implementing the functionality described below.
[0018] Memory modules 2Q2a~f and memory controllers 204a-c of FIG. 2 may be analogous to (e.g., have functions and/or components similar to) memory modules 102a-f and memory controllers 1G4a-c, respectively, of FIG. 1. In some implementations, each of memory modules 202a-f may include a plurality of memory devices. For exampie, memory modules 202a-f may include dynamic random-access memory (DRAM) devices and/or memristor memory devices.
[0019] Monitoring module 206 may maintain a table 214 of indicators of memory devices in which a permanent error has been detected. For example, table 214 may include a memory device number of, and/or an address segment common to ail memory addresses in, a memory device in which a permanent error has been detected. In some impiementations, table 214 may be stored in non-volatile memory (MVfVI) 212. NVM 212 may be, for exampie, a solid-state drive (SSD), hard disk drive (HDD), or memristor memory. Monitoring module 208 ma identify, based on the indicators of memory devices in which a permanent error has been detected, a first subset of memor controllers 204a-c, each memory controller in the first subset being communicatively coupled to a memory module, of memory modules 202a-f, on which a permanent error has been detected. In some implementations, monitoring module 208 may transmit to configuration module 208, during boot time after a system reboot, the indicators of memory devices in which a permanent error has been detected.
[0020] Configuration module 208 may transmit, to the first subset of memory controllers 2Q4a-c, a signal to enable an AECC mode. The AECC mode may be, for example, DDDC, Chipkill, Extended ECC, or Chipspare. Memory controllers, of memory controllers 204a-c, that are not in the first subset do not receive the signal and do not have the AECC mode enabled, as discussed above with respect to FIG, 1 , In some implementations, configuration module 208 may transmit the signal to the first subset during boot time after a system reboot. Thus, permanent errors may be detected during runtime, and an AECC mode may be enabled on the appropriate memory controllers during the system's next boot time,
[0021] In some implementations, monitoring moduie 206 may store, in table 214, indicators of memory devices that have been erased, and may transmit to configuration moduie 208, during boot time after a system reboot, the indicators of memory devices that have been erased. An indicator of a memory device that has been erased may include, for example, a memory device number of, and/or an address segment common to all memory addresses in, a memory device that has been erased. As used herein with respect to a memory device, the term "erase" or "erasure" should be understood to refer to ignoring and/or correcting data read from the memory device. A memory device ma be erased, for example, when the memory device is known to be defective (e.g., permanent errors have been detected in the memory device).
[0022] Configuration module 208 may identify, based on the indicators of memory devices that have been erased, a second subset of memory controllers 204a-c, Memory controllers in the second subset may be communicatively coupled to memory modules, of memory modules 2Q2a-f, having memory devices corresponding to the indicators of memory devices that have been erased. Configuration module 208 may instruct the second subset to erase the memory devices corresponding to the indicators of memory devices that have been erased. Thus, erasure information may be retained across system reboots, and memory devices erased during runtime may automatically be erased after the next reboot, without expending system resources to rediscover which devices have permanent errors and should be erased, in addition, obtaining erasure information prior to runtime may ai!ow a memory controller to avoid accessing multiple defective memory devices at the same time during runtime.
[0023] in some implementations, monitoring module 206 may be implemented in management processor 210. Management processor 210 may use an application programming interface (API) to transmit, to configuration moduie 208, tie indicators of memory devices in which a permanent error has been detected and the indicators of memory devices that have been erased. Such indicators may be transmitted, for example, during boot time after a system reboot.
[0024] in some implementations, monitoring module 208 may delete from table 214, after a service event, the indicators of memory devices in which a permanent error has been detected and the indicators of memory devices that have been erased. A service event may include repairing or replacing memory modules o which a permanent error has been detected. At the beginning of the first runtime after a service event, all memor modules may be free of permanent errors, and thus aii entries in table 214 may be deleted and all memory controllers may be set to operate without an AECC mode enabled.
[0025] FIG. 3 is a block diagram of an example device 300 that includes a machine-readable storage medium encoded with instructions to enable selective transmission of a signai for advanced error correction control to memory controiiers. Device 300 may be implemented, for example, in an electronic user device (e.g., notebook computer, desktop computer, workstation, tablet computing device, mobile phone, or eiectronic book reader) or in a server, in FIG, 3, device 300 includes processor 302 and machine-readable storage medium 304.
[0026] Processor 302 may include a central processing unit (CPU), microprocessor (e.g., semiconductor-based microprocessor), and/or other hardware device suitable for retrieval and/or execution of instructions stored in machine-readable storage medium 304. Processor 302 may fetch, decode, and/ or execute instructions 306 and 308 to enable selective transmission of a signal for advanced error correction control to memory controiiers, as described below. As an alternative or in addition to retrieving and/or executing instructions, processor 302 may include an electronic circuit comprising a number of electronic components for performing the functionality of instructions 308 and/or 308.
[0027] Machine-readable storage medium 304 may be any suitable electronic, magnetic, optical , or other physical storage device that contains or stores executable instructions. Thus, machine-readable storage medium 304 may include, for example, a random-access memory (RAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), a storage device, an optical disc, and the like, in some implementations, machine-readable storage medium 304 may include a non-transitory storage medium, where the term "non-transitory" does not encompass transitory propagating signals. As described in detail below, machine- readable storage medium 30 may be encoded with a set of executable instructions 308 and 308,
[0028] Instructions 306 may identify, based on indicators of permanent errors detected in a plurality of memory modules, a subset of a plurality of memory controllers. The indicators of permanent errors may inciude, for example, addresses or parts of addresses of memory locations in which a permanent error has been detected. Each of the plurality of memory controllers {e.g., memory controllers 1G4a~c or 204a~c) may be communicatively coupled to a respective subset of the plurality of memory modules. The plurality of memory modules (e.g., memory modules 102a-f or 202a-f) may include SIMMs, DIMMs, and/or other memory modules suitable for mounting memory ICs. Each memory controller in the identified subset may be communicatively coupled to a memory module, of the plurality of memor modules, on which a permanent error has been detected,
[0029] In some implementations, each of the plurality of memor modules may include a plurality of memory devices, and the indicators of permanent errors detected in the plurality of memory modules may include indicators of memory devices in which a permanent error has been detected. An indicator of a memory device in which a permanent error has been detected may include, for example, a memory device number of, and/or an address segment common to all memory addresses in, a memory device in which a permanent error has been detected. In some Implementations, the indicators of memory devices in which a permanent error has been detected may be received via an API,
[0030] instructions 308 may transmit, to the identified subset, a signa! to enable an AECC mode. The AECC mode may be, for example, DDDC, Chipkii!, Extended ECC, or Chipspare. Memory controllers, of the plurality of memory controllers, that are not in the identified subset do not receive the signal and do not have the AECC mode enabled, as discussed above with respect to FIG, 1 In some implementations, the signai may be transmitted to t e identified subset during boot time after a system reboot.
[0031] FIG. 4 is a block diagram of an example device 400 that includes a machine-readabie storage medium encoded with instructions to enable erasure of memory devices during boot time. Device 400 may be implemented, for example, in an electronic user device (e.g., notebook computer, desktop computer, workstation, tablet computing device, mobile phone, or electronic book reader) or in a server, in FIG. 4, device 400 includes processor 402 and machine- readabie storage medium 404.
[0032] As with processor 302 of FIG. 3, processor 402 may include a CPU, microprocessor (e.g., semiconductor-based microprocessor), and/or other hardware device suitable for retrieval and/or execution of instructions stored in machine-readabie storage medium 404. Processor 402 may fetch, decode, and/ or execute instructions 408, 408, 410, 412, 414, and 416 to enable erasure of memory devices during boot time, as described beiow. As an alternative or in addition to retrieving and/or executing instructions, processor 402 may include an electronic circuit comprising a number of electronic components for performing the functionality of instructions 408, 408, 410, 412, 414, and/or 416.
[0033] As with machine-readable storage medium 304 of FiG., 3, machine- readable storage medium 404 may be any suitable physical storage device that stores executable instaictions. Instructions 406 and 408 on machine-readabie storage medium 404 may be analogous to instructions 306 and 308, respectively, on machine-readabie storage medium 304. instructions 406 may identify, based on indicators of permanent errors detected in a plurality of memory modules, a first subset of a piuraiity of memory controllers, as discussed above with respect to - 0 -
F!G, 3. Each of the plurality of memory modules may include a plurality of memory devices, and the indicators of permanent errors detected in the plurality of memory modules may include indicators of memory devices in which a permanent error has been detected, instructions 410 may receive, after a system reboot, the indicators of memory devices in which a permanent error has been detected. Such indicators may be received, for example, via an API. In some implementations, the indicators of memory devices in which a permanent error has been detected may be stored in a table, as discussed above with respect to FiG. 2.
[0034] instructions 412 may receive via an APi, during boot time after a system reboot, indicators of memory devices that have been erased. An indicator of a memory device that has been erased may include, for example, a memory device number of, and/or an address segment common to aSi memor addresses in, a memory devsce that has been erased. In some implementations, the indicators of memory devices that have been erased may be stored in a table, as discussed above with respect to FiG. 2,
£0035] instructions 414 may identify, based on the indicators of memory devices that have been erased, a second subset of the plurality of memory controllers. Memory controllers in the second subset may be communicatively coupied to memory modules, of the plurality of memory modules, having memory devices corresponding to the indicators of memory devices that have been erased. Instructions 416 may transmit commands to the second subset to erase the memory devices corresponding to the indicators of memory devices that have been erased, as discussed above with respect to FIG. 2,
[0036] Methods related to adaptive and selective advanced error correction control are discussed with respect to FIGS. 5-6. FiG. 5 is a flowchart of an example method 500 for selectively enabling advanced error correction control on memory controllers. Although execution of method 500 is described below with reference to processor 302 of FIG. 3, it should be understood that execution of method 500 may be performed by other suitabl devices, such as processor 402 of FIG. 4. Method 500 may be implemented in the form of executable instructions stored on a machine-readable storage medium and/or in the form of electronic circuitry. [0037] Method 500 may start in block 502, where processor 302 may receive indicators of permanent errors detected in a plurality of memory modules, in some implementations, each of the plurality of memory modules may include a plurality of memory devices, and the indicators of permanent errors detected in the plurality of memory modules may include indicators of memory devices in which a permanent error has been detected.
[0038] In block 504, processor 302 may identify, based on the indicators of permanent errors detected in the plurality of memory modules, a subset of a plurality of memory controllers. Each of the plurality of memory controllers may be communicatively coupled to a respective subset of the plurality of memory modules. Each memory controller in the identified subset of memor controllers may be communicatively coupled to a memory module, of the plurality of memory modules, on which a permanent error has been detected.
[0039] In block 508, processor 302 may transmit, to the identified subset of memory controllers, a signal to enable an AECC mode. The AECC mode may be, for example, DDDC, ChipkiiS, Extended ECC, or Chipspare. Memory controllers, of the plurality of memory controllers, that ar not In the identified subset of memory controllers do not receive the signal and do not have the AECC mode enabled, as discussed above with respect to FIG. 1. in some implementations, the signal may be transmitted to the identified subset of memory controllers during boot time after a system reboot. Thus, permanent errors may be detected during runtime, and an AECC mode may be enabled on the appropriate memor controllers during the system's next boot time,
[0040] FIG. 6 is a flowchart of an example method 800 for using error information during boot time. Although execution of method 600 is described below with reference to processor 402 of FIG. 4, it should be understood that execution of method 800 may be performed by other suitable devices, such as processor 302 of FIG, 3. Some blocks of method 600 may be performed in parallel with and/or after method 500. Method 600 may be implemented in the form of executable instructions stored on a machine-readable storage medium and/or in the form of electronic circuitry. [0041] Method 800 may start in block 802, where processor 402 may receive, during boot time after a system reboot, indicators of memory devices that have been erased. The memory devices may be among a plurality of memory devices on a plurality of memory modules. Each of a plurality of memory controllers may be communicatively coupled to a respective subset of the plurality of memory modules.
[0042] in block 604, processor 402 may determine for each of the plurality of memory controllers, during boot time after the system reboot, and based on the indicators of memory devices that have been erased, whether any memory modules, of the respective subset of the plurality of memory modules communicatively coupled to the respective memory controller, have a memory device corresponding to any of the indicators of memory devices that have been erased. If, in block 804, processor 402 determines that no memory modules have any memory devices corresponding to any of the indicators of memory devices that hav been erased, method 600 may proceed to block 608, where system runtime may commence.
£0043] If, in block 804, processor 402 determines that some memory modules have some memory devices corresponding to indicators of memory devices that have been erased, method 800 may proceed to block 808, where processor 402 may transmit, during boot time after the system reboot, to memory controllers determined to be communicatively coupled to memory modules having a memory device corresponding to any of the indicators of memory devices that have been erased, commands to erase the memory devices corresponding to the indicators of memory devices that have been erased. Thus, erasure information may be retained across system reboots, and memory devices erased during runtime may automatically be erased after the next reboot. In addition, obtaining erasure information prior to runtime may allow a memory controller to avoid accessing multiple defective memory devices at the same time during runtime,
[0044] The foregoing disclosure describes adaptive and selective advanced error correction control. An AECC mode may be automatically enabled on memory controllers coupled to defective memory devices, and disabled on memory controllers coupled to error-free memory devices, allowing optimization of both performance and memory resiliency without external user input.

Claims

e c|ajm;
1. A system comprising:
a plurality of memory modules;
a piuraiity of memory controllers, wherein each of the piuraiity of memory controllers is communicatively coupled to a respective subset of the plurality of memory modules;
a monitoring module to track permanent errors detected in the plurality of memory modules; and
a configuration module to:
identify, based on the tracked permanent errors, a first subset of the piuraiity of memory controllers, wherein each memory controller in the first subset is communicatively coupled to a memory module, of the piuraiity of memory modules, on which a permanent error has been detected: and
transmit, to the first subset, a signal to enable an advanced error correction control (AECC) mode, wherein memor controllers, of the piuraiity of memory controllers, that are not in the first subset do not receive the signal and do not have the AECC mode enabled.
2. The system of claim 1 , wherein each of the piuraiity of memory modules comprises a piuraiity of memory devices, and wherein the monitoring module is further to maintain a table of indicators of memory devices in which a permanent error has been detected.
3. The system of claim 2, wherein the table is stored in a non-volatile memory,
4. The system of claim 3, wherein:
the monitoring module is further to transmit to the configuration module, during boot time after a system reboot, the indicators of memory devices in which a permanent error has been detected; and
the configuration module is further to transmit the signal to the first subset during boot time after the system reboot.
5. The system of claim 4, wherein:
the monitoring module is further to:
store, in the tafoie, indicators of memory devices that have been erased; and
transmit to the configuration module, during boot time after the system reboot, the indicators of memory devices that have been erased; and the configuration module is further to:
identify, based on the indicators of memory devices that have been erased, a second subset of the piuraiity of memory controiiers, wherein memory controllers in the second subset are communicatively coupled to memory modules, of the piuraiity of memory modules, having memory devices corresponding to the indicators of memory devices that have been erased; and instruct the second subset to erase the memory devices corresponding to the indicators of memory devices that have been erased,
6. The system of claim 5, wherein:
the monitoring module is implemented in a management processor: and
the management processor uses an application programming interface (API) to transmit, to the configuration module, the indicators of memory devices in which a permanent error has been detected and the indicators of memory devices that have been erased.
7. The system of ciaim 5, wherein the monitoring module is further to delete from the table, after a service event, the indicators of memory devices in which a permanent error has been detected and the indicators of memory devices that have been erased.
8. The system of ciaim 1 , wherein the AECC mode is double-device data correction (DDDC).
9. A machine-readable storage medium encoded with instructions executable by a processor, the machine-readable storage medium comprising:
instructions to identify, based on indicators of permanent errors detected in a plurality of memory modules, a first subset of a piurality of memory controllers, wherein each of the plurality of memory controllers is
communicatively coupled to a respective subset of the plurality of memory modules, and wherein each memory controller in the first subset is
communicatively coupled to a memor module, of the piurality of memory modules, on which a permanent error has been detected; and
instructions to transmit, to the first subset, a signal to enable an advanced error correction control (AECC) mode, wherein memory controllers, of the plurality of memory controllers, that are not in the first subset do not receive the signal and do not have the AECC mode enabled.
10. The machine-readable storage medium of claim 9, wherein each of the piurality of memory modules comprises a piurality of memory devices, and wherein the indicators of permanent errors detected in the pluralit of memory modules comprise indicators of memory devices in which a permanent error has been detected, the machine-readable storage medium further comprising:
instructions to receive, via an application programming interface (API), the indicators of memory devices in which a permanent error has been detected; and
instructions to transmit the signal to the first subset during boot time after a system reboot.
11. The machine-readable storage medium of claim 10, further comprising:
instructions to receive via the API, during boot time after the system reboot, indicators of memory devices that have been erased;
instructions to identify, based on the indicators of memory devices that have been erased, a second subset of the plurality of memory controilers, wherein memory controllers in the second subset are communicativeiy coupled to memory modules, of the plurality of memory modules, having memory devices corresponding to the indicators of memory devices that have been erased; and instructions to transmit commands to the second subset to erase the memory devices corresponding to the indicators of memory devices that have been erased.
12. A method comprising:
receiving indicators of permanent errors detected in a plurality of memory modules;
identifying, based on the indicators of permanent errors detected in the plurality of memory modules, a first subset of a plurality of memory controllers, wherein each of the plurality of memory controllers is
communicatively coupled to a respective subset of the plurality of memory modules, and wherein each memory controller in the first subset is
communicatively coupled to a memory module, of the plurality of memory modules, on which a permanent error has been detected; and
transmitting, to the first subset, a signal to enable an advanced error correction control (AECC) mode, wherein memory controllers, of the plurality of memory controllers, that are not in the first subset do not receive the signal and do not have the AECC mode enabled.
13. The method of claim 12, wherein:
each of the plurality of memory modules comprises a plurality of memory devices;
the indicators of permanent errors detected in the plurality of memory modules comprise indicators of memory devices in which a permanent error has been detected; and
the signal is transmitted to the first subset during boot time after a system reboot.
14. The method of claim 13, further comprising: receiving, during boot time after the system reboot, indicators of memory devices that have been erased;
determining for each of the plurality of memory controllers, during boot time after the system reboot, and based on the indicators of memory devices thai have been erased, whether any memory modules, of the respective subset of the plurality of memory modules communicatively coupled to the respecifve memory controller, have a memory device corresponding to any of th indicators of memory devices that have been erased; and
transmitting during boot time after the system reboot, to memory controllers determined to be communicatively coupled to memory modules having a memory devic corresponding to any of the indicators of memory devices that have been erased, commands to erase the memory devices corresponding to the indicators of memory devices that have been erased,
15. The method of claim 14, wherein the indicators of memory devices in which a permanent error has been detected and the indicators of memory devices that have been erased are received via an application programming interface (API).
PCT/US2015/016575 2015-02-19 2015-02-19 Enabling advanced error correction control on subset of memory controllers WO2016133518A1 (en)

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Citations (4)

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Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020016942A1 (en) * 2000-01-26 2002-02-07 Maclaren John M. Hard/soft error detection
US20080022154A1 (en) * 2005-03-24 2008-01-24 Fujitsu Limited Information processing device
US20080301530A1 (en) * 2007-06-01 2008-12-04 Carol Spanel Apparatus and method for distinguishing temporary and permanent errors in memory modules
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