WO2016127422A1

WO2016127422A1 - System, device and method for processing data

Info

Publication number: WO2016127422A1
Application number: PCT/CN2015/073082
Authority: WO
Inventors: 庄良; 梁文亮
Original assignee: 华为技术有限公司
Priority date: 2015-02-15
Filing date: 2015-02-15
Publication date: 2016-08-18
Also published as: CN107111662B; CN107111662A

Abstract

A system, device and method for processing data, which can shorten the FPGA program development cycle and reduce the FPGA program development complexity. The system comprises a general-purpose processor node (110) and a plurality of FPGA nodes (120), wherein the system is provided with a configuration document library, the configuration document library comprising at least one configuration document corresponding to each FPGA node of the plurality of FPGA nodes. Each configuration document corresponding to each FPGA node is used for configuring the FPGA node to realize an algorithm module; the general-purpose processor node is used for determining at least one target configuration document from a plurality of configuration documents included in the configuration document library according to information about at least one target algorithm module, and sending a configuration message to at least one target FPGA node, wherein the configuration message is used for indicating the target configuration document corresponding to the target FPGA node; and the target FPGA node is used for receiving the configuration message sent by the general-purpose processor node, and executing a configuration operation according to the target configuration document indicated in the configuration message.

Description

System, apparatus and method for processing data

Technical field

Embodiments of the present invention relate to the field of data processing and, more particularly, to systems, apparatus, and methods for processing data.

Background technique

With the development of Internet technology and the expanding market demand for high-performance computing, cluster computing is becoming more and more popular. In cluster computing, heterogeneous clusters are the future development trend. At the same time, because Field Programmable Gate Array (FPGA) has irreplaceable acceleration performance for some algorithms, FPGA is used as an accelerator in cluster computing. This has caused more and more attention.

However, the FPGA development process is much more complicated than the general-purpose processor development process. For algorithms of the same complexity, the program development cycle of FPGAs is much longer than the program development cycle of general-purpose processors. The typical FPGA program development process generally includes the following steps: establishing engineering, synthesis, mapping, place and route, and timing analysis. If the design result is correct and the timing analysis results meet the timing constraints, the configuration file can be generated; otherwise, if the design result is not If the correct or timing analysis results do not meet the timing constraints, the next iteration is required until the design requirements are fully met.

In the prior art, each FPGA node is independent of each other, and one FPGA node is responsible for the data plane and control plane of each algorithm module at the same time. As the capacity of FPGAs grows larger and the design becomes more complex, it takes ten minutes for a single compilation time and several hours for a long time. In addition, if you need to adjust the number of a certain algorithm module during the debugging process, you need to re-complete the above steps to generate a new configuration file. For the case of frequent design changes, the FPGA program debugging will cost a lot. time. How to shorten the development cycle of FPGA is a technical problem to be solved in this field.

Summary of the invention

Embodiments of the present invention provide a system, apparatus, and method for processing data, which can shorten the program development cycle of the FPGA and reduce the complexity of FPGA program development.

In a first aspect, an embodiment of the present invention provides a system for processing data, including: a general-purpose processor node and a plurality of field-editable gate array FPGA nodes, wherein the system is provided with a configuration file library, and the configuration file library Include corresponding to each of the plurality of FPGA nodes to One less configuration file, each configuration file corresponding to each FPGA node is configured to configure the FPGA node to implement an algorithm module; the general processor node is configured to include, according to information of at least one target algorithm module, from the configuration file library Determining at least one target configuration file in a plurality of configuration files, wherein the target configuration file is configured to configure a target FPGA module in the plurality of FPGA nodes to implement the target algorithm module; the general purpose processor node is further configured to The target FPGA node sends a configuration message, where the configuration message is used to indicate a target configuration file corresponding to the target FPGA node; the target FPGA node is configured to receive the configuration message sent by the general-purpose processor node, and according to the target indicated in the configuration message Configuration file to perform configuration operations.

In a first possible implementation manner, the configuration file library includes multiple first configuration files corresponding to the first one of the plurality of FPGA nodes, where the plurality of first configuration files include multiple available systems. Each of the algorithm modules corresponds to at least one first configuration file, and the different algorithm modules correspond to different first configuration files.

In combination with the foregoing possible implementation manners, in a second possible implementation manner, the multiple FPGA nodes have different types, where two FPGA nodes of the same type of FPGAs implement the same algorithm module In the same configuration file, two FPGA nodes having different types in the multiple FPGA nodes implement the same algorithm module and correspond to different configuration files.

In combination with the foregoing possible implementation manners, in a third possible implementation manner, the target configuration file includes: algorithm module logic for implementing the target algorithm module; basic information logic for describing the target FPGA node and the target algorithm Module; interface logic for implementing an interface function of the target FPGA node to communicate with the general purpose processor node.

In combination with the foregoing possible implementation manner, in a fourth possible implementation, the basic information logic is used to describe a type of the target FPGA node; the basic information logic is further used to describe a name of the target algorithm module, and the target algorithm module. The number of instantiations and the data processing performance of the target FPGA node when implementing the target algorithm module.

In combination with the foregoing possible implementation manner, in a fifth possible implementation, the information of the at least one target algorithm module includes: a name of the at least one target algorithm module, a target number of the at least one target algorithm module, and the at least one target The target processing time of the algorithm module.

In combination with the foregoing possible implementation manner, in a sixth possible implementation, the general-purpose processor node is specifically configured to: determine at least one corresponding to the at least one target algorithm module from multiple configuration files included in the configuration file library a configuration file; a letter according to the at least one target algorithm module And determining the at least one target configuration file from at least one configuration file corresponding to the at least one target algorithm module.

In combination with the foregoing possible implementation manner, in a seventh possible implementation, the general-purpose processor node is specifically configured to: determine at least one FPGA node that is available from the multiple FPGA nodes; and information according to the at least one target algorithm module And determining, by the plurality of configuration files included in the configuration file library, at least one target FPGA node from the at least one available FPGA node; determining, from the plurality of configuration files included in the configuration file library, the at least one target FPGA node and the The at least one target profile corresponding to the at least one target algorithm module.

In combination with the foregoing possible implementation manner, in an eighth possible implementation, before determining at least one target configuration file from the multiple configuration files included in the configuration file library, the general-purpose processor node is further configured to: input according to user Determining information of a plurality of required algorithm modules including the at least one target algorithm module; determining, by the plurality of required algorithm modules, the implementation by the plurality of FPGA nodes according to the information of the plurality of required algorithm modules The at least one target algorithm module, wherein an algorithm module other than the at least one target module of the plurality of required algorithm modules is implemented by the general purpose processor node.

In combination with the foregoing possible implementation manner, in a ninth possible implementation manner, the general-purpose processor node is further configured to: determine a calling sequence of the at least one target FPGA node; send a call message to the target FPGA node according to the calling sequence The call message is used to indicate that the target FPGA node processes the data to be processed by using the specified target algorithm module; the target FPGA node is further configured to: receive the call message sent by the general processor node, and wait for the call message according to the call message The data is processed for processing and the processing results are sent to the general purpose processor node.

In combination with the foregoing possible implementation manners, in the tenth possible implementation manner, the number of instantiations of the target algorithm module corresponding to the target configuration file is multiple, and the plurality of instantiated the target algorithm modules are in the FPGA node. The call message carries the address information of the target FPGA node, the number information of the specified target algorithm module in the plurality of instantiated target algorithm modules, and the to-be-processed data.

In combination with the foregoing possible implementation manner, in an eleventh possible implementation manner, the general-purpose processor node is further configured to: send mode switching indication information to the first target FPGA node in the at least one target FPGA node, where the mode conversion The indication information is used to indicate that the first target FPGA node enters a power saving mode; or an FPGA node other than the at least one target FPGA node of the plurality of FPGA nodes is added to the at least one target FPGA node.

In combination with the foregoing possible implementation manner, in a twelfth possible implementation, the configuration file library is stored in the general-purpose processor node; or the system further includes: a shared server, where the configuration file library is stored in the shared server The general purpose processor node is further configured to obtain information of the plurality of configuration files included in the configuration file library from the shared server.

In a second aspect, an apparatus for processing data is provided for use in a system for processing data, the system being provided with a configuration file library including each of a plurality of field editable gate array FPGA nodes At least one configuration file corresponding to the FPGA node, each configuration file corresponding to each of the FPGA nodes is configured to configure the FPGA node to implement an algorithm module, and the device includes: a determining unit, configured to use information according to the at least one target algorithm module, Determining at least one target configuration file from a plurality of configuration files included in the configuration file library, wherein the target configuration file is configured to configure a target FPGA module of the plurality of FPGA nodes to implement the target algorithm module; and a sending unit, configured to The at least one target FPGA node determined by the determining unit sends a configuration message, where the configuration message is used to indicate a target configuration file corresponding to the target FPGA node.

In combination with the above possible implementation manner, in a fifth possible implementation manner, the at least one object The information of the target algorithm module includes: a name of the at least one target algorithm module, a target number of the at least one target algorithm module, and a target processing time of the at least one target algorithm module.

In combination with the foregoing possible implementation manner, in a sixth possible implementation, the determining unit is specifically configured to: determine at least one configuration file corresponding to the at least one target algorithm module from multiple configuration files included in the configuration file library And determining, according to the information of the at least one target algorithm module, the at least one target configuration file from at least one configuration file corresponding to the at least one target algorithm module.

In combination with the foregoing possible implementation manner, in a seventh possible implementation, the determining unit is specifically configured to: determine, from the multiple FPGA nodes, at least one FPGA node that is available; according to the information of the at least one target algorithm module and the Configuring a plurality of configuration files included in the file library, determining at least one target FPGA node from the at least one available FPGA node; determining, from the plurality of configuration files included in the configuration file library, the at least one target FPGA node and the at least one The at least one target configuration file corresponding to the target algorithm module.

In combination with the foregoing possible implementation manner, in an eighth possible implementation manner, the determining unit is further configured to: before determining at least one target configuration file from the plurality of configuration files included in the configuration file library, determine, according to user input, Information of a plurality of required algorithm modules including the at least one target algorithm module; determining, according to the information of the plurality of required algorithm modules, the at least one implemented by the plurality of FPGA nodes from the plurality of required algorithm modules a target algorithm module, wherein an algorithm module other than the at least one target module of the plurality of required algorithm modules is implemented by the general purpose processor node.

In combination with the foregoing possible implementation manner, in a ninth possible implementation manner, the determining unit is further configured to determine a calling order of the at least one target FPGA node; the sending unit is further configured to use the calling sequence determined by the determining unit, Sending a call message to the target FPGA node, the call message is used to indicate that the target FPGA node processes the data to be processed by using a specified target algorithm module; the device further includes: a receiving unit, configured to receive the target FPGA node according to the sending unit The data processing result sent by the call message sent.

In combination with the foregoing possible implementation manners, in the tenth possible implementation manner, the number of instantiations of the target algorithm module corresponding to the target configuration file is multiple, and the plurality of instantiated the target algorithm modules are in the FPGA node. The call message includes address information of the target FPGA node, number information of the specified target algorithm module in the plurality of instantiated target algorithm modules, and the to-be-processed data.

In combination with the foregoing possible implementation manner, in an eleventh possible implementation, the sending unit is further configured to send mode switching indication information to the first target FPGA node in the at least one target FPGA node, where the mode switching indication information is used. Instructing the first target FPGA node to enter a power saving mode; or the determining unit is further configured to add an FPGA node other than the at least one target FPGA node to the at least one target FPGA node.

In conjunction with the foregoing possible implementation manner, in a twelfth possible implementation, the method further includes: a storage unit, configured to store the configuration file library.

In a third aspect, there is provided another apparatus for processing data, applied to a system for processing data, the system being provided with a configuration file library comprising each of a plurality of field editable gate array FPGA nodes At least one configuration file corresponding to each FPGA node, each configuration file corresponding to each FPGA node is configured to configure the FPGA node to implement an algorithm module, and the device includes: a receiving unit, configured to receive a call sent by the general processor node a message, the call message is used to indicate that the FPGA node processes the data to be processed by using a target algorithm module, where the FPGA node is configured with a target configuration file for causing the FPGA node to implement the target algorithm module, and a processing unit is configured to The calling message received by the receiving unit processes the data to be processed to obtain a processing result, and the sending unit is configured to send the processing result obtained by the processing unit to the general-purpose processor node.

In a first possible implementation manner, the number of instantiations of the target algorithm module corresponding to the target configuration file is multiple, and the plurality of instantiated target algorithm modules are sequentially numbered in the FPGA node; the call message The address information of the target FPGA node, the number information of the adopted target algorithm module in the plurality of instantiated target algorithm modules, and the to-be-processed data are included.

In conjunction with the foregoing possible implementation manner, in a second possible implementation manner, before receiving the call message sent by the general-purpose processor node, the receiving unit is further configured to receive a configuration message sent by the general-purpose processor node, where the configuration message is The device is configured to: the target configuration file that is allocated by the general-purpose processor node to the FPGA node; the device further includes: an acquiring unit, configured to acquire the target configuration file according to the configuration message received by the receiving unit; The configuration operation is performed according to the target configuration file acquired by the obtaining unit.

In combination with the foregoing possible implementation manner, in a second possible implementation manner, the configuration message carries the target configuration file; the acquiring unit is specifically configured to obtain the target configuration file from the configuration message.

In combination with the above possible implementation manners, in a third possible implementation, the configuration file library And the configuration message carries the indication information for indicating the target configuration file; the obtaining unit is specifically configured to be configured from the general-purpose processor node according to the indication information carried in the configuration message. The target configuration file is obtained in the profile repository.

In combination with the foregoing possible implementation manner, in a fourth possible implementation manner, the target configuration file includes: algorithm module logic, configured to implement the target algorithm module; basic information logic, configured to describe the FPGA node and the target algorithm module Interface logic for implementing the interface function of the FPGA node to communicate with the general purpose processor node.

In combination with the foregoing possible implementation manner, in a fifth possible implementation, the basic information logic is used to describe a type of the FPGA node; the basic information logic is further used to describe a name of the target algorithm module, and the target algorithm module The number of instances and the data processing performance of the FPGA node when implementing the target algorithm module.

In combination with the foregoing possible implementation manner, in a sixth possible implementation, the receiving unit is further configured to receive mode switching indication information sent by the general-purpose processor node, where the mode switching indication information is used to indicate that the FPGA node enters power saving. The configuration unit is further configured to perform a configuration operation of the idle configuration file according to the mode conversion indication information received by the receiving unit, where the idle configuration file is not used to configure the FPGA node to implement any effective algorithm module.

In conjunction with the foregoing possible implementation manners, in a seventh possible implementation, the idle configuration file includes: basic information logic for describing the FPGA node, and interface logic for implementing the FPGA node and the general processor node. Interface function of communication.

In a fourth aspect, a method for processing data is provided for use in a system for processing data, the system being provided with a configuration file library including each of a plurality of field editable gate array FPGA nodes At least one configuration file corresponding to the FPGA node, each configuration file corresponding to each FPGA node is configured to configure the FPGA node to implement an algorithm module, and the method includes: according to information of at least one target algorithm module, from the configuration file library Determining at least one target configuration file among the plurality of configuration files, wherein the target configuration file is configured to configure a target FPGA node of the plurality of FPGA nodes to implement the target algorithm module; and send a configuration message to at least one target FPGA node, The configuration message is used to indicate a target configuration file corresponding to the target FPGA node.

In a first possible implementation manner, the configuration file library includes multiple first configuration files corresponding to the first one of the plurality of FPGA nodes, where the plurality of first configuration files include multiple available systems. At least one first configuration file corresponding to each algorithm module in the algorithm module, And different algorithm modules correspond to different first profiles.

In combination with the foregoing possible implementation manner, in a sixth possible implementation, the determining, according to the information of the at least one target algorithm module, the at least one target configuration file from the multiple configuration files included in the configuration file library, including: Determining, in the plurality of configuration files included in the configuration file library, at least one configuration file corresponding to the at least one target algorithm module; according to the information of the at least one target algorithm module, from at least one configuration file corresponding to the at least one target algorithm module Determine the at least one target profile.

In combination with the foregoing possible implementation manner, in a seventh possible implementation, the determining, according to the information of the at least one target algorithm module, the at least one target configuration file from the multiple configuration files included in the configuration file library, including: Determining at least one FPGA node available among the plurality of FPGA nodes; determining at least one target FPGA node from the available at least one FPGA node according to the information of the at least one target algorithm module and the plurality of configuration files included in the configuration file library; The at least one target configuration file corresponding to the at least one target FPGA node and the at least one target algorithm module is determined from a plurality of configuration files included in the configuration file library.

In combination with the above possible implementation manners, in the eighth possible implementation manner, in the slave configuration Before determining at least one target configuration file among the plurality of configuration files included in the file library, the method further includes: determining, according to the user input, information of the plurality of required algorithm modules including the at least one target algorithm module; Determining, by the information of the required algorithm module, the at least one target algorithm module implemented by the plurality of FPGA nodes from the plurality of required algorithm modules, wherein the plurality of required algorithm modules are other than the at least one target module The algorithm module is implemented by the general purpose processor node.

In conjunction with the foregoing possible implementation manners, in a ninth possible implementation manner, the method further includes: determining a calling order of the at least one target FPGA node; sending, according to the calling sequence, a call message to the target FPGA node, the calling message And is used to indicate that the target FPGA node processes the data to be processed by using a specified target algorithm module; and receives a data processing result sent by the target FPGA node according to the call message.

In combination with the foregoing possible implementation manner, in an eleventh possible implementation manner, the method further includes: sending, to the first target FPGA node of the at least one target FPGA node, mode switching indication information, where the mode switching indication information is used. Instructing the first target FPGA node to enter a power saving mode; or adding an FPGA node other than the at least one target FPGA node among the plurality of FPGA nodes to the at least one target FPGA node.

In a fifth aspect, there is provided another method for processing data, applied to a system for processing data, the system being provided with a configuration file library comprising each of a plurality of field editable gate array FPGA nodes At least one configuration file corresponding to each FPGA node, each configuration file corresponding to each FPGA node is configured to configure the FPGA node to implement an algorithm module, and the method includes: receiving an invocation message sent by a general processor node, the invocation message Instructing the FPGA node to process the data to be processed by using the target algorithm module, wherein the FPGA node is configured with a target configuration file for causing the FPGA node to implement the target algorithm module; and processing the data to be processed according to the call message, Obtaining a processing result; transmitting the processing result to the general purpose processor node.

In a first possible implementation manner, the target profile corresponds to the target algorithm module The number of instantiations is multiple, and the plurality of instantiated target algorithm modules are sequentially numbered in the FPGA node; the call message includes address information of the target FPGA node, and the target algorithm module used in the plurality of instantiations The number information in the target algorithm module and the data to be processed.

In conjunction with the foregoing possible implementation manner, in a second possible implementation manner, before the receiving the initiating message sent by the general-purpose processor node, the method further includes: receiving a configuration message sent by the general-purpose processor node, where the configuration message is used by And indicating the target configuration file allocated by the general-purpose processor node to the FPGA node; acquiring the target configuration file according to the configuration message; and performing a configuration operation of the target configuration file.

In combination with the foregoing possible implementation manner, in a third possible implementation, the configuration message carries the target configuration file, and the acquiring the target configuration file according to the configuration message includes: obtaining the target configuration file from the configuration message. .

In combination with the foregoing possible implementation manner, in a fourth possible implementation, the configuration file library is set on the general-purpose processor node, and the configuration message carries indication information for indicating the target configuration file; The message, the obtaining the target configuration file, includes: obtaining the target configuration file from the configuration file library set by the general processor node according to the indication information carried in the configuration message.

In combination with the foregoing possible implementation manner, in a fifth possible implementation manner, the target configuration file includes: algorithm module logic, configured to implement the target algorithm module; basic information logic, configured to describe the FPGA node and the target algorithm module Interface logic for implementing the interface function of the FPGA node to communicate with the general purpose processor node.

In combination with the foregoing possible implementation manner, in a sixth possible implementation, the basic information logic is used to describe a type of the FPGA node; the basic information logic is further used to describe a name of the target algorithm module, and the target algorithm module The number of instances and the data processing performance of the FPGA node when implementing the target algorithm module.

In combination with the foregoing possible implementation manner, in a seventh possible implementation, the method further includes: receiving mode switching indication information sent by the general processor node, where the mode switching indication information is used to indicate that the FPGA node enters a power saving mode. According to the mode conversion indication information, a configuration operation of the idle configuration file is not performed, and the idle configuration file is not used to configure the FPGA node to implement any effective algorithm module.

In combination with the foregoing possible implementation manner, in an eighth possible implementation manner, the idle configuration file includes: basic information logic, configured to describe the FPGA node; and interface logic, configured to implement the An interface function that the FPGA node communicates with the general purpose processor node.

Based on the foregoing technical solution, a system, apparatus, and method for processing data provided by an embodiment of the present invention, by setting a standard configuration file library, and a general-purpose processor node includes, according to information of at least one target algorithm module, from the configuration file library. Determining at least one target profile in the plurality of profiles, wherein each target profile in the at least one target profile is configured to configure a target FPGA node to implement a target algorithm module, and the general processor node is at least Each target FPGA node in a target FPGA node sends a configuration message, where the configuration message is used to indicate a target configuration file allocated by the general-purpose processor node to the target FPGA node, and the target FPGA node performs a configuration operation according to the configuration message, Virtualizes FPGA node resources and translates the FPGA program development process into a general-purpose processor node program development process, thereby shortening the FPGA program development cycle and reducing the complexity of FPGA program development, improving system performance and user experience.

DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings to be used in the embodiments of the present invention or the description of the prior art will be briefly described below. Obviously, the drawings described below are only the present invention. For some embodiments, other drawings may be obtained from those of ordinary skill in the art without departing from the drawings.

FIG. 1 is a schematic block diagram of a system for processing data according to an embodiment of the present invention.

2 is a configuration example of an algorithm module in a system for processing data according to an embodiment of the present invention.

FIG. 3 is a schematic block diagram of an example of a system for processing data according to an embodiment of the present invention.

FIG. 4 is a schematic block diagram of another example of a system for processing data according to an embodiment of the present invention.

FIG. 5 is a schematic block diagram of an apparatus for processing data according to an embodiment of the present invention.

FIG. 6 is a schematic block diagram of an apparatus for processing data according to another embodiment of the present invention.

FIG. 7 is a schematic block diagram of an apparatus for processing data according to another embodiment of the present invention.

FIG. 8 is a schematic block diagram of an apparatus for processing data according to another embodiment of the present invention.

FIG. 9 is a schematic block diagram of a computing device according to an embodiment of the present invention.

FIG. 10 is a schematic flowchart of a method for processing data according to an embodiment of the present invention.

FIG. 11 is a schematic flowchart of a method for processing data according to another embodiment of the present invention.

detailed description

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are a part of the embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of the present invention.

It should be understood that the technical solutions of the embodiments of the present invention can be applied to various communication systems, such as a Global System of Mobile communication (GSM) system, a Code Division Multiple Access (CDMA) system, and a wideband code. Wideband Code Division Multiple Access (WCDMA) system, General Packet Radio Service (GPRS), Long Term Evolution (LTE) system, LTE Frequency Division Duplex (FDD) System, LTE Time Division Duplex (TDD), Universal Mobile Telecommunication System (UMTS), Worldwide Interoperability for Microwave Access (WiMAX) communication system, and the like.

It should also be understood that the technical solution of the embodiments of the present invention can also be applied to various image processing systems, such as an image processing system, a DNA sequence mapping field, a big data field, and the like.

1 is a schematic block diagram of a system 100 for processing data in accordance with an embodiment of the present invention, which may be any system or device capable of processing data using general purpose processor nodes and FPGA nodes. In the following, the system 100 for processing data is applied to the field of communication as an example. However, the system 100 for processing data can also be applied to other fields, which is not limited by the embodiment of the present invention.

As shown in FIG. 1, the system 100 for processing data includes: a general purpose processor node 110 and a plurality of FPGA nodes 120, wherein

The system 100 is provided with a configuration file library including at least one configuration file corresponding to each of the plurality of FPGA nodes 120, and each configuration file corresponding to each of the FPGA nodes 120 is used to configure the configuration file. The FPGA node 120 implements an algorithm module;

The general purpose processor node 110 is configured to determine at least one target configuration file from the plurality of configuration files included in the configuration file library according to the information of the at least one target algorithm module, where the target configuration file is used to configure the multiple FPGA nodes. Target FPGA node 120 in 120 achieves the target Algorithm module

The general purpose processor node 110 is further configured to send a configuration message to the at least one target FPGA node 120, where the configuration message is used to indicate a target configuration file corresponding to the target FPGA node 120;

The target FPGA node 120 is configured to receive the configuration message sent by the general-purpose processor node 110, and perform a configuration operation according to the target configuration file indicated in the configuration message.

Therefore, a system for processing data according to an embodiment of the present invention, by setting a standard profile library, and a general-purpose processor node determining from a plurality of profiles included in the profile library according to information of at least one target algorithm module At least one target profile, wherein each target profile in the at least one target profile is configured to configure a target FPGA node to implement a target algorithm module, and the general processor node to the at least one target Each target FPGA node in the FPGA node sends a configuration message, where the configuration message is used to indicate a target configuration file allocated by the general-purpose processor node to the target FPGA node, and the target FPGA node performs a configuration operation according to the configuration message, which can enable the FPGA The node resources are virtualized, and the program development flow of the FPGA is converted into the program development flow of the general processor node, thereby shortening the program development cycle of the FPGA and reducing the complexity of the FPGA program development, improving the system performance and the user experience.

In the system 100 for processing data, the general purpose processor node 110 can be directly or indirectly connected to each of the plurality of FPGA nodes 120, for example, the general purpose processor node 110 can communicate with the switch Each of the FPGA nodes 120 is connected. The general purpose processor node 110 can form a cluster of nodes with the plurality of FPGA nodes 120. At this time, the control plane and the data plane of the node cluster may be separated, wherein the general-purpose processor node 110 may implement a control plane of the node cluster for managing and controlling the algorithm modules implemented by the multiple FPGA nodes 120. The FPGA node 120 can implement the data plane of the node cluster for implementing one or more algorithm modules under the control of the general-purpose processor node 110, but the embodiment of the present invention is not limited thereto.

Optionally, the general-purpose processor node may be an x86, an ARM (Acorn RISC machine), a MIPS or a PowerPC, and the like, which is not limited by the embodiment of the present invention.

The system 100 for processing data may be provided with a standard configuration file library, which may include a plurality of configuration files, wherein each of the plurality of configuration files may be used only for configuring one FPGA node. An algorithm module is implemented, and at least one configuration file corresponding to each of the plurality of FPGA nodes may be included in the plurality of configuration files. Specifically, a configuration file corresponding to the FPGA node can be used to configure the FPGA node to implement a The algorithm module is configured to configure the resource of the FPGA node as the algorithm module, so that the FPGA node can implement an algorithm corresponding to the algorithm module. Optionally, the multiple configuration files may be obtained through an existing program development process, for example, by establishing steps of engineering, synthesis, mapping, place and route, and timing analysis, but the embodiment of the present invention is not limited thereto. It should be understood that, in the embodiment of the present invention, after obtaining the configuration file library, the FPGA program development may be implemented by a process similar to the development of a general-purpose processing program. At this time, the algorithm module implemented by the FPGA node may be standardized and reused, and may be used during use. Corresponding to a call function in a general-purpose processor node, it is no longer necessary to perform FPGA program development through the existing process, thereby greatly reducing the complexity of FPGA node program development and improving program development efficiency.

As an optional embodiment, for the same FPGA node, the configuration file library may include a configuration file corresponding to each of the multiple algorithm modules available in the system, and different algorithm modules correspond to different configuration files, where The configuration file corresponding to an algorithm module is used to configure the FPGA node to implement the algorithm module. In addition, for the same FPGA node, each of the plurality of algorithm modules may correspond to at least one configuration file, and the non-configuration file in the at least one configuration file may be used to configure the FPGA node to implement different numbers of the algorithms. Modules, and corresponding to different data processing performance, but embodiments of the invention are not limited thereto.

In an optional embodiment, the configuration file library includes a plurality of first configuration files corresponding to the first one of the plurality of FPGA nodes, wherein the plurality of first configuration files include multiple algorithm modules available to the system. Each of the algorithm modules corresponds to at least one first configuration file, and the different algorithm modules correspond to different first configuration files.

At this time, the plurality of first configuration files may include at least one first configuration file corresponding to the first algorithm module and at least one first configuration file corresponding to the second algorithm module, the first algorithm module being different from the second An algorithm module, and the at least one first configuration file corresponding to the first algorithm module is different from the at least one first configuration file corresponding to the second algorithm module.

As another alternative embodiment, the configuration file in the configuration file library can be used to configure one type of FPGA node, ie, the same type of FPGA node corresponds to the same configuration file for the same algorithm module parameter. At this time, the configuration file library further includes a plurality of second configuration files corresponding to the second FPGA nodes of the plurality of FPGA nodes, wherein the first FPGA node and the second FPGA node have different types and are the same The at least one first configuration file corresponding to the algorithm module is different from the at least one second configuration file.

Correspondingly, the plurality of FPGA nodes have different types, wherein the plurality of FPGA nodes Two FPGA nodes of the same type corresponding to the same configuration file when implementing the same algorithm module, and two FPGA nodes having different types of the plurality of FPGA nodes corresponding to different algorithm files when implementing the same algorithm module.

As another alternative embodiment, a plurality of algorithm modules usable by the system and different types of FPGA nodes included in the plurality of FPGA nodes may be arbitrarily combined, the profile library may include at least corresponding to each combination of all combinations A configuration file. An example of a configuration file library is shown in Table 1, where the type of FPGA node can be determined by the manufacturer and model of the FPGA node. At this time, the three parameters of the type of the FPGA node, the type of the algorithm module, and the number of the instance of the algorithm module may determine a unique configuration file, but the embodiment of the present invention is not limited thereto.

Table 1 Example of a configuration file library

The various algorithms that can be used in the system may be specific to all algorithms of the communication system, all algorithms in the field of image processing, or all algorithms in the field of big data, which are not limited by the embodiments of the present invention.

Optionally, the target configuration file includes:

Algorithm module logic for implementing the target algorithm module;

Basic information logic for describing the target FPGA node and the target algorithm module;

Interface logic for implementing the interface function of the target FPGA node to communicate with the general purpose processor node 110.

The general purpose processor node 110 can communicate with the target FPGA node based on the interface logic, such as data delivery, receiving processing results, and the like. The basic information logic may include information for describing the target FPGA node and the target algorithm module of the target profile configuration, wherein the information of the target FPGA node may include any information capable of indicating the type of the target FPGA node, for example, The manufacturer of the target FPGA node and the model of the target FPGA node, but the embodiment of the present invention is not limited thereto. The information of the target algorithm module may include a name of the target algorithm module, an instance number of the target algorithm module, and the target FPGA node implements the foregoing number The processing performance of the target algorithm module, for example, processing delay, processing precision, and the like, the embodiment of the present invention is not limited thereto.

As an optional embodiment, the basic information logic is used to describe the type of the target FPGA node; the basic information logic is further used to describe the name of the target algorithm module, the number of instantiations of the target algorithm module, and the target FPGA node implementation. Data processing performance when the target algorithm module.

The profile repository can be stored in the general purpose processor node 110. At this point, the general purpose processor node 110 can directly query the stored profile library. Alternatively, the profile repository can be stored on other nodes in the system. For example, the system 100 also includes a shared server and the profile repository is stored in the shared server. At this time, the general-purpose processor node 110 may query the configuration file library stored in the shared server through a communication interface with the shared server, and determine the at least one target configuration file according to the query result.

For example, the general-purpose processor node 110 may send a query message to the shared server, where the query message may carry information of the at least one target algorithm module, for example, identification information of the at least one target algorithm module, or further carry the multiple The mode information of the FPGA node or the information of the FPGA node in the power saving mode among the plurality of FPGA nodes, the embodiment of the present invention is not limited thereto. After receiving the query message, the shared server may determine the at least one target configuration file according to the request message, and send a query response to the general-purpose processor node 110, where the query response carries the at least one target configuration file. Instructions or carry the at least one target profile. At this time, the general-purpose processor node 110 may determine the at least one target configuration file according to the query response, and the embodiment of the present invention is not limited thereto.

As another optional embodiment, after receiving the query message, the sharing server may determine, according to information of the at least one target algorithm module carried in the query message, information about a configuration file corresponding to the at least one target algorithm module. And transmitting, to the general-purpose processor node 110, at least one configuration file corresponding to the at least one target algorithm module, wherein a configuration file corresponding to the at least one target algorithm module may be used to configure the FPGA node to implement the target algorithm module. Correspondingly, the general-purpose processor node 110 may receive the indication information sent by the shared server for indicating at least one configuration file corresponding to the at least one target algorithm module, and determine the at least one target configuration file according to the indication information. Specifically, the general-purpose processor node 110 may be configured according to information of the at least one target algorithm module and a specific criterion, such as speed priority or resource priority, from at least one configuration file corresponding to the at least one target algorithm module indicated by the indication information. Determine the at least one target profile. For example, according to the at least one target algorithm module The target number and the target calculation time determine the at least one target profile, but the embodiment of the present invention is not limited thereto.

In an optional embodiment, the information of the at least one target algorithm module includes: a name of the at least one target algorithm module, a target number of the at least one target algorithm module, and a target processing time of the at least one target algorithm module.

The information of the at least one target algorithm module may also include other performance requirements, for example, target processing precision, and the like, which is not limited by the embodiment of the present invention.

The general purpose processor node 110 may determine, according to information of the at least one target algorithm module, at least one target FPGA node implementing the at least one target algorithm module and a corresponding target configuration file. As an optional embodiment, the determining, by the general-purpose processor node 110, the at least one target configuration file from the plurality of configuration files included in the configuration file library may include:

The general purpose processor node 110 determines at least one configuration file corresponding to the target algorithm module from the plurality of configuration files;

The general purpose processor node 110 determines the target configuration file from at least one configuration file corresponding to the target algorithm module according to the information of the target algorithm module.

The general purpose processor node 110 may first determine at least one configuration file corresponding to the at least one target algorithm module, and determine at least one at least one configuration file corresponding to the at least one target algorithm module according to the information of the at least one target algorithm module. a target configuration file, if the number of the FPGA nodes corresponding to the at least one target configuration file is multiple, the general-purpose processor node 110 may be from a plurality of FPGA nodes corresponding to the at least one target configuration file according to a certain standard. Determining at least one target FPGA node, the standard may be randomly selected, or selecting a corresponding one of a plurality of FPGA nodes in a power saving mode, and the like. If the number of the FPGA nodes corresponding to the at least one target configuration file is one, the general-purpose processor node 110 may determine the FPGA node corresponding to the at least one target configuration file as the target FPGA node, but the embodiment of the present invention is not limited thereto. .

As another alternative embodiment, the general purpose processor node 110 may further determine the at least one target configuration file and the at least one target FPGA node according to the current mode of the plurality of FPGA nodes and the information of the at least one target algorithm module. Accordingly, the general purpose processor node 110 is specifically configured to:

Determining at least one FPGA node available from the plurality of FPGA nodes 120;

Information according to the at least one target algorithm module and multiple configurations included in the profile library a file, determining at least one target FPGA node from the at least one available FPGA node;

The at least one target configuration file corresponding to the at least one target FPGA node and the at least one target algorithm module is determined from a plurality of configuration files included in the configuration file library.

The general purpose processor node 110 can determine a current mode of each of the plurality of FPGA nodes 120. An FPGA node can currently have one of two modes: a power saving mode and a working mode, wherein, in the province The electrical mode FPGA node is not configured with a configuration file or is configured with a configuration file that is not used to implement any valid algorithm module. The FPGA node in the working mode is configured with a configuration file for implementing an effective algorithm module. The general-purpose processor node 110 may determine the FPGA node currently in the power-saving mode among the plurality of FPGA nodes as an available FPGA node, but the embodiment of the present invention is not limited thereto.

The general purpose processor node 110 can determine at least one configuration file corresponding to the available at least one FPGA node and the at least one target algorithm module, and based on the basic information logic in the at least one configuration file and the at least one target algorithm module The performance requirement information determines at least one target FPGA node and a corresponding target configuration file from the at least one available FPGA node, but the embodiment of the present invention is not limited thereto.

For example, the at least one target algorithm module and its target calculation time are specifically: 28 antennas × 14 Fast Fourier Transformation (FFT) modules, the target calculation time is 100 μs; 6 antennas × 13 turbo modules, targets The calculation time is 50 μs. At this time, the general-purpose processor node 110 may determine a plurality of configuration files corresponding to the FFT module included in the configuration file library, and according to the current mode of the multiple FPGA nodes, the multiple configuration files corresponding to the FFT module, and the FFT module. The target number and target calculation time, it is determined that the 28×14 FFT modules are implemented by three FPGA nodes, and a target configuration file for configuring the FPGA node to implement the FFT module is sent to each of the three FPGA nodes. In addition, the general-purpose processor node 110 may determine a plurality of configuration files corresponding to the turbo module included in the configuration file library, and according to the current mode of the multiple FPGA nodes, multiple configuration files corresponding to the turbo module, and the turbo module. The target number and the target calculation time are determined to implement the 6×13 turbo modules by using two FPGA nodes, and a target configuration file for configuring the FPGA node to implement the turbo module is sent to each of the two FPGA nodes.

As another optional embodiment, the at least one target algorithm module may include at least two different types of algorithm modules, and at this time, the general-purpose processor node 110 may determine at least two target FPGA nodes from the plurality of FPGA nodes 120. Where the at least two target FPGA nodes are Each FPGA target node is used to implement one of the at least two different types of algorithm modules. A target FPGA node may be used only to implement multiple target algorithm modules of one type, and different target FPGA nodes may be used to implement the same type or different kinds of target algorithm modules, and embodiments of the present invention are not limited thereto.

The general purpose processor node 110 can also be used to determine information for the at least one target algorithm module prior to determining the at least one target configuration file. As an alternative embodiment, the general purpose processor node 110 can determine information of the at least one target algorithm module based on user input. The user input can be specifically an instruction input by the user or an executable program input by the user to the general purpose processor node, the user input can indicate information of the algorithm module required by at least one user. As an optional embodiment, the algorithm modules required by the at least one user may all be implemented by the FPGA node. In this case, the general-purpose processor node 110 may determine at least one required algorithm module as the at least one target algorithm module. As another embodiment, the number of the at least one required algorithm module is multiple. At this time, the general-purpose processor node 110 may determine a part of the plurality of required algorithm modules as the target algorithm module implemented by the FPGA node. And another portion of the algorithm module is implemented by the general purpose processor node 110.

Correspondingly, before the general-purpose processor node 110 determines at least one target configuration file from the plurality of configuration files included in the configuration file library, the general-purpose processor node 110 is further configured to:

Determining information of a plurality of required algorithm modules including the at least one target algorithm module according to user input;

Determining, by the plurality of required algorithm modules, the at least one target algorithm module implemented by the plurality of FPGA nodes, wherein an algorithm module other than the at least one target module of the plurality of required algorithm modules is processed by the general Node implementation.

At this time, the plurality of required algorithm modules may be composed of the at least one target algorithm module and at least one other algorithm module, wherein the at least one target algorithm module is implemented by the FPGA node 120, and the at least one other algorithm module is configured by a general purpose processor Node 110 is implemented and the other algorithm modules can be of a different kind than the at least one target algorithm module. The general purpose processor node 110 can determine the at least one target algorithm module in a variety of ways. Specifically, the general purpose processor node 110 can determine the at least one target algorithm module using a power consumption minimum principle. For example, in a scenario where the power consumption limitation is high, if the FFT algorithm is implemented in the FPGA, the calculation time is long, but the power consumption of the FPGA node when implementing the FFT algorithm is lower than that of the general-purpose processor, the general-purpose processor node 110 can Determining the FFT algorithm module as a target algorithm module such that the FFT module is at the FPGA node Implemented on. The general purpose processor node 110 can also determine the at least one target algorithm module using a computation time optimal strategy. For example, in a scenario with real-time requirements for computation time, if a general-purpose processor node (eg, an ARM processing node) processes the FFT algorithm module longer than the FPGA, the general-purpose processor node 110 can determine the FFT algorithm module as The at least one target algorithm module is such that the FFT module is implemented on the FPGA node, but the embodiment of the present invention is not limited thereto.

In the example shown in FIG. 2, the plurality of required algorithm modules include one algorithm 1 module, three algorithm 2 modules, one algorithm 3 module, one algorithm 4 module, two algorithm 5 modules, and three algorithms. 6 modules. The general purpose processor node 110 determines that the algorithm 1 module, the algorithm 3 module, and the algorithm 4 module are implemented by the general purpose processor node 110 itself, and the algorithm 2 module, the algorithm 5 module, and the algorithm 6 module are implemented by the FPGA node. Optionally, the algorithm 1-6 may be a Transport Block Cyclic Redundancy Check (TB-CRC) and a Code Block Cyclic Redundancy Check (CB-CRC), respectively. Scrambling or Quantized Amplitude Modulation (QAM), Demodulation Reference Signal (DMRS) or Physical Downlink Shared Channel (PDSCH) or Resource Element Map (Re-Map) BF (Beamforming) / RS (Reference Signal) - Map and Fast Fourier Transformation (FFT), but the embodiment of the present invention is not limited thereto.

The general purpose processor node 110 may send a configuration message to each of the at least one target PFGA node, the configuration message may carry indication information indicating a target configuration file allocated for the target FPGA node, or be carried as The target profile assigned by the target FPGA node. After receiving the configuration message sent by the general-purpose processor node, each target FPGA node may acquire the target configuration file according to the configuration message, and perform a configuration operation for the target configuration file. After the target configuration file is configured, the number of the target algorithm modules instantiated in the target FPGA node is equal to the number of instantiations described in the basic information logic of the target configuration file, and the target FPGA node is in the target FPGA node. The instantiated multiple target algorithm modules are numbered sequentially. In addition, after the target FPGA node is configured with the corresponding target configuration file, the target FPGA node is in the working mode, and the logic resources required by the target FPGA node are used. Wherein, when the data to be processed sent by the general-purpose processor node 110 is not received, the target FPGA node only implements “basic information logic” and “interface logic”, and other logic resources will not be used to reduce the performance of the FPGA node. Consumption, wherein the other logical resources include but are not limited to: Bram, Slice, DSP, DCM, DLL, and the like. As another alternative embodiment, the general processing The node node 110 is also used to:

Determining a calling order of the at least one target FPGA node;

And according to the calling sequence, sending a call message to the at least one target FPGA node, the call message is used to indicate that the target FPGA node processes the data to be processed by using the specified target algorithm module.

Correspondingly, the target FPGA node is further configured to: receive the call message sent by the general-purpose processor node 110, process the processed data according to the call message, and send the processing result to the general-purpose processor node.

The general purpose processor node 110 can determine the calling order of the at least one target FPGA node according to the user input and the target algorithm module respectively implemented by the at least one FPGA node, and invoke the at least one target FPGA node according to the order. When the general purpose processor node 110 invokes a target one of the at least one target FPGA node, the general purpose processor node 110 may send an invocation message to the target FPGA node, the invocation message may be used to indicate the target FPGA node. The data to be processed is processed by using a specified target algorithm module in a plurality of instantiated target algorithm modules.

Optionally, the number of instantiations of the target algorithm module corresponding to the target configuration file is multiple, and the plurality of instantiated target algorithm modules are sequentially numbered in the FPGA node. At this time, the invocation message carries the address information of the target FPGA node, the number information of the specified target algorithm module in the plurality of instantiated target algorithm modules, and the to-be-processed data. The target FPGA node may process the to-be-processed data by using the target algorithm module corresponding to the number information carried in the call message, and return the processing result to the general-purpose processor node 110.

As an optional embodiment, the call message may be implemented in the form of a call function, wherein the call function may have the following form: Func fft (dst IP, src IP, fft module num, data), where fft() Represents a function for calling the fft module, dst IP represents the IP address of the destination node, src IP represents the address of the source node (ie, the general processor node), fft module num represents the number of the calling fft module, and data represents the data to be processed.

In the example shown in FIG. 3, nine FPGA nodes 120 (acceleration cards) are used to implement the FFT module, and each FPGA node is instantiated with multiple FFT modules. Seven FPGA nodes 120 are used to implement turbo modules, and each turbo node can be instantiated with multiple turbo modules. The general purpose processor node 110 can send an invocation message through the switch, which instructs which FPGA node is called and which algorithm module on the FPGA node is invoked, but the embodiment of the present invention is not limited thereto.

As another alternative embodiment, the general purpose processor node 110 is further configured to:

Transmitting mode transition indication information to the first target FPGA node of the at least one target FPGA node, the mode transition indication information is used to indicate that the first target FPGA node enters a power saving mode; or

Adding an FPGA node other than the at least one target FPGA node among the plurality of FPGA nodes to the at least one target FPGA node.

The above described node resource configuration function of the general purpose processor node 110 can be implemented by a resource management module in the general purpose processor node 110. As another alternative embodiment, the general purpose processor node 110 may determine that FPGA node resources need to be released during initialization or during data processing to save FPGA resources. Specifically, when the general purpose processor node determines that the FPGA node resource needs to be released (for example, releasing the first target FPGA node), the general purpose processor node may configure the mode of the first target FPGA node from the working mode to the power saving mode. Or deleting the first target FPGA node from the list of to-be-called FPGA nodes stored in the general-purpose processor node, so that the general-purpose processor node does not invoke the first target FPGA node during current data processing, and A general purpose processor node can assign a new configuration file to the first target FPGA node. At this time, the control module in the general-purpose processor node may send a resource release message to the resource management module, where the resource release message may be implemented in the form of a resource release function delete_FPGA_card (IP_addr), where IP_addr represents the address of the released FPGA node. However, embodiments of the invention are not limited thereto.

As an optional embodiment, in order to further reduce the power consumption of the FPGA node, the general-purpose processor node may send, to the first target FPGA node, mode conversion indication information for indicating that the first target FPGA node enters a power saving mode, When receiving the mode switching indication information, the first target FPGA node may acquire an idle configuration file that is not used to configure the first target FPGA node to implement any valid algorithm module, and perform a configuration operation for the idle configuration file. In this way, the first target FPGA node may be in the power saving mode, but the embodiment of the present invention is not limited thereto.

As another alternative embodiment, the general purpose processor node may also request new FPGA node resources during data processing. At this time, the general purpose processor node may determine the second target FPGA node from the at least one FPGA node in the power saving mode, and add the second target FPGA node to the at least one target FPGA node. Specifically, the general-purpose processor node 110 may determine a configuration file corresponding to the second target FPGA node, and send the corresponding configuration file to the second target FPGA node.

At this time, the control module of the general-purpose processor node 110 may send a resource request message to the resource management module, and the resource request message may be implemented in the form of a resource request function create_FPGA_card (algorithm module name, number of algorithm modules, calculation time). The resource management module may determine the second target FPGA node according to the resource request message, and send a resource request response carrying the information of the second target FPGA node to the control module, but the embodiment of the present invention is not limited thereto.

As another alternative embodiment, the system 100 can include a plurality of general purpose processor nodes and a plurality of FPGA nodes. 4, the system for processing data 100 may include a general-purpose processor nodes M _1, M ₂ th FPGA nodes and switches, M ₁ and M ₂ are integers greater than 1, wherein the M ₁ th each general purpose processor, a general purpose processor node node may communicate with node M ₂ th FPGA FPGA some or all nodes, each node of the FPGA FPGA M ₂ th node M ₁ may be the general purpose processor nodes Some or all of the general purpose processor nodes in the communication. Optionally, the system 100 can communicate by using 10Gigabit Ethernet (10GE) or infiniband network, but the embodiment of the present invention is not limited thereto. Each of the general-purpose processor node M ₁ in the general-purpose processor nodes may be stored in the profile database, which profile database may include a plurality of profiles each FPGA M ₂ th node of the node corresponding to the FPGA, wherein Multiple configuration files corresponding to the same FPGA node may be used to configure a plurality of different algorithm modules available to the FPGA node implementation system, and each configuration file is used to configure the FPGA node to implement an algorithm module, but the present invention The embodiment is not limited to this.

It should be noted that the examples of FIG. 2 to FIG. 4 are intended to assist those skilled in the art to better understand the embodiments of the present invention and are not intended to limit the scope of the embodiments of the present invention. A person skilled in the art will be able to make various modifications and changes in accordance with the examples of FIG. 2 to FIG. 4, and such modifications or variations are also within the scope of the embodiments of the present invention.

Therefore, a system for processing data according to an embodiment of the present invention, by setting a standard profile library, and a general-purpose processor node determining from a plurality of profiles included in the profile library according to information of at least one target algorithm module At least one target profile, wherein each target profile in the at least one target profile is configured to configure a target FPGA node to implement a target algorithm module, and the general purpose processor node to each of the at least one target FPGA node The target FPGA node sends a configuration message indicating the target configuration file corresponding to the target FPGA node, which can virtualize the FPGA node resources, and convert the FPGA program development process into a program development process of the general processor node, thereby shortening the FPGA The program development cycle and reduce the complexity of FPGA program development, improve system performance and user experience.

FIG. 5 is a schematic diagram of an apparatus 200 for processing data according to an embodiment of the present invention. The apparatus 200 is applied to a system for processing data. The system is provided with a configuration file library, and the configuration file library includes multiple sites. At least one configuration file corresponding to each FPGA node in the gate array FPGA node may be edited, and each configuration file corresponding to each FPGA node is used to configure the FPGA node to implement an algorithm module. As shown in FIG. 5, the apparatus 200 includes:

The determining unit 210 is configured to determine, according to the information of the at least one target algorithm module, at least one target configuration file from the plurality of configuration files included in the configuration file library, where the target configuration file is used to configure the plurality of FPGA nodes. The target FPGA node implements the target algorithm module;

The sending unit 220 is configured to send, to the at least one target FPGA node determined by the determining unit 210, a configuration message, where the configuration message is used to indicate a target configuration file corresponding to the target FPGA node.

Therefore, an apparatus for processing data according to an embodiment of the present invention determines at least one target configuration file from a plurality of configuration files included in a configuration file library according to information of at least one target algorithm module, wherein the at least one target configuration file Each target configuration file in the file is configured to configure a target FPGA node to implement a target algorithm module, and the general purpose processor node sends to each of the at least one target FPGA node to indicate that the target FPGA node corresponds to The configuration message of the target profile can virtualize the FPGA node resources and convert the FPGA program development process into the program development flow of the general processor node, thereby shortening the FPGA program development cycle and reducing the complexity of FPGA program development. Improve system performance and user experience.

As an optional embodiment, the configuration file library may include multiple configuration files, wherein each of the multiple configuration files may be used only for configuring one FPGA node to implement an algorithm module, and the multiple At least one configuration file corresponding to each of the plurality of FPGA nodes may be included in the configuration file.

As another optional embodiment, for the same FPGA node, the configuration file library may include a configuration file corresponding to each of the multiple algorithm modules available in the system, and different algorithm modules correspond to different configuration files. The configuration file corresponding to an algorithm module is used to configure an FPGA node to implement the algorithm module. In addition, for the same FPGA node, each of the plurality of algorithm modules may correspond to at least one configuration file, and the non-configuration file in the at least one configuration file may be used to configure the FPGA node to implement different numbers of the algorithms. Modules, and corresponding to different data processing performance, but embodiments of the invention are not limited thereto.

As another optional embodiment, the multiple FPGA nodes have different types, wherein two FPGA nodes of the same type having the same type implement the same algorithm module, corresponding to the same configuration file, the multiple Two FPGA nodes with different types in the FPGA node correspond to different configuration files when implementing the same algorithm module.

The algorithm in the configuration file library may be an algorithm of the communication system, an algorithm in the field of image processing, or an algorithm in the field of big data, which is not limited by the embodiment of the present invention.

Optionally, the target configuration file includes:

Algorithm module logic for implementing the target algorithm module;

Interface logic for implementing an interface function between the target FPGA node and the general purpose processor node.

The profile repository can be stored in the device 200. At this time, the device 200 may further include a storage unit for storing the configuration file library. Accordingly, the determining unit 210 may determine the at least one target configuration file by querying the configuration file library stored by the storage unit. Alternatively, the profile repository can be stored in other nodes, such as a shared server, and the like. At this time, the determining unit 210 may determine the at least one target configuration file by querying the configuration file library stored in the shared server.

For example, the determining unit 210 may include a sending subunit, a receiving subunit, and a determining subunit, where the sending subunit may be configured to send a query message to the shared server, where the query message may carry information of the at least one target algorithm module. For example, the identity of the at least one target algorithm module The information, or further carrying the mode information of the multiple FPGA nodes or the information of the FPGA nodes in the power saving mode among the plurality of FPGA nodes, the embodiment of the present invention is not limited thereto. After receiving the query message, the shared server may determine the at least one target configuration file according to the request message, and send a query response to the device 200, where the query response carries indication information indicating the at least one target configuration file. Or carry the at least one target profile. At this time, the receiving subunit may receive the query response sent by the shared server, and the determining subunit may determine the at least one target configuration file according to the query response received by the receiving subunit, and the embodiment of the present invention is not limited thereto.

As another optional embodiment, after receiving the query message sent by the sending subunit, the sharing server may determine, according to the information of the at least one target algorithm module carried in the query message, the at least one target algorithm module. Corresponding configuration file information, and sending at least one configuration file corresponding to the at least one target algorithm module to the device 200, where the configuration file corresponding to the at least one target algorithm module can be used to configure the FPGA node to implement the target algorithm Module. Correspondingly, the receiving subunit may receive indication information that is sent by the sharing server to indicate at least one configuration file corresponding to the at least one target algorithm module, and the determining subunit may be configured according to the indication information received by the receiving subunit. Determine the at least one target profile. Specifically, the determining subunit may determine, according to the information of the at least one target algorithm module and a specific criterion, such as speed priority or resource priority, from the at least one configuration file corresponding to the at least one target algorithm module indicated by the indication information. At least one target profile. For example, the at least one target profile is determined according to the target number of the at least one target algorithm module and the target calculation time, but the embodiment of the present invention is not limited thereto.

Optionally, the information of the at least one target algorithm module includes: a name of the at least one target algorithm module, a target number of the at least one target algorithm module, and a target processing time of the at least one target algorithm module.

As an optional embodiment, the determining unit 210 is specifically configured to:

Determining at least one configuration file corresponding to the at least one target algorithm module from a plurality of configuration files included in the configuration file library;

Determining the at least one target configuration file from the at least one configuration file corresponding to the at least one target algorithm module according to the information of the at least one target algorithm module.

As an optional embodiment, the determining unit 210 may determine at least one target configuration file corresponding to the at least one target algorithm module according to the current mode of the multiple FPGA nodes. At this time, the determining unit 210 is specifically configured to:

Determining at least one FPGA node available from the plurality of FPGA nodes;

Determining at least one target FPGA node from the available at least one FPGA node according to the information of the at least one target algorithm module and the plurality of configuration files included in the configuration file library;

As another optional embodiment, the at least one target algorithm module may include at least two different types of algorithm modules. In this case, the determining unit 210 may determine at least two target FPGA nodes from the plurality of FPGA nodes, where Each of the at least two target FPGA nodes is configured to implement one of the at least two different types of algorithm modules. A target FPGA node may be used only to implement multiple target algorithm modules of one type, and different target FPGA nodes may be used to implement the same type or different kinds of target algorithm modules, and embodiments of the present invention are not limited thereto.

As another optional embodiment, the determining unit 210 is further configured to:

Determining information of a plurality of required algorithm modules including the at least one target algorithm module according to user input before determining at least one target profile from the plurality of profiles included in the profile library;

Determining, by the information of the plurality of required algorithm modules, the at least one target algorithm module implemented by the plurality of FPGA nodes from the plurality of required algorithm modules, wherein the at least one of the plurality of required algorithm modules Algorithm modules outside the target module are implemented by the general purpose processor node.

The determining unit 210 can determine the at least one target algorithm module in a plurality of manners. Specifically, the determining unit 210 may determine the at least one target algorithm module by using a power consumption minimum principle. For example, in a scenario where the power consumption limitation is high, if the FFT algorithm is implemented in the FPGA, the calculation time is long, but the power consumption of the FPGA node when implementing the FFT algorithm is lower than that of the general-purpose processor, the determining unit 210 may perform the FFT. The algorithm module is determined to be a target algorithm module such that the FFT module is implemented on the FPGA node. The determining unit 210 may also determine the at least one target algorithm module by using a calculation time optimal strategy. For example, in a scenario where the computing time has real-time requirements, if the general processor node (eg, ARM) processes the FFT algorithm module longer than the FPGA, the determining unit 210 may determine the FFT algorithm module as the at least one target. Algorithm module to make The FFT module is implemented on the FPGA node, but the embodiment of the present invention is not limited thereto.

As another alternative embodiment, the apparatus 200 can also determine the calling order of the at least one target FPGA node and invoke the at least one target FPGA node in accordance with the order. At this time, the determining unit 210 is further configured to determine a calling order of the at least one target FPGA node;

The sending unit 220 is further configured to send, according to the calling sequence determined by the determining unit 210, a call message to the target FPGA node, where the call message is used to instruct the target FPGA node to process the data to be processed by using the specified target algorithm module.

Correspondingly, the apparatus 200 further includes: a receiving unit, configured to receive a data processing result sent by the target FPGA node according to the call message sent by the sending unit 220.

As an optional embodiment, the number of instantiations of the target algorithm module corresponding to the target configuration file is multiple, and the plurality of instantiated target algorithm modules are sequentially numbered in the FPGA node;

The call message includes address information of the target FPGA node, number information of the specified target algorithm module in the plurality of instantiated target algorithm modules, and the to-be-processed data.

The call message can be implemented by calling the function Func fft(dst IP, src IP, fft module num, data), where fft() represents a function for calling the fft module, dst IP represents the IP address of the destination node, src IP Indicates the address of the source node (ie, the general-purpose processor node), the fft module num indicates the number of the called fft module, and the data indicates the data to be processed, but the embodiment of the present invention is not limited thereto.

As another optional embodiment, the sending unit 220 is further configured to send, to the first target FPGA node of the at least one target FPGA node, mode switching indication information, where the mode switching indication information is used to indicate that the first target FPGA node enters Power saving mode; or

The determining unit 210 is further configured to add an FPGA node other than the at least one target FPGA node to the at least one target FPGA node.

The apparatus 200 provided by the embodiments of the present invention may correspond to the general-purpose processor node 110 in a system for processing data according to an embodiment of the present invention, and the above and other operations of the respective modules in the apparatus 200 may be used to implement a general-purpose processor. The function of the node 110 is not described here for brevity.

Therefore, an apparatus for processing data according to an embodiment of the present invention determines at least one target configuration file from a plurality of configuration files included in a configuration file library according to information of at least one target algorithm module, wherein the at least one target configuration file Each target configuration file in the file is configured to configure a target FPGA node to implement a target algorithm module, and the general purpose processor node sends to each of the at least one target FPGA node to indicate the target FPGA section The configuration message of the target configuration file corresponding to the point can virtualize the FPGA node resources and convert the program development flow of the FPGA into the program development process of the general processor node, thereby shortening the program development cycle of the FPGA and reducing the complexity of the FPGA program development. Degrees to improve system performance and user experience.

FIG. 6 shows an apparatus 300 for processing data provided by another embodiment of the present invention. The apparatus 300 is applied to a system for processing data, the system being provided with a configuration file library including at least one configuration file corresponding to each of the plurality of field editable gate array FPGA nodes, each of the Each configuration file corresponding to the FPGA node is used to configure the FPGA node to implement an algorithm module. As shown in FIG. 6, the apparatus 300 includes:

The receiving unit 310 is configured to receive a call message sent by the general-purpose processor node, where the call message is used to instruct the FPGA node to process the data to be processed by using the target algorithm module, where the FPGA node is configured to enable the FPGA node to achieve the target The target configuration file of the algorithm module;

The processing unit 320 is configured to process the to-be-processed data according to the call message received by the receiving unit 310 to obtain a processing result.

The sending unit 330 is configured to send the processing result obtained by the processing unit 320 to the general-purpose processor node.

Therefore, an apparatus for processing data according to an embodiment of the present invention configures a target configuration file included in a standard configuration file library for configuring an FPGA node to implement a function of a target algorithm module, and the FPGA node is based on a general purpose The call message sent by the processor node performs data processing and sends the processing result to the general-purpose processor node, which can virtualize the FPGA node resource and convert the program development flow of the FPGA into the program development process of the general-purpose processor node, thereby shortening FPGA program development cycle and reduce the complexity of FPGA program development, improve system performance and user experience.

The FPGA node is configured with a target configuration file for causing the FPGA node to implement a target algorithm module. Specifically, a plurality of target algorithm modules having the same type may be instantiated in the FPGA node, wherein the plurality of the target algorithm modules of the instantiation are sequentially numbered.

The call message includes address information of the target FPGA node, number information of the target algorithm module in the plurality of instantiated target algorithm modules, and the to-be-processed data.

Optionally, as another embodiment, before receiving the call message sent by the general-purpose processor node, the receiving unit 310 is further configured to receive a configuration message sent by the general-purpose processor node, where the configuration message is used to indicate the general-purpose processor. The target profile assigned by the node to the FPGA node. Accordingly, the apparatus 300 further includes:

An obtaining unit, configured to acquire the target configuration file according to the configuration message received by the receiving unit 310;

And a configuration unit, configured to perform a configuration operation according to the target configuration file acquired by the acquiring unit.

As an optional embodiment, the configuration message carries the target configuration file. At this time, the obtaining unit is specifically configured to obtain the target configuration file from the configuration message.

As another alternative embodiment, the profile repository is located on the general purpose processor node and the configuration message carries indication information indicating the target profile. At this time, the obtaining unit is specifically configured to obtain the target configuration file from the configuration file library set by the general-purpose processor node according to the indication information carried in the configuration message.

Optionally, as another embodiment, the target configuration file includes:

Algorithm module logic for implementing the target algorithm module;

Basic information logic for describing the FPGA node and the target algorithm module;

Interface logic for implementing an interface function of the FPGA node to communicate with the general purpose processor node.

Optionally, as another embodiment, the basic information logic is used to describe a type of the FPGA node; the basic information logic is further used to describe a name of the target algorithm module, an instantiation quantity of the target algorithm module, and the FPGA node. Data processing performance when implementing the target algorithm module.

Optionally, in another embodiment, the receiving unit 310 is further configured to receive the mode switching indication information sent by the general-purpose processor node, where the mode switching indication information is used to indicate that the FPGA node enters a power saving mode;

The configuration unit is further configured to perform a configuration operation of the idle configuration file according to the mode conversion indication information received by the receiving unit, where the idle configuration file is not used to configure the FPGA node to implement any effective algorithm module.

As an optional embodiment, the idle configuration file includes:

Basic information logic for describing the FPGA node;

The apparatus 300 provided by the embodiments of the present invention may correspond to the target FPGA node 120 in the system for processing data according to an embodiment of the present invention, and the above and other operations of the respective modules in the apparatus 300 may be used to implement the target FPGA node 120. The function, for the sake of brevity, will not be repeated here.

FIG. 7 is a schematic diagram of an apparatus 400 for processing data according to an embodiment of the present invention. The apparatus 400 is applied to a system for processing data, and the system is provided with a configuration file library, and the configuration file library includes a plurality of sites. At least one configuration file corresponding to each FPGA node in the gate array FPGA node may be edited, and each configuration file corresponding to each FPGA node is used to configure the FPGA node to implement an algorithm module. As shown in FIG. 7, the apparatus 400 includes:

The processor 410 is configured to determine, according to the information of the at least one target algorithm module, at least one target configuration file from the plurality of configuration files included in the configuration file library, where the target configuration file is used to configure the plurality of FPGA nodes. The target FPGA node implements the target algorithm module;

The transmitter 420 is configured to send, to the at least one target FPGA node determined by the processor 410, a configuration message, where the configuration message is used to indicate a target configuration file corresponding to the target FPGA node.

It should be understood that, in the embodiment of the present invention, the processor 410 may be a central processing unit ("CPU"), and the processor 410 may also be other general-purpose processors. Digital signal processor (DSP), application specific integrated circuit (ASIC) or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, etc. The general purpose processor may be a microprocessor or the processor or any conventional processor or the like.

The apparatus 400 for processing data may also include a memory, which may include read only memory and random access memory, and provides instructions and data to the processor 410. A portion of the memory may also include a non-volatile random access memory. For example, the memory can also store information of the device type.

In the implementation process, each step of the foregoing method may be completed by an integrated logic circuit of hardware in the processor 410 or an instruction in a form of software. The steps of the method disclosed in the embodiments of the present invention may be directly implemented as a hardware processor, or may be performed by a combination of hardware and software modules in the processor. The software module can be located in a conventional storage medium such as random access memory, flash memory, read only memory, programmable read only memory or electrically erasable programmable memory, registers, and the like. The storage medium is located in the memory, and the processor 410 reads the information in the memory and completes the steps of the above method in combination with the hardware thereof. To avoid repetition, it will not be described in detail here.

The configuration file library may include a plurality of configuration files, wherein each of the plurality of configuration files may be used only for configuring one FPGA node to implement an algorithm module, and the plurality of configuration files may include At least one configuration file corresponding to each of the plurality of FPGA nodes.

At this time, the plurality of first configuration files may include at least one first configuration file corresponding to the first algorithm module and at least one first configuration file corresponding to the second algorithm module, the first algorithm mode The block is different from the second algorithm module, and the at least one first configuration file corresponding to the first algorithm module is different from the at least one first configuration file corresponding to the second algorithm module.

Optionally, the target configuration file includes:

Algorithm module logic for implementing the target algorithm module;

The profile repository can be stored in the device 400. At this time, the apparatus 400 may further include a memory for storing the configuration file library, and correspondingly, the processor 410 may determine the at least one target configuration file by querying the configuration file library stored in the memory. Alternatively, the profile repository can be stored in other nodes, such as a shared server, and the like. At this time, the processor 410 may determine the at least one target configuration file by querying the configuration file library stored in the shared server.

As an optional embodiment, the processor 410 is specifically configured to:

And from the at least one target algorithm module according to the information of the at least one target algorithm module The at least one target profile is determined in at least one of the configuration files.

As an optional embodiment, the processor 410 may determine at least one target configuration file corresponding to the at least one target algorithm module according to the current mode of the plurality of FPGA nodes. At this time, the processor 410 is specifically configured to:

Determining at least one FPGA node available from the plurality of FPGA nodes;

As another optional embodiment, the at least one target algorithm module may include at least two different types of algorithm modules. In this case, the processor 410 may determine at least two target FPGA nodes from the plurality of FPGA nodes, where Each of the at least two target FPGA nodes is configured to implement one of the at least two different types of algorithm modules. A target FPGA node may be used only to implement multiple target algorithm modules of one type, and different target FPGA nodes may be used to implement the same type or different kinds of target algorithm modules, and embodiments of the present invention are not limited thereto.

As another alternative embodiment, the processor 410 is further configured to:

The processor 410 can determine the at least one target algorithm module in a variety of ways. Specifically, the processor 410 may determine the at least one target algorithm module by using a power consumption minimum principle. For example, in a scenario where the power consumption limitation is high, if the FFT algorithm is implemented in the FPGA, the calculation time is long, but the power consumption of the FPGA node when implementing the FFT algorithm is lower than that of the general-purpose processor, the processor 410 can perform the FFT. The algorithm module is determined to be a target algorithm module such that the FFT module is implemented on the FPGA node. The processor 410 can also determine the at least one target algorithm module using a computation time optimal strategy. For example, in a scenario where the computation time has real-time requirements, if a general-purpose processor node (such as an ARM processing node) processes the FFT algorithm module longer than the FPGA, then the location The processor 410 may determine the FFT algorithm module as the at least one target algorithm module, so that the FFT module is implemented on the FPGA node, but the embodiment of the present invention is not limited thereto.

As another alternative embodiment, the processor 410 can also determine the calling order of the at least one target FPGA node and invoke the at least one target FPGA node in accordance with the order. At this time, the processor 410 is further configured to determine a calling order of the at least one target FPGA node;

The transmitter 420 is further configured to send, according to the calling sequence determined by the processor 410, a call message to the target FPGA node, where the call message is used to indicate that the target FPGA node processes the data to be processed by using a specified target algorithm module.

Correspondingly, the apparatus 400 further includes: a receiver, configured to receive a data processing result sent by the target FPGA node according to the call message sent by the transmitter 420.

As another optional embodiment, the transmitter 420 is further configured to send mode transition indication information to the first target FPGA node of the at least one target FPGA node, where the mode transition indication information is used to indicate that the first target FPGA node enters Power saving mode; or

The processor 410 is further configured to add an FPGA node other than the at least one target FPGA node among the plurality of FPGA nodes to the at least one target FPGA node.

The apparatus 400 provided by the embodiments of the present invention may correspond to the general-purpose processor node 110 in a system for processing data according to an embodiment of the present invention, and the above and other operations of the respective modules in the apparatus 400 may be used to implement a general-purpose processor. The function of the node 110 is not described here for brevity.

Therefore, an apparatus for processing data according to an embodiment of the present invention determines at least one target configuration file from a plurality of configuration files included in a configuration file library according to information of at least one target algorithm module, wherein the at least one target configuration file Each target profile in the file is used to configure a target FPGA node to implement a target algorithm module, and the general processor node is at least Each target FPGA node in a target FPGA node sends a configuration message indicating a target profile corresponding to the target FPGA node, which can virtualize the FPGA node resources and convert the FPGA program development process into a general-purpose processor node. Program development process to shorten the FPGA development cycle and reduce the complexity of FPGA program development, improve system performance and user experience.

FIG. 8 illustrates an apparatus 500 for processing data provided by another embodiment of the present invention. The apparatus 500 is applied to a system for processing data, the system being provided with a configuration file library including at least one configuration file corresponding to each of the plurality of field editable gate array FPGA nodes, each of the Each configuration file corresponding to the FPGA node is used to configure the FPGA node to implement an algorithm module. As shown in FIG. 8, the apparatus 500 includes:

The receiver 510 is configured to receive a call message sent by the general-purpose processor node, where the call message is used to instruct the FPGA node to process the data to be processed by using the target algorithm module, where the FPGA node is configured to enable the FPGA node to achieve the target The target configuration file of the algorithm module;

The processor 520 is configured to process the to-be-processed data according to the call message received by the receiver 510 to obtain a processing result.

The transmitter 530 is configured to send the processing result obtained by the processor 520 to the general-purpose processor node.

It should be understood that in the embodiment of the present invention, the processor 520 may be an FPGA. The apparatus 500 for processing data can also include a memory, which can include read only memory and random access memory, and provides instructions and data to the processor 520. A portion of the memory may also include a non-volatile random access memory. For example, the memory can also store information of the device type.

In the implementation process, each step of the foregoing method may be completed by an integrated logic circuit of hardware in the processor 520 or an instruction in a form of software. The steps of the method disclosed in connection with the embodiments of the present invention It can be directly implemented as a hardware processor or completed by a combination of hardware and software modules in the processor. The software module can be located in a conventional storage medium such as random access memory, flash memory, read only memory, programmable read only memory or electrically erasable programmable memory, registers, and the like. The storage medium is located in the memory, and the processor 520 reads the information in the memory and completes the steps of the above method in combination with the hardware thereof. To avoid repetition, it will not be described in detail here.

Optionally, as another embodiment, before receiving the call message sent by the general-purpose processor node, the receiver 510 is further configured to receive a configuration message sent by the general-purpose processor node, where the configuration message is used to indicate the general-purpose processor. The target profile assigned by the node to the FPGA node. Correspondingly, the processor 520 is configured to acquire the target configuration file according to the indication information received by the receiver 510, and perform a configuration operation according to the target configuration file.

As an optional embodiment, the configuration message carries the target configuration file. At this time, the processor 520 is specifically configured to obtain the target configuration file from the configuration message.

As another alternative embodiment, the profile repository is located on the general purpose processor node and the configuration message carries indication information indicating the target profile. At this time, the processor 520 is specifically configured to obtain the target configuration file from the configuration file library set by the general processor node according to the configuration message.

Optionally, as another embodiment, the target configuration file includes:

Algorithm module logic for implementing the target algorithm module;

Optionally, in another embodiment, the receiver 510 is further configured to receive mode conversion indication information sent by the general-purpose processor node, where the mode conversion indication information is used to indicate that the FPGA node enters a power-saving mode;

As an optional embodiment, the idle configuration file includes:

Basic information logic for describing the FPGA node;

Apparatus 500 provided by an embodiment of the present invention may correspond to target FPGA node 120 in a system for processing data according to an embodiment of the present invention, and the above and other operations of respective modules in apparatus 500 may be used to implement target FPGA node 120. The function, for the sake of brevity, will not be repeated here.

FIG. 9 shows a computing device 600 according to an embodiment of the present invention. The computing device 600 includes:

Processor 602, memory 604, input/output interface 606, communication interface 608, and bus 610. Among them, the processor 602, the memory 604, the input/output interface 606, and the communication interface 608 implement a communication connection with each other through the bus 610.

The processor 602 may be a general-purpose CPU, a microprocessor or an FPGA, an application specific integrated circuit (ASIC) or one or more integrated circuits for executing related programs to implement the embodiments of the present invention. Technical solutions.

The memory 604 may be a read only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). Memory 604 can store operating systems and other applications. Implemented by software or firmware In the technical solution provided by the embodiment of the present invention, the program code for implementing the technical solution provided by the embodiment of the present invention is saved in the memory 604 and executed by the processor 602.

The input/output interface 606 is for receiving input data and information, and outputting data such as operation results.

Communication interface 608 enables communication between computing device 600 and other devices or communication networks using transceivers such as, but not limited to, transceivers.

Bus 610 can include a path for communicating information between various components of computing device 600, such as processor 602, memory 604, input/output interface 606, and communication interface 608.

In particular, the memory 604 can be used to store executable instructions, as well as to store various information, such as a configuration file library. The processor 602 can read the information stored by the memory 604 via the bus system 610 or store the results of the query to the memory 604. In addition, when the computing device 600 is running, the processor 602 can execute the executable instructions stored in the memory 604 to perform the various processes in the foregoing method embodiments, but the embodiments of the present invention are not limited thereto.

A system for processing data by a user and a general-purpose processor node according to an embodiment of the present invention are described in detail above with reference to FIGS. 1 through 9, and a method for processing data according to an embodiment of the present invention will be described below with reference to FIGS. 10 and 11. method.

FIG. 10 is a schematic diagram of a method 700 for processing data provided by an embodiment of the present invention. The method 700 can be applied to a system for processing data, the system being provided with a configuration file library including at least one configuration file corresponding to each of the plurality of field editable gate array FPGA nodes, each Each configuration file corresponding to the FPGA node is used to configure the FPGA node to implement an algorithm module. As shown in FIG. 10, the method 700 includes:

S710. Determine, according to information of the at least one target algorithm module, at least one target configuration file from multiple configuration files included in the configuration file library, where the target configuration file is used to configure a target FPGA node in the multiple FPGA nodes. The target algorithm module;

S720. Send a configuration message to the at least one target FPGA node, where the configuration message is used to indicate a target configuration file corresponding to the target FPGA node.

Therefore, a method for processing data according to an embodiment of the present invention determines at least one target configuration file from a plurality of configuration files included in a configuration file library according to information of at least one target algorithm module, wherein the at least one target configuration Each target configuration file in the file is configured to configure a target FPGA node to implement a target algorithm module, and the general purpose processor node sends to each of the at least one target FPGA node to indicate that the target FPGA node corresponds to Configuration message of the target profile, which enables virtualization of the FPGA node resources, and The FPGA development process is converted to a general-purpose processor node program development process, thereby shortening the FPGA program development cycle and reducing the complexity of FPGA program development, improving system performance and user experience.

As another alternative embodiment, the target configuration file includes:

Algorithm module logic for implementing the target algorithm module;

Optionally, the basic information logic is used to describe a type of the target FPGA node; the basic information logic is further used to describe a name of the target algorithm module, an instantiation quantity of the target algorithm module, and the target FPGA node implements the target algorithm. Data processing performance at the time of module.

As another optional embodiment, S710, determining, according to the information of the at least one target algorithm module, the at least one target configuration file from the multiple configuration files included in the configuration file library, including:

Determining at least one FPGA node available from the plurality of FPGA nodes;

As another alternative embodiment, before S710, the method 700 further includes:

As another alternative embodiment, the method 700 further includes:

Determining a calling order of the at least one target FPGA node;

And sending, according to the calling sequence, a call message to the target FPGA node, where the call message is used to indicate that the target FPGA node processes the data to be processed by using a specified target algorithm module;

Receiving a data processing result sent by the target FPGA node according to the call message.

As another optional embodiment, the number of instantiations of the target algorithm module corresponding to the target configuration file is multiple, and the plurality of instantiated target algorithm modules are sequentially numbered in the FPGA node;

As another alternative embodiment, the method 700 further includes:

The method 700 for processing data in accordance with an embodiment of the present invention may be implemented by a general purpose processor node 110, a device 200 for processing data, or a device 400 for processing data, each of which may be performed by the various modules of the above described apparatus. And other operations and/or functions are implemented, and for brevity, no further details are provided herein.

Therefore, a method for processing data according to an embodiment of the present invention determines at least one target from a plurality of configuration files included in a configuration file library according to information of at least one target algorithm module a configuration file, wherein each target profile in the at least one target profile is configured to configure a target FPGA node to implement a target algorithm module, and the general purpose processor node to each of the at least one target FPGA node The node sends a configuration message indicating the target configuration file corresponding to the target FPGA node, which can virtualize the FPGA node resources, and convert the program development flow of the FPGA into a program development process of the general processor node, thereby shortening the program development of the FPGA. Cycles and reduces the complexity of FPGA program development, improving system performance and user experience.

FIG. 11 illustrates another method 800 for processing data provided by an embodiment of the present invention. The method 800 can be applied to a system for processing data, the system being provided with a configuration file library including at least one configuration file corresponding to each of the plurality of field editable gate array FPGA nodes, each Each configuration file corresponding to the FPGA node is used to configure the FPGA node to implement an algorithm module. As shown in FIG. 11, the method 800 includes:

S810. Receive a call message sent by a general-purpose processor node, where the call message is used to instruct the FPGA node to process the data to be processed by using the target algorithm module, where the FPGA node is configured with a target configuration for enabling the FPGA node to implement the target algorithm module. file;

S820. Process the data to be processed according to the call message to obtain a processing result.

S830. Send the processing result to the general-purpose processor node.

Therefore, a method for processing data according to an embodiment of the present invention configures a target configuration file included in a standard configuration file library, the target configuration file is used to configure an FPGA node to implement a function of a target algorithm module, and the FPGA node is based on a general purpose The call message sent by the processor node performs data processing and sends the processing result to the general-purpose processor node, which can virtualize the FPGA node resource and convert the program development flow of the FPGA into the program development process of the general-purpose processor node, thereby shortening FPGA program development cycle and reduce the complexity of FPGA program development, improve system performance and user experience.

Correspondingly, the invocation message includes address information of the target FPGA node, number information of the target algorithm module in the plurality of instantiated target algorithm modules, and the to-be-processed data.

As another alternative embodiment, prior to S810, the method 800 further includes:

Receiving a configuration message sent by the general-purpose processor node, where the configuration message is used to indicate the target configuration file allocated by the general-purpose processor node to the FPGA node;

Obtaining the target configuration file according to the configuration message;

Perform the configuration operation of the target profile.

As another optional embodiment, the configuration message carries the target configuration file. In this case, the obtaining unit is specifically configured to obtain the target configuration file from the configuration message.

As another alternative embodiment, the profile repository is located on the general purpose processor node and the configuration message carries indication information indicating the target profile. At this time, S810, according to the configuration message, acquiring the target configuration file, including:

According to the configuration message, the target configuration file is obtained from the configuration file library set by the general processor node.

As another alternative embodiment, the target configuration file includes:

Algorithm module logic for implementing the target algorithm module;

As another optional embodiment, the basic information logic is used to describe the type of the FPGA node; the basic information logic is further used to describe the name of the target algorithm module, the number of instantiations of the target algorithm module, and the implementation of the FPGA node. Data processing performance when the target algorithm module.

As another alternative embodiment, the method 800 further includes:

Receiving mode conversion indication information sent by the general-purpose processor node, where the mode conversion indication information is used to indicate that the FPGA node enters a power-saving mode;

According to the mode conversion indication information, a configuration operation of the idle configuration file is not performed, and the idle configuration file is not used to configure the FPGA node to implement any effective algorithm module.

As an optional embodiment, the idle configuration file includes:

Basic information logic for describing the FPGA node;

The method 800 for processing data according to an embodiment of the present invention may be implemented by a target FPGA node 120, a device 300 for processing data, or a device 500 for processing data, the respective flows of which may be by the above-described and Other operations and/or function implementations are not described herein for brevity.

Therefore, a method for processing data according to an embodiment of the present invention is based on at least one item Determining, by the algorithm module, at least one target configuration file from a plurality of configuration files included in the configuration file library, wherein each target configuration file in the at least one target configuration file is used to configure a target FPGA node to achieve a target An algorithm module, and the general purpose processor node sends a configuration message indicating a target profile corresponding to the target FPGA node to each of the at least one target FPGA node, enabling the FPGA node resource to be virtualized, and the FPGA The program development process is converted to a program development flow of a general-purpose processor node, thereby shortening the program development cycle of the FPGA and reducing the complexity of FPGA program development, improving system performance and user experience.

It should be understood that the size of the sequence numbers of the above processes does not imply a sequence of executions, and the order of execution of the processes should be determined by its function and internal logic, and should not be construed as limiting the implementation process of the embodiments of the present invention.

It should be understood that in the embodiments of the present invention, the term and/or merely an association relationship describing the associated object indicates that there may be three relationships. For example, A and/or B may indicate that A exists separately, and A and B exist simultaneously, and B cases exist alone. In addition, the character / in this paper generally indicates that the contextual object is an OR relationship.

Those skilled in the art will appreciate that the various method steps and elements described in connection with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both, in order to clearly illustrate hardware and software. Interchangeability, the steps and composition of the various embodiments have been generally described in terms of function in the foregoing description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the solution. A person skilled in the art can use different methods to implement the description for each particular application, but such implementation should not be considered to be beyond the scope of the present invention.

A person skilled in the art can clearly understand that, for the convenience and brevity of the description, the specific working process of the system, the device and the unit described above can refer to the corresponding process in the foregoing method embodiment, and details are not described herein again.

In the several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the device embodiments described above are merely illustrative. For example, the division of the unit is only a logical function division. In actual implementation, there may be another division manner, for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be indirect coupling through some interfaces, devices or units or Communication connections can also be electrical, mechanical or other forms of connection.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the embodiments of the present invention.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a standalone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention contributes in essence or to the prior art, or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium. A number of instructions are included to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like, which can store program codes. .

The above is only the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any equivalent person can be easily conceived within the technical scope of the present invention by any person skilled in the art. Modifications or substitutions are intended to be included within the scope of the invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

A system for processing data, comprising: a general purpose processor node and a plurality of field editable gate array FPGA nodes, wherein

The system is provided with a configuration file library, the configuration file library includes at least one configuration file corresponding to each of the plurality of FPGA nodes, and each configuration file corresponding to each of the FPGA nodes is used for a configuration The FPGA node implements an algorithm module;

The general-purpose processor node is configured to determine, according to information of the at least one target algorithm module, at least one target configuration file from a plurality of configuration files included in the configuration file library, where the target configuration file is used to configure the multiple The target FPGA module in the FPGA node implements the target algorithm module;

The general-purpose processor node is further configured to send a configuration message to the at least one target FPGA node, where the configuration message is used to indicate a target configuration file corresponding to the target FPGA node;

The target FPGA node is configured to receive the configuration message sent by the general-purpose processor node, and perform a configuration operation according to the target configuration file indicated in the configuration message.
The system according to claim 1, wherein the configuration file library comprises a plurality of first configuration files corresponding to a first one of the plurality of FPGA nodes, wherein the plurality of first configuration files The at least one first configuration file corresponding to each of the plurality of algorithm modules available in the system is included, and the different algorithm modules correspond to different first configuration files.
The system according to claim 1 or 2, wherein the plurality of FPGA nodes have different types, wherein two FPGA nodes of the same type having the same type implement the same algorithm module In the same configuration file, two FPGA nodes having different types of the plurality of FPGA nodes implement the same algorithm module and correspond to different configuration files.
The system according to any one of claims 1 to 3, wherein the target profile comprises:

Algorithm module logic for implementing the target algorithm module;

Basic information logic for describing the target FPGA node and the target algorithm module;

The interface logic is configured to implement an interface function of the target FPGA node to communicate with the general-purpose processor node.
The system of claim 4 wherein said basic information logic is used Describe the type of the target FPGA node;

The basic information logic is further configured to describe a name of the target algorithm module, an instantiation number of the target algorithm module, and data processing performance when the target FPGA node implements the target algorithm module.
The system according to any one of claims 1 to 5, wherein the information of the at least one target algorithm module comprises: a name of the at least one target algorithm module, a target number of the at least one target algorithm module And a target processing time of the at least one target algorithm module.
The system according to any one of claims 1 to 6, wherein the general purpose processor node is specifically configured to:

Determining at least one configuration file corresponding to the at least one target algorithm module from a plurality of configuration files included in the configuration file library;

Determining the at least one target configuration file from at least one configuration file corresponding to the at least one target algorithm module according to the information of the at least one target algorithm module.
The system according to any one of claims 1 to 6, wherein the general purpose processor node is specifically configured to:

Determining at least one FPGA node available from the plurality of FPGA nodes;

Determining at least one target FPGA node from the available at least one FPGA node according to the information of the at least one target algorithm module and the plurality of configuration files included in the configuration file library;

The at least one target configuration file corresponding to the at least one target FPGA node and the at least one target algorithm module is determined from a plurality of configuration files included in the configuration file library.
The system according to any one of claims 1 to 8, wherein the general purpose processor node is further used before determining at least one target profile from a plurality of profiles included in the profile library :

Determining information of a plurality of required algorithm modules including the at least one target algorithm module according to user input;

Determining, by the information of the plurality of required algorithm modules, the at least one target algorithm module implemented by the plurality of FPGA nodes from the plurality of required algorithm modules, wherein the plurality of required algorithm modules An algorithm module other than the at least one target module is used by the general purpose processor Node implementation.
The system according to any one of claims 1 to 9, wherein the general purpose processor node is further configured to:

Determining a calling order of the at least one target FPGA node;

And sending, according to the calling sequence, an invocation message to the target FPGA node, where the invoking message is used to indicate that the target FPGA node processes the data to be processed by using a specified target algorithm module;

The target FPGA node is also used to:

Receiving the call message sent by the general-purpose processor node, processing the to-be-processed data according to the call message, and sending a processing result to the general-purpose processor node.
The system according to claim 10, wherein the number of instantiations of the target algorithm module corresponding to the target profile is multiple, and the plurality of instantiated target algorithm modules are in the FPGA node. Numbered sequentially;

The invocation message carries address information of the target FPGA node, number information of the specified target algorithm module in the plurality of instantiated target algorithm modules, and the to-be-processed data.
The system according to any one of claims 1 to 11, wherein the general purpose processor node is further configured to:

Transmitting mode transition indication information to the first target FPGA node of the at least one target FPGA node, the mode transition indication information being used to indicate that the first target FPGA node enters a power saving mode; or

Adding an FPGA node other than the at least one target FPGA node among the plurality of FPGA nodes to the at least one target FPGA node.
The system according to any one of claims 1 to 12, wherein the profile repository is stored in the general purpose processor node; or

The system further includes: a shared server, the configuration file library is stored in the shared server, and the general-purpose processor node is further configured to acquire, from the shared server, information of multiple configuration files included in the configuration file library. .
An apparatus for processing data, characterized by being applied to a system for processing data, the system being provided with a configuration file library, each of the plurality of field editable gate array FPGA nodes At least one configuration file corresponding to the FPGA node, each configuration file corresponding to each of the FPGA nodes is configured to configure the FPGA node to implement an algorithm module, The device includes:

a determining unit, configured to determine, according to information of the at least one target algorithm module, at least one target configuration file from a plurality of configuration files included in the configuration file library, where the target configuration file is used to configure the multiple FPGA nodes The target FPGA node in the implementation implements the target algorithm module;

And a sending unit, configured to send, to the at least one target FPGA node determined by the determining unit, a configuration message, where the configuration message is used to indicate a target configuration file corresponding to the target FPGA node.
The apparatus according to claim 14, wherein the configuration file library comprises a plurality of first configuration files corresponding to a first one of the plurality of FPGA nodes, wherein the plurality of first configuration files The at least one first configuration file corresponding to each of the plurality of algorithm modules available in the system is included, and the different algorithm modules correspond to different first configuration files.
The apparatus according to claim 14 or 15, wherein the plurality of FPGA nodes have different types, wherein two FPGA nodes of the same type having the same type implement the same algorithm module In the same configuration file, two FPGA nodes having different types of the plurality of FPGA nodes implement the same algorithm module and correspond to different configuration files.
The apparatus according to any one of claims 14 to 16, wherein the target profile comprises:

Algorithm module logic for implementing the target algorithm module;

Basic information logic for describing the target FPGA node and the target algorithm module;

The interface logic is configured to implement an interface function of the target FPGA node to communicate with the general-purpose processor node.
The apparatus according to claim 17, wherein said basic information logic is used to describe a type of said target FPGA node;

The basic information logic is further configured to describe a name of the target algorithm module, an instantiation number of the target algorithm module, and data processing performance when the target FPGA node implements the target algorithm module.
The apparatus according to any one of claims 14 to 18, wherein the information of the at least one target algorithm module comprises: a name of the at least one target algorithm module, the The target number of at least one target algorithm module and the target processing time of the at least one target algorithm module.
The device according to any one of claims 14 to 19, wherein the determining unit is specifically configured to:

Determining at least one configuration file corresponding to the at least one target algorithm module from a plurality of configuration files included in the configuration file library;

Determining the at least one target configuration file from at least one configuration file corresponding to the at least one target algorithm module according to the information of the at least one target algorithm module.
The device according to any one of claims 14 to 19, wherein the determining unit is specifically configured to:

Determining at least one FPGA node available from the plurality of FPGA nodes;

Determining at least one target FPGA node from the available at least one FPGA node according to the information of the at least one target algorithm module and the plurality of configuration files included in the configuration file library;

The at least one target configuration file corresponding to the at least one target FPGA node and the at least one target algorithm module is determined from a plurality of configuration files included in the configuration file library.
The device according to any one of claims 14 to 21, wherein the determining unit is further configured to:

Determining information of a plurality of required algorithm modules including the at least one target algorithm module according to user input before determining at least one target configuration file from the plurality of configuration files included in the configuration file library;

Determining, by the information of the plurality of required algorithm modules, the at least one target algorithm module implemented by the plurality of FPGA nodes from the plurality of required algorithm modules, wherein the plurality of required algorithm modules An algorithm module other than the at least one target module is implemented by the general purpose processor node.
The apparatus according to any one of claims 14 to 22, wherein the determining unit is further configured to determine a calling order of the at least one target FPGA node;

The sending unit is further configured to send, according to the calling sequence determined by the determining unit, a call message to the target FPGA node, where the call message is used to indicate that the target FPGA node uses a specified target algorithm module to process data. Process

The device also includes:

a receiving unit, configured to receive a data processing result that is sent by the target FPGA node according to the call message sent by the sending unit.
The apparatus according to claim 23, wherein the number of instantiations of the target algorithm module corresponding to the target profile is multiple, and the plurality of instantiated target algorithm modules are in the FPGA node. Numbered sequentially;

The call message includes address information of the target FPGA node, number information of the specified target algorithm module in the plurality of instantiated target algorithm modules, and the to-be-processed data.
The apparatus according to any one of claims 14 to 24, wherein the transmitting unit is further configured to send mode switching indication information to a first target FPGA node of the at least one target FPGA node, the mode The conversion indication information is used to indicate that the first target FPGA node enters a power saving mode; or

The determining unit is further configured to add an FPGA node other than the at least one target FPGA node among the plurality of FPGA nodes to the at least one target FPGA node.
The apparatus according to any one of claims 14 to 25, further comprising:

a storage unit for storing the configuration file library.
An apparatus for processing data, characterized by being applied to a system for processing data, the system being provided with a configuration file library, each of the plurality of field editable gate array FPGA nodes At least one configuration file corresponding to the FPGA node, each configuration file corresponding to each of the FPGA nodes is used to configure the FPGA node to implement an algorithm module, and the device includes:

a receiving unit, configured to receive a call message sent by a general-purpose processor node, where the call message is used to instruct the FPGA node to process a data to be processed by using a target algorithm module, where the FPGA node is configured to enable the FPGA node Implementing a target configuration file of the target algorithm module;

a processing unit, configured to process the to-be-processed data according to the call message received by the receiving unit, to obtain a processing result;

And a sending unit, configured to send, to the general-purpose processor node, the processing result obtained by the processing unit.
The apparatus according to claim 27, wherein the number of instantiations of the target algorithm module corresponding to the target profile is multiple, and the plurality of instantiated target algorithm modules are The FPGA nodes are numbered sequentially;

The call message includes address information of the target FPGA node, number information of the adopted target algorithm module in the plurality of instantiated target algorithm modules, and the to-be-processed data.
The device according to claim 27 or 28, wherein the receiving unit is further configured to receive a configuration message sent by the general-purpose processor node, before receiving the call message sent by the general-purpose processor node, a configuration message is used to indicate the target configuration file allocated by the general-purpose processor node to the FPGA node;

The device also includes:

An obtaining unit, configured to acquire the target configuration file according to the configuration message received by the receiving unit;

And a configuration unit, configured to perform a configuration operation according to the target configuration file acquired by the acquiring unit.
[Correct according to Rule 91 12.03.2015]

The device according to claim 29, wherein the configuration message carries the target configuration file;

The obtaining unit is specifically configured to acquire the target configuration file from the configuration message.
[Correct according to Rule 91 12.03.2015]

The apparatus according to claim 29, wherein said profile library is disposed on said general purpose processor node, and said configuration message carries indication information for indicating said target profile;

The obtaining unit is configured to obtain the target configuration file from the configuration file library set by the general-purpose processor node according to the indication information carried in the configuration message.
[Correct according to Rule 91 12.03.2015]

The apparatus according to any one of claims 27 to 31, wherein the target profile comprises:

Algorithm module logic for implementing the target algorithm module;

Basic information logic for describing the FPGA node and the target algorithm module;

Interface logic for implementing an interface function of the FPGA node to communicate with the general purpose processor node.
[Correct according to Rule 91 12.03.2015]

The apparatus according to claim 32, wherein said basic information logic is used to describe a type of said FPGA node;

The basic information logic is further configured to describe a name of the target algorithm module, an instantiation number of the target algorithm module, and data processing performance when the FPGA node implements the target algorithm module.
[Correct according to Rule 91 12.03.2015]

The apparatus according to any one of claims 29 to 33, wherein the receiving unit is further configured to receive mode switching indication information sent by the general-purpose processor node, where the mode switching indication information is used to indicate Said FPGA node enters power saving mode;

The configuration unit is further configured to perform a configuration operation of the idle configuration file according to the mode conversion indication information received by the receiving unit, where the idle configuration file is not used to configure the FPGA node to implement any effective algorithm module.
[Correct according to Rule 91 12.03.2015]

The device according to claim 34, wherein the idle configuration file comprises:

Basic information logic for describing the FPGA node;

Interface logic for implementing an interface function of the FPGA node to communicate with the general purpose processor node.
A method for processing data, characterized by being applied to a system for processing data, the system being provided with a configuration file library, each of the plurality of field editable gate array FPGA nodes At least one configuration file corresponding to the FPGA node, each configuration file corresponding to each of the FPGA nodes is used to configure the FPGA node to implement an algorithm module, and the method includes:

Determining, according to information of the at least one target algorithm module, at least one target configuration file from a plurality of configuration files included in the configuration file library, wherein the target configuration file is configured to configure a target FPGA node of the plurality of FPGA nodes Implementing the target algorithm module;

And sending a configuration message to the at least one target FPGA node, where the configuration message is used to indicate a target configuration file corresponding to the target FPGA node.
[Correct according to Rule 91 12.03.2015]
The method according to claim 36, wherein the configuration file library comprises a plurality of first configuration files corresponding to a first one of the plurality of FPGA nodes, wherein the plurality of first configuration files The at least one first configuration file corresponding to each of the plurality of algorithm modules available in the system is included, and the different algorithm modules correspond to different first configuration files.
[Correct according to Rule 91 12.03.2015]
The method according to claim 36 or 37, wherein the plurality of FPGA nodes have different types, wherein two FPGA nodes of the same type having the same type implement the same algorithm module In the same configuration file, two FPGA nodes having different types of the plurality of FPGA nodes implement the same algorithm module and correspond to different configuration files.
[Correct according to Rule 91 12.03.2015]

The method according to any one of claims 36 to 38, wherein the target profile comprises:

Algorithm module logic for implementing the target algorithm module;

Basic information logic for describing the target FPGA node and the target algorithm module;

The interface logic is configured to implement an interface function of the target FPGA node to communicate with the general-purpose processor node.
[Correct according to Rule 91 12.03.2015]

The method of claim 39, wherein said basic information logic is used to describe a type of said target FPGA node;

The basic information logic is further configured to describe a name of the target algorithm module, an instantiation number of the target algorithm module, and data processing performance when the target FPGA node implements the target algorithm module.
[Correct according to Rule 91 12.03.2015]
The method according to any one of claims 36 to 40, wherein the information of the at least one target algorithm module comprises: a name of the at least one target algorithm module, a target number of the at least one target algorithm module The target processing time of the at least one target algorithm module.
[Correct according to Rule 91 12.03.2015]

The method according to any one of claims 36 to 41, wherein the determining at least one target configuration file from a plurality of configuration files included in the configuration file library according to information of at least one target algorithm module, include:

Determining at least one configuration file corresponding to the at least one target algorithm module from a plurality of configuration files included in the configuration file library;

Determining the at least one target configuration file from at least one configuration file corresponding to the at least one target algorithm module according to the information of the at least one target algorithm module.
[Correct according to Rule 91 12.03.2015]

The method according to any one of claims 36 to 41, wherein the determining at least one target configuration file from a plurality of configuration files included in the configuration file library according to information of at least one target algorithm module, include:

Determining at least one FPGA node available from the plurality of FPGA nodes;

Determining at least one target FPGA node from the available at least one FPGA node according to the information of the at least one target algorithm module and the plurality of configuration files included in the configuration file library;

The at least one target configuration file corresponding to the at least one target FPGA node and the at least one target algorithm module is determined from a plurality of configuration files included in the configuration file library.
[Correct according to Rule 91 12.03.2015]

The method according to any one of claims 36 to 43 wherein before the determining at least one target profile from the plurality of profiles included in the profile library, the method further comprises:

Determining information of a plurality of required algorithm modules including the at least one target algorithm module according to user input;

Determining, by the information of the plurality of required algorithm modules, the at least one target algorithm module implemented by the plurality of FPGA nodes from the plurality of required algorithm modules, wherein the plurality of required algorithm modules An algorithm module other than the at least one target module is implemented by the general purpose processor node.
[Correct according to Rule 91 12.03.2015]

The method according to any one of claims 36 to 44, wherein the method further comprises:

Determining a calling order of the at least one target FPGA node;

And sending, according to the calling sequence, an invocation message to the target FPGA node, where the invoking message is used to indicate that the target FPGA node processes the data to be processed by using a specified target algorithm module;

Receiving a data processing result sent by the target FPGA node according to the call message.
[Correct according to Rule 91 12.03.2015]

The method according to claim 45, wherein the number of instantiations of the target algorithm module corresponding to the target profile is multiple, and the plurality of instantiated target algorithm modules are in the FPGA node. Numbered sequentially;

The call message includes address information of the target FPGA node, number information of the specified target algorithm module in the plurality of instantiated target algorithm modules, and the to-be-processed data.
[Correct according to Rule 91 12.03.2015]

The method according to any one of claims 36 to 46, wherein the method further comprises:

Transmitting mode transition indication information to the first target FPGA node of the at least one target FPGA node, the mode transition indication information being used to indicate that the first target FPGA node enters a power saving mode; or

Adding an FPGA node other than the at least one target FPGA node among the plurality of FPGA nodes to the at least one target FPGA node.
A method for processing data, characterized by being applied to a system for processing data, the system being provided with a configuration file library, the configuration file library comprising a plurality of field editable gate arrays At least one configuration file corresponding to each of the FPGA nodes in the column, each configuration file corresponding to each of the FPGA nodes is configured to configure the FPGA node to implement an algorithm module, and the method includes:

Receiving a call message sent by a general-purpose processor node, the call message is used to instruct the FPGA node to process the data to be processed by using a target algorithm module, where the FPGA node is configured to enable the FPGA node to implement the target algorithm module Target profile

Processing the to-be-processed data according to the invocation message to obtain a processing result;

The processing result is sent to the general purpose processor node.
[Correct according to Rule 91 12.03.2015]

The method according to claim 48, wherein the number of instances of the target algorithm module corresponding to the target profile is multiple, and the plurality of instantiated target algorithm modules are in the FPGA node. Numbered sequentially;

The call message includes address information of the target FPGA node, number information of the adopted target algorithm module in the plurality of instantiated target algorithm modules, and the to-be-processed data.
[Correct according to Rule 91 12.03.2015]

The method according to claim 48 or claim 49, wherein before the receiving the invocation message sent by the general processor node, the method further comprises:

Receiving a configuration message sent by the general-purpose processor node, where the configuration message is used to indicate the target configuration file that is allocated by the general-purpose processor node to the FPGA node;

Obtaining the target configuration file according to the configuration message;

Perform the configuration operation of the target configuration file.
[Correct according to Rule 91 12.03.2015]

The method according to claim 50, wherein the configuration message carries the target configuration file;

Obtaining the target configuration file according to the configuration message, including:

Obtaining the target configuration file from the configuration message.
[Correct according to Rule 91 12.03.2015]

The method according to claim 50, wherein said profile library is disposed on said general purpose processor node, and said configuration message carries indication information for indicating said target profile;

Obtaining the target configuration file according to the configuration message, including:

Obtaining the target configuration file from the configuration file library set by the general-purpose processor node according to the indication information carried in the configuration message.
[Correct according to Rule 91 12.03.2015]

The FPGA node according to any one of claims 48 to 52, wherein the target configuration file comprises:

Algorithm module logic for implementing the target algorithm module;

Basic information logic for describing the FPGA node and the target algorithm module;

Interface logic for implementing an interface function of the FPGA node to communicate with the general purpose processor node.
[Correct according to Rule 91 12.03.2015]

The method of claim 53, wherein said basic information logic is used to describe a type of said FPGA node;

The basic information logic is further configured to describe a name of the target algorithm module, an instantiation number of the target algorithm module, and data processing performance when the FPGA node implements the target algorithm module.
[Correct according to Rule 91 12.03.2015]

The method according to any one of claims 50 to 54, wherein the method further comprises:

Receiving mode conversion indication information sent by the general-purpose processor node, where the mode conversion indication information is used to indicate that the FPGA node enters a power-saving mode;

According to the mode conversion indication information, a configuration operation of an idle configuration file is not performed, and the idle configuration file is not used to configure the FPGA node to implement any effective algorithm module.
[Correct according to Rule 91 12.03.2015]

The method of claim 55, wherein the idle profile comprises:

Basic information logic for describing the FPGA node;

Interface logic for implementing an interface function of the FPGA node to communicate with the general purpose processor node.