WO2016123748A1 - 一种闪存存储系统及其读写、删除方法 - Google Patents

一种闪存存储系统及其读写、删除方法 Download PDF

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Publication number
WO2016123748A1
WO2016123748A1 PCT/CN2015/072172 CN2015072172W WO2016123748A1 WO 2016123748 A1 WO2016123748 A1 WO 2016123748A1 CN 2015072172 W CN2015072172 W CN 2015072172W WO 2016123748 A1 WO2016123748 A1 WO 2016123748A1
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Prior art keywords
storage block
physical storage
address
flash
backend
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PCT/CN2015/072172
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English (en)
French (fr)
Inventor
李超
丁杰
周文
刘建伟
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北京麓柏科技有限公司
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Priority to PCT/CN2015/072172 priority Critical patent/WO2016123748A1/zh
Publication of WO2016123748A1 publication Critical patent/WO2016123748A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems

Definitions

  • the present invention relates to the field of storage, and in particular, to a flash storage system and a method for reading, writing, and deleting the same.
  • Flash Due to the limited lifetime of Flash, it is a common practice to add a level 1 cache before Flash to reduce the erasure of Flash.
  • the read and write access size of the storage system is 4 KB, and the write unit of flash memory is page.
  • the capacity of a single page can reach 16KB, 32KB.
  • the access request size 4KB as the cache load, flush unit will cause write amplification. Increase the number of flash erasing and reduce the flash life. If you simply request the cache according to the page size, it will cause a waste of cache space, thus reducing the cache hit rate.
  • Traditional flash memory caches require two data copies during read and write, which reduces cache access speed. Affect the performance of the entire storage system.
  • the present invention provides a flash memory storage system and a method for reading, writing and deleting the same to reduce the intermediate copy process between the cache and the back end flash memory.
  • a write data method for a flash storage system including a cache, a main control module, a cache metadata record table, and a write map; wherein the write map is used to store a logical storage block in the cache Corresponding relationship with the physical storage block, the cache metadata record table is configured to store a correspondence between the metadata table address, the physical storage block, and the back end flash address; the method for writing data of the flash storage system includes the following steps:
  • the main control module receives a command sent by the front-end application to write data in the first write logical storage block to the first back-end flash address;
  • the main control module reads the write mapping table, and obtains a first physical storage block in the cache corresponding to the first write logical storage block;
  • the main control module calculates the first backend flash address, and obtains the first backend a first metadata table address corresponding to the flash address;
  • the main control module reads the cache metadata record table, and obtains a current backend flash address corresponding to the first metadata table address;
  • S5 the The main control module determines whether the first backend flash address is the same as the current backend flash address;
  • S7 if the first backend flash address is different from the current backend flash address, storing data of a current physical storage block
  • the flash storage system further includes a reference count table, a free physical block FIFO, and a reclamation module
  • the free physical block FIFO is configured to store free physical storage blocks in the cache
  • the counter table is used for Storing a physical storage block and a corresponding number of references.
  • the free physical block FIFO allocates an empty physical storage block, setting a reference number of the allocated physical storage block to a first reference number of times; and further including reclaiming the physical storage Block step: for the replaced physical storage block, reading the reference number of the corresponding physical storage block in the reference count table, and if the reference number of the corresponding physical storage block is greater than the first reference number of times, the corresponding physical storage block The number of times of reference is reduced by the number of times of reference. If the number of references of the corresponding physical storage block is equal to the value of the first reference number, the recycling module writes the corresponding physical storage block into the free physical block FIFO.
  • the cache metadata record table is further configured to store a physical storage block valid flag bit corresponding to the physical storage block, and the value of the corresponding physical storage block valid flag bit is stored before the physical storage block stores the data.
  • the value of the corresponding physical storage block valid flag bit is set to a valid value after the physical storage block stores data; in the step S6, the first physical storage block is replaced with the Before the current physical storage block corresponding to the current back-end flash address in the cache metadata record table, the method further includes: determining, in the cache metadata record table, the current physical storage block corresponding to the current back-end flash address Whether the value of the physical storage block valid flag is a valid value or a non-valid value, and if it is a valid value, the step of reclaiming the physical storage block is performed.
  • the flash storage system further includes a cache metadata status table.
  • the physical storage block has multiple, and multiple physical storage blocks are respectively associated with the back end flash memory.
  • the address-based consecutive plurality of back-end flash addresses correspond to each other;
  • the cache metadata record table is further configured to store a physical storage block valid flag bit corresponding to the physical storage block, and the corresponding physical storage block before the physical storage block stores the data
  • the value of the valid flag bit is set to a non-valid value, and the value of the corresponding physical memory block valid flag bit is set to a valid value after the physical memory block stores the data;
  • the cache metadata state table is used to store the metadata table address, And occupying a corresponding relationship between the flag bit and the empty flag bit, where the value of the occupied flag bit includes an occupied value and an unoccupied value indicating that the entry corresponding to the metadata table address is occupied and not occupied, respectively.
  • the value of the flag bit includes a non-null value and a null value respectively indicating that the physical memory block in the metadata table address is written data and not written data;
  • the method further includes the following steps: S3.1, the main control module reads the cache metadata record table, and determines whether the value of the occupied flag bit corresponding to the address of the first metadata table is occupied.
  • step S6 the method further includes the following steps: S6.1: determining, in the cache metadata record table, whether a value of a physical storage block valid identifier of a physical storage block corresponding to the first backend flash address is Valid value; S6.2, if it is a valid value, the step of reclaiming the physical storage block is performed, and step S6.4 is performed; S6.3, if it is not a valid value, the value of the corresponding physical storage block valid identifier is set to a valid value, and Step S6.4; S6.4, writing the first physical storage block to the cache metadata record table Corresponding location.
  • a new physical memory block is allocated for the first write logical memory block from the free physical block FIFO after step S6 and step S7.
  • the present invention also provides a read data method for a flash memory storage system, the flash memory storage system including a cache, a main control module, a cache metadata record table, and a read map; wherein the read map is stored in the cache Reading a correspondence between the logical storage block and the physical storage block, where the cache metadata record table is used to store a correspondence between the metadata table address, the physical storage block, and the back end flash address; the read data of the flash storage system
  • the method includes the following steps: S1, the main control module receives a command sent by the front-end application to write data of the first back-end flash address into the first read-out logical storage block; S2, the main control module pairs the Calculating a first back-end flash address to obtain a first metadata table address corresponding to the first back-end flash address; S3, the main control module reads the cache metadata record table, and obtains the first The current backend flash address corresponding to the metadata table address; S4, the main control module determines whether the first backend flash address is the same as the current backend
  • the flash storage system further includes a reference count table, a free physical block FIFO, and a reclamation module
  • the free physical block FIFO is configured to store free physical storage blocks in the cache
  • the counter table is used for Storing the physical storage block and the corresponding number of reference times, and when the free physical block FIFO allocates the free physical storage block, setting the reference number of the allocated physical storage block to the first reference number of times
  • the method further includes the following steps: S6.1, referencing the new physical storage block The number is increased by a set number of references, and the number of references of the old physical storage block corresponding to the first read logical storage block in the read mapping table is reduced by the set reference number; for the replaced and replaced physical a storage block, the number of times of referencing the physical storage block in the reference count table is read, and if the reference number of the physical storage block is greater than the first reference number of times, the reference number of the corresponding physical storage block is decreased by a reference number of times. If the number of references of the physical storage block is equal to the first reference number of times, the recycling module writes the corresponding physical storage block into the free physical block FIFO.
  • the flash storage system further includes a cache metadata status table.
  • the physical storage block has multiple, and multiple physical storage blocks are respectively associated with the back end flash memory. Address is a plurality of consecutive back-end flash addresses corresponding to the reference;
  • the cache metadata record table is further configured to store a physical storage block valid flag bit corresponding to the physical storage block, and the corresponding physical storage block valid flag before the physical storage block stores the data The value of the bit is set to a non-valid value, and the value of the corresponding physical memory block valid flag bit is set to a valid value after the physical storage block stores the data;
  • the cache metadata state table is used to store the metadata table address, the occupation flag Corresponding relationship between the bit and the empty flag bit, the value of the occupied flag bit includes an occupied value and an unoccupied value respectively indicating that the entry corresponding to the metadata table address is occupied and not occupied, the empty flag bit
  • the value includes a non-null value and a null value respectively indicating that the physical storage block in the metadata table address
  • the present invention also provides a method for deleting data of a flash storage system, the flash storage system including a cache, a main control module, and a cache metadata record table; wherein the cache metadata record table is used to store a metadata table address and physical storage Corresponding relationship between the block and the back-end flash address;
  • the method for deleting data of the flash storage system includes the following steps: S1, the main control module receives a command issued by the front-end application to delete data of the first back-end flash address; S2 The main control module calculates the first back-end flash address to obtain a first metadata table address corresponding to the first back-end flash address; S3, the main control module reads the cache element a data record table, obtaining a current back-end flash address corresponding to the first metadata table address; S4, the main control module determines whether the first back-end flash address is the same as the current back-end flash address; S5, if The first back-end flash address is the same as the current back-end flash address, and the entry corresponding to the current back
  • the present invention also provides a flash memory storage system including a cache, a main control module, a cache metadata record table, a read map table, and a write map table; wherein the write map table is used to store a write logic block in the cache Corresponding relationship with the physical storage block, the read mapping table is configured to store a correspondence between the logical storage block and the physical storage block in the cache, where the cache metadata record table is used to store the metadata table address and the physical storage block.
  • the main control module is configured to receive a command issued by the front end application to write data in the first write logical storage block to the first back end flash memory address; the main control module For reading the write mapping table, acquiring a first physical storage block in the cache corresponding to the first write logical storage block; the main control module is configured to use the first backend flash address Performing a calculation to obtain a first metadata table address corresponding to the first back-end flash address; the main control module is configured to read the cache metadata record table, and obtain the address corresponding to the first metadata table address a current back-end flash address; the main control module is configured to determine whether the first back-end flash address is the same as the current back-end flash address, and if the first back-end flash address is the same as the current back-end flash address, Then The first physical storage block replaces a current physical storage block corresponding to the current backend flash address in the cache metadata record table; if the first backend flash address is different from the current backend flash address, Sto
  • the flash storage system further includes a reference count table, a free physical block FIFO, and a reclamation module
  • the free physical block FIFO is configured to store free physical storage blocks in the cache
  • the counter table is used for Storing the physical storage block and the corresponding number of reference times, when the free physical block FIFO allocates the free physical storage block, setting the reference number of the allocated physical storage block to the first reference number of times;
  • the number of times of reference of the current physical storage block corresponding to the first back-end flash address is increased by a reference number of times, and Dereferencing the number of times of reference of the old physical storage block corresponding to the first read logical storage block in the mapping table minus the set reference number; writing the new physical storage block to the read mapping table Adding a reference number of times of the new physical storage block to a reference number of times, and referencing the old physical storage block corresponding to the first read logical storage block in the read mapping table
  • one entry of the cache metadata record table has four physical storage blocks, each of which has a size of 4 KB.
  • the flash memory storage system can reduce unnecessary writing or reading to the back-end flash memory, realize zero copy on the read-write data path, eliminate unnecessary intermediate copying process, thereby improving reading and writing efficiency; and can make the front-end application Read and write access matches the size of the backend flash.
  • FIG. 1 is a schematic diagram showing the workflow of a flash memory storage system according to an embodiment of the present invention
  • FIG. 2 is a schematic block diagram of a flash memory storage system according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of address translation of a logical storage block and a physical storage block in a cache according to an embodiment of the present invention
  • FIG. 4 is a schematic flow chart of recycling a physical storage block according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a process of processing a command completion queue according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a cache metadata record table according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a cache metadata state table according to an embodiment of the present invention.
  • FIG. 8 is a schematic flowchart of deleting back-end flash memory data according to an embodiment of the present invention.
  • FIG. 9 is a flow chart showing data writing to a back end flash memory according to an embodiment of the present invention.
  • FIG. 10 is a flow chart of reading data from a back end flash memory according to an embodiment of the present invention.
  • FIG. 11 is a schematic diagram of a write mapping table in an initial state according to an embodiment of the present invention.
  • FIG. 12 is a schematic diagram of a read mapping table in an initial state according to an embodiment of the present invention.
  • FIG. 13 is a schematic diagram of a cache metadata state table in an initial state according to an embodiment of the present invention.
  • FIG. 14 is a schematic diagram of idle physical block FIFO storage in an initial state according to an embodiment of the present invention.
  • 15 is a schematic diagram of the idle physical block FIFO of FIG. 14 after allocating a part of physical storage blocks to a write mapping table;
  • 16 is a schematic diagram of a cache metadata record table before a first write request according to an embodiment of the present invention.
  • FIG. 17 is a schematic diagram of the cache metadata record table of FIG. 16 after the first write request
  • FIG. 18 is a schematic diagram of a first write request pre-write mapping table according to an embodiment of the present invention.
  • 19 is a schematic diagram of the write mapping table of FIG. 18 after the first write request
  • 20 is a schematic diagram of a cache metadata state table before a first write request according to an embodiment of the present invention
  • 21 is a schematic diagram of a cache metadata state table after a first write request according to an embodiment of the present invention.
  • 22 is a schematic diagram of a cache metadata record table before a read request according to an embodiment of the present invention.
  • FIG. 23 is a schematic diagram of the cache metadata record table of FIG. 22 after the read request;
  • 24 is a schematic diagram of reading a mapping table before a read request according to an embodiment of the present invention.
  • 25 is a schematic diagram of the read mapping table of FIG. 24 after the read request is passed;
  • 26 is a schematic diagram of a cache metadata state table before a read request according to an embodiment of the present invention.
  • FIG. 27 is a schematic diagram of the cache metadata status table of FIG. 26 after the read request is passed;
  • FIG. 28 is a schematic diagram of a command sent by a main control module to a back end flash memory according to an embodiment of the present invention
  • FIG. 29 is a schematic diagram of a state table of the cache metadata before the command ID of FIG. 28 is 16;
  • FIG. 30 is a schematic diagram of a cache metadata state table after the command ID of FIG. 28 is 16 is recovered.
  • FIG. 1 is a schematic diagram showing the workflow of a flash memory storage system according to an embodiment of the present invention.
  • the flash memory storage system includes: a cache, a read/write request address mapping module, a cache free block management module, a cache metadata record table, a cache metadata state table, and a main control module, where the main control module is cached.
  • the read and write access requests to the cache are all in the size of 4 KB, and the cache is in accordance with the size of 4 KB.
  • PBN is the physical block num, the physical storage block number, and its corresponding LBN, that is, logic block num, logical storage block number.
  • the cache system virtualizes a small number of logical storage blocks for front-end access. Take 1GB of cache space as an example. It contains 256K physical storage blocks. The cache system can virtualize 1K logical storage blocks (also 4KB size) for use by front-end applications. There is no relationship between this 1K and the previous 256K size. Both values and relationships can be used.
  • the front-end application then issues a command to the cached master module to move the 4KB data in logical memory block 1 to an address in the back-end flash memory, as shown in step 2.
  • the cache does not necessarily write it to the flash memory of the backend storage immediately, but temporarily exists in its own space. However, a completion message is sent to the front-end application to inform them that the data movement has been completed, as shown in step 3.
  • the front-end application receives the completion message and considers that the data has been written to the back-end flash memory, releasing the logical memory block 1. Thus, the subsequent write request can be operated again using the logical memory block 1.
  • the front-end application When the front-end application wants to read the data of a back-end address from the back-end flash memory, it first sends a command to let the cache system move the data of an address at the back end to an idle logical storage block, assuming that the logical storage block 1 , as shown in step 2.
  • the cache will prepare the data and place it on logical storage block 1. It is possible that the data itself is stored in the cache, that is, the cache hit, or it may be read from the backend flash into the cache.
  • a completion message will be sent to inform the front end that the data is ready, as shown in step 3.
  • the front end will read the data of logical address 1 and complete the access, as shown in step 1.
  • the front-end application access also has a delete request requesting the deletion of data from an address stored in the backend. This is to improve flash utilization, only delete requests that are available in flash storage systems.
  • the cache system After receiving this request, the cache system first checks whether the data of the address is stored in itself, and if so, deletes it, and then passes the command to the flash memory of the back end to report the completion of the request to the front end application.
  • Step 4 in Figure 1 is when the cache system sends commands to the backend module during a flush, load, or delete operation.
  • Step 5 is when the backend module completes the flush, load, and del operations, and returns to the cache system.
  • Step 6 is that the backend module controls and completes the exchange of the data in the cache and the data stored in the backend according to the command information of flush and load.
  • FIG. 2 a structural diagram of a flash memory storage system of an embodiment will be described below with respect to each configuration.
  • the physical cache unit is a piece of DDR for storing actual data. It is divided into several physical storage blocks according to the size of 4KB.
  • the front-end application access request reads the data of a logical storage block in the cache.
  • the address mapping module maps the address to an actual physical storage block in the cache according to certain rules. For example, the front-end access request wants to read the data of the cache logical storage block 1, but the current request actually reads the data of the cached physical storage block 15.
  • the read/write request address mapping module has two mapping tables inside, one is a read mapping table, and one is a write mapping table.
  • Each write logical storage block has an entry in the write mapping table, corresponding to a physical storage block, specifically, a write logical storage block number corresponding to a physical storage block number in one entry.
  • Each read logical storage block has an entry in the read mapping table corresponding to one physical storage block. Taking the above as an example, if the cache system provides 1K write logical storage blocks, the write mapping table has 1K entries, which can be stored in a ram.
  • the read and write request address mapping module can be connected in series between the front end and the physical cache unit bus, as shown in FIG. For example, if the read/write request address mapping module can intercept the read address, the logical storage block number of the read address is used as the address index of the read mapping table, and the physical storage block number corresponding to the logical storage block number in the ram is obtained, and the physical storage block is obtained. The number is sent to the physical cache as the final read address.
  • a logical storage block 1 may correspond to the physical storage block 10
  • the next logical access may correspond to the physical storage block 50.
  • the write map will map its write address to another actual physical storage block according to certain rules.
  • the cache free block management module is responsible for managing the application and recycling of cached physical memory blocks. It consists of a reference count table, a free block FIFO queue and a recycle module.
  • the queue depth of the free physical block FIFO is the same as the number of entries in the reference count table. As shown in the above example, it is also 256K, which stores the number of the currently available physical memory block.
  • the free physical block FIFO When the free physical block FIFO is stored as empty, it represents a physical memory block that is currently unavailable. When the free physical block FIFO is not empty, each number in it represents the corresponding physical storage block in the cache is available. In the initial state, all physical memory blocks are in the free physical block FIFO and are in an unused state.
  • the main control module applies for a new physical storage block, it reads a free physical storage block number from the free physical block FIFO and returns it to the main control module for use. When a physical storage block is used and is recycled by the reclaim module, it is written back to the free physical block FIFO.
  • the recycle module is connected to the main control module (FTL) completion queue. Whenever there is new data in the completion queue (that is, a new command is completed), the recovery module will detect the new data, and after processing, pass the information of the completion queue to the main control module.
  • FTL main control module
  • the workflow of the recycling module is as shown in Figure 5.
  • the processing flow of the queue is completed.
  • the processing flow is as follows:
  • the four physical storage blocks in the write command are sequentially read out. Number and read 4 valid flags. For each valid physical storage block number, use its number as the address index of the reference count table, and read out the corresponding counter value (reference number value) in the reference count table. If it is equal to 1, it means that there is only one logical storage block. Mapped to this physical block, set its counter to 0, reclaim the physical block, and write the physical block number back to the free block FIFO. If it is greater than 1, it means that there is more than 1 logical memory block mapped to this physical storage block, and the value of its counter is decremented by 1 (the number of references is set), but it is not recycled.
  • the free physical block FIFO sets the free block reference count value assigned to it to 1 each time a new free block is allocated (the first reference number value).
  • the cache metadata record table is used to record which data is currently cached.
  • Each page size flash memory corresponds to an entry in the cache metadata record table. Taking pagesize16KB as an example, each record in the cache metadata record table corresponds to 16KB space. Since the physical storage block is 4 KB, each entry contains 4 physical storage blocks and a flag indicating whether each physical storage block is valid. Each entry also contains an address for the back-end flash storage (back-end flash address).
  • the storage address (metadata table address) of the cache metadata can be obtained based on the backend address (GBAx) hash transform.
  • the main control module is responsible for processing the request of the front-end application and managing the entire cache.
  • each entry corresponds to a table entry in the cache metadata record table, that is, an address and a cache element of an entry of the cache metadata state table.
  • the address of the corresponding entry of the data record table is the same.
  • the cache metadata status table includes the following flags:
  • the occupation flag bit indicates whether the corresponding entry of the cache metadata status table is being used, and has two values lock and unlock. If it is lock, it means occupation, prohibit operation; if it is unlock, it means unoccupied. Allow operation.
  • the change flag bit indicates whether the 16 KB corresponding to the entry in the cache metadata status table has been changed. It has two values: dirty (indicating that the data has been modified) and clean (indicating that the data has not been modified). For example, a physical storage block that has just been loaded into the cache from the back end flash memory, and the value of the change flag bit of the cache metadata status table corresponding to the physical storage block is clean. The value of the change flag is clean. If there is no change, when the buffer is flushed, it is not necessary to repeatedly write to the back-end flash memory.
  • the empty flag bit indicates whether the corresponding entry of the cache metadata status table is valid. At initialization, the value of the empty flag bit of all entries is empty.
  • the main control module is responsible for processing specific read and write requests, it will parse and execute the read and write commands sent by the front-end application.
  • Front-end commands are divided into three categories: delete request, write request, and read request.
  • the front-end application requests to delete the data on a back-end flash address, and the master module first checks if the address is in the cache. If it is, the cached data is deleted. Then notify the backend module to delete this place The data on the address. After the back-end module is completed, the front-end application is notified via the main control module, and the deletion has been completed.
  • the main control module first reads the write mapping table, obtains the physical storage block number corresponding to the logical storage block number, and then performs hash processing on the back-end flash address to obtain the address of the cached metadata record table (that is, the cache).
  • the address of the metadata status table is the address of the metadata status table.
  • the main control module reads the metadata status table, determines whether the value of the occupied flag bit of the entry corresponding to the address of the cache metadata status table is lock, and if it is a lock, it waits until the value of the occupied flag bit Unlock until.
  • the main control module further reads the value of the empty flag bit of the entry in the metadata status table. If the value of the empty flag of the entry is empty, a new entry is created (the so-called creation is created in the entry, and can also be called assignment in the entry), as shown in Figure 6.
  • the value in the empty entry may be an illegal value, for example, a value greater than the actually allocated physical storage block number, and then the physical storage block number is written into the corresponding position of the entry. Because the write operation size is 4KB, the space of one entry is 16KB, and the position of 4 physical storage blocks is determined. According to the remainder of the back-end flash address divided by 4, the physical storage block is written to the first physical storage block position. .
  • the back-end flash address is 0x0000, and can be divided by 4, written in the first physical storage block position. If it is 0x0002, it is written in the third physical storage block position, and the back end of this entry.
  • the flash address GBAX is 0x0000; then the value of the corresponding physical storage block valid flag is set to be valid, and the four physical storage block valid identifiers are composed of four bit numbers, which in turn represent the first physical storage block to the fourth physical
  • the storage block, 1 is valid, 0 is invalid; then the empty and dirty identifiers of the cache metadata state table are set to not empty and dirty respectively, and the completion command is returned.
  • the main control module further determines whether the current backend flash address in the entry is the same as the backend flash address to be operated this time.
  • the flush command is sent to the backend module.
  • the command format is preceded by a command ID and an operation flag (flush operation), that is, four entries in the entry.
  • the contents of the physical storage block are sequentially stored in the corresponding back-end flash addresses.
  • back-end flash address indicates a cache hit and continues to determine whether the valid flag corresponding to the physical block is valid.
  • the physical storage block number is directly written into the entry, and the corresponding valid bit is marked as valid, and the completion command is returned.
  • the main control module performs hash processing on the back-end flash address to obtain the place of the cache metadata record table.
  • Address that is, the address of the cache metadata status table.
  • the main control module reads the metadata status table to determine whether the lock flag of the entry is a lock. If it is a lock, it will wait until the lock flag is unlock.
  • the main control module further according to the empty flag of the metadata status table. If the empty flag is empty, a new entry is created (that is, the value is assigned in the entry), and a new entry is created. Apply for 4 free physical storage block numbers and write a corresponding physical storage block number to the location requested by the read mapping table. The old physical storage block number of the location is released, and the physical storage block valid flag bits corresponding to the four physical storage blocks are all identified as valid. In the cache metadata status table, the lock flag bit, the empty flag bit, and the clean flag bit are set. They are identified as lock, not empty, and clean.
  • the main control module sends a command, asking the back-end module to read the 16KB data on the back-end flash address to the four physical storage blocks in turn. Because the read takes time, the lock flag of the entry in the cache metadata status table is set to lock, so that the entry is locked, and other commands are not allowed to operate on the entry until the backend module will data. Read it in. After the cache system receives the completion command of the backend module, it returns a completion command to the frontend module, and sets the lock flag bit of the entry in the cache metadata state table to unlock.
  • the main control module further determines whether the current backend flash address in the entry is the same as the backend address to be operated this time.
  • the flush command is sent to the backend module.
  • the command format is preceded by a command ID and an operation flag (flush operation), that is, four physical storage blocks of the entry.
  • the data is stored in the corresponding back-end flash address.
  • Flush do not need to wait for completion
  • create a new entry that is, reassign the entry
  • apply for 4 free physical storage block numbers when creating and write a corresponding physical storage block number to read Map the location of the request and release the old physical storage block number of the corresponding location in the read mapping table.
  • the physical storage block valid flag bits of the four physical storage blocks are identified as valid in the cache metadata state table, and the lock flag bit, the empty flag bit, and the clean flag bit are respectively identified as lock, not empty, and clean.
  • the master module sends a command asking the backend module to read 16KB of data on the backend flash address to the four physical blocks.
  • the main control module of the cache system After the main control module of the cache system receives the completion command of the backend module, the completion command is returned to the front end module, and the lock flag position of the entry in the cache metadata status table is unlock.
  • backend address If the backend address is the same, it indicates a cache hit, and continues to determine whether the physical storage block valid flag corresponding to the physical storage block is valid.
  • the main control module sends a command to request the back-end module to read the data on the back-end flash address to the new physical storage block, but the physical storage block whose original physical storage block identifier is valid will not be overwritten. Only the physical memory blocks that were originally invalid are read and overwritten. Received backend mode in the cache system After the completion command of the block, the completion command is returned to the front-end module, and the lock flag of the corresponding entry is set to unlock.
  • the physical storage block number is written to the location requested by the read mapping table, and the reference count of the physical storage block number is incremented by one, and The old physical storage block number of the location in the read mapping table is released.
  • the reference number of the physical storage block is incremented by one in the reference count table, and when a physical storage block is deleted from the read mapping table, the reference count table is The number of references to the physical memory block is decremented by one to ensure that the physical memory blocks in the read map are not reclaimed.
  • the size is 4KB, which is equal to the front-end application access size.
  • Figure 11 to Figure 15 are the initial state of each data table or memory:
  • the write mapping table In the initial state, the write mapping table has assigned the corresponding physical storage block number for each logical block number, as shown in FIG.
  • the read mapping table remains empty, and all entries are written to an invalid physical storage block number. For example, "X" indicates a value greater than the effective physical storage block number, indicating that the current state is the initial state, so that the front-end application reads in a certain When the logical storage block number is read, no data is returned, as shown in Figure 12.
  • the cache metadata record table is empty, because there is no data stored in the cache, and the cache metadata state table (with 250 entries in it) is empty, unlock, and clean.
  • the free physical block FIFO is full, and all physical storage block numbers (1000) are stored therein. All physical memory blocks in the initial state are unused idle states.
  • the master module In the initial state, the master module first applies for 100 physical storage blocks (the number of logical storage blocks) in the idle FIFO queue, writes them to the write mapping table, and assigns a physical to each logical storage block in the write mapping table. Store the block number. Since all physical storage blocks are initially in the free physical block FIFO, after the main control module allocates the first 100 physical storage block numbers to the write mapping table, the free physical block FIFO has only 900 physical storage blocks left, as shown in FIG. Shown. Subsequent physical storage blocks are used differently, and the recycling order is different. The order of the physical storage block numbers in the free physical block FIFO will be messy.
  • the first write request as shown in Figures 16-21.
  • the front-end application writes the data to logical storage block 1 first. Since there is a write mapping table, at this time, logical address 1 corresponds to physical storage block 1, so the data is actually written into physical storage block 1.
  • the front-end application sends a command to write the data of logical storage block 1 to an address GBAx of the back end, assuming that the lowest two bits of GBAx are 00.
  • the master control module receives this command and hashes the GBAx, and the corresponding cache metadata address index is 15 (hypothesis). And querying the write address mapping table, and obtaining that the current logical storage block 1 corresponds to the physical storage block 1.
  • the main control module reads the cache metadata status table and finds that the status of the entry of address 15 is empty, unlock, and clean (because all entries are initialized after initialization).
  • the main control module creates a new entry in the location of the cache metadata record table 15 and writes the physical storage block 1 to the first physical storage block location.
  • the four cases of the lowest two bits of GBAx 00 to 11 determine that the physical storage block is to be written to the first position, which in turn corresponds to the first physical storage block position of the entry to the fourth physical storage block position.
  • the last two digits of GBAx in the cache metadata record table are 0, because the size of one entry in the metadata record table is 16 KB, which is 4 times larger than the front-end command 4 KB address, so the last two addresses are recorded as 0.
  • Unlock and dirty refer to the newer data of this entry (and the data stored by the backend GBAx). ratio).
  • the main control module applies for a new physical storage block (assumed to be 101) to the idle physical block FIFO, and writes the first position of the write mapping table (the position of the logical storage block 1), as shown in FIG. 19, and now writes the logical storage again. Block 1, actually writes to physical memory block 101.
  • the main control module returns a command completion to the front end application.
  • the front-end application sends a command requesting that the data of the back-end address GBAy be read onto the logical storage block 2. Then the front-end application waits for the command to complete, and then accesses the logical storage block 2 to obtain the data.
  • the main control module performs a hash calculation on GBAy, and obtains that the address of the corresponding cache metadata record table is 30 (hypothesis).
  • the entry of the current address 30 has data, but the backend storage address corresponding to the entry is GBAz, which is different from the backend address GBAy to be accessed, that is, the cache does not hit, and needs to be
  • the data of this entry (that is, the old entry) is first written to the back-end flash and the new data needed is loaded.
  • the main control module first finds that the metadata address 30 has data, but the backend address GBAz is not equal to GBAy.
  • the main control module reads the status table and finds that the dirty flag of the location of the metadata address 30 is dirty, indicating that the data of the corresponding four physical storage blocks needs to be written to the back-end flash memory.
  • the main control module sends a command to notify the backend module to write the data of the physical storage block 123, the physical storage block 75, the physical storage block 50, and the physical storage block 100 (16 KB in total) into the 16 KB space starting from the address of GBAz.
  • the main control module does not need to wait for the previous command to complete, and immediately erases the entry 30 of the metadata record table, and creates a new entry, that is, re-assigns the entry 30.
  • Applying 4 new physical storage blocks to the cache free block management module assuming physical storage block 400, physical storage block 500, physical storage block 600, and physical storage block 700, sequentially writing them to the first to fourth positions Physical storage block location.
  • the physical memory block 500 at the second physical memory block location is written to the location of the read mapping table 2.
  • the old physical memory block corresponding to the read mapping table 2 is the physical memory block 20, where the request for front-end access indicates that the data of the logical memory block 2 is no longer needed, and thus the physical memory block 20 is released.
  • the physical memory block 20 does not necessarily write to the free physical block FIFO, depending on the current reference count of the physical memory block 20. This section describes the specific process in the recycling module.
  • the main control module sends a command again, requesting the back-end module to sequentially read the 16KB data starting from GBAy (address low 2 bits to 0, address 16KB alignment) to physical storage blocks 400, 500, 600, and 700 (4 KB per physical storage block). in.
  • GBAy address low 2 bits to 0, address 16KB alignment
  • the master module sets this entry to lock, clean, and not empty in the cache metadata state table.
  • the main control module Since the reading takes time, the main control module does not immediately return the completion command to the front end. He needs to wait for the backend module to return the reading completion, and then the lock flag of the entry 30 is set to unlock.
  • a backend command is completed, as shown in Figures 28-30.
  • the cache system issues two commands to the back-end flash memory, the command ID number 15 is a flush (write) operation, and the command ID number 16 is a load (read) operation. Now the backend module returns these two commands to complete.
  • the reclaim module For the command with ID number 15, the reclaim module first checks that the operation type is a write operation, and then the valid physical storage block number, in this case, two, physical storage block 18 and physical storage block 2, are discarded. The recycling process is still carried out as described previously.
  • the front end is not notified after the reclamation is completed, because the command return of the write operation has been returned before.
  • the recovery module performs a hash calculation on GBAy. According to the above example, it corresponds to the 30th entry of the metadata record table. At that time, the cache system sets the lock flag of the entry to lock. At this time, the data is read back, and the cache system will set the lock flag of the entry to unlock, and notify the front-end module that the previous read command is completed.

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Abstract

一种闪存存储系统及其读写、删除方法，闪存存储系统包括缓存、主控模块、缓存元数据记录表、读映射表和写映射表，所述写映射表用于存储在缓存中写入逻辑存储块与物理存储块的对应关系，所述读映射表用于存储在缓存中读出逻辑存储块与物理存储块的对应关系，所述缓存元数据记录表用于存储元数据表地址、物理存储块和后端闪存地址之间的对应关系。本闪存存储系统，可以减少对后端闪存的不必要写入或读出，实现读写数据通路上的零拷贝，消除不必要的中间拷贝过程，从而提高读写效率；并且可以使前端应用的读写访问与后端闪存大小相匹配。

Description

一种闪存存储系统及其读写、删除方法 【技术领域】
本发明涉及存储领域，具体涉及一种闪存存储系统及其读写、删除方法。
【背景技术】
使用NAND Flash的固态存储系统逐渐成为一种新的广受欢迎的存储系统(Solid State Disk，SSD)。随着闪存技术的发展，MLC(Multi-Level Cell)的单page容量从4KB逐渐发展到8KB，16KB，32KB，随着TLC技术的成熟，单page容量会达到64KB，128KB甚至更高。然而Flash的使用寿命是有限的(25nm MLC擦写次数在3000次左右)。零拷贝(zero-copy)最初是实现主机或路由器等设备高速网络接口的主要技术。零拷贝技术后来泛指可以减少数据拷贝和共享总线操作的次数，消除数据在存储器之间不必要的中间拷贝过程，有效地提高通信效率，是设计高速接口通道、实现高速服务器和路由器的关键技术之一。当前缓存技术的两大不足：
由于Flash使用寿命有限，在Flash之前增加一级缓存，从而减少对Flash的擦写，是传统通用做法，但存储系统读写访问大小是4KB，而闪存的写入单位是page。而随着闪存技术发展，单page的容量可达16KB，32KB。如果按照传统做法，以访问请求大小4KB作为缓存的load，flush单位，则会造成写放大。增加Flash擦写次数，降低Flash寿命。如果单纯按照page大小申请缓存，则会造成缓存空间的浪费，从而降低缓存命中率。传统闪存的缓存在读写时，需要经过两次数据拷贝，从而降低了缓存的访问速度。影响整个存储系统的性能。
【发明内容】
为了克服现有技术的不足，本发明提供了一种闪存存储系统及其读写、删除方法，以减少缓存与后端闪存之间的中间拷贝过程。
一种闪存存储系统的写数据方法，所述闪存存储系统包括缓存、主控模块、缓存元数据记录表和写映射表；其中，所述写映射表用于存储在缓存中写入逻辑存储块与物理存储块的对应关系，所述缓存元数据记录表用于存储元数据表地址、物理存储块和后端闪存地址之间的对应关系；所述闪存存储系统的写数据方法包括如下步骤：
S1，所述主控模块接收前端应用发出的将第一写入逻辑存储块中的数据写入第一后端闪存地址的命令；S2，所述主控模块读取所述写映射表，获取与所述第一写入逻辑存储块对应的所述缓存中的第一物理存储块；S3，所述主控模块对所述第一后端闪存地址进行计算，获得与所述第一后端闪存地址对应的第一元数据表地址；S4，所述主控模块读取所述缓存元数据记录表，获取与所述第一元数据表地址对应的当前后端闪存地址；S5，所述主控模块判断所述第一后端闪存地址与当前后端闪存地址是否相同；S6，若所述第一后端闪存地址与所述当前后端闪存地址相同，则将所述第一物理存储块替换所述缓存元数据记录表中与所述当前后端闪存地址对应的当前物理存储 块；S7，若所述第一后端闪存地址与所述当前后端闪存地址不同，则将所述缓存元数据记录表中与所述当前后端闪存地址对应的当前物理存储块的数据存储到后端闪存的当前后端闪存地址中，并将所述第一后端闪存地址和第一物理存储块分别替代所述当前后端闪存地址和当前物理存储块。
在一个实施例中，所述闪存存储系统还包括引用计数表、空闲物理块FIFO和回收模块，所述空闲物理块FIFO用于存放所述缓存中空闲的物理存储块，所述计数表用于存储物理存储块与对应的引用次数，当所述空闲物理块FIFO将空闲的物理存储块分配出去时，将分配出去的物理存储块的引用次数设置为第一引用次数值；还包括回收物理存储块步骤：对于被替换的物理存储块，读取所述引用计数表中对应物理存储块的引用次数，若对应物理存储块的引用次数大于所述第一引用次数值则将对应的物理存储块的引用次数减设定引用次数，若对应物理存储块的引用次数等于第一引用次数值，则所述回收模块将对应的物理存储块写入所述空闲物理块FIFO中。
在一个实施例中，所述缓存元数据记录表还用于存储与物理存储块对应的物理存储块有效标志位，在所述物理存储块存储数据之前对应的物理存储块有效标志位的值被置为非有效值，在所述物理存储块存储数据之后对应的物理存储块有效标志位的值被置为有效值；在所述步骤S6中，在将所述第一物理存储块替换所述缓存元数据记录表中与所述当前后端闪存地址对应的当前物理存储块之前，还包括如下步骤：在所述缓存元数据记录表中判断所述当前后端闪存地址对应的当前物理存储块的物理存储块有效标志位的值是有效值还是非有效值，若是有效值则执行回收物理存储块步骤。
在一个实施例中，所述闪存存储系统还包括缓存元数据状态表；所述缓存元数据记录表中，所述物理存储块具有多个，多个物理存储块分别与以所述后端闪存地址为基准的连续多个后端闪存地址相对应；所述缓存元数据记录表还用于存储与物理存储块对应的物理存储块有效标志位，在物理存储块存储数据之前对应的物理存储块有效标志位的值被置为非有效值，在物理存储块存储数据之后对应的物理存储块有效标志位的值被置为有效值；所述缓存元数据状态表用于存储元数据表地址、占用标志位和空标志位之间的对应关系，所述占用标志位的值包括分别表示所述元数据表地址对应的表项被占用和没有被占用的占用值和非占用值，所述空标志位的值包括分别表示所述元数据表地址中的物理存储块被写入数据和没有被写入数据的非空值和空值；在所述步骤S3与步骤S4之间，还包括如下步骤：S3.1，所述主控模块读取所述缓存元数据记录表，判断所述第一元数据表地址对应的占用标志位的值是否为占用值，若是则等待，否则执行步骤S3.2；S3.2，所述主控模块判断所述第一元数据表地址对应的空标志位的值是否为非空值，若是则执行步骤S4；在所述步骤S6中，还包括如下步骤：S6.1，判断所述缓存元数据记录表中，与所述第一后端闪存地址对应的物理存储块的物理存储块有效标识的值是否为有效值；S6.2，若是有效值则执行回收物理存储块步骤，并执行步骤S6.4；S6.3，若不是有效值则将对应的物理存储块有效标识的值设为有效值，并执行步骤S6.4；S6.4，将所述第一物理存储块写入所述缓存元数据记录表 的对应位置。
在一个实施例中，在步骤S6和步骤S7后，从所述空闲物理块FIFO中为所述第一写入逻辑存储块分配新的物理存储块。
本发明还提供了一种闪存存储系统的读数据方法，所述闪存存储系统包括缓存、主控模块、缓存元数据记录表和读映射表；其中，所述读映射表用于存储在缓存中读出逻辑存储块与物理存储块的对应关系，所述缓存元数据记录表用于存储元数据表地址、物理存储块和后端闪存地址之间的对应关系；所述闪存存储系统的读数据方法包括如下步骤：S1，所述主控模块接收前端应用发出的将第一后端闪存地址的数据写入第一读出逻辑存储块中的命令；S2，所述主控模块对所述第一后端闪存地址进行计算，获得与所述第一后端闪存地址对应的第一元数据表地址；S3，所述主控模块读取所述缓存元数据记录表，获取与所述第一元数据表地址对应的当前后端闪存地址；S4，所述主控模块判断所述第一后端闪存地址与当前后端闪存地址是否相同；S5，若所述第一后端闪存地址与所述当前后端闪存地址相同，则将所述缓存元数据记录表中与所述第一后端闪存地址对应的当前物理存储块写入所述读映射表中且与所述第一读出逻辑存储块相对应；S6，若所述第一后端闪存地址与所述当前后端闪存地址不同，则将所述缓存元数据记录表中与所述当前后端闪存地址对应的当前物理存储块的数据存储到后端闪存的当前后端闪存地址中，并将所述第一后端闪存地址和新的物理存储块分别替代所述当前后端闪存地址和当前物理存储块，并将所述新的物理存储块写入所述读映射表中且与所述第一读出逻辑存储块相对应。
在一个实施例中，所述闪存存储系统还包括引用计数表、空闲物理块FIFO和回收模块，所述空闲物理块FIFO用于存放所述缓存中空闲的物理存储块，所述计数表用于存储所述物理存储块与对应的引用次数，当所述空闲物理块FIFO将空闲的物理存储块分配出去时，将分配出去的物理存储块的引用次数设置为第一引用次数值；还包括回收物理存储块步骤：在步骤S5中，当所述第一后端闪存地址对应的当前物理存储块写入所述读映射表中后，还包括如下步骤：S5.1，将与所述第一后端闪存地址对应的当前物理存储块的引用次数增加设定引用次数，并将所述读映射表中与所述第一读出逻辑存储块对应的旧的物理存储块的引用次数减所述设定引用次数；在步骤S6中，将所述新的物理存储块写入所述读映射表中后，还包括如下步骤：S6.1，将所述新的物理存储块的引用次数增加设定引用次数，并将所述读映射表中与所述第一读出逻辑存储块对应的旧的物理存储块的引用次数减所述设定引用次数；对于替换和被替换的物理存储块，读取所述引用计数表中物理存储块的引用次数，若物理存储块的引用次数大于所述第一引用次数值，则将对应的物理存储块的引用次数减设定引用次数，若物理存储块的引用次数等于第一引用次数值，则所述回收模块将对应的物理存储块写入所述空闲物理块FIFO中。
在一个实施例中，所述闪存存储系统还包括缓存元数据状态表；所述缓存元数据记录表中，所述物理存储块具有多个，多个物理存储块分别与以所述后端闪存地址为 基准的连续多个后端闪存地址相对应；所述缓存元数据记录表还用于存储与物理存储块对应的物理存储块有效标志位，在物理存储块存储数据之前对应的物理存储块有效标志位的值被置为非有效值，在物理存储块存储数据之后对应的物理存储块有效标志位的值被置为有效值；所述缓存元数据状态表用于存储元数据表地址、占用标志位和空标志位之间的对应关系，所述占用标志位的值包括分别表示所述元数据表地址对应的表项被占用和没有被占用的占用值和非占用值，所述空标志位的值包括分别表示所述元数据表地址中的物理存储块被写入数据和没有被写入数据的非空值和空值；在所述步骤S2与步骤S3之间，还包括如下步骤：S3.1，所述主控模块读取所述缓存元数据记录表，判断所述第一元数据表地址对应的占用标志位的值是否为占用值，若是则等待，否则执行步骤S3.2；S3.2，所述主控模块判断所述第一元数据表地址对应的空标志位的值是否为非空值，若是则执行步骤S3；在所述步骤S5中，还包括如下步骤：S5.1，判断所述缓存元数据记录表中，与所述第一后端闪存地址对应的物理存储块的物理存储块有效标识的值是否为有效值；S5.2，若是有效值则执行回收物理存储块步骤；S5.3，若不是有效值则将对应的物理存储块有效标识的值设为有效值。
本发明还一种闪存存储系统的删除数据方法，所述闪存存储系统包括缓存、主控模块和缓存元数据记录表；其中，所述缓存元数据记录表用于存储元数据表地址、物理存储块和后端闪存地址之间的对应关系；所述闪存存储系统的删除数据方法包括如下步骤：S1，所述主控模块接收前端应用发出的删除第一后端闪存地址的数据的命令；S2，所述主控模块对所述第一后端闪存地址进行计算，获得与所述第一后端闪存地址对应的第一元数据表地址；S3，所述主控模块读取所述缓存元数据记录表，获取与所述第一元数据表地址对应的当前后端闪存地址；S4，所述主控模块判断所述第一后端闪存地址与当前后端闪存地址是否相同；S5，若所述第一后端闪存地址与所述当前后端闪存地址相同，则将当前后端闪存地址对应的表项删除，并执行步骤S7；S6，若所述第一后端闪存地址与所述当前后端闪存地址不同，则执行步骤S7；S7，将所述删除第一后端闪存地址的数据的命令发送到后端闪存。
本发明还提供了一种闪存存储系统，包括缓存、主控模块、缓存元数据记录表、读映射表和写映射表；其中，所述写映射表用于存储在缓存中写入逻辑存储块与物理存储块的对应关系，所述读映射表用于存储在缓存中读出逻辑存储块与物理存储块的对应关系，所述缓存元数据记录表用于存储元数据表地址、物理存储块和后端闪存地址之间的对应关系；所述主控模块用于接收前端应用发出的将第一写入逻辑存储块中的数据写入第一后端闪存地址的命令；所述主控模块用于读取所述写映射表，获取与所述第一写入逻辑存储块对应的所述缓存中的第一物理存储块；所述主控模块用于对所述第一后端闪存地址进行计算，获得与所述第一后端闪存地址对应的第一元数据表地址；所述主控模块用于读取所述缓存元数据记录表，获取与所述第一元数据表地址对应的当前后端闪存地址；所述主控模块用于判断所述第一后端闪存地址与当前后端闪存地址是否相同，若所述第一后端闪存地址与所述当前后端闪存地址相同，则将所 述第一物理存储块替换所述缓存元数据记录表中与所述当前后端闪存地址对应的当前物理存储块；若所述第一后端闪存地址与所述当前后端闪存地址不同，则将所述缓存元数据记录表中与所述当前后端闪存地址对应的当前物理存储块的数据存储到后端闪存的当前后端闪存地址中，并将所述第一后端闪存地址和第一物理存储块分别替代所述当前后端闪存地址和当前物理存储块；所述主控模块用于接收前端应用发出的将第一后端闪存地址的数据写入第一读出逻辑存储块中的命令；所述主控模块用于对所述第一后端闪存地址进行计算，获得与所述第一后端闪存地址对应的第一元数据表地址；所述主控模块用于读取所述缓存元数据记录表，获取与所述第一元数据表地址对应的当前后端闪存地址；所述主控模块用于判断所述第一后端闪存地址与当前后端闪存地址是否相同；若所述第一后端闪存地址与所述当前后端闪存地址相同，则将所述缓存元数据记录表中与所述第一后端闪存地址对应的当前物理存储块写入所述读映射表中且与所述第一读出逻辑存储块相对应；若所述第一后端闪存地址与所述当前后端闪存地址不同，则将所述缓存元数据记录表中与所述当前后端闪存地址对应的当前物理存储块的数据存储到后端闪存的当前后端闪存地址中，并将所述第一后端闪存地址和新的物理存储块分别替代所述当前后端闪存地址和当前物理存储块，并将所述新的物理存储块写入所述读映射表中且与所述第一读出逻辑存储块相对应。
在一个实施例中，所述闪存存储系统还包括引用计数表、空闲物理块FIFO和回收模块，所述空闲物理块FIFO用于存放所述缓存中空闲的物理存储块，所述计数表用于存储所述物理存储块与对应的引用次数，当所述空闲物理块FIFO将空闲的物理存储块分配出去时，将分配出去的物理存储块的引用次数设置为第一引用次数值；当所述第一后端闪存地址对应的当前物理存储块写入所述读映射表中后，将与所述第一后端闪存地址对应的当前物理存储块的引用次数增加设定引用次数，并将所述读映射表中与所述第一读出逻辑存储块对应的旧的物理存储块的引用次数减所述设定引用次数；将所述新的物理存储块写入所述读映射表中后，将所述新的物理存储块的引用次数增加设定引用次数，并将所述读映射表中与所述第一读出逻辑存储块对应的旧的物理存储块的引用次数减所述设定引用次数；对于替换和被替换的物理存储块，读取所述引用计数表中物理存储块的引用次数，若物理存储块的引用次数大于所述第一引用次数值，则将对应的物理存储块的引用次数减设定引用次数，若物理存储块的引用次数等于第一引用次数值，则所述回收模块将对应的物理存储块写入所述空闲物理块FIFO中。
在一个实施例中，所述缓存元数据记录表的一个表项中具有四个物理存储块，每个物理存储块的大小为4KB。
本闪存存储系统，可以减少对后端闪存的不必要写入或读出，实现读写数据通路上的零拷贝，消除不必要的中间拷贝过程，从而提高读写效率；并且可以使前端应用的读写访问与后端闪存大小相匹配。
【附图说明】
图1是本发明一种实施例的闪存存储系统工作流程示意图；
图2是本发明一种实施例的闪存存储系统原理框图；
图3是本发明一种实施例的缓存中逻辑存储块和物理存储块地址转换示意图；
图4是本发明一种实施例的回收物理存储块的流程示意图；
图5是本发明一种实施例的命令完成队列处理流程示意图；
图6是本发明一种实施例的缓存元数据记录表示意图；
图7是本发明一种实施例的缓存元数据状态表示意图；
图8是本发明一种实施例的删除后端闪存数据的流程示意图；
图9是本发明一种实施例的向后端闪存写入数据的流程示意图；
图10是本发明一种实施例的从后端闪存读入数据的流程示意图；
图11是本发明一种实施例的初始状态时写映射表示意图；
图12是本发明一种实施例的初始状态时读映射表示意图；
图13是本发明一种实施例的初始状态时缓存元数据状态表示意图；
图14是本发明一种实施例的初始状态时空闲物理块FIFO存储示意图；
图15是图14的空闲物理块FIFO在分配一部分物理存储块给写映射表后的示意图；
图16是本发明一种实施例的第一次写请求前缓存元数据记录表示意图；
图17是图16的缓存元数据记录表在第一次写请求后的示意图；
图18是本发明一种实施例的第一次写请求前写映射表的示意图；
图19是图18的写映射表在第一次写请求后的示意图；
图20是本发明一种实施例的第一次写请求前缓存元数据状态表的示意图；
图21是本发明一种实施例的缓存元数据状态表在第一次写请求后的示意图；
图22是本发明一种实施例的在某一次读请求前缓存元数据记录表的示意图；
图23是图22缓存元数据记录表在该次读请求后的示意图；
图24是本发明一种实施例的在某一次读请求前读映射表的示意图；
图25是图24的读映射表在经过该次读请求后的示意图；
图26是本发明一种实施例的在某一次读请求前缓存元数据状态表的示意图；
图27是图26的缓存元数据状态表在经过该次读请求后的示意图；
图28是本发明一种实施例的主控模块发送给后端闪存的命令示意图；
图29是图28的命令ID为16回收前缓存元数据状态表示意图；
图30是图28的命令ID为16回收后缓存元数据状态表示意图。
【具体实施方式】
以下对发明的较佳实施例作进一步详细说明。
如图1所示，本发明一种实施例的闪存存储系统工作流程示意图。
在本实施例中，本闪存存储系统包括：缓存、读写请求地址映射模块、缓存空闲块管理模块、缓存元数据记录表、缓存元数据状态表和主控模块，所述主控模块在缓存系统内。
本实施例中，对缓存的读写访问请求都是以4KB为大小，将缓存按照4KB的大小 划分为若干个物理存储块。例如容量为1GB的DDR，会划分为1GB/4KB＝256K个物理存储块，称为PBN1～PBN256K。PBN即physical block num，物理存储块编号，与其对应的是LBN，即logic block num，逻辑存储块编号。
缓存系统会虚拟少量逻辑存储块，给前端访问使用，以1GB缓存空间为例，它含有256K个物理存储块。缓存系统可以虚拟出1K个逻辑存储块(也是4KB大小)，给前端应用使用，这个1K和前面的256K大小之间没有关系，两者可以采用其他的数值及关系。
前端应用写访问时，首先先选择1个空闲的逻辑存储块(初始时所有块都是空闲的)，将数据写入该逻辑存储块，假设为逻辑存储块1，如图1的步骤1所示。
然后前端应用向缓存的主控模块发命令，让其将逻辑存储块1内的4KB数据搬到后端闪存存储的某个地址，如步骤2所示。
缓存不一定立刻将其实际写入后端存储的闪存中，而是暂时存在自身空间内。但会向前端应用发送一个完成消息，告知其此数据搬移已经完成，如步骤3所示。
前端应用收到完成消息，认为该数据已经写入后端的闪存，将逻辑存储块1释放掉。这样后面的写请求就可以再次利用逻辑存储块1进行操作。
前端应用想从后端闪存中读取某个后端地址的数据时，先送命令，让缓存系统将后端某个地址的数据搬到某个空闲的逻辑存储块，假设是逻辑存储块1，如步骤2所示。
缓存会将数据准备好，放在逻辑存储块1上。有可能这个数据本身就存在缓存内，即缓存命中，也可能是从后端闪存读进缓存内的。
缓存准备好后，会送完成消息，告知前端数据已经准备好，如步骤3所示。
前端会读取逻辑地址1的数据，完成访问，如步骤1所示。
除了读写请求，前端应用访问会还有一种删除请求，请求将后端存储的某个地址的数据删除。这是为了提高闪存利用率，只有闪存存储系统才有的删除请求。接收到这个请求后，缓存系统会首先检查自身内是否储存了该地址的数据，如果有，则将其删除，然后将这个命令传递给后端的闪存，向前端应用报告请求完成。
图1中的步骤4是缓存系统在写(flush)、读(load)或删除(del)操作时向后端模块发送命令。
步骤5是后端模块完成flush，load，del操作时，向缓存系统返回完成。
步骤6是后端模块根据flush和load的命令信息，控制并完成缓存内数据和后端存储数据的交换。
如图2所示，一种实施例的闪存存储系统结构图，以下对各个构成进行说明。
物理存储块
也即物理缓存单元，是一块DDR，用于存储实际的数据。它被按照4KB的大小，划分为若干个物理存储块。
读写请求地址映射模块
如图3所示，前端应用访问请求在读取缓存中的某一逻辑存储块的数据时，读请 求地址映射模块会按照一定的规则将该地址映射到缓存中某一实际的物理存储块上。例如，前端访问请求想读取缓存逻辑存储块1的数据，但本次请求实际读取的是缓存的物理存储块15的数据。
读写请求地址映射模块内部有两张映射表，一张是读映射表，一张是写映射表。每一个写入逻辑存储块在写映射表中都有一个表项，对应一个物理存储块，具体是一个表项中一个写入逻辑存储块号对应一个物理存储块号。每一个读出逻辑存储块在读映射表中都有一个表项，对应一个物理存储块。以上面为例，假设缓存系统提供1K个写入逻辑存储块，则该写映射表有1K个表项，可以存放在一个ram中。
读写请求地址映射模块可以串联在前端和物理缓存单元总线之间，如图2所示。例如读写请求地址映射模块可以截取读地址，则用读地址的逻辑存储块号，作为读映射表的地址索引，获取ram中该逻辑存储块号对应的物理存储块号，将此物理存储块号作为最终读地址发送给物理缓存。
读映射表和写映射表中的内容是由主控模块实时动态更新的。某一次逻辑存储块1可能对应物理存储块10，下一次访问时，逻辑存储块1可能就对应物理存储块50了。
和读请求地址映射类似，前端访问请求在写缓存中某一块数据时，写映射表会按照一定的规则将其写地址映射到其他的某一实际物理存储块上。
缓存空闲块管理模块
缓存空闲块管理模块负责管理缓存的物理存储块的申请和回收。它包括1张引用计数表、1个空闲块FIFO队列和1个回收模块组成。
对于所有缓存的物理存储块，引用计数表都有一个对应的表项，以上面为例：容量为1GB的DDR，会划分为1GB/4KB＝256K个物理存储块，则引用计数表内会有256K个表项。
空闲物理块FIFO的队列深度和引用计数表的表项数相同，如上例所示，也是256K，存放的是当前空闲可用的物理存储块的编号。当空闲物理块FIFO存储为空时，代表当前无可用的物理存储块。当空闲物理块FIFO不为空时，里面每一个数字代表缓存中对应的物理存储块可用。初始状态时，所有物理存储块都在空闲物理块FIFO中，都是未使用的状态。当主控模块申请使用新的物理存储块时，会从空闲物理块FIFO中读出一个空闲物理存储块编号，返回给主控模块使用。当某一个物理存储块使用完毕，被回收模块回收时，会被再写回空闲物理块FIFO。
回收模块与主控模块(FTL)完成队列相连。每当完成队列有新数据时(即有新的命令完成了)，回收模块会检测新数据，处理后，将完成队列的信息传递给主控模块。
如图4所示是回收模块工作流程，如图5所示是完成队列处理流程，处理流程如下：
1.若此完成的命令是读命令(load)，或者删除命令。则不进行任何操作，直接传递给主控模块。
2.若此完成的命令是写命令(flush)，则依次读出该写命令中4个物理存储块编 号，并读出4个有效标志位。对每一个有效的物理存储块编号，把其编号作为引用计数表的地址索引，读出引用计数表中对应的计数器值(引用次数值)，如果其等于1，则表示只有1个逻辑存储块映射到了这个物理存储块上，将其计数器置为0，把物理存储块回收掉，将该物理存储块编号写回空闲物理块FIFO。如果其大于1，表示有多余1个逻辑存储块映射到了这个物理存储块上，将其计数器的值减1(设定引用次数)，但不将其回收。
空闲物理块FIFO在每次分配新空闲块时，会将其分配出去的空闲块引用计数值设为1(第一引用次数值)。
缓存元数据记录表
如图6所示，缓存元数据记录表用来记录缓存当前缓存了哪些数据。
每一个page size大小的闪存，对应缓存元数据记录表中的一个表项。以pagesize16KB为例，缓存元数据记录表中每一条记录对应的是16KB空间。由于物理存储块时是4KB，则每一个表项内包含4个物理存储块以及每个物理存储块是否有效的标志。每一条表项还包含一个后端闪存存储的地址(后端闪存地址)。缓存元数据的存放地址(元数据表地址)可以是基于后端地址(GBAx)hash变换得到的。
主控模块
主控模块负责处理前端应用的请求，管理整个缓存。
如图7所示，它包括一个缓存元数据状态表，每一个表项都和缓存元数据记录表中的表项一一对应，即缓存元数据状态表的某一个表项的地址与缓存元数据记录表的对应表项的地址相同。
缓存元数据状态表包括以下标志位：
占用标志位(lock标志位)，表明缓存元数据状态表的对应表项是否正在被使用，其具有两个值lock和unlock，若是lock则表示占用，禁止操作；若是unlock则表示未被占用，允许操作。
改动标志位(dirty标志位)，表明缓存元数据状态表对应表项对应的16KB是否经过改动，其具有dirty(表示数据被改动过)和clean(表示数据没有被改动过)两个值。例如刚从后端闪存读(load)进缓存的某个物理存储块，该物理存储块对应的缓存元数据状态表的改动标志位的值为clean。对于改动标志位的值是clean的，在没有更改过的情况下，在写(flush)出缓存时，是不用重复写到后端闪存存储的。
空标志位(empty标志位)，表明缓存元数据状态表的对应表项是否有效，在初始化时，所有表项的空标志位的值都是empty。
主控模块负责处理具体读写请求，它会解析并执行前端应用发来的读写命令。
前端命令分为3类：删除请求、写请求和读请求
删除请求
如图8所示，前端应用请求删除某个后端闪存地址上的数据，主控模块会先检查此地址是否在缓存内。若在，则将缓存的数据删除。然后通知后端模块删除掉这个地 址上的数据。后端模块完成后，经由主控模块通知前端应用，已完成删除。
写请求
如图9所示，主控模块先读取写映射表，获得逻辑存储块号对应的物理存储块号，然后对后端闪存地址做hash处理，得到缓存元数据记录表的地址(也即缓存元数据状态表的地址)。
主控模块读取元数据状态表，判断该缓存元数据状态表的地址对应的表项的占用标志位的值是否为lock，如果是lock，则会一直等待，等到该占用标志位的值为unlock为止。
如果该表项的占用标志位的值为unlock，则主控模块进一步读取元数据状态表中该表项的空标志位的值。若该表项的空标志位的值为empty，则创建一个新表项(此处所谓创建，是在该表项中创建，也可以称之为在该表项中赋值)，如图6所示，空的表项中的数值可以是一个非法值，例如是大于实际分配的物理存储块号的数值，然后将该物理存储块号写进该表项的对应位置。因为写操作大小是4KB，一条表项的空间是16KB，包含4个物理存储块的位置，根据后端闪存地址除以4的余数，来决定该物理存储块写入第儿个物理存储块位置。例如，后端闪存地址后儿位是0x0000，可以整除4，则写在第一个物理存储块位置上，若是0x0002，则写在第三个物理存储块位置上，而这个表项的后端闪存地址GBAX则为0x0000；然后将对应的物理存储块有效标志的值设成有效，四个物理存储块有效标识由四个比特位数组成，依次表示第一个物理存储块至第四个物理存储块，1代表有效，0代表无效；然后再把缓存元数据状态表的empty标识、dirty标识分别设成not empty和dirty，返回完成命令。
如果该表项空标志位的值为not empty，则主控模块进一步判断表项中的当前后端闪存地址是否和本次要操作的后端闪存地址相同。
如果不同，则将该表项的内容发送一条flush命令到后端模块，命令格式是表项内容前面附加上一个命令ID和操作标志(flush操作)，也就是说，将该表项中四个物理存储块中的内容依次存储到对应的后端闪存地址中。
然后创建新表项(对该表项重新赋值)，和前面一样，将本次写操作的物理存储块号写到对应位置，将对应的物理存储块有效标志设成有效，把元数据状态表的empty标识和dirty标识分别设成not empty和dirty，返回完成命令。
如果后端闪存地址相同，则说明缓存命中，继续判断该物理存储块对应的有效标志是否有效。
若无效，则该地址还没写入数据，直接将该物理存储块号写入表项，并将对应有效位标识成有效，返回完成命令。
若有效，则该地址的数据被覆盖，将旧的物理存储块号回收，再将该物理存储块号写入表项。返回完成命令。
读请求
如图10所示，主控模块对后端闪存地址做hash处理，得到缓存元数据记录表的地 址(也即缓存元数据状态表的地址)。
主控模块读取元数据状态表，判断该表项的lock标识位是否为lock，如果为lock，则会一直等待，等到lock标志位为unlock为止。
如果该表项的标志位是unlock，则主控模块进一步根据元数据状态表的empty标志位，若empty标志位为empty，则创建一个新表项(也即在该表项中赋值)，创建的时候申请4个空闲的物理存储块号，并将其中对应的一个物理存储块号写到读映射表请求的位置上。将该位置的旧物理存储块号释放，将4个物理存储块对应的物理存储块有效标志位都标识为有效，在缓存元数据状态表中，将lock标志位、empty标志位和clean标识位分别标识为lock、not empty和clean。然后主控模块发送一条命令，要求后端模块将后端闪存地址上的16KB数据依次分别读到这4个物理存储块上。由于读取需要时间，此时将缓存元数据状态表中该表项的lock标志位设置为lock，从而将该表项锁定，不允许其他命令对此表项进行操作，直到后端模块将数据读入为止。在缓存系统接收到后端模块的完成命令后，才会向前端模块返回完成命令，并将缓存元数据状态表中的该表项的lock标志位设置为unlock。
如果该表项的empty标志位为not empty，则主控模块进一步判断该表项中的当前后端闪存地址是否和本次要操作的后端地址相同。
如果不同，则将该表项的内容发送一条flush命令到后端模块，命令格式是表项内容前面附加上一个命令ID和操作标志(flush操作)，即将该表项的四个物理存储块中的数据存储到对应的后端闪存地址中。Flush后(不需要等待完成)，创建一个新表项(即对该表项重新赋值)，创建的时候申请4个空闲的物理存储块号，并将其中对应的一个物理存储块号写到读映射表请求的位置上，并将读映射表中对应位置的旧物理存储块号释放。然后在缓存元数据状态表中将4个物理存储块的物理存储块有效标志位都标识为有效，并将lock标志位、empty标志位和clean标志位分别标识为lock、not empty和clean。主控模块发送一条命令，要求后端模块将后端闪存地址上的16KB数据读到这4个物理存储块上。
在缓存系统的主控模块接收到后端模块的完成命令后，才会向前端模块返回完成命令，并将缓存元数据状态表中该表项的lock标志位置为unlock。
如果后端地址相同，则说明缓存命中，继续判断该物理存储块对应的物理存储块有效标志是否有效。
若无效，则该表项对应的地址还没读入数据，为该表项内所有无效的物理存储块位置，申请新的物理存储块，并将其中对应的一个物理存储块号写到读映射表请求的位置上，并将读映射表中对应位置的旧物理存储块号释放。将4个物理存储块都标识为有效，在缓存元数据状态表中将lock标志位、empty标志位和clean标志位分别标志为lock、not empty和clean。然后主控模块再发送一条命令，要求后端模块将后端闪存地址上的数据读到这儿个新的物理存储块上，但原先物理存储块标识位为有效的物理存储块不会被覆盖，仅读取并覆盖原先无效的物理存储块。在缓存系统接收到后端模 块的完成命令后，才会向前端模块返回完成命令，并将对应表项的lock标志位设置为unlock。
若对应的物理存储块标志位为有效，说明该数据已经在缓存中，将该物理存储块号写到读映射表请求的位置上，并将该物理存储块号的引用计数加1，同时将读映射表中该位置的旧物理存储块号释放。
对于写入读映射表的物理存储块，在引用计数表中将该物理存储块的引用次数加1，而当某个物理存储块从读映射表被删除时，则在引用计数表中将该物理存储块的引用次数减1，从而保证读映射表中的物理存储块不被回收。
实施例1
假设物理存储块共有1000个，大小是4KB，等于前端应用访问大小。
假设后端闪存系统的page size是16KB，则缓存元数据记录表和缓存元数据状态表都是250个表项，因为他们是基于page size的，1000*4KB＝250*16KB。
假设前端应用能看到的虚拟逻辑存储块有100个，多少个可以随意，主要目的是考虑处理延时，多设儿个便于并行处理。
如图11至15是各个数据表或存储器初始状态下：
初始状态时，写映射表已经为各个逻辑块号分配好了对应的物理存储块号，如图11所示。读映射表保持空的状态，所有表项写入一个无效的物理存储块号，例如“X”表示一个大于有效物理存储块号的数值，表示当前为初始状态，这样在前端应用读入某个读入逻辑存储块号时，则无数据返回，如图12所示。
如图13所示，初始状态时，缓存元数据记录表是空的，因为缓存中没有存放任何数据，缓存元数据状态表(里面有250条表项)都是empty，unlock，clean的状态。
如图14所示，初始状态时，空闲物理块FIFO是满的，里面存放着所有的物理存储块号(1000个)。初始状态下所有物理存储块都是未使用的空闲状态。
初始状态时，主控模块会在空闲FIFO队列中先申请100个(逻辑存储块数目)物理存储块，将其写到写映射表中，为写映射表中的每一个逻辑存储块分配一个物理存储块号。由于初始时所有物理存储块在空闲物理块FIFO中，在主控模块将前100个物理存储块号分配到写映射表后，空闲物理块FIFO就只剩下900个物理存储块，如图15所示。后续物理存储块使用情况不同，回收先后不同，空闲物理块FIFO里的物理存储块号的顺序将会是杂乱的。
第一次写请求，如图16至21所示。
前端应用将数据先写到了逻辑存储块1中。由于有写映射表，此时逻辑地址1对应的是物理存储块1，所以数据实际被写到了物理存储块1中。
前端应用发下命令，将逻辑存储块1的数据写到后端某个地址GBAx，假设GBAx最低两位的比特为00。
主控模块接收到了这个命令，将GBAx做hash运算，得出其对应的缓存元数据地址索引是15(假设)。并查询写地址映射表，得出当前逻辑存储块1对应物理存储块1。
主控模块读取缓存元数据状态表，发现地址15的表项状态是empty、unlock和clean(因为初始化之后所有表项都是这个状态)。
主控模块在缓存元数据记录表15的位置新建一个表项，将物理存储块1写到第一个物理存储块位置。GBAx最低两位比特00～11的4种情况，决定了该物理存储块要写到第儿个位置，依次对应表项的第一个物理存储块位置到第四个物理存储块位置。
缓存元数据记录表中的GBAx的后两位是0，因为元数据记录表的一条表项大小是16KB，和前端命令4KB地址相比大4倍，所以最后两位地址记录成0即可。
将缓存元数据状态表第15个表项设为not empty、unlock和dirty，代表本表项已被使用，unlock和dirty则分别指本表项的数据较新一些(和后端GBAx存储的数据比)。
主控模块在向空闲物理块FIFO申请一个新物理存储块(假设是101)，写入写映射表第一个位置(逻辑存储块1的位置)，如图19所示，现在再来写逻辑存储块1，实际就写入物理存储块101了。
主控模块向前端应用返回命令完成。
某一次读请求，如图22至27所示。
若干次操作后，前端应用发送命令，要求将后端地址GBAy的数据，读到逻辑存储块2上。然后前端应用等待命令完成后，再访问逻辑存储块2获得数据。
主控模块对GBAy进行hash计算，得出其对应的缓存元数据记录表的地址是30(假设)。
如图22所示，当前地址30的表项是有数据的，但是该该表项对应的后端存储地址是GBAz，与要访问的后端地址GBAy并不相同，也即缓存没有命中，需要先将这个表项(也即旧表项)的数据写到后端闪存中，同时将需要的新数据读(load)进来。
主控模块先查出元数据地址30是有数据的，但后端地址GBAz并不等于GBAy。
主控模块读取状态表，发现元数据地址30的位置的dirty标志位是dirty，说明需要将对应的四个物理存储块的数据写到后端闪存。
主控模块发送命令，通知后端模块将物理存储块123、物理存储块75、物理存储块50和物理存储块100的数据(共16KB)，写入到GBAz这个地址起始的16KB空间中。
主控模块不需要等待上个命令完成，立刻将元数据记录表的表项30擦掉，新建一个表项，即对表项30重新赋值。向缓存空闲块管理模块申请4个新的物理存储块，假设是物理存储块400、物理存储块500、物理存储块600和物理存储块700，将其依次写到第一个到第四个位置的物理存储块位置。
假设GBAy的末两位是01，代表是4个4KB中的第2个，因此将第二个物理存储块位置上的物理存储块500写到读映射表2的位置上。
在写之前，读映射表2对应的旧物理存储块是物理存储块20，此处前端访问的请求表示已经不再需要逻辑存储块2的数据了，因此物理存储块20会被释放。当然物理存储块20不一定会写到空闲物理块FIFO中，这取决物理存储块20的当前引用计数。 这部分在回收模块中有描述具体过程。
主控模块再发一个命令，要求后端模块将GBAy(地址低2bit为0，地址16KB对齐)开始的16KB数据依次读到物理存储块400、500、600和700(每个物理存储块4KB)中。
主控模块将此表项在缓存元数据状态表中置为lock、clean和not empty。
由于读取需要时间，主控模块此时不会立刻向前端返回完成命令，他需要先等待后端模块返回读取完成，然后再讲表项30的lock标志位设置为unlock。
某一次后端命令完成，如图28至30所示。
如图28所示，缓存系统发给后端闪存两个命令，命令ID号15的是一次flush(写)操作，命令ID号16的是一次load(读)操作。现在后端模块返回这两个命令完成。
对于ID号15的命令，回收模块会先检查其操作类型是写操作，然后将其中有效的物理存储块号，本例中是两个，物理存储块18和物理存储块2，回收掉。回收流程依然按照之前描述的方式进行。
回收完成后并不会通知前端，因为写操作的命令返回在之前就返回过了。
对与ID号16的命令，回收模块会对GBAy进行hash计算，按上面实例，它对应元数据记录表的第30个表项。当时缓存系统将该表项的lock标志位设置为了lock，此时数据读取回来，缓存系统会将该表项的lock标志位置为unlock，同时通知前端模块，之前的这条读命令完成了。
以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明由所提交的权利要求书确定的专利保护范围。

Claims (12)

  1. 一种闪存存储系统的写数据方法，其特征是，所述闪存存储系统包括缓存、主控模块、缓存元数据记录表和写映射表；其中，所述写映射表用于存储在缓存中写入逻辑存储块与物理存储块的对应关系，所述缓存元数据记录表用于存储元数据表地址、物理存储块和后端闪存地址之间的对应关系；所述闪存存储系统的写数据方法包括如下步骤：
    S1，所述主控模块接收前端应用发出的将第一写入逻辑存储块中的数据写入第一后端闪存地址的命令；
    S2，所述主控模块读取所述写映射表，获取与所述第一写入逻辑存储块对应的所述缓存中的第一物理存储块；
    S3，所述主控模块对所述第一后端闪存地址进行计算，获得与所述第一后端闪存地址对应的第一元数据表地址；
    S4，所述主控模块读取所述缓存元数据记录表，获取与所述第一元数据表地址对应的当前后端闪存地址；
    S5，所述主控模块判断所述第一后端闪存地址与当前后端闪存地址是否相同；
    S6，若所述第一后端闪存地址与所述当前后端闪存地址相同，则将所述第一物理存储块替换所述缓存元数据记录表中与所述当前后端闪存地址对应的当前物理存储块；
    S7，若所述第一后端闪存地址与所述当前后端闪存地址不同，则将所述缓存元数据记录表中与所述当前后端闪存地址对应的当前物理存储块的数据存储到后端闪存的当前后端闪存地址中，并将所述第一后端闪存地址和第一物理存储块分别替代所述当前后端闪存地址和当前物理存储块。
  2. 如权利要求1所述的闪存存储系统的写数据方法，其特征是，所述闪存存储系统还包括引用计数表、空闲物理块FIFO和回收模块，所述空闲物理块FIFO用于存放所述缓存中空闲的物理存储块，所述计数表用于存储物理存储块与对应的引用次数，当所述空闲物理块FIFO将空闲的物理存储块分配出去时，将分配出去的物理存储块的引用次数设置为第一引用次数值；
    还包括回收物理存储块步骤：
    对于被替换的物理存储块，读取所述引用计数表中对应物理存储块的引用次数，若对应物理存储块的引用次数大于所述第一引用次数值则将对应的物理存储块的引用次数减设定引用次数，若对应物理存储块的引用次数等于第一引用次数值，则所述回收模块将对应的物理存储块写入所述空闲物理块FIFO中。
  3. 如权利要求2所述的闪存存储系统的写数据方法，其特征是，所述缓存元数据记录表还用于存储与物理存储块对应的物理存储块有效标志位，在所述物理存储块存储数据之前对应的物理存储块有效标志位的值被置为非有效值，在所述物理存储块存储数据之后对应的物理存储块有效标志位的值被置为有效值；
    在所述步骤S6中，在将所述第一物理存储块替换所述缓存元数据记录表中与所述当前后端闪存地址对应的当前物理存储块之前，还包括如下步骤：
    在所述缓存元数据记录表中判断所述当前后端闪存地址对应的当前物理存储块的物理存储块有效标志位的值是有效值还是非有效值，若是有效值则执行回收物理存储块步骤。
  4. 如权利要求2所述的闪存存储系统的写数据方法，其特征是：所述闪存存储系统还包括缓存元数据状态表；
    所述缓存元数据记录表中，所述物理存储块具有多个，多个物理存储块分别与以所述后端闪存地址为基准的连续多个后端闪存地址相对应；
    所述缓存元数据记录表还用于存储与物理存储块对应的物理存储块有效标志位，在物理存储块存储数据之前对应的物理存储块有效标志位的值被置为非有效值，在物理存储块存储数据之后对应的物理存储块有效标志位的值被置为有效值；
    所述缓存元数据状态表用于存储元数据表地址、占用标志位和空标志位之间的对应关系，所述占用标志位的值包括分别表示所述元数据表地址对应的表项被占用和没有被占用的占用值和非占用值，所述空标志位的值包括分别表示所述元数据表地址中的物理存储块被写入数据和没有被写入数据的非空值和空值；
    在所述步骤S3与步骤S4之间，还包括如下步骤：
    S3.1，所述主控模块读取所述缓存元数据记录表，判断所述第一元数据表地址对应的占用标志位的值是否为占用值，若是则等待，否则执行步骤S3.2；
    S3.2，所述主控模块判断所述第一元数据表地址对应的空标志位的值是否为非空值，若是则执行步骤S4；
    在所述步骤S6中，还包括如下步骤：
    S6.1，判断所述缓存元数据记录表中，与所述第一后端闪存地址对应的物理存储块的物理存储块有效标识的值是否为有效值；
    S6.2，若是有效值则执行回收物理存储块步骤，并执行步骤S6.4；
    S6.3，若不是有效值则将对应的物理存储块有效标识的值设为有效值，并执行步骤S6.4；
    S6.4，将所述第一物理存储块写入所述缓存元数据记录表的对应位置。
  5. 如权利要求2所述的闪存存储系统的写数据方法，其特征是：
    在步骤S6和步骤S7后，从所述空闲物理块FIFO中为所述第一写入逻辑存储块分配新的物理存储块。
  6. 一种闪存存储系统的读数据方法，其特征是，所述闪存存储系统包括缓存、主控模块、缓存元数据记录表和读映射表；其中，所述读映射表用于存储在缓存中读出逻辑存储块与物理存储块的对应关系，所述缓存元数据记录表用于存储元数据表地址、物理存储块和后端闪存地址之间的对应关系；所述闪存存储系统的读数据方法包括如下步骤：
    S1，所述主控模块接收前端应用发出的将第一后端闪存地址的数据写入第一读出逻辑存储块中的命令；
    S2，所述主控模块对所述第一后端闪存地址进行计算，获得与所述第一后端闪存地址对应的第一元数据表地址；
    S3，所述主控模块读取所述缓存元数据记录表，获取与所述第一元数据表地址对应的当前后端闪存地址；
    S4，所述主控模块判断所述第一后端闪存地址与当前后端闪存地址是否相同；
    S5，若所述第一后端闪存地址与所述当前后端闪存地址相同，则将所述缓存元数据记录表中与所述第一后端闪存地址对应的当前物理存储块写入所述读映射表中且与所述第一读出逻辑存储块相对应；
    S6，若所述第一后端闪存地址与所述当前后端闪存地址不同，则将所述缓存元数据记录表中与所述当前后端闪存地址对应的当前物理存储块的数据存储到后端闪存的当前后端闪存地址中，并将所述第一后端闪存地址和新的物理存储块分别替代所述当前后端闪存地址和当前物理存储块，并将所述新的物理存储块写入所述读映射表中且与所述第一读出逻辑存储块相对应。
  7. 如权利要求6所述的闪存存储系统的读数据方法，其特征是，
    所述闪存存储系统还包括引用计数表、空闲物理块FIFO和回收模块，所述空闲物理块FIFO用于存放所述缓存中空闲的物理存储块，所述计数表用于存储所述物理存储块与对应的引用次数，当所述空闲物理块FIFO将空闲的物理存储块分配出去时，将分配出去的物理存储块的引用次数设置为第一引用次数值；还包括回收物理存储块步骤：
    在步骤S5中，当所述第一后端闪存地址对应的当前物理存储块写入所述读映射表中后，还包括如下步骤：
    S5.1，将与所述第一后端闪存地址对应的当前物理存储块的引用次数增加设定引用次数，并将所述读映射表中与所述第一读出逻辑存储块对应的旧的物理存储块的引用次数减所述设定引用次数；
    在步骤S6中，将所述新的物理存储块写入所述读映射表中后，还包括如下步骤：
    S6.1，将所述新的物理存储块的引用次数增加设定引用次数，并将所述读映射表中与所述第一读出逻辑存储块对应的旧的物理存储块的引用次数减所述设定引用次数；
    对于替换和被替换的物理存储块，读取所述引用计数表中物理存储块的引用次数，若物理存储块的引用次数大于所述第一引用次数值，则将对应的物理存储块的引用次数减设定引用次数，若物理存储块的引用次数等于第一引用次数值，则所述回收模块将对应的物理存储块写入所述空闲物理块FIFO中。
  8. 如权利要求7所述的闪存存储系统的读数据方法，其特征是，所述闪存存储系统还包括缓存元数据状态表；
    所述缓存元数据记录表中，所述物理存储块具有多个，多个物理存储块分别与以 所述后端闪存地址为基准的连续多个后端闪存地址相对应；
    所述缓存元数据记录表还用于存储与物理存储块对应的物理存储块有效标志位，在物理存储块存储数据之前对应的物理存储块有效标志位的值被置为非有效值，在物理存储块存储数据之后对应的物理存储块有效标志位的值被置为有效值；
    所述缓存元数据状态表用于存储元数据表地址、占用标志位和空标志位之间的对应关系，所述占用标志位的值包括分别表示所述元数据表地址对应的表项被占用和没有被占用的占用值和非占用值，所述空标志位的值包括分别表示所述元数据表地址中的物理存储块被写入数据和没有被写入数据的非空值和空值；
    在所述步骤S2与步骤S3之间，还包括如下步骤：
    S3.1，所述主控模块读取所述缓存元数据记录表，判断所述第一元数据表地址对应的占用标志位的值是否为占用值，若是则等待，否则执行步骤S3.2；
    S3.2，所述主控模块判断所述第一元数据表地址对应的空标志位的值是否为非空值，若是则执行步骤S3；
    在所述步骤S5中，还包括如下步骤：
    S5.1，判断所述缓存元数据记录表中，与所述第一后端闪存地址对应的物理存储块的物理存储块有效标识的值是否为有效值；
    S5.2，若是有效值则执行回收物理存储块步骤；
    S5.3，若不是有效值则将对应的物理存储块有效标识的值设为有效值。
  9. 一种闪存存储系统的删除数据方法，其特征是，所述闪存存储系统包括缓存、主控模块和缓存元数据记录表；其中，所述缓存元数据记录表用于存储元数据表地址、物理存储块和后端闪存地址之间的对应关系；所述闪存存储系统的删除数据方法包括如下步骤：
    S1，所述主控模块接收前端应用发出的删除第一后端闪存地址的数据的命令；
    S2，所述主控模块对所述第一后端闪存地址进行计算，获得与所述第一后端闪存地址对应的第一元数据表地址；
    S3，所述主控模块读取所述缓存元数据记录表，获取与所述第一元数据表地址对应的当前后端闪存地址；
    S4，所述主控模块判断所述第一后端闪存地址与当前后端闪存地址是否相同；
    S5，若所述第一后端闪存地址与所述当前后端闪存地址相同，则将当前后端闪存地址对应的表项删除，并执行步骤S7；
    S6，若所述第一后端闪存地址与所述当前后端闪存地址不同，则执行步骤S7；
    S7，将所述删除第一后端闪存地址的数据的命令发送到后端闪存。
  10. 一种闪存存储系统，其特征是，包括缓存、主控模块、缓存元数据记录表、读映射表和写映射表；其中，所述写映射表用于存储在缓存中写入逻辑存储块与物理存储块的对应关系，所述读映射表用于存储在缓存中读出逻辑存储块与物理存储块的对应关系，所述缓存元数据记录表用于存储元数据表地址、物理存储块和后端闪存地 址之间的对应关系；
    所述主控模块用于接收前端应用发出的将第一写入逻辑存储块中的数据写入第一后端闪存地址的命令；
    所述主控模块用于读取所述写映射表，获取与所述第一写入逻辑存储块对应的所述缓存中的第一物理存储块；
    所述主控模块用于对所述第一后端闪存地址进行计算，获得与所述第一后端闪存地址对应的第一元数据表地址；
    所述主控模块用于读取所述缓存元数据记录表，获取与所述第一元数据表地址对应的当前后端闪存地址；
    所述主控模块用于判断所述第一后端闪存地址与当前后端闪存地址是否相同，若所述第一后端闪存地址与所述当前后端闪存地址相同，则将所述第一物理存储块替换所述缓存元数据记录表中与所述当前后端闪存地址对应的当前物理存储块；若所述第一后端闪存地址与所述当前后端闪存地址不同，则将所述缓存元数据记录表中与所述当前后端闪存地址对应的当前物理存储块的数据存储到后端闪存的当前后端闪存地址中，并将所述第一后端闪存地址和第一物理存储块分别替代所述当前后端闪存地址和当前物理存储块；
    所述主控模块用于接收前端应用发出的将第一后端闪存地址的数据写入第一读出逻辑存储块中的命令；
    所述主控模块用于对所述第一后端闪存地址进行计算，获得与所述第一后端闪存地址对应的第一元数据表地址；
    所述主控模块用于读取所述缓存元数据记录表，获取与所述第一元数据表地址对应的当前后端闪存地址；
    所述主控模块用于判断所述第一后端闪存地址与当前后端闪存地址是否相同；若所述第一后端闪存地址与所述当前后端闪存地址相同，则将所述缓存元数据记录表中与所述第一后端闪存地址对应的当前物理存储块写入所述读映射表中且与所述第一读出逻辑存储块相对应；若所述第一后端闪存地址与所述当前后端闪存地址不同，则将所述缓存元数据记录表中与所述当前后端闪存地址对应的当前物理存储块的数据存储到后端闪存的当前后端闪存地址中，并将所述第一后端闪存地址和新的物理存储块分别替代所述当前后端闪存地址和当前物理存储块，并将所述新的物理存储块写入所述读映射表中且与所述第一读出逻辑存储块相对应。
  11. 如权利要求10所述的闪存存储系统，其特征是，
    所述闪存存储系统还包括引用计数表、空闲物理块FIFO和回收模块，所述空闲物理块FIFO用于存放所述缓存中空闲的物理存储块，所述计数表用于存储所述物理存储块与对应的引用次数，当所述空闲物理块FIFO将空闲的物理存储块分配出去时，将分配出去的物理存储块的引用次数设置为第一引用次数值；
    当所述第一后端闪存地址对应的当前物理存储块写入所述读映射表中后，将与所 述第一后端闪存地址对应的当前物理存储块的引用次数增加设定引用次数，并将所述读映射表中与所述第一读出逻辑存储块对应的旧的物理存储块的引用次数减所述设定引用次数；
    将所述新的物理存储块写入所述读映射表中后，将所述新的物理存储块的引用次数增加设定引用次数，并将所述读映射表中与所述第一读出逻辑存储块对应的旧的物理存储块的引用次数减所述设定引用次数；
    对于替换和被替换的物理存储块，读取所述引用计数表中物理存储块的引用次数，若物理存储块的引用次数大于所述第一引用次数值，则将对应的物理存储块的引用次数减设定引用次数，若物理存储块的引用次数等于第一引用次数值，则所述回收模块将对应的物理存储块写入所述空闲物理块FIFO中。
  12. 如权利要求10所述的闪存存储系统，其特征是，所述缓存元数据记录表的一个表项中具有四个物理存储块，每个物理存储块的大小为4KB。
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111162794A (zh) * 2018-11-08 2020-05-15 北京忆芯科技有限公司 译码数据缓存方法和译码器
CN111857578A (zh) * 2020-06-30 2020-10-30 浪潮(北京)电子信息产业有限公司 一种数据信息的读写方法、装置、设备及存储介质
CN112416811A (zh) * 2020-11-18 2021-02-26 深圳市硅格半导体有限公司 基于数据关联度的垃圾回收方法、闪存及装置
CN112684981A (zh) * 2020-12-23 2021-04-20 北京浪潮数据技术有限公司 固态硬盘读操作记录方法、系统、装置及可读存储介质
CN114968849A (zh) * 2021-12-24 2022-08-30 苏州启恒融智信息科技有限公司 提高编程缓存利用率的方法及其设备
US11526445B2 (en) 2019-05-13 2022-12-13 Rambus Inc. Managing memory maintenance operations in a memory system having backing storage media
CN116450537A (zh) * 2023-06-19 2023-07-18 联和存储科技(江苏)有限公司 Nand闪存固件烧录方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101727395A (zh) * 2008-10-17 2010-06-09 深圳市朗科科技股份有限公司 闪存设备的管理系统、方法及闪存设备
CN102866955A (zh) * 2012-09-14 2013-01-09 记忆科技(深圳)有限公司 一种闪存数据管理方法及系统
US20130166825A1 (en) * 2011-12-27 2013-06-27 Jin Yeong Kim Method Of Controlling Non-Volatile Memory, Non-Volatile Memory Controller Therefor, And Memory System Including The Same
CN103425600A (zh) * 2013-08-23 2013-12-04 中国人民解放军国防科学技术大学 一种固态盘闪存转换层中的地址映射方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101727395A (zh) * 2008-10-17 2010-06-09 深圳市朗科科技股份有限公司 闪存设备的管理系统、方法及闪存设备
US20130166825A1 (en) * 2011-12-27 2013-06-27 Jin Yeong Kim Method Of Controlling Non-Volatile Memory, Non-Volatile Memory Controller Therefor, And Memory System Including The Same
CN102866955A (zh) * 2012-09-14 2013-01-09 记忆科技(深圳)有限公司 一种闪存数据管理方法及系统
CN103425600A (zh) * 2013-08-23 2013-12-04 中国人民解放军国防科学技术大学 一种固态盘闪存转换层中的地址映射方法

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111162794B (zh) * 2018-11-08 2023-10-20 北京忆芯科技有限公司 译码数据缓存方法和译码器
CN111162794A (zh) * 2018-11-08 2020-05-15 北京忆芯科技有限公司 译码数据缓存方法和译码器
US11526445B2 (en) 2019-05-13 2022-12-13 Rambus Inc. Managing memory maintenance operations in a memory system having backing storage media
US20230135017A1 (en) * 2019-05-13 2023-05-04 Rambus Inc. Managing memory maintenance operations in a memory system having backing storage media
CN111857578A (zh) * 2020-06-30 2020-10-30 浪潮(北京)电子信息产业有限公司 一种数据信息的读写方法、装置、设备及存储介质
CN112416811A (zh) * 2020-11-18 2021-02-26 深圳市硅格半导体有限公司 基于数据关联度的垃圾回收方法、闪存及装置
CN112416811B (zh) * 2020-11-18 2024-02-27 深圳市硅格半导体有限公司 基于数据关联度的垃圾回收方法、闪存及装置
CN112684981A (zh) * 2020-12-23 2021-04-20 北京浪潮数据技术有限公司 固态硬盘读操作记录方法、系统、装置及可读存储介质
CN112684981B (zh) * 2020-12-23 2023-12-22 北京浪潮数据技术有限公司 固态硬盘读操作记录方法、系统、装置及可读存储介质
CN114968849B (zh) * 2021-12-24 2023-10-13 苏州启恒融智信息科技有限公司 提高编程缓存利用率的方法及其设备
CN114968849A (zh) * 2021-12-24 2022-08-30 苏州启恒融智信息科技有限公司 提高编程缓存利用率的方法及其设备
CN116450537B (zh) * 2023-06-19 2023-08-29 联和存储科技(江苏)有限公司 Nand闪存固件烧录方法
CN116450537A (zh) * 2023-06-19 2023-07-18 联和存储科技(江苏)有限公司 Nand闪存固件烧录方法

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