Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
  • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
  • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
  • H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
  • H01L21/76262—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using selective deposition of single crystal silicon, i.e. SEG techniques
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
  • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers

Definitions

• the field of the disclosure relates to preparation of silicon- germanium-on-insulator structures and, in particular, methods that involve use of a germanium buffer layer and to donor structures and bonded structures used to prepare such silicon-germanium-on-insulator structures.
• Multi-layered structures comprising a device layer with a device quality surface, such as a silicon-geranium device layer, are useful for a number of different purposes.
• Silicon-germanium based devices may be characterized by enhanced electrical properties.
• Such silicon-germanium device layers may be fabricated on an insulator to reduce parasitic capacitances and improve isolation.
• Silicon-germanium-on- insulator (SGOI) structures can be used to produce a variety of devices including CMOS and MOSFET devices.
• Multi-layered structures including donor structures used to produce SGOI structures by layer transfer may include multiple layers of material having differing coefficients of thermal expansion. During manufacture of such structures, however, the different rates of thermal expansion can create very large stresses in the multi-layered structures when they are heated, which can fracture the device layer or substrate. This places severe constraints on the maximum temperature that these dissimilar pairs can be exposed to during manufacture.
• One aspect of the present disclosure is directed to a multi- layered semiconductor donor structure having two major, generally parallel surfaces, one of which is a front surface and the other of which is a back surface.
• the donor structure comprises a single crystal silicon handle layer and a device layer comprising silicon and germanium.
• a relaxed buffer layer is disposed between the single crystal silicon handle layer and the device layer.
• the buffer layer comprises at least about 90 wt% germanium.
• the single crystal semiconductor handle layer and semiconductor buffer layer form a handle-buffer interface.
• Another aspect of the present disclosure is directed to a method for preparing a multi-layered crystalline structure.
• Ions selected from the group consisting of hydrogen, helium and combinations thereof are implanted into a donor structure having a central axis and an implantation surface generally perpendicular to the central axis.
• the donor structure comprises a semiconductor device layer comprising silicon and germanium, a handle layer, and a relaxed germanium buffer layer which is positioned along the central axis of the donor structure between the device surface and the handle layer.
• the relaxed germanium buffer layer comprises at least about 90 wt% germanium.
• the ions are implanted into the donor structure through the implantation surface to an implantation depth sufficient to form in the implanted donor structure a damage layer which is generally perpendicular to the axis and located in the buffer layer and/or in the handle layer.
• the implanted donor structure is bonded to a second structure to form a bonded structure.
• the donor structure is cleaved along the damaged layer to form a multi-layered crystalline structure comprising the second structure, the device layer and residual material.
• the residual material comprises at least a portion of the buffer layer and optionally a portion of the handle layer. The residual material is removed from the multi-layered crystalline structure.
• Figure 1A is a cross-sectional, schematic drawing of a donor structure for preparing a SiGe-on-insulator structure
• Figure IB is a cross-sectional, schematic drawing of a second structure, prior to bonding with the donor structure of Figure 1A.
• Figure 2 is a cross-sectional, schematic drawing of a bonded structure, resulting from contacting a surface of the donor structure of Figure 1A with the second structure of Figure IB;
• Figure 3 is a cross-sectional, schematic drawing showing separation of the bonded structure along the damage layer in the germanium buffer layer;
• Figure 4 is a cross-sectional, schematic drawing of the SiGe-on- insulator structure.
• Figure 5 is a cross-sectional, schematic drawing of another embodiment of the donor structure having a passivation layer and an etch stop layer.
• SiGe-on-insulator silicon- germanium-on-insulator structure
• SiGe-on-insulator silicon- germanium-on-insulator structure
• the use of a strain-relaxed germanium buffer layer in a donor structure may be used to transfer a high-quality silicon- germanium layer to produce a silicon-germanium-on-insulator structure.
• the bonded structure is cleaved in the germanium buffer layer and residual material may be removed to produce a device-quality silicon-germanium layer.
• the germanium buffer layer of the donor structure may include a reduced number of threading dislocations relative to
• threading dislocations which are present may more readily glide and be annihilated during buffer layer growth and subsequent anneals.
• the high mobility of threading dislocations in the germanium buffer layer prevents dislocation pile-ups from forming in the device layer.
• Such dislocation pile-ups are associated with a high stress field which drives surface atom migration leading to large surface roughness and undulations.
• a high stress field may cause layer transfer failure and/or make the device layer susceptible to defect formation in device fabrication.
• High amounts of threading dislocations e.g., dislocation density > 10 8 per cm 2
• pile-ups may result in a stress field that scatters carriers which reduces carrier mobility and causes poor device performance.
• Reducing the amount of dislocation pile-ups in the germanium buffer also reduces stress between the germanium buffer layer and the germanium- silicon device layer which reduces bow and deformation of the donor structure which allows for better device layer transfer.
• the lattice mismatch between the strain-relaxed germanium buffer layer and the silicon-germanium device layer creates tensile stress in the silicon-germanium device layer which promotes surface atom migration resulting in smoothing of the silicon-germanium device layer during growth.
• Dislocations that remain in the germanium buffer layer promote strain relaxation of the silicon-germanium device layer without creating dislocations in the device layer.
• the germanium buffer layer may be sufficiently smoothed by use of a thermal anneal without use of a chemical-mechanical-polish as in conventional methods.
• Relatively thick germanium buffers e.g., about 500 nm or more with about 5 ⁇ or more or even 10 ⁇ or more being preferred
• the germanium buffer layer of the donor structure may be recycled multiple times.
• the multi-layered crystalline structure of the present disclosure may be prepared by implanting ions into a donor structure comprising a semiconductor device layer comprising germanium and silicon, a handle layer and a germanium buffer layer, bonding the implanted donor structure to a second structure to form a bonded structure, cleaving the handle layer and a portion of the germanium buffer layer from the device layer which remains bonded to the second structure and optionally etching the residual germanium buffer layer from the device layer thereby exposing the device layer.
• the donor structure provides the device layer for the final multi-layered crystalline structure.
• the other substrate will be referred to hereinafter as the "second structure. "
• the second structure may be comprised of single crystal silicon, sapphire, quartz crystal, glass, silicon carbide, silicon, gallium nitride, aluminum nitride, gallium aluminum nitride, gallium arsenic, indium gallium arsenic or any combination thereof.
• the Si-Ge-on-insulator structure produced according to the present disclosure may be any diameter suitable for use by those of skill in the art including, for example, about 200 mm, about 300 mm, greater than about 300 mm or even about 450 mm.
• the donor structure 10 comprises a central axis 12 and two major, generally parallel surfaces, one of which is a front surface 16 (also referred to herein as "implantation surface") and the other of which is the back surface 2, both surfaces being generally perpendicular to the central axis 12.
• the donor structure 10 includes a silicon-germanium device layer 14, a handle layer 20 and a germanium buffer layer 22, which is positioned along the central axis 12 of the donor structure 10 between the device layer 14 and the handle layer 20.
• the handle layer 20 and germanium buffer layer 22 form a handle-buffer interface and the germanium buffer layer 22 and silicon-germanium device layer 14 form a buffer-device layer interface.
• the donor structure 10 may include an optional dielectric layer 8 at the surface of the donor structure.
• the device layer 14 comprises silicon and germanium and, in some embodiments, contains silicon and germanium according to the formula:
• the device layer 14 may contain at least about 95 wt% silicon and germanium (i.e., contain about 5 wt% or less of compounds other than silicon and germanium) or at least about 97.5 wt%, at least about 99 wt%, at least about 99.9 wt% silicon and germanium or even consist essentially of silicon and germanium (i.e., contain other compounds in only impurity amounts).
• the silicon-germanium device layer 14 has an average thickness which is suitable for use in the production of microelectronic or photovoltaic devices; however the device layer may have a thickness greater than those typically used without departing from the scope of the present disclosure.
• the device layer 14 has an average thickness of at least about 5 nm, typically at least about 8 nm and may have a thickness of from about 5 nm to about 300 nm.
• the germanium buffer layer 22 comprises at least about 90 wt% germanium or, as in other embodiments, at least about 95 wt%, at least about 97.5 wt%, at least about 99 wt%, at least about 99.9 wt% germanium or consists essentially of germanium.
• the germanium buffer layer 22 has an average thickness of at least about 500 nm or at least about 750 nm, at least about 1 ⁇ , at least about 2 ⁇ , at least about 3 ⁇ or even at least about 4 ⁇ (e.g., from about 500 nm to about 10 ⁇ , from about 500 nm to about 5 ⁇ , from about 750 nm to about 10 ⁇ or from about 1 ⁇ to about 5 ⁇ ).
• the handle layer comprises single crystal silicon.
• the handle layer comprises at least about 90 wt% silicon or, as in other embodiments, at least about 95 wt%, at least about 97.5 wt%, at least about 99 wt% or at least about 99.9 wt% silicon.
• the handle layer 20 may have any thickness capable of providing sufficient structural integrity to allow delamination of the device layer 14 and at least a portion of the germanium buffer layer 22 and the handle layer 20 without departing from the scope of the present disclosure.
• the handle layer 20 may have an average thickness of at least about 100 ⁇ , typically at least about 200 ⁇ and may have a thickness of from about 100 ⁇ to about 900 ⁇ or even from about 500 ⁇ to about 800 ⁇ .
• the donor structure 10 may further include a bonding layer, such as an oxide layer, deposited oxides, TEOS, CVD nitrides, or organic adhesives, on its surface prior to or after the implantation of ions into the donor structure 10 and/or prior to the bonding of the donor structure 10 to the second structure 26 (Fig. IB).
• a bonding layer may be formed on the second structure 26 prior to bonding. The application of the bonding layer provides a bonding interface between the donor structure 10 and the second structure 26 so as to prevent the formation of interfacial gaps that may occur during direct bonding of the donor structure 10 and the second structure 26.
• the bonding layer may have an average thickness of at least about 10 nm, and may have an average thickness of at least about 1 ⁇ or at least about 3 ⁇ or greater.
• the relaxed germanium buffer layer 22 may be formed by epitaxy. Suitable epitaxial processes may involve contacting the surface of the single crystal substrate 20 with a germanium gas (GeH 4 , Ge2H 6 or their halides) at a temperature between about 300°C to about 700°C and a pressure between about 1 kPa to about 100 kPa.
• a germanium gas GeH 4 , Ge2H 6 or their halides
• the germanium buffer layer 22 becomes relaxed upon generation of misfit dislocations at the buffer-handle layer interface. At the two ends of the misfit dislocation is a threading dislocation.
• any germanium buffer layer 22 with a thickness of about 1 nm begins to relax without a thermal treatment.
• Buffer layers 22 with a thickness of at least about 5 nm (e.g., about 10 nm or more) may be fully relaxed without thermal treatment.
• X-ray diffraction (to determine the lattice constant) may be used to characterize the degree of strain relaxation in the germanium buffer layer 22.
• the lattice constant of the germanium buffer layer 22 may be compared with bulk germanium to determine the degree of strain relaxation.
• the strain-relaxed germanium buffer layer 22 may include a density of threading dislocations less than other conventional buffer layers.
• the density of threading dislocations in the germanium buffer layer 22 of the donor structure 10 is less than about lxlO 8 per cm , less than about 5x10 per cm , less than about 1x10 per cm , less than about 5x10 per cm 2 , less than about lxl O 6 per cm 2 , less than about 5xl0 5 per cm 2 or even less than about lxlO 5 dislocations per cm 2 .
• the buffer 22 and substrate 20 are annealed to reduce the threading dislocations in the germanium buffer layer 22 and to smooth its surface.
• the anneal may be performed in a hydrogen, nitrogen and/or argon atmosphere and at a temperature of at least about 600°C.
• the anneal may be performed for at least about one second (e.g., at least about 5 seconds or at least about 10 seconds). Generally, anneals of about 30 seconds or less are sufficient to reduce threading dislocation and smooth the surface, however longer anneals may be used.
• the silicon-germanium device layer 14 may be deposited by epitaxial deposition by use of a mixture of one or more silicon gases (SiH 4 , Si23 ⁇ 4, Si 3 3 ⁇ 4 or their halides) and one or more germanium gases (GeH 4 , Ge23 ⁇ 4 or their halides) at a temperature between about 300°C to about 700°C and a pressure between 1 kPa to about 100 kPa.
• silicon gases SiH 4 , Si23 ⁇ 4, Si 3 3 ⁇ 4 or their halides
• germanium gases GeH 4 , Ge23 ⁇ 4 or their halides
• the silicon-germanium layer 14 is relatively uniform in the distribution of silicon and germanium throughout its thickness (e.g., the concentration (molar or weight concentration) of silicon and/or germanium does not vary by more than about 25% between the top and bottom of the layer 14 or no more than about 10%, no more than about 5% or no more than about 1 % variance between the top and bottom of the layer 14).
• the donor structure 100 includes an etch stop layer 50 disposed between the silicon- germanium device layer 14 and the germanium buffer layer 22.
• the buffer layer 22 and etch stop layer 50 form a buffer-etch stop interface and the etch-stop layer 50 and device layer 14 form a device-etch stop interface.
• the etch stop layer 50 may be composed of silicon (e.g., at least about 90 wt%, at least about 95 wt% or at least about 99 wt%) and may be deposited by epitaxy at a temperature between about 300°C to about 600°C and a pressure between about 1 kPa to about 100 kPa.
• the etch stop layer 50 may have an average thickness of at least about 0.5 nm or at least about 1 nm, at least about 5 nm or at least about 10 nm (e.g., from about 0.5 nm to about 20 nm).
• the etch stop layer 50 may be strained or relaxed. In some embodiments, the etch stop layer 50 is strained to prevent generation of additional defects, such as threading dislocations, which improves the silicon-germanium device layer 14 quality.
• the donor structure 100 may also contain a silicon passivation layer 54 disposed on the silicon-germanium device layer 14.
• the passivation layer 54 acts to reduce device leakage and to enhance device performance in the resulting SiGe-on- insulator structure.
• the silicon passivation layer 54 may be may be composed of silicon (e.g., at least about 90 wt%, at least about 95 wt% or at least about 99 wt%) and may be deposited by epitaxy under similar conditions as the etch stop layer 50 described above.
• the passivation layer 54 may have a thickness of at least about 0.5 nm (e.g., about 0.5 nm to about 2 nm).
• the donor structure 100 is shown with both an etch stop layer 50 and a passivation layer 54, the structure may comprise an etch stop layer 50 without a passivation layer 54 or may comprise a passivation layer 54 without an etch stop layer 50.
• the surface of the germanium buffer layer 22 is smoothed before depositing the silicon-germanium device layer 14 (Fig. 1A) or the etch stop layer 50 (Fig. 5).
• the surface of the germanium buffer layer 22 may be smoothed by the thermal anneal described above.
• the anneal may reduce the surface roughness (RMS) of the buffer layer 22 to less than about 1 nm at a scan size of about 2 ⁇ x about 2 ⁇ or less than about 0.75 nm or even less than about 0.5 nm at a scan size of about 2 ⁇ x about 2 ⁇ (e.g., from about 0.1 nm to about 1 nm, from about 0.1 nm to about 0.75 nm, from about 0.25 nm to about 1 nm or from about 0.25 nm to about 0.75 nm at a scan size of about 2 ⁇ x about 2 ⁇ ).
• the desired surface roughness e.g., less than about 1 nm, less than about 0.75 nm or even less than about 0.5 nm
• the donor structure may include a dielectric layer 8 disposed on the surface of the silicon-germanium device layer 14 (Fig. 1A) or on the surface of the passivation layer 54 (Fig. 5).
• the dielectric layer 8 may be composed of silicon dioxide or silicon nitride and may also act as the bonding layer described above.
• the dielectric layer 8 may be formed by thermally annealing the structure in an atmosphere containing oxygen at a temperature between about 700°C and about 900°C and a pressure from about 0.1 kPa and about 100 kPa.
• the dielectric layer 8 may have an average thickness between about 1 nm and about 100 nm.
• ions such as hydrogen and/or helium ions
• the ions are implanted through the implantation surface 16 at a substantially uniform depth.
• the ions are implanted through the implantation surface 16 and into the germanium buffer 22 to an implantation depth that is greater than the thickness of the device layer 14 and any additional optional layer such as a dielectric layer 8, passivation layer 54 (Fig. 5) or etch stop layer 50.
• the ions may be implanted through the implantation surface 16 and into the handle layer 20.
• the ion implantation defines a damage layer 24 in the layer in which the ions are implanted.
• the ion implantation defines a damage layer 24 within the germanium buffer layer 22.
• ions are implanted to an average depth that is sufficient to ensure a satisfactory transfer of the device layer 14 upon a subsequent bonding and cleaving process.
• the implantation depth is minimized to decrease the amount of germanium buffer layer 22 transferred with the device layer 14.
• the ions are implanted to a depth of at least about 200 A or even at least about 1 ⁇ beneath the implantation surface depending on the thicknesses of the device layer 14.
• the ions may be implanted to a depth of at least about 20 nm, typically at least about 90 nm, at least about 250 nm or even at least about 500 nm.
• implantation depths may be used without departing from the scope of the present disclosure as they merely increase the amount of buffer layer 22 and/or handle layer 20 that will be removed after cleaving to reveal the device layer 14. As such, it may be preferable to implant the ions to a depth of from about 200 A to about 1 ⁇ or even from about 20 nm to about 500 nm.
• Ion implantation may be achieved using means known in the art.
• implantation may be achieved in a manner according to the process of U. S. Patent No. 6,790,747, the entire contents of which are incorporated herein by reference for all relevant and consistent purposes.
• an energy of, for example, at least about 10 keV, at least about 20 keV, at least about 80 keV, or at least about 120 keV may be used to implant hydrogen at a dosage of at least about 1 x 10 16
• the concentration of hydrogen implanted may be from about 2 x 10 16 ions/cm 2 to about 6 x 10 16 ions/cm 2 . It should be noted, that hydrogen may be implanted as H 2 + or alternatively as H + without departing from the scope of the present disclosure.
• an energy of, for example, at least about 10 keV, at least about 20 keV, at least about 30 keV, at least about 50 keV, at least about 80 KeV or even at least about 120 keV may be used to implant helium at a dosage of at least
• the concentration of helium implanted may be from about 1 x 10 16 ions/cm 2 to about 3 x 10 16 ions/cm 2 .
• both hydrogen and helium ions are implanted. It should be noted that the implantation of hydrogen and helium in combination may be done concurrently or sequentially with hydrogen being implanted prior to the helium or alternatively, with helium being implanted prior to the hydrogen.
• the hydrogen and helium are implanted sequentially with the helium being implanted first using at least about 10 keV, at least about 20 keV, or at least about 30 keV, at least about 50 keV, at least about 80 KeV or even at least about 120 keV to implant helium at a dosage of at least about 5 x 10 15 ions/cm 2 , at least about 1 x 10 16 ions/cm 2 , at least about 5 x 10 16 ions/cm 2 , or even at least about 1 x 10 17 ions/cm 2 and then implanting hydrogen at substantially the same depth as the helium using at least about 10 keV, at least about 20 keV, at least about 30 keV, at least about 50 keV, at least about 80 KeV or even at least about 120 keV to implant hydrogen at a dosage of at least about 5 x 10 15 ions/cm 2 , at least about 1 x 10 16 ions/cm 2 , at least about
• about 1 x 10 He ions/cm are implanted using about 36 keV into the donor structure after which about 5 x 10 15 H 2 + ions/cm 2 are implanted at about 48 keV or alternatively about 1 x 10 16 H + ions/cm 2 are implanted at about 24 keV into the donor structure.
• the specific amount of energy required to perform the implantation of the ions into the donor structure depends on type and form of ion(s) selected, the crystallographic structure of the material through which and into which the ions are being implanted and the desired implantation depth. It should be noted that the implantation may be carried out at any temperature suitable for such implantation. Typically, however, the implantation may be carried out at room temperature. It should be further noted that in this regard, the implantation temperature referred to is the global temperature and that localized temperature spikes may occur at the actual site of the ion beam due to the nature of ion implantation.
• the donor structure 10 may be thermally treated to begin the formation a cleave plane at the damage layer 24.
• the donor structure may be thermally treated at a temperature of from about 150°C to about 375°C for a period of from about 1 hour to about 100 hours.
• this thermal treatment may be combined with a thermal treatment performed after the bonding of the donor structure 10 to the second structure 26 so as to simultaneously strengthen the bond between the donor structure 10 and the second structure 26 and begin the formation of the cleave plane at the damage layer 24.
• the second structure 26 comprises either a single wafer or a multi-layered wafer having a bonding surface 28.
• the second structure 26 comprises a single substrate.
• the substrate may be comprised of a material selected from the group consisting of single crystal silicon, sapphire, quartz crystal, glass, silicon carbide, silicon, gallium nitride, aluminum nitride, gallium aluminum nitride or any combination thereof.
• the second structure 26 comprises a single crystal silicon wafer.
• the substrate 26 may have a thickness between about 200 ⁇ and about 1500 ⁇ or between about 500 ⁇ and about 750 ⁇ .
• the second structure includes a dielectric layer (not shown) disposed thereon.
• the dielectric layer may be composed of silicon dioxide or silicon nitride and may also act as a bonding layer to assist in bonding the donor structure 10 to the second structure 26.
• the dielectric layer may be formed as explained above in regard to the dielectric layer 8 of the donor structure 10.
• at least one of the donor structure 10 and the second structure 26 includes a dielectric layer.
• a dielectric layer is formed on both the donor structure 10 and the second structure 26, i.e., the dielectric layers may act as bonding layers for layer transfer. After bonding, the two bonded dielectric layers combine to form the dielectric layer of the Si- Ge-on-insulator structure.
• the dielectric layer may be thermally grown as described above with regard to dielectric layer 8. Alternatively, it may be deposited by CVD (e.g., for silicon dioxide, silicon nitride), atomic layer deposition (e.g., for aluminum oxide, hafnium oxide, zirconium oxide) or molecular beam epitaxy (e.g., for niobium oxide, gadolinium oxide and other rare earth oxides).
• CVD e.g., for silicon dioxide, silicon nitride
• atomic layer deposition e.g., for aluminum oxide, hafnium oxide, zirconium oxide
• molecular beam epitaxy e.g., for niobium oxide, gadolinium oxide and other rare earth oxides.
• forming the final multi-layered crystalline structure comprises transferring the silicon-germanium device layer 14 (or passivation layer 54 or bonding layer if used) of the donor structure 10 onto the second structure 26.
• this transfer is achieved by contacting the implantation surface 16 to the bonding surface 28 of the second structure 26 in order to form a single, bonded structure 30 (Fig. 2) with a bond interface 32 between the two surfaces, and then cleaving or separating the bonded structure along the cleave plane formed along the damage layer 24.
• the implantation surface 16 and/or the bonding surface 28 may optionally undergo cleaning, a brief etching, and/or planarization to prepare these surfaces for bonding, using techniques known in the art. Without being bound by a particular theory, it is generally believed that the quality of both surfaces prior to bonding will have a direct impact on the quality or strength of the resulting bond interface.
• a bonding layer may be formed on the implantation surface and/or the bonding surface prior to bonding the donor structure 10 to the second structure 26. It should be noted that when forming a bonding layer on the donor structure 10, such formation may be performed prior to or after the implantation step.
• the bonding layer may comprise any material suitable for bonding the donor structure 10 to the second structure 26 including for example an oxide layer such as silicon dioxide, silicon nitride, deposited oxides, such as TEOS, and bonding adhesives.
• the inclusion of the bonding layer provides a bonding interface between the donor structure 10 and the second structure 26 so as to prevent the formation of interfacial gaps that may occur during direct bonding of the donor structure 10 and the second structure 26.
• the thermal oxide growth temperature may range from at least about 800°C to about 1100°C (and no more than about 943°C if grown on the donor structure 10), and the thickness of the bonding layer typically ranges from about 10 nm to about 200 nm.
• the atmosphere under which the bonding layer is grown typically comprises oxygen, nitrogen, argon, and/or mixtures thereof for dry oxidations and water vapor for wet oxidations.
• CVD deposited oxides are typically deposited at low temperatures (i.e.
• the roughness of the surface is one way by which the surface quality is quantitatively measured, with lower surface roughness values corresponding to a higher quality surface. Therefore, the implantation surface 16 of the donor structure 10 and/or the bonding surface 28 of the second structure 26 may undergo processing to reduce the surface roughness. For example, in one embodiment, the surface roughness is less than about 5 A. This lowered RMS value can be achieved prior to bonding by cleaning and/or planarization.
• Cleaning may be carried out according to a wet chemical cleaning procedure, such as a hydrophilic surface preparation process.
• a hydrophilic surface preparation process is a RCA SCI clean process, wherein the surfaces are contacted with a solution containing ammonium hydroxide, hydrogen peroxide, and water at a ratio of, for example, 1 :4:20 at about 60°C for about 10 minutes, followed by a deionized water rinse and spin dry.
• Planarization may be carried out using a chemical mechanical polishing (CMP) technique.
• CMP chemical mechanical polishing
• one or both of the surfaces may be subjected to a plasma activation to increase the resulting bond strength before, after, or instead of a wet cleaning process.
• the plasma environment may include, for example, oxygen, ammonia, argon, nitrogen, diborane, or phosphine.
• oxygen, ammonia, argon, nitrogen, diborane, or phosphine may be used in one preferred
• the plasma activation environment is selected from the group consisting of nitrogen, oxygen, and combinations thereof.
• the donor structure 10 is bonded to the second structure 26 by bringing the implantation surface 16 of the donor structure 10 and the bonding surface 28 of the second structure 26 together to form a bond interface 32.
• wafer bonding may be achieved using essentially any technique known in the art, provided the energy employed to achieve formation of the bond interface is sufficient to ensure the integrity of the bond interface is sustained during subsequent processing, such as layer transfer by mechanical cleaving or thermal separation. Typically, however, wafer bonding is achieved by contacting the
• typically heating takes place at temperatures of at least about 200°C, at least about 300°C, at least about 400°C, or even about 500°C or more for a period of time of at least about 5 minutes, about 30 minutes, about 60 minutes, or even about 300 minutes or more.
• this low temperature thermal anneal may be performed in addition to, or in place of, the thermal treatment of the donor structure 10 prior to bonding, which is described above.
• the low temperature thermal anneal of the bonded structure 30 facilitates both the strengthening of the bond interface as well as the formation of the cleave plane that is located along the damage layer 24.
• the resulting bonded structure 30 is subjected to conditions sufficient to induce a fracture along the damage layer 24 within the germanium buffer layer 22 or handle layer 20.
• this fracture may be achieved using techniques known in the art, such as by a mechanical or thermal cleave.
• fracturing is achieved by annealing the bonded structure 30 at an elevated temperature for a period of time to induce fracture.
• the annealing temperature may be at least about 200°C, at least about 250°C or higher.
• the anneal may even be carried out at temperatures of at least about 350°C, about 450°C, about 550°C, about 650°C, or even about 750°C, typically at temperatures of from about 200°C to about 750°C, and more typically from about 200°C to about 400°C. It should be noted, however, that because of the differing coefficients of thermal expansion of the various material involved, it is often preferable to carry out the aforementioned anneal at lower temperatures. As such, the anneal may be preferably carried out using an annealing temperature of from about 200°C to about 300°C. The anneal is performed over a time period of at least about 5 minutes, about 30 minutes, about 60 minutes, or even about 300 minutes. Higher annealing temperatures will require shorter anneal times, and vice versa. The annealing step can be conducted in an ambient or inert atmosphere, e.g., argon or nitrogen.
• an ambient or inert atmosphere e.g., argon or nitrogen.
• the separation i.e., fracturing the structure along the damage layer 24 within the germanium buffer layer 22 or handle layer 20
• the separation includes the application of mechanical force, either alone or in addition to the annealing process.
• the actual means of applying such a mechanical force is not critical to this disclosure; i.e., any known method of applying a mechanical force to induce separation in a semiconductor structure may be employed, so long as substantial damage to the device layer 14 is avoided.
• structure 34 comprises the handle layer 20 and some portion 38 of the germanium buffer layer 22.
• Structure 36 comprises the second structure 26, the dielectric layer 8, the silicon-germanium layer 14 and a residual portion 40 of the germanium buffer layer 22 on the surface thereof.
• structure 34 comprises the a portion of the handle layer and structure 36 comprises the second structure 26, dielectric layer 8, silicon-germanium device layer 14, germanium buffer layer 22 and the residual portion of the handle layer 20.
• the residual portion 40 of the germanium buffer layer 22 has a thickness that is approximately equivalent to the depth at which ions were implanted into the germanium buffer layer 22. Accordingly, this thickness is typically greater than about 10 nm.
• the residual portion 40 may optionally be at least about 20 nm, about 50 nm, about 75 nm, about 100 nm, about 200 nm thick or more.
• the thickness is sufficient to avoid damage to the silicon- germanium device layer 14 upon separation; for example, in one preferred embodiment, the residual portion is between about 20 nm to about 200 nm thick.
• the structure 34 may be recycled for use as a donor structure 1A to produce additional SiGe-on-insulator structures.
• the structure 34 may be smoothed and a silicon-germanium device layer 14 and dielectric layer 8 may be deposited to form the donor structure 10 (Fig. 1A) for further processing.
• bonded structure 36 is subjected to additional processing to produce a multi-layered crystalline structure having desirable features for device fabrication thereon.
• the bonded structure 36 may be subjected to one or more processing steps in order to remove the residual germanium buffer layer 40.
• the residual portion 40 is preferably removed via etching.
• the etching composition may be selected according to various factors, including the composition of the residual portion 40 of the germanium buffer layer 22 and the selectivity of the etchant.
• the entire residual portion 40 of the germanium buffer layer 22 is removed via a wet etching process using an etchant comprising NH 4 OH, H2O2 and H 2 0.
• This etchant is generally known to those skilled in the art and is commonly referred to as an "SCI " solution.
• Such an etching process is typically carried out at a temperature of from about 50°C to about 80°C, with the time period of such an etch depending on the thickness of the layer to be removed, the exact composition of the SCI composition, and the temperature under which the etch is performed.
• the final multi-layered crystalline structure 42 comprises the second structure 26, dielectric layer 8 and the silicon-germanium device layer 14.
• the donor structure 100 may be bonded to the second structure 26 and processed as described above with reference to the donor structure 10 (Fig. 1A).
• the residual germanium buffer layer 40 may be removed by etching.
• the etch stop layer 50 acts to limit the etch and prevent the silicon-germanium device layer 14 from being etched.
• the etch stop layer 50 may be removed by either a dry etch as disclosed by Oehrlein et al. in J. Electrochem. Soc, vol. 138(5) , p. 1443-1452 (1991) or a wet etch as disclosed by Loup et al. in ECS Trans, vol. 58(6), p. 47-55 (2013), both of which are incorporated herein by reference for all relevant and consistent purposes.
• the multi-layered crystalline structure 42 prepared in accordance with the present disclosure may have a substantially uniform thickness ranging from about 300 ⁇ ⁇ about 800 ⁇ .
• the device layer 14 has a thickness of from about 5 nm to about 200 nm
• the dielectric layer 8 has a thickness of from about 10 nm to about 3000 nm
• the second structure 26 has a thickness of from about 300 ⁇ to about 800 ⁇ .
• Multi-layered crystalline structures manufactured according to this disclosure may be used in various technologies.
• the multi-layered crystalline structures of this disclosure are suitable for use in the manufacture of a multi- layered microelectronic or nanoelectronic device comprising a microelectronic or nanoelectronic component and the multi-layered crystalline structure of the instant disclosure.
• Suitable devices include, but are not limited to logic CMOS devices.
• concentrations, temperatures or other physical or chemical properties or characteristics is meant to cover variations that may exist in the upper and/or lower limits of the ranges of the properties or characteristics, including, for example, variations resulting from rounding, measurement methodology or other statistical variation.
• containing and “having” are intended to be inclusive and mean that there may be additional elements other than the listed elements.
• the use of terms indicating a particular orientation e.g., “top”, “bottom”, “side”, etc.) is for convenience of description and does not require any particular orientation of the item described.

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• 2015
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