WO2016095255A1 - 网口保护电路及电视机 - Google Patents

网口保护电路及电视机 Download PDF

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Publication number
WO2016095255A1
WO2016095255A1 PCT/CN2014/094992 CN2014094992W WO2016095255A1 WO 2016095255 A1 WO2016095255 A1 WO 2016095255A1 CN 2014094992 W CN2014094992 W CN 2014094992W WO 2016095255 A1 WO2016095255 A1 WO 2016095255A1
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WO
WIPO (PCT)
Prior art keywords
diode
network signal
protection circuit
signal processing
processing chip
Prior art date
Application number
PCT/CN2014/094992
Other languages
English (en)
French (fr)
Inventor
贺顺亮
Original Assignee
深圳Tcl数字技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳Tcl数字技术有限公司 filed Critical 深圳Tcl数字技术有限公司
Priority to EP14908290.1A priority Critical patent/EP3236654B1/en
Priority to US15/536,141 priority patent/US9979928B2/en
Publication of WO2016095255A1 publication Critical patent/WO2016095255A1/zh

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/10—Adaptations for transmission by electrical cable
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/10—Adaptations for transmission by electrical cable
    • H04N7/102—Circuits therefor, e.g. noise reducers, equalisers, amplifiers
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/60—Network structure or processes for video distribution between server and client or between remote clients; Control signalling between clients, server and network components; Transmission of management data between server and client, e.g. sending from server to client commands for recording incoming content stream; Communication details between server and client 
    • H04N21/61—Network physical structure; Signal processing
    • H04N21/615—Signal processing at physical level
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/60—Network structure or processes for video distribution between server and client or between remote clients; Control signalling between clients, server and network components; Transmission of management data between server and client, e.g. sending from server to client commands for recording incoming content stream; Communication details between server and client 
    • H04N21/61—Network physical structure; Signal processing
    • H04N21/6156—Network physical structure; Signal processing specially adapted to the upstream path of the transmission network
    • H04N21/6175—Network physical structure; Signal processing specially adapted to the upstream path of the transmission network involving transmission via Internet
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/10—Adaptations for transmission by electrical cable
    • H04N7/106—Adaptations for transmission by electrical cable for domestic distribution

Definitions

  • the present invention relates to the field of electronic technologies, and in particular, to a network port protection circuit and a television set.
  • the network port circuit includes an Ethernet interface 101, a first isolation transformer T11, a second isolation transformer T12, a network signal processing chip 102, a resistor R11, a resistor R12, and a capacitor C11.
  • the Ethernet interface 101 is configured to receive and send a network signal;
  • the first isolation transformer T11 is configured to isolate the receiving data end of the Ethernet interface 101 from the network signal receiving chip 102;
  • the second isolation transformer T12 is configured to isolate the transmit data end of the Ethernet interface 101 from the network signal receiving chip 102;
  • the network signal processing chip 102 is configured to process the network signal.
  • the positive end RX+ of the receiving data end of the Ethernet interface 101 is connected to the first end of the second primary side coil of the first isolation transformer T11, and the negative end RX- of the receiving data end of the Ethernet interface 101 Connecting with the first end of the first primary winding of the first isolation transformer T11; the second end of the first primary winding of the first isolation transformer T11 and the second primary of the first isolation transformer T11
  • the second end of the coil is connected to the first end of the capacitor C11 via the resistor R11; the second end of the capacitor C11 is grounded;
  • the positive terminal TX+ of the transmit data end of the Ethernet interface 101 and the second isolation transformer T12 a first end of the fourth primary coil is connected, and a negative end TX- of the transmit data end of the Ethernet interface 101 is connected to a first end of the third primary coil of the second isolation transformer T12; the second isolation a second end of the third primary winding of the transformer T12 and a second end of the fourth primary winding of the second isolation transformer T12 are connected to the first end
  • the transmit data positive terminal TX1+ of 102 is connected.
  • the receiving data negative terminal RX1 of the network signal processing chip 102 is provided with an electrostatic protection circuit 1021
  • the receiving data positive end RX1+ of the network signal processing chip 102 is provided with an electrostatic protection circuit 1022, and the network signal processing chip 102 is provided.
  • the transmit data positive terminal TX1+ is provided with an electrostatic protection circuit 1023
  • the transmit data positive terminal TX1+ of the network signal processing chip 102 is provided with an electrostatic protection circuit 1024.
  • the static electricity protection circuit 1021 includes a diode D11 and a diode D12 (the diode D11 and the diode D12 are diodes having a small parasitic capacitance).
  • the cathode of the diode D11 is connected to the working voltage input terminal VCC1 of the network signal processing chip 102, and the anode of the diode D11 and the receiving data negative terminal RX1 of the network signal processing chip 102 and the diode respectively.
  • the cathode of D12 is connected; the anode of the diode D12 is grounded; the static protection circuit 1022 includes a diode D13 and a diode D14 (diodes D13 and D14 are diodes having a small parasitic capacitance).
  • the cathode of the diode D13 is connected to the operating voltage input terminal VCC1 of the network signal processing chip 102, and the anode of the diode D13 and the receiving data positive terminal RX1+ and the diode D14 of the network signal processing chip 102, respectively.
  • the cathode connection; the anode of the diode D14 is grounded;
  • the static protection circuit 1023 includes a diode D15 and a diode D16 (diode D15 and diode D16 are diodes having a small parasitic capacitance).
  • the cathode of the diode D15 is connected to the working voltage input terminal VCC1 of the network signal processing chip 102, and the anode of the diode D15 is respectively connected with the negative data terminal TX1- of the network signal processing chip 102 and the diode.
  • the cathode of D16 is connected; the anode of the diode D16 is grounded; the static protection circuit 1024 includes a diode D17 and a diode D18 (diode D17 and diode D18 are diodes having a small parasitic capacitance).
  • the cathode of the diode D17 is connected to the operating voltage input terminal VCC1 of the network signal processing chip 102, and the anode of the diode D17 and the transmitting data positive terminal TX1+ and the diode D18 of the network signal processing chip 102, respectively.
  • the cathode connection; the anode of the diode D18 is grounded.
  • the common mode interference voltage is simultaneously applied to the positive terminal RX+ of the receiving data terminal of the Ethernet interface 101, the negative terminal RX- of the receiving data terminal, the positive terminal TX+ of the transmitting data terminal, and the signal line of the negative terminal TX- of the transmitting data terminal.
  • the static electricity protection circuit 1021, the static electricity protection circuit 1022, the static electricity protection circuit 1023, and the static electricity protection circuit 1021 of the network port signal processing chip 102 have a certain protection against the common mode interference voltage, if the common mode interference voltage is sufficient When large, the large enough common mode interference voltage will break through the first isolation transformer T11 and the second isolation transformer T12, thereby affecting or even damaging the network signal processing chip 102, thereby affecting or even damaging the network function of the television; When the signal line of the positive terminal RX+ of the receiving data end of the Ethernet interface 101 and the signal line of the negative terminal RX- of the receiving data terminal are interfered by the differential mode voltage of opposite phase, a large differential mode is formed between the two signal lines.
  • the differential mode current will be transmitted to the secondary side through the primary side of the first isolation transformer T11, thereby affecting or even damaging the network signal processing chip 102; If the signal line of the positive terminal TX+ of the transmitting data end of the Ethernet interface 101 and the signal line of the negative terminal TX- of the transmitting data end are interfered by the differential mode voltage of opposite phase, a comparison is also formed between the two signal lines.
  • the large differential mode current which is transmitted to the secondary side through the primary side of the second isolation transformer T12, also affects or even damages the network signal processing chip 102, thereby affecting or even damaging the network function of the television.
  • the main object of the present invention is to provide a low-cost network port protection circuit capable of protecting common mode interference and differential mode interference.
  • the present invention provides a network port protection circuit, where the network port protection circuit includes an Ethernet interface, a first isolation transformer, a second isolation transformer, a network signal processing chip, and a first interference protection circuit;
  • the Ethernet interface is configured to receive and send a network signal
  • the first isolation transformer is configured to isolate a receiving data end of the Ethernet interface from the network signal receiving chip
  • the second isolation transformer is configured to isolate a transmitting data end of the Ethernet interface from the network signal receiving chip
  • the first interference protection circuit is configured to protect common mode interference and differential mode interference of the receiving data end of the Ethernet interface
  • the network signal processing chip is configured to process the network signal
  • a receiving data end of the Ethernet interface is connected to a primary side of the first isolation transformer; the first interference protection circuit is connected between a secondary side of the first isolation transformer and the network signal receiving chip The transmitting data end of the Ethernet interface is connected to the primary side of the second isolation transformer; the secondary side of the second isolation transformer is connected to the network signal processing chip.
  • the first interference protection circuit includes a first clamping diode, a second clamping diode, a first resistor and a second resistor; wherein
  • An anode of the first clamping diode and an anode of the second clamping diode are both grounded; a cathode of the first clamping diode is connected to a first end of a secondary side coil of the first isolation transformer; a cathode of the second clamping diode is connected to a second end of the secondary side coil of the first isolation transformer; a cathode of the first clamping diode is further connected to the network signal processing chip via the first resistor Receiving a negative connection of the data; the cathode of the second clamping diode is further connected to the positive end of the received data of the network signal processing chip via the second resistor.
  • the network port protection circuit further includes a second interference protection circuit for protecting common mode interference and differential mode interference of the transmit data end of the Ethernet interface; the second interference protection circuit is connected to the The secondary side of the second isolation transformer is between the network signal receiving chip.
  • the second interference protection circuit includes a third clamping diode, a fourth clamping diode, a third resistor, and a fourth resistor; wherein
  • An anode of the third clamping diode and an anode of the fourth clamping diode are both grounded; a cathode of the third clamping diode is connected to a first end of a secondary side coil of the second isolation transformer; a cathode of the fourth clamping diode is connected to a second end of the secondary side coil of the second isolation transformer; a cathode of the third clamping diode is further connected to the network signal processing chip via the third resistor Transmitting a data negative terminal connection; a cathode of the fourth clamping diode is further connected to a positive end of the transmission data of the network signal processing chip via the fourth resistor.
  • the network port protection circuit further includes a fifth resistor, a sixth resistor, and a first capacitor;
  • the primary side coil of the first isolation transformer includes a first primary coil and a second primary coil;
  • the primary side coil of the second isolation transformer includes a third primary coil and a fourth primary coil; among them,
  • a positive end of the receiving data end of the Ethernet interface is connected to a first end of the second primary side coil, and a negative end of the receiving data end of the Ethernet interface is connected to a first end of the first primary side coil;
  • the second end of the first primary coil and the second end of the second primary coil are both connected to the first end of the first capacitor via the fifth resistor; the second of the first capacitor Grounded at the end;
  • a positive end of the transmit data end of the Ethernet interface is connected to a first end of the fourth primary side coil, and a negative end of the transmit data end of the Ethernet interface is connected to a first end of the third primary side coil;
  • the second end of the third primary coil and the second end of the fourth primary coil are both connected to the first end of the first capacitor via the sixth resistor.
  • the negative end of the receiving data of the network signal processing chip is provided with a first static electricity protection circuit;
  • the first static electricity protection circuit comprises a first diode and a second diode;
  • a cathode of the first diode is connected to an operating voltage input end of the network signal processing chip, and an anode of the first diode and a receiving data negative end of the network signal processing chip and the second The cathode of the diode is connected; the anode of the second diode is grounded.
  • the received data front end of the network signal processing chip is provided with a second static electricity protection circuit;
  • the second static electricity protection circuit includes a third diode and a fourth diode;
  • a cathode of the third diode is connected to an operating voltage input end of the network signal processing chip, and an anode of the third diode and a receiving data positive end and the fourth of the network signal processing chip respectively
  • the cathode of the diode is connected; the anode of the fourth diode is grounded.
  • the negative end of the transmission data of the network signal processing chip is provided with a third static electricity protection circuit;
  • the third static electricity protection circuit includes a fifth diode and a sixth diode;
  • a cathode of the fifth diode is connected to an operating voltage input end of the network signal processing chip, and an anode of the fifth diode and a negative end of the transmission data of the network signal processing chip and the sixth
  • the cathode of the diode is connected; the anode of the sixth diode is grounded.
  • a positive electrode end of the transmission data of the network signal processing chip is provided with a fourth static electricity protection circuit; and the fourth static electricity protection circuit includes a seventh diode and an eighth diode;
  • a cathode of the seventh diode is connected to an operating voltage input end of the network signal processing chip, and an anode of the seventh diode and a transmitting data positive end of the network signal processing chip and the eighth
  • the cathode of the diode is connected; the anode of the eighth diode is grounded.
  • the present invention further provides a television set, the television set includes a network port protection circuit, and the network port protection circuit includes an Ethernet interface, a first isolation transformer, a second isolation transformer, and network signal processing. a chip and a first interference protection circuit;
  • the Ethernet interface is configured to receive and send a network signal
  • the first isolation transformer is configured to isolate a receiving data end of the Ethernet interface from the network signal receiving chip
  • the second isolation transformer is configured to isolate a transmitting data end of the Ethernet interface from the network signal receiving chip
  • the first interference protection circuit is configured to protect common mode interference and differential mode interference of the receiving data end of the Ethernet interface
  • the network signal processing chip is configured to process the network signal
  • a receiving data end of the Ethernet interface is connected to a primary side of the first isolation transformer; the first interference protection circuit is connected between a secondary side of the first isolation transformer and the network signal receiving chip The transmitting data end of the Ethernet interface is connected to the primary side of the second isolation transformer; the secondary side of the second isolation transformer is connected to the network signal processing chip.
  • the network port protection circuit comprises an Ethernet interface, a first isolation transformer, a second isolation transformer, a network signal processing chip and a first interference protection circuit;
  • the Ethernet interface is configured to receive and transmit a network signal;
  • a first isolation transformer is configured to isolate a receiving data end of the Ethernet interface from the network signal receiving chip;
  • the second isolation transformer is configured to receive a data end of the Ethernet interface and receive the network signal
  • the chip is isolated;
  • the first interference protection circuit is configured to protect common mode interference and differential mode interference of the receiving data end of the Ethernet interface;
  • the network signal processing chip is configured to process the network signal;
  • the receiving data end of the Ethernet interface is connected to the primary side of the first isolation transformer;
  • the first interference protection circuit is connected between the secondary side of the first isolation transformer and the network signal receiving chip;
  • a transmitting data end of the Ethernet interface is connected to a primary side of the second isolation transformer; a secondary side of the second isolation transformer Connected to the network signal processing chip.
  • the network port protection circuit of the invention can
  • FIG. 1 is a schematic diagram of a circuit structure of a network port circuit in the prior art
  • FIG. 2 is a schematic diagram showing the circuit structure of an embodiment of a network port protection circuit of the present invention.
  • the invention provides a network port protection circuit.
  • FIG. 2 is a schematic diagram showing the circuit structure of an embodiment of the network port protection circuit of the present invention.
  • the network port protection circuit includes an Ethernet interface 201, a first isolation transformer T21, a second isolation transformer T22, a network signal processing chip 202, a first interference protection circuit 203, and a second interference protection circuit 204.
  • the Ethernet interface 201 is configured to receive and send a network signal.
  • the Ethernet interface 201 is an RJ45 network port.
  • the first isolation transformer T21 is configured to isolate the receiving data end of the Ethernet interface 201 from the network signal receiving chip 202;
  • the second isolation transformer T22 is configured to isolate the transmit data end of the Ethernet interface 201 from the network signal receiving chip 202;
  • the first interference protection circuit 203 is configured to protect common mode interference and differential mode interference of the receiving data end of the Ethernet interface 201;
  • the second interference protection circuit 204 is configured to protect common mode interference and differential mode interference of the data end of the Ethernet interface 201;
  • the network signal processing chip 202 is configured to process the network signal.
  • the receiving data end of the Ethernet interface 201 is connected to the primary side of the first isolation transformer T21; the first interference protection circuit 203 is connected to the secondary side of the first isolation transformer T21.
  • the network signal receiving chip 202; the transmitting data end of the Ethernet interface 201 is connected to the primary side of the second isolation transformer T22; the second interference protection circuit 204 is connected to the second isolation
  • the secondary side of the transformer T22 is between the network signal receiving chip 202.
  • the first interference protection circuit 203 includes a first clamping diode ZD1, a second clamping diode ZD2, a first resistor R1, and a second resistor R2.
  • the resistances of the first resistor R1 and the second resistor R2 are 2.2 ohms;
  • the anode of the first clamping diode ZD1 and the anode of the second clamping diode ZD2 are both grounded; the cathode of the first clamping diode ZD1 and the secondary side coil of the first isolation transformer T21 ( The first end of the second clamping diode ZD2 is connected to the second end of the secondary side winding of the first isolation transformer T21; the cathode of the first clamping diode ZD1 is further The first resistor R1 is connected to the receiving data negative terminal RX2- of the network signal processing chip 202; the cathode of the second clamping diode ZD2 is further connected to the network signal processing chip 202 via the second resistor R2. The receiving data is connected to the positive end RX2+.
  • the second interference protection circuit 204 includes a third clamping diode ZD3, a fourth clamping diode ZD4, a third resistor R3, and a fourth resistor R4.
  • the resistance of the third resistor R3 and the fourth resistor R4 is 2.2 ohms;
  • the anode of the third clamping diode ZD3 and the anode of the fourth clamping diode ZD4 are both grounded; the cathode of the third clamping diode ZD3 and the secondary side coil of the second isolation transformer T22 ( The first end of the second clamping diode ZD4 is connected to the second end of the secondary side winding of the second isolation transformer T22; the cathode of the third clamping diode ZD3 is further The third resistor R3 is connected to the transmission data negative terminal TX2- of the network signal processing chip 202; the cathode of the fourth clamping diode ZD4 is further connected to the network signal processing chip 202 via the fourth resistor R4. The transmit data is sent to the positive terminal TX2+.
  • the network port protection circuit of the embodiment further includes a fifth resistor R5, a sixth resistor R6, and a first capacitor C1;
  • the primary side coil of the first isolation transformer T21 includes a first primary coil and a second primary The coil (not labeled);
  • the primary side coil of the second isolation transformer T22 includes a third primary coil and a fourth primary coil (not labeled).
  • the positive end RX+ of the receiving data end of the Ethernet interface 201 is connected to the first end of the second primary side coil of the first isolation transformer T21.
  • the negative end RX- of the receiving data end of the Ethernet interface 201 is a first end of the first primary winding of the first isolation transformer T21 is connected; a second end of the first primary winding of the first isolation transformer T21 and a second primary winding of the first isolation transformer T21
  • the second end of the second capacitor R5 is connected to the first end of the first capacitor C1; the second end of the first capacitor C1 is grounded; the positive end TX+ of the transmit data end of the Ethernet interface 201 Connected to the first end of the fourth primary winding of the second isolation transformer T22, the negative terminal TX- of the transmitting data end of the Ethernet interface 201 and the third primary winding of the second isolation transformer T22 Connected to one end; the second end of the third primary winding of the second isolation transformer T22 and the second end of the fourth primary winding of the second isolation transformer T22 are
  • the receiving data negative terminal RX2- of the network signal processing chip 202 is provided with a first static electricity protection circuit 2021.
  • the first static electricity protection circuit 2021 includes a first diode D1 and a second diode D2.
  • the cathode of the first diode D1 is connected to the working voltage input terminal VCC2 of the network signal processing chip 202, and the anode of the first diode D1 and the receiving data of the network signal processing chip 202 respectively.
  • a negative terminal RX2- and a cathode of the second diode D2 are connected; an anode of the second diode D2 is grounded;
  • the receiving data positive terminal RX2+ of the network signal processing chip 202 is provided with a second static electricity protection circuit 2022.
  • the second static electricity protection circuit 2022 includes a third diode D3 and a fourth diode D4.
  • the cathode of the third diode D3 is connected to the working voltage input terminal VCC2 of the network signal processing chip 202, and the anode of the third diode D3 and the receiving data of the network signal processing chip 202 respectively.
  • a positive terminal RX2+ is connected to a cathode of the fourth diode D4; an anode of the fourth diode D4 is grounded;
  • the transmitting data negative terminal TX2- of the network signal processing chip 202 is provided with a third static electricity protection circuit 2023.
  • the third static electricity protection circuit 2023 includes a fifth diode D5 and a sixth diode D6.
  • the cathode of the fifth diode D5 is connected to the working voltage input terminal VCC2 of the network signal processing chip 202, and the anode of the fifth diode D5 and the network signal processing chip 202 respectively transmit data.
  • a negative terminal TX2- is connected to a cathode of the sixth diode D6; an anode of the sixth diode D6 is grounded;
  • the transmitting data positive terminal TX2+ of the network signal processing chip 202 is provided with a fourth static electricity protection circuit 2024.
  • the fourth static electricity protection circuit 2024 includes a seventh diode D7 and an eighth diode D8.
  • the cathode of the seventh diode D7 is connected to the working voltage input terminal VCC2 of the network signal processing chip 202, and the anode of the seventh diode D7 and the network signal processing chip 202 respectively transmit data.
  • the positive terminal TX2+ is connected to the cathode of the eighth diode D8; the anode of the eighth diode D8 is grounded.
  • the working principle of the network port protection circuit in this embodiment is specifically described as follows: when the common mode interference voltage exceeds the reverse of the first clamping diode ZD1 and the second clamping diode ZD2 in the first interference protection circuit 203 When the voltage is breakdown, the first clamping diode ZD1 and the second clamping diode ZD2 are reverse-conducted, and the negative terminal RX- of the receiving data end of the Ethernet interface 201 and the positive terminal RX+ of the receiving data end are The voltage on the signal line is clamped at a lower voltage level, thereby protecting the network signal processing chip 202 of the subsequent stage from being damaged; similarly, when the common mode interference voltage exceeds the above in the second interference protection circuit 204 When the reverse breakdown voltage of the third clamping diode ZD3 and the fourth clamping diode ZD4 is reversed, the third clamping diode ZD3 and the fourth clamping diode ZD4 are reverse-conducted, and the Ethernet The voltage on the negative terminal TX- of the transmitting data terminal of
  • the first clamping diode ZD1 in the first interference preventing circuit 203 is first reversely broken down (because both points A and B in the figure)
  • the current is i3, and the current i3 flows down through the fourth diode D4 in the network signal processing chip 202 and the second clamping diode ZD2 in the first interference protection circuit 203.
  • the forward voltage drop of the fourth diode D4 is VD4
  • the forward voltage of the second clamping diode ZD2 is VZD2
  • VZD2 is greater than VD4
  • the fourth diode D4 is preferentially turned on, but the current flowing through the fourth diode D4 is limited to a certain current value i2 (specific current), as long as the setting is appropriate in this embodiment
  • the second resistor R2 of the magnitude of the resistance is such that the current i2 flowing through the fourth diode D4 is not too large, so that the fourth diode D4 is not burned by overcurrent, and further
  • the fourth diode D4 is protected, that is, the network signal processing chip 202 is protected.
  • the first clamping diode ZD1 and the anode of the second clamping diode ZD2 are both grounded, the first clamping diode ZD1 and the second clamping diode are ZD2 also has a protective effect on the common mode interference voltage.
  • the second interference protection circuit 204 can also function to protect the network signal processing chip 202.
  • the network port protection circuit of the embodiment includes an Ethernet interface, a first isolation transformer, a second isolation transformer, a network signal processing chip, a first interference protection circuit, and a second interference protection circuit;
  • the Ethernet interface is used for receiving and transmitting a network signal;
  • the first isolation transformer is configured to isolate a receiving data end of the Ethernet interface from the network signal receiving chip;
  • the second isolation transformer is configured to send a data end of the Ethernet interface
  • the network signal receiving chip performs isolation;
  • the first interference protection circuit is configured to protect common mode interference and differential mode interference of the receiving data end of the Ethernet interface; and the second interference protection circuit is configured to The common mode interference and the differential mode interference of the transmitting data end of the Ethernet interface are protected; and the network signal processing chip is configured to process the network signal.
  • the receiving data end of the Ethernet interface is connected to the primary side of the first isolation transformer; the first interference protection circuit is connected to the secondary side of the first isolation transformer and the network signal receiving chip The transmitting data end of the Ethernet interface is connected to the primary side of the second isolation transformer; the second interference protection circuit is connected to the secondary side of the second isolation transformer and the network signal receiving Between the chips.
  • the network port protection circuit of the embodiment can protect the common mode interference and the differential mode interference; and the network port protection circuit of the invention has low cost; and the invention also has the advantages of simple circuit structure and easy implementation.
  • the present invention also provides a television set, which includes a network port protection circuit.
  • the circuit structure of the network port protection circuit and the working principle thereof can be referred to the above embodiments, and details are not described herein again.
  • the television set of the embodiment adopts the technical solution of the above-mentioned network port protection circuit, the television set has all the beneficial effects of the above-mentioned network port protection circuit.

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Abstract

本发明公开了一种网口保护电路，该电路包括以太网接口、第一隔离变压器、第二隔离变压器、网络信号处理芯片及第一干扰防护电路；以太网接口用于接收和发送网络信号；第一隔离变压器用于对以太网接口的接收数据端和网络信号接收芯片进行隔离；第二隔离变压器用于对以太网接口的发送数据端和网络信号接收芯片进行隔离；第一干扰防护电路用于对以太网接口的接收数据端的共模干扰和差模干扰进行防护；网络信号处理芯片用于对所述网络信号进行处理。本发明还公开了一种电视机。本发明网口保护电路对共模干扰及差模干扰都能够进行防护；并且，本发明还具有成本低、电路结构简单及易实现的优点。

Description

网口保护电路及电视机
技术领域
本发明涉及电子技术领域，特别涉及一种网口保护电路及电视机。
背景技术
随着互联网技术的快速发展，带网口的互联网电视也逐步得到普及，在电视机上插上一根网线，用户便能在电视机上在线浏览网页、看电视及欣赏电影等。但是，当用户在室外使用了较长的网线时（如该用户将宽带网络从邻居家接入到室内），由于较长的网线暴露在室外，在雷电天气时，雷电有可能在网线上感应产生较大的共模干扰电压和差模干扰电压，该较大的共模干扰电压和差模干扰电压会影响甚至损坏电视机内网口电路中的网络信号处理芯片，从而影响甚至损坏电视机的网络功能。
图1是现有技术中网口电路一实施例的电路结构示意图。如图1所示，该网口电路包括以太网接口101、第一隔离变压器T11、第二隔离变压器T12、网络信号处理芯片102、电阻R11、电阻R12及电容C11。其中，所述以太网接口101用于接收和发送网络信号；所述第一隔离变压器T11用于对所述以太网接口101的接收数据端和所述网络信号接收芯片102进行隔离；所述第二隔离变压器T12用于对所述以太网接口101的发送数据端和所述网络信号接收芯片102进行隔离；所述网络信号处理芯片102用于对所述网络信号进行处理。具体地，所述以太网接口101的接收数据端的正端RX+与所述第一隔离变压器T11的第二原边线圈的第一端连接，所述以太网接口101的接收数据端的负端RX-与所述第一隔离变压器T11的第一原边线圈的第一端连接；所述第一隔离变压器T11的第一原边线圈的第二端及所述第一隔离变压器T11的第二原边线圈的第二端均经电阻R11与电容C11的第一端连接；所述电容C11的第二端接地；所述以太网接口101的发送数据端的正端TX+与所述第二隔离变压器T12的第四原边线圈的第一端连接，所述以太网接口101的发送数据端的负端TX-与所述第二隔离变压器T12的第三原边线圈的第一端连接；所述第二隔离变压器T12的第三原边线圈的第二端及所述第二隔离变压器T12的第四原边线圈的第二端均经电阻R12与电容C11的第一端连接；所述第一隔离变压器T11的次边侧线圈的第一端与所述网络信号处理芯片102的接收数据负端RX1-连接，所述第一隔离变压器T11的次边侧线圈的第二端与所述网络信号处理芯片102的接收数据正端RX1+连接；所述第二隔离变压器T12的次边侧线圈的第一端与所述网络信号处理芯片102的发送数据负端TX1-连接，所述第二隔离变压器T12的次边侧线圈的第二端与所述网络信号处理芯片102的发送数据正端TX1+连接。另外，所述网络信号处理芯片102的接收数据负端RX1-设有静电防护电路1021，所述网络信号处理芯片102的接收数据正端RX1+设有静电防护电路1022，所述网络信号处理芯片102的发送数据正端TX1+设有静电防护电路1023，所述网络信号处理芯片102的发送数据正端TX1+设有静电防护电路1024。其中，静电防护电路1021包括二极管D11和二极管D12（二极管D11和二极管D12均为寄生电容很小的二极管）。其中，所述二极管D11的阴极与所述网络信号处理芯片102的工作电压输入端VCC1连接，所述二极管D11的阳极分别与所述网络信号处理芯片102的接收数据负端RX1-及所述二极管D12的阴极连接；所述二极管D12的阳极接地；静电防护电路1022包括二极管D13和二极管D14（二极管D13和二极管D14均为寄生电容很小的二极管）。其中，所述二极管D13的阴极与所述网络信号处理芯片102的工作电压输入端VCC1连接，所述二极管D13的阳极分别与所述网络信号处理芯片102的接收数据正端RX1+及所述二极管D14的阴极连接；所述二极管D14的阳极接地；静电防护电路1023包括二极管D15和二极管D16（二极管D15和二极管D16均为寄生电容很小的二极管）。其中，所述二极管D15的阴极与所述网络信号处理芯片102的工作电压输入端VCC1连接，所述二极管D15的阳极分别与所述网络信号处理芯片102的发送数据负端TX1-及所述二极管D16的阴极连接；所述二极管D16的阳极接地；静电防护电路1024包括二极管D17和二极管D18（二极管D17和二极管D18均为寄生电容很小的二极管）。其中，所述二极管D17的阴极与所述网络信号处理芯片102的工作电压输入端VCC1连接，所述二极管D17的阳极分别与所述网络信号处理芯片102的发送数据正端TX1+及所述二极管D18的阴极连接；所述二极管D18的阳极接地。
参照图1，假如共模干扰电压同时加到以太网接口101的接收数据端的正端RX+、接收数据端的负端RX-、发送数据端的正端TX+及发送数据端的负端TX-的信号线时，虽然网口信号处理芯片102内部的静电防护电路1021、静电防护电路1022、静电防护电路1023及静电防护电路1021对该共模干扰电压具有一定的抵御防护作用，但若该共模干扰电压足够大时，该足够大的共模干扰电压则会击穿所述第一隔离变压器T11和第二隔离变压器T12，进而影响甚至损坏网络信号处理芯片102，从而影响甚至损坏电视机的网络功能；假如以太网接口101的接收数据端的正端RX+的信号线和接收数据端的负端RX-的信号线受到相位相反的差模电压干扰时，则会在该两信号线之间形成较大的差模电流，该差模电流会通过第一隔离变压器T11的原边传递到次边，进而影响甚至损坏网络信号处理芯片102；同理，假如以太网接口101的发送数据端的正端TX+的信号线和发送数据端的负端TX-的信号线受到相位相反的差模电压干扰时，则会在该两信号线之间也形成较大的差模电流，该差模电流会通过第二隔离变压器T12的原边传递到次边，同样会影响甚至损坏网络信号处理芯片102，从而影响甚至损坏电视机的网络功能。
发明内容
本发明的主要目的是提供一种能对共模干扰和差模干扰进行防护的低成本网口保护电路。
为实现上述目的，本发明提供一种网口保护电路，所述网口保护电路包括以太网接口、第一隔离变压器、第二隔离变压器、网络信号处理芯片及第一干扰防护电路；其中，
所述以太网接口，用于接收和发送网络信号；
所述第一隔离变压器，用于对所述以太网接口的接收数据端和所述网络信号接收芯片进行隔离；
所述第二隔离变压器，用于对所述以太网接口的发送数据端和所述网络信号接收芯片进行隔离；
所述第一干扰防护电路，用于对所述以太网接口的接收数据端的共模干扰和差模干扰进行防护；
所述网络信号处理芯片，用于对所述网络信号进行处理；
所述以太网接口的接收数据端与所述第一隔离变压器的原边侧连接；所述第一干扰防护电路连接于所述第一隔离变压器的次边侧和所述网络信号接收芯片之间；所述以太网接口的发送数据端与所述第二隔离变压器的原边侧连接；所述第二隔离变压器的次边侧与所述网络信号处理芯片连接。
优选地，所述第一干扰防护电路包括第一钳位二极管、第二钳位二极管、第一电阻及第二电阻；其中，
所述第一钳位二极管的阳极和所述第二钳位二极管的阳极均接地；所述第一钳位二极管的阴极与所述第一隔离变压器的次边侧线圈的第一端连接；所述第二钳位二极管的阴极与所述第一隔离变压器的次边侧线圈的第二端连接；所述第一钳位二极管的阴极还经所述第一电阻与所述网络信号处理芯片的接收数据负端连接；所述第二钳位二极管的阴极还经所述第二电阻与所述网络信号处理芯片的接收数据正端连接。
优选地，所述网口保护电路还包括用于对所述以太网接口的发送数据端的共模干扰和差模干扰进行防护的第二干扰防护电路；所述第二干扰防护电路连接于所述第二隔离变压器的次边侧和所述网络信号接收芯片之间。
优选地，所述第二干扰防护电路包括第三钳位二极管、第四钳位二极管、第三电阻及第四电阻；其中，
所述第三钳位二极管的阳极和所述第四钳位二极管的阳极均接地；所述第三钳位二极管的阴极与所述第二隔离变压器的次边侧线圈的第一端连接；所述第四钳位二极管的阴极与所述第二隔离变压器的次边侧线圈的第二端连接；所述第三钳位二极管的阴极还经所述第三电阻与所述网络信号处理芯片的发送数据负端连接；所述第四钳位二极管的阴极还经所述第四电阻与所述网络信号处理芯片的发送数据正端连接。
优选地，所述网口保护电路还包括第五电阻、第六电阻及第一电容；所述第一隔离变压器的原边侧线圈包括第一原边线圈和第二原边线圈；所述第二隔离变压器的原边侧线圈包括第三原边线圈和第四原边线圈； 其中，
所述以太网接口的接收数据端的正端与所述第二原边线圈的第一端连接，所述以太网接口的接收数据端的负端与所述第一原边线圈的第一端连接；所述第一原边线圈的第二端及所述第二原边线圈的第二端均经所述第五电阻与所述第一电容的第一端连接；所述第一电容的第二端接地；
所述以太网接口的发送数据端的正端与所述第四原边线圈的第一端连接，所述以太网接口的发送数据端的负端与所述第三原边线圈的第一端连接；所述第三原边线圈的第二端及所述第四原边线圈的第二端均经所述第六电阻与所述第一电容的第一端连接。
优选地，所述网络信号处理芯片的接收数据负端设有第一静电防护电路；所述第一静电防护电路包括第一二极管和第二二极管；其中，
所述第一二极管的阴极与所述网络信号处理芯片的工作电压输入端连接，所述第一二极管的阳极分别与所述网络信号处理芯片的接收数据负端及所述第二二极管的阴极连接；所述第二二极管的阳极接地。
优选地，所述网络信号处理芯片的接收数据正端设有第二静电防护电路；所述第二静电防护电路包括第三二极管和第四二极管；其中，
所述第三二极管的阴极与所述网络信号处理芯片的工作电压输入端连接，所述第三二极管的阳极分别与所述网络信号处理芯片的接收数据正端和所述第四二极管的阴极连接；所述第四二极管的阳极接地。
优选地，所述网络信号处理芯片的发送数据负端设有第三静电防护电路；所述第三静电防护电路包括第五二极管和第六二极管；其中，
所述第五二极管的阴极与所述网络信号处理芯片的工作电压输入端连接，所述第五二极管的阳极分别与所述网络信号处理芯片的发送数据负端和所述第六二极管的阴极连接；所述第六二极管的阳极接地。
优选地，所述网络信号处理芯片的发送数据正端设有第四静电防护电路；所述第四静电防护电路包括第七二极管和第八二极管；其中，
所述第七二极管的阴极与所述网络信号处理芯片的工作电压输入端连接，所述第七二极管的阳极分别与所述网络信号处理芯片的发送数据正端和所述第八二极管的阴极连接；所述第八二极管的阳极接地。
此外，为实现上述目的，本发明还提供一种电视机，所述电视机包括网口保护电路，所述网口保护电路包括以太网接口、第一隔离变压器、第二隔离变压器、网络信号处理芯片及第一干扰防护电路；其中，
所述以太网接口，用于接收和发送网络信号；
所述第一隔离变压器，用于对所述以太网接口的接收数据端和所述网络信号接收芯片进行隔离；
所述第二隔离变压器，用于对所述以太网接口的发送数据端和所述网络信号接收芯片进行隔离；
所述第一干扰防护电路，用于对所述以太网接口的接收数据端的共模干扰和差模干扰进行防护；
所述网络信号处理芯片，用于对所述网络信号进行处理；
所述以太网接口的接收数据端与所述第一隔离变压器的原边侧连接；所述第一干扰防护电路连接于所述第一隔离变压器的次边侧和所述网络信号接收芯片之间；所述以太网接口的发送数据端与所述第二隔离变压器的原边侧连接；所述第二隔离变压器的次边侧与所述网络信号处理芯片连接。
本发明提供的网口保护电路，包括以太网接口、第一隔离变压器、第二隔离变压器、网络信号处理芯片及第一干扰防护电路；所述以太网接口用于接收和发送网络信号；所述第一隔离变压器用于对所述以太网接口的接收数据端和所述网络信号接收芯片进行隔离；所述第二隔离变压器用于对所述以太网接口的发送数据端和所述网络信号接收芯片进行隔离；所述第一干扰防护电路用于对所述以太网接口的接收数据端的共模干扰和差模干扰进行防护；所述网络信号处理芯片用于对所述网络信号进行处理；所述以太网接口的接收数据端与所述第一隔离变压器的原边侧连接；所述第一干扰防护电路连接于所述第一隔离变压器的次边侧和所述网络信号接收芯片之间；所述以太网接口的发送数据端与所述第二隔离变压器的原边侧连接；所述第二隔离变压器的次边侧与所述网络信号处理芯片连接。本发明网口保护电路能够对共模干扰和差模干扰进行防护；并且，本发明网口保护电路的成本低；同时，本发明还具有电路结构简单及易实现的优点。
附图说明
图1是现有技术中网口电路的电路结构示意图；
图2是本发明网口保护电路一实施例的电路结构示意图。
本发明目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
本发明提供一种网口保护电路。
参照图2，图2是本发明网口保护电路一实施例的电路结构示意图。
本实施例中，该网口保护电路包括以太网接口201、第一隔离变压器T21、第二隔离变压器T22、网络信号处理芯片202、第一干扰防护电路203及第二干扰防护电路204。
其中，所述以太网接口201，用于接收和发送网络信号；本实施例中，所述以太网接口201为RJ45网口；
所述第一隔离变压器T21，用于对所述以太网接口201的接收数据端和所述网络信号接收芯片202进行隔离；
所述第二隔离变压器T22，用于对所述以太网接口201的发送数据端和所述网络信号接收芯片202进行隔离；
所述第一干扰防护电路203，用于对所述以太网接口201的接收数据端的共模干扰和差模干扰进行防护；
所述第二干扰防护电路204，用于对所述以太网接口201的发送数据端的共模干扰和差模干扰进行防护；
所述网络信号处理芯片202，用于对所述网络信号进行处理。
本实施例中，所述以太网接口201的接收数据端与所述第一隔离变压器T21的原边侧连接；所述第一干扰防护电路203连接于所述第一隔离变压器T21的次边侧和所述网络信号接收芯片202之间；所述以太网接口201的发送数据端与所述第二隔离变压器T22的原边侧连接；所述第二干扰防护电路204连接于所述第二隔离变压器T22的次边侧和所述网络信号接收芯片202之间。
具体地，本实施例中，所述第一干扰防护电路203包括第一钳位二极管ZD1、第二钳位二极管ZD2、第一电阻R1及第二电阻R2。本实施例中，所述第一电阻R1及第二电阻R2的阻值为2.2欧姆；
其中，所述第一钳位二极管ZD1的阳极和所述第二钳位二极管ZD2的阳极均接地；所述第一钳位二极管ZD1的阴极与所述第一隔离变压器T21的次边侧线圈（图未标号）的第一端连接；所述第二钳位二极管ZD2的阴极与所述第一隔离变压器T21的次边侧线圈的第二端连接；所述第一钳位二极管ZD1的阴极还经所述第一电阻R1与所述网络信号处理芯片202的接收数据负端RX2-连接；所述第二钳位二极管ZD2的阴极还经所述第二电阻R2与所述网络信号处理芯片202的接收数据正端RX2+连接。
本实施例中，所述第二干扰防护电路204包括第三钳位二极管ZD3、第四钳位二极管ZD4、第三电阻R3及第四电阻R4。本实施例中，所述第三电阻R3及第四电阻R4的阻值为2.2欧姆；
其中，所述第三钳位二极管ZD3的阳极和所述第四钳位二极管ZD4的阳极均接地；所述第三钳位二极管ZD3的阴极与所述第二隔离变压器T22的次边侧线圈（图未标号）的第一端连接；所述第四钳位二极管ZD4的阴极与所述第二隔离变压器T22的次边侧线圈的第二端连接；所述第三钳位二极管ZD3的阴极还经所述第三电阻R3与所述网络信号处理芯片202的发送数据负端TX2-连接；所述第四钳位二极管ZD4的阴极还经所述第四电阻R4与所述网络信号处理芯片202的发送数据正端TX2+连接。
进一步地，本实施例网口保护电路还包括第五电阻R5、第六电阻R6及第一电容C1；所述第一隔离变压器T21的原边侧线圈包括第一原边线圈和第二原边线圈（图未标号）；所述第二隔离变压器T22的原边侧线圈包括第三原边线圈和第四原边线圈（图未标号）。
其中，所述以太网接口201的接收数据端的正端RX+与所述第一隔离变压器T21的第二原边线圈的第一端连接，所述以太网接口201的接收数据端的负端RX-与所述第一隔离变压器T21的第一原边线圈的第一端连接；所述第一隔离变压器T21的第一原边线圈的第二端及所述第一隔离变压器T21的第二原边线圈的第二端均经所述第五电阻R5与所述第一电容C1的第一端连接；所述第一电容C1的第二端接地；所述以太网接口201的发送数据端的正端TX+与所述第二隔离变压器T22的第四原边线圈的第一端连接，所述以太网接口201的发送数据端的负端TX-与所述第二隔离变压器T22的第三原边线圈的第一端连接；所述第二隔离变压器T22的第三原边线圈的第二端及所述第二隔离变压器T22的第四原边线圈的第二端均经所述第六电阻R6与所述第一电容C1的第一端连接。
另外，本实施例中，所述网络信号处理芯片202的接收数据负端RX2-设有第一静电防护电路2021。所述第一静电防护电路2021包括第一二极管D1和第二二极管D2。其中，所述第一二极管D1的阴极与所述网络信号处理芯片202的工作电压输入端VCC2连接，所述第一二极管D1的阳极分别与所述网络信号处理芯片202的接收数据负端RX2-及所述第二二极管D2的阴极连接；所述第二二极管D2的阳极接地；
所述网络信号处理芯片202的接收数据正端RX2+设有第二静电防护电路2022。所述第二静电防护电路2022包括第三二极管D3和第四二极管D4。其中，所述第三二极管D3的阴极与所述网络信号处理芯片202的工作电压输入端VCC2连接，所述第三二极管D3的阳极分别与所述网络信号处理芯片202的接收数据正端RX2+和所述第四二极管D4的阴极连接；所述第四二极管D4的阳极接地；
所述网络信号处理芯片202的发送数据负端TX2-设有第三静电防护电路2023。所述第三静电防护电路2023包括第五二极管D5和第六二极管D6。其中，所述第五二极管D5的阴极与所述网络信号处理芯片202的工作电压输入端VCC2连接，所述第五二极管D5的阳极分别与所述网络信号处理芯片202的发送数据负端TX2-和所述第六二极管D6的阴极连接；所述第六二极管D6的阳极接地;
所述网络信号处理芯片202的发送数据正端TX2+设有第四静电防护电路2024。所述第四静电防护电路2024包括第七二极管D7和第八二极管D8。其中，所述第七二极管D7的阴极与所述网络信号处理芯片202的工作电压输入端VCC2连接，所述第七二极管D7的阳极分别与所述网络信号处理芯片202的发送数据正端TX2+和所述第八二极管D8的阴极连接；所述第八二极管D8的阳极接地。
本实施例网口保护电路的工作原理具体描述如下：当共模干扰电压超过所述第一干扰防护电路203中的所述第一钳位二极管ZD1及所述第二钳位二极管ZD2的反向击穿电压时，所述第一钳位二极管ZD1及所述第二钳位二极管ZD2会反向导通，并将所述以太网接口201的接收数据端的负端RX-和接收数据端的正端RX+信号线上的电压钳位在较低的电压水平，从而能够保护后级的网络信号处理芯片202不被损坏；同理，当共模干扰电压超过所述第二干扰防护电路204中的所述第三钳位二极管ZD3及所述第四钳位二极管ZD4的反向击穿电压时，所述第三钳位二极管ZD3及所述第四钳位二极管ZD4会反向导通，并所述以太网接口201的发送数据端的负端TX-和发送数据端的正端TX+信号线上的电压钳位在较低的电压水平，从而能够保护后级的网络信号处理芯片202不被损坏。
当差模干扰电压加到所述以太网接口201的接收数据端时，所述第一干扰防护电路203内的第一钳位二极管ZD1首先被反向击穿（由于图中A、B两点都是接地的），形成电流i3，电流i3再向下流经所述网络信号处理芯片202内的第四二极管D4和所述第一干扰防护电路203内的第二钳位二极管ZD2。假定所述第四二极管D4的正向导通压降为VD4，所述第二钳位二极管ZD2的正向导通电压为VZD2，如果VZD2小于 VD4，则必定所述第二钳位二极管ZD2 优先导通，所述第四二极管D4不导通（此时图中电流i3=电流i4），从而使得所述第四二极管D4受到保护。如果VZD2大于 VD4，那么所述第四二极管D4会优先导通，但流经所述第四二极管D4的电流会被限制在一定的电流值i2内（具体电流），本实施例只要设置适当阻值大小的第二电阻R2，便能使得流经所述第四二极管D4中的电流i2不会太大，从而使所述第四二极管D4不会因过流而烧毁，进而使得所述第四二极管D4受到保护，也即使得所述网络信号处理芯片202受到了保护。同时，本实施例中，由于所述第一钳位二极管ZD1的阳极和所述第二钳位二极管ZD2的阳极均接地，因此，所述第一钳位二极管ZD1和所述第二钳位二极管ZD2对共模干扰电压也具有保护作用。同理，当差模干扰电压加到所述以太网接口201的发送数据端时，所述第二干扰防护电路204也能起到保护所述网络信号处理芯片202的作用。
本实施例网口保护电路，包括以太网接口、第一隔离变压器、第二隔离变压器、网络信号处理芯片、第一干扰防护电路及第二干扰防护电路；所述以太网接口用于接收和发送网络信号；所述第一隔离变压器用于对所述以太网接口的接收数据端和所述网络信号接收芯片进行隔离；所述第二隔离变压器用于对所述以太网接口的发送数据端和所述网络信号接收芯片进行隔离；所述第一干扰防护电路用于对所述以太网接口的接收数据端的共模干扰和差模干扰进行防护；所述第二干扰防护电路用于对所述以太网接口的发送数据端的共模干扰和差模干扰进行防护；所述网络信号处理芯片用于对所述网络信号进行处理。其中，所述以太网接口的接收数据端与所述第一隔离变压器的原边侧连接；所述第一干扰防护电路连接于所述第一隔离变压器的次边侧和所述网络信号接收芯片之间；所述以太网接口的发送数据端与所述第二隔离变压器的原边侧连接；所述第二干扰防护电路连接于所述第二隔离变压器的次边侧和所述网络信号接收芯片之间。本实施例网口保护电路能够对共模干扰和差模干扰进行防护；并且，本发明网口保护电路的成本低；同时，本发明还具有电路结构简单及易实现的优点。
本发明还提供一种电视机，该电视机包括网口保护电路，该网口保护电路的电路结构及其工作原理可参照上述实施例，在此不再赘述。理所应当地，由于本实施例的电视机采用了上述网口保护电路的技术方案，因此该电视机具有上述网口保护电路所有的有益效果。
以上仅为本发明的优选实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (18)

  1. 一种网口保护电路，其特征在于，包括以太网接口、第一隔离变压器、第二隔离变压器、网络信号处理芯片及第一干扰防护电路；其中，
    所述以太网接口，用于接收和发送网络信号；
    所述第一隔离变压器，用于对所述以太网接口的接收数据端和所述网络信号接收芯片进行隔离；
    所述第二隔离变压器，用于对所述以太网接口的发送数据端和所述网络信号接收芯片进行隔离；
    所述第一干扰防护电路，用于对所述以太网接口的接收数据端的共模干扰和差模干扰进行防护；
    所述网络信号处理芯片，用于对所述网络信号进行处理；
    所述以太网接口的接收数据端与所述第一隔离变压器的原边侧连接；所述第一干扰防护电路连接于所述第一隔离变压器的次边侧和所述网络信号接收芯片之间；所述以太网接口的发送数据端与所述第二隔离变压器的原边侧连接；所述第二隔离变压器的次边侧与所述网络信号处理芯片连接。
  2. 如权利要求1所述的网口保护电路，其特征在于，所述第一干扰防护电路包括第一钳位二极管、第二钳位二极管、第一电阻及第二电阻；其中，
    所述第一钳位二极管的阳极和所述第二钳位二极管的阳极均接地；所述第一钳位二极管的阴极与所述第一隔离变压器的次边侧线圈的第一端连接；所述第二钳位二极管的阴极与所述第一隔离变压器的次边侧线圈的第二端连接；所述第一钳位二极管的阴极还经所述第一电阻与所述网络信号处理芯片的接收数据负端连接；所述第二钳位二极管的阴极还经所述第二电阻与所述网络信号处理芯片的接收数据正端连接。
  3. 如权利要求2所述的网口保护电路，其特征在于，所述网口保护电路还包括用于对所述以太网接口的发送数据端的共模干扰和差模干扰进行防护的第二干扰防护电路；所述第二干扰防护电路连接于所述第二隔离变压器的次边侧和所述网络信号接收芯片之间。
  4. 如权利要求3所述的网口保护电路，其特征在于，所述第二干扰防护电路包括第三钳位二极管、第四钳位二极管、第三电阻及第四电阻；其中，
    所述第三钳位二极管的阳极和所述第四钳位二极管的阳极均接地；所述第三钳位二极管的阴极与所述第二隔离变压器的次边侧线圈的第一端连接；所述第四钳位二极管的阴极与所述第二隔离变压器的次边侧线圈的第二端连接；所述第三钳位二极管的阴极还经所述第三电阻与所述网络信号处理芯片的发送数据负端连接；所述第四钳位二极管的阴极还经所述第四电阻与所述网络信号处理芯片的发送数据正端连接。
  5. 如权利要求4所述的网口保护电路，其特征在于，所述网口保护电路还包括第五电阻、第六电阻及第一电容；所述第一隔离变压器的原边侧线圈包括第一原边线圈和第二原边线圈；所述第二隔离变压器的原边侧线圈包括第三原边线圈和第四原边线圈； 其中，
    所述以太网接口的接收数据端的正端与所述第二原边线圈的第一端连接，所述以太网接口的接收数据端的负端与所述第一原边线圈的第一端连接；所述第一原边线圈的第二端及所述第二原边线圈的第二端均经所述第五电阻与所述第一电容的第一端连接；所述第一电容的第二端接地；
    所述以太网接口的发送数据端的正端与所述第四原边线圈的第一端连接，所述以太网接口的发送数据端的负端与所述第三原边线圈的第一端连接；所述第三原边线圈的第二端及所述第四原边线圈的第二端均经所述第六电阻与所述第一电容的第一端连接。
  6. 如权利要求5所述的网口保护电路，其特征在于，所述网络信号处理芯片的接收数据负端设有第一静电防护电路；所述第一静电防护电路包括第一二极管和第二二极管；其中，
    所述第一二极管的阴极与所述网络信号处理芯片的工作电压输入端连接，所述第一二极管的阳极分别与所述网络信号处理芯片的接收数据负端及所述第二二极管的阴极连接；所述第二二极管的阳极接地。
  7. 如权利要求6所述的网口保护电路，其特征在于，所述网络信号处理芯片的接收数据正端设有第二静电防护电路；所述第二静电防护电路包括第三二极管和第四二极管；其中，
    所述第三二极管的阴极与所述网络信号处理芯片的工作电压输入端连接，所述第三二极管的阳极分别与所述网络信号处理芯片的接收数据正端和所述第四二极管的阴极连接；所述第四二极管的阳极接地。
  8. 如权利要求7所述的网口保护电路，其特征在于，所述网络信号处理芯片的发送数据负端设有第三静电防护电路；所述第三静电防护电路包括第五二极管和第六二极管；其中，
    所述第五二极管的阴极与所述网络信号处理芯片的工作电压输入端连接，所述第五二极管的阳极分别与所述网络信号处理芯片的发送数据负端和所述第六二极管的阴极连接；所述第六二极管的阳极接地。
  9. 如权利要求8所述的网口保护电路，其特征在于，所述网络信号处理芯片的发送数据正端设有第四静电防护电路；所述第四静电防护电路包括第七二极管和第八二极管；其中，
    所述第七二极管的阴极与所述网络信号处理芯片的工作电压输入端连接，所述第七二极管的阳极分别与所述网络信号处理芯片的发送数据正端和所述第八二极管的阴极连接；所述第八二极管的阳极接地。
  10. 一种电视机，其特征在于，所述电视机包括网口保护电路，所述网口保护电路包括以太网接口、第一隔离变压器、第二隔离变压器、网络信号处理芯片及第一干扰防护电路；其中，
    所述以太网接口，用于接收和发送网络信号；
    所述第一隔离变压器，用于对所述以太网接口的接收数据端和所述网络信号接收芯片进行隔离；
    所述第二隔离变压器，用于对所述以太网接口的发送数据端和所述网络信号接收芯片进行隔离；
    所述第一干扰防护电路，用于对所述以太网接口的接收数据端的共模干扰和差模干扰进行防护；
    所述网络信号处理芯片，用于对所述网络信号进行处理；
    所述以太网接口的接收数据端与所述第一隔离变压器的原边侧连接；所述第一干扰防护电路连接于所述第一隔离变压器的次边侧和所述网络信号接收芯片之间；所述以太网接口的发送数据端与所述第二隔离变压器的原边侧连接；所述第二隔离变压器的次边侧与所述网络信号处理芯片连接。
  11. 如权利要求10所述的电视机，其特征在于，所述第一干扰防护电路包括第一钳位二极管、第二钳位二极管、第一电阻及第二电阻；其中，
    所述第一钳位二极管的阳极和所述第二钳位二极管的阳极均接地；所述第一钳位二极管的阴极与所述第一隔离变压器的次边侧线圈的第一端连接；所述第二钳位二极管的阴极与所述第一隔离变压器的次边侧线圈的第二端连接；所述第一钳位二极管的阴极还经所述第一电阻与所述网络信号处理芯片的接收数据负端连接；所述第二钳位二极管的阴极还经所述第二电阻与所述网络信号处理芯片的接收数据正端连接。
  12. 如权利要求11所述的电视机，其特征在于，所述网口保护电路还包括用于对所述以太网接口的发送数据端的共模干扰和差模干扰进行防护的第二干扰防护电路；所述第二干扰防护电路连接于所述第二隔离变压器的次边侧和所述网络信号接收芯片之间。
  13. 如权利要求12所述的电视机，其特征在于，所述第二干扰防护电路包括第三钳位二极管、第四钳位二极管、第三电阻及第四电阻；其中，
    所述第三钳位二极管的阳极和所述第四钳位二极管的阳极均接地；所述第三钳位二极管的阴极与所述第二隔离变压器的次边侧线圈的第一端连接；所述第四钳位二极管的阴极与所述第二隔离变压器的次边侧线圈的第二端连接；所述第三钳位二极管的阴极还经所述第三电阻与所述网络信号处理芯片的发送数据负端连接；所述第四钳位二极管的阴极还经所述第四电阻与所述网络信号处理芯片的发送数据正端连接。
  14. 如权利要求13所述的电视机，其特征在于，所述网口保护电路还包括第五电阻、第六电阻及第一电容；所述第一隔离变压器的原边侧线圈包括第一原边线圈和第二原边线圈；所述第二隔离变压器的原边侧线圈包括第三原边线圈和第四原边线圈； 其中，
    所述以太网接口的接收数据端的正端与所述第二原边线圈的第一端连接，所述以太网接口的接收数据端的负端与所述第一原边线圈的第一端连接；所述第一原边线圈的第二端及所述第二原边线圈的第二端均经所述第五电阻与所述第一电容的第一端连接；所述第一电容的第二端接地；
    所述以太网接口的发送数据端的正端与所述第四原边线圈的第一端连接，所述以太网接口的发送数据端的负端与所述第三原边线圈的第一端连接；所述第三原边线圈的第二端及所述第四原边线圈的第二端均经所述第六电阻与所述第一电容的第一端连接。
  15. 如权利要求14所述的电视机，其特征在于，所述网络信号处理芯片的接收数据负端设有第一静电防护电路；所述第一静电防护电路包括第一二极管和第二二极管；其中，
    所述第一二极管的阴极与所述网络信号处理芯片的工作电压输入端连接，所述第一二极管的阳极分别与所述网络信号处理芯片的接收数据负端及所述第二二极管的阴极连接；所述第二二极管的阳极接地。
  16. 如权利要求15所述的电视机，其特征在于，所述网络信号处理芯片的接收数据正端设有第二静电防护电路；所述第二静电防护电路包括第三二极管和第四二极管；其中，
    所述第三二极管的阴极与所述网络信号处理芯片的工作电压输入端连接，所述第三二极管的阳极分别与所述网络信号处理芯片的接收数据正端和所述第四二极管的阴极连接；所述第四二极管的阳极接地。
  17. 如权利要求16所述的电视机，其特征在于，所述网络信号处理芯片的发送数据负端设有第三静电防护电路；所述第三静电防护电路包括第五二极管和第六二极管；其中，
    所述第五二极管的阴极与所述网络信号处理芯片的工作电压输入端连接，所述第五二极管的阳极分别与所述网络信号处理芯片的发送数据负端和所述第六二极管的阴极连接；所述第六二极管的阳极接地。
  18. 如权利要求17所述的电视机，其特征在于，所述网络信号处理芯片的发送数据正端设有第四静电防护电路；所述第四静电防护电路包括第七二极管和第八二极管；其中，
    所述第七二极管的阴极与所述网络信号处理芯片的工作电压输入端连接，所述第七二极管的阳极分别与所述网络信号处理芯片的发送数据正端和所述第八二极管的阴极连接；所述第八二极管的阳极接地。
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