WO2016095109A1 - Procédé et dispositif de traitement de transmission pour un canal de commande de liaison descendante physique amélioré - Google Patents

Procédé et dispositif de traitement de transmission pour un canal de commande de liaison descendante physique amélioré Download PDF

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Publication number
WO2016095109A1
WO2016095109A1 PCT/CN2014/093974 CN2014093974W WO2016095109A1 WO 2016095109 A1 WO2016095109 A1 WO 2016095109A1 CN 2014093974 W CN2014093974 W CN 2014093974W WO 2016095109 A1 WO2016095109 A1 WO 2016095109A1
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Prior art keywords
symbol
processing
dcis
dci
mapping
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PCT/CN2014/093974
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English (en)
Chinese (zh)
Inventor
郑中亮
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华为技术有限公司
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Priority to CN201480083862.3A priority Critical patent/CN107005303B/zh
Priority to PCT/CN2014/093974 priority patent/WO2016095109A1/fr
Publication of WO2016095109A1 publication Critical patent/WO2016095109A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B7/00—Radio transmission systems, i.e. using radiation field
    • H04B7/24—Radio transmission systems, i.e. using radiation field for communication between two or more posts
    • H04B7/26—Radio transmission systems, i.e. using radiation field for communication between two or more posts at least one of which is mobile
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received

Definitions

  • the embodiments of the present invention relate to the field of communications technologies, and in particular, to an enhanced physical downlink control channel (English: Enhanced Physical Downlink Control Channel, EPDCCH) transmission processing method and device.
  • an enhanced physical downlink control channel English: Enhanced Physical Downlink Control Channel, EPDCCH
  • EPDCCH is a downlink physical control channel newly defined in Release 11 (English: Release 11, LTE for short), which is used to transmit downlink control information. (English: Downlink Control Information, referred to as: DCI).
  • the EPDCCH transmission process is as shown in FIG. 1 , and each DCI independently completes Cyclic Redundancy Check (CRC) addition, CRC masking, coding, rate matching, and Scrambling, modulation, power control (power control), layer mapping and precoding, subcarrier mapping processing, and then EPDCCH and other downlink channels along with the symbol for inverse fast Fourier transform (English: Inverse Fast Fourier Transformation, abbreviation :IFFT) Time-frequency conversion processing.
  • CRC Cyclic Redundancy Check
  • the transmission time interval (English: Transmission Time Interval, TTI for short) includes two time slots (English: slot), for example, each time slot includes 7 symbols, and each resource block in each symbol ( English: Resource Block (abbreviation: RB) includes 12 resource elements (English: Resource Element, abbreviated as RE).
  • Each symbol is numbered according to 0-11, so the subcarrier mapping process in DCI
  • Each DCI is mapped to multiple symbols in one TTI, and the same DCI is mapped to the REs with the same number in each symbol, so that EPDCCHs with multiple DCIs are mapped on each symbol.
  • the layer mapping and precoding of all the DCIs in one TTI are required to start the IFFT processing on the first symbol in the TTI, which results in a high processing delay requirement of the EPDCCH.
  • the embodiments of the present invention provide an EPDCCH transmission processing method and device, which are used to solve the technical problem that the processing delay of the EPDCCH in the prior art is tight.
  • an embodiment of the present invention provides a network device, including: a memory and a processor, where the memory stores a code of an EPDCCH transmission processing method, where the processor is configured to invoke the code to perform the following operations:
  • mapping the first DCI to the RE of the first symbol in the TTI where the N is greater than Or an integer equal to 1, transmitting the N DCIs in the TTI, the first symbol is any one of the TTIs, and the first DCI includes at least one of the N DCIs;
  • Performing, in the current symbol time, a first process on the RE of the first symbol where the first process includes: scrambling processing, modulation processing, power control processing, layer mapping and precoding processing, and inverse fast Fourier transform a process other than the second process in the IFFT process, the first symbol being any symbol after the current symbol, and the second process is to map the first DCI to the first symbol
  • the processor is configured to map the first DCI to the RE of the first symbol in the TTI, including: the processor is specifically configured to: in the current symbol And acquiring a part of data of the first DCI to be mapped to the RE of the first symbol; and mapping the acquired part of the data of the first DCI to the RE of the first symbol.
  • the first symbol is a next symbol of the current symbol.
  • the processor is configured to perform, after performing rate matching processing on the N downlink control signals DCI, and performing layer mapping and precoding processing on the N DCIs,
  • the first DCI is mapped to the RE of the first symbol in the TTI
  • the processor is specifically configured to perform layer mapping and pre-processing on the N DCIs after performing rate matching processing on the N DCIs.
  • the N DCIs are mapped onto the RE of the TTI.
  • the processor is configured to perform N DCI Mapping the first DCI to the RE of the first symbol in the TTI after performing the rate matching process and performing layer mapping and precoding processing on the N DCIs, including: the processor is specifically used, in the pair After the N DCIs perform rate matching processing and perform scrambling processing on the N DCIs, mapping the first DCI to the RE of the first symbol;
  • the processor is configured to perform a first process on the RE of the first symbol in a time of the current symbol, where the processor is specifically configured to: in the time of the current symbol, the first symbol
  • the RE performs scrambling processing, modulation processing, power control processing, layer mapping and precoding processing, and IFFT processing.
  • the processor is used to perform N DCI Mapping the first DCI to the RE of the first symbol in the TTI after performing the rate matching process and performing layer mapping and precoding processing on the N DCIs, including: the processor is specifically used, in the pair After the N DCIs are subjected to the scrambling process and before the N DCIs are modulated, the first DCI is mapped to the RE of the first symbol;
  • the processor is configured to perform a first process on the RE of the first symbol in a time of the current symbol, where the processor is specifically configured to: in the time of the current symbol, the first symbol
  • the RE performs modulation processing, power control processing, layer mapping and precoding processing, and IFFT processing.
  • the processor is used to perform N DCI Mapping the first DCI to the RE of the first symbol in the TTI after performing the rate matching process and performing layer mapping and precoding processing on the N DCIs, including: the processor is specifically used, in the pair After the N DCIs are modulated, and before the N DCIs are subjected to the power control process, the first DCI is mapped to the RE of the first symbol;
  • the processor is configured to perform a first process on the RE of the first symbol in a time of the current symbol, where the processor is specifically configured to: in the time of the current symbol, the first symbol
  • the RE performs power control processing, layer mapping and precoding processing, and IFFT processing.
  • the processor is configured to perform N DCI Mapping the first DCI to the RE of the first symbol in the TTI, after the performing the rate matching process, and performing the layer mapping and the precoding processing on the N DCIs, including: the processor is specifically configured to: Mapping the first DCI to the RE of the first symbol after performing power control processing on the N DCIs and performing layer mapping and precoding processing on the N DCIs;
  • the processor is configured to perform a first process on the RE of the first symbol in a time of the current symbol, where the processor is specifically configured to: in the time of the current symbol, the first symbol
  • the RE performs layer mapping and precoding processing, and IFFT processing.
  • an embodiment of the present invention provides a network device, including:
  • a mapping unit configured to map the first DCI to the RE of the first symbol in the TTI after performing rate matching processing on the N DCIs and performing layer mapping and precoding processing on the N DCIs, where
  • the N is an integer greater than or equal to 1.
  • the NTIs are transmitted in the TTI, the first symbol is any one of the TTIs, and the first DCI includes the N DCIs. at least one;
  • a processing unit configured to perform a first process on the RE of the first symbol in a time of a current symbol, where the first process includes: a scrambling process, a modulation process, a power control process, a layer mapping, and a precoding process, a process other than the second process in the inverse fast Fourier transform IFFT process, the first symbol being any symbol after the current symbol, and the second process is to map the first DCI to Processing performed after the rate matching process on the RE of the first symbol.
  • the mapping unit is configured to map the first DCI to the RE of the first symbol in the TTI, where the mapping unit is specifically configured to be used in the current And acquiring a part of data of the first DCI to be mapped to the RE of the first symbol; and mapping the acquired part of the data of the first DCI to the RE of the first symbol.
  • the first symbol is a next symbol of the current symbol.
  • the mapping unit is configured to perform, after performing rate matching processing on the N downlink control signals DCI, and performing layer mapping and precoding processing on the N DCIs, Mapping the first DCI to the RE of the first symbol in the TTI, the mapping unit is specifically configured to perform layer mapping on the N DCIs after performing rate matching processing on the N DCIs Before the precoding process, the N DCIs are mapped onto the RE of the TTI.
  • the mapping unit is configured to perform, after performing rate matching processing on the N DCIs, and performing layer mapping and precoding processing on the N DCIs,
  • the mapping of the first DCI to the RE of the first symbol in the TTI includes: the mapping unit is specifically configured to: after performing rate matching processing on the N DCIs, and before performing scrambling processing on the N DCIs Mapping the first DCI to the RE of the first symbol;
  • the processing unit is configured to perform a first process on the RE of the first symbol in a time of the current symbol, where the processing unit is configured to: in the time of the current symbol, the first The symbol RE is subjected to scrambling processing, modulation processing, power control processing, layer mapping and precoding processing, and IFFT processing.
  • the mapping unit is used to After the DCI performs the rate matching process, and performs the layer mapping and the precoding process on the N DCIs, mapping the first DCI to the RE of the first symbol in the TTI, including: the mapping unit is specifically used to After performing the scrambling process on the N DCIs and performing modulation processing on the N DCIs, mapping the first DCI to the REs of the first symbol;
  • the processing unit is configured to perform a first process on the RE of the first symbol in a time of the current symbol, where the processing unit is configured to: in the time of the current symbol, the first The RE of the symbol performs modulation processing, power control processing, layer mapping and precoding processing, and IFFT processing.
  • the mapping unit is used to After the DCI performs the rate matching process, and performs the layer mapping and the precoding process on the N DCIs, mapping the first DCI to the RE of the first symbol in the TTI, including: the mapping unit is specifically used to After performing modulation processing on the N DCIs and performing power control processing on the N DCIs, mapping the first DCI to the RE of the first symbol;
  • the processing unit is configured to perform a first process on the RE of the first symbol in a time of the current symbol, where the processing unit is configured to: in the time of the current symbol, the first The RE of the symbol performs power control processing, layer mapping and precoding processing, and IFFT processing.
  • the mapping unit is used to After the DCI performs rate matching processing and performs layer mapping and precoding processing on the N DCIs, Mapping the first DCI to the RE of the first symbol in the TTI, the mapping unit is specifically configured to perform layer mapping on the N DCIs after performing power control processing on the N DCIs Mapping the first DCI to the RE of the first symbol before the precoding process;
  • the processing unit is configured to perform a first process on the RE of the first symbol in a time of the current symbol, where the processing unit is configured to: in the time of the current symbol, the first The RE of the symbol performs layer mapping and precoding processing, and IFFT processing.
  • an embodiment of the present invention provides an EPDCCH transmission processing method, including:
  • mapping the first DCI to the RE of the first symbol in the TTI where the N is greater than Or an integer equal to 1, transmitting the N DCIs in the TTI, the first symbol is any one of the TTIs, and the first DCI includes at least one of the N DCIs;
  • Performing, in the current symbol time, a first process on the RE of the first symbol where the first process includes: scrambling processing, modulation processing, power control processing, layer mapping and precoding processing, and inverse fast Fourier transform a process other than the second process in the IFFT process, the first symbol being any symbol after the current symbol, and the second process is to map the first DCI to the first symbol
  • mapping the first DCI to the RE of the first symbol in the TTI includes:
  • the first symbol is a next symbol of the current symbol.
  • mapping the first DCI to The RE of the first symbol in the TTI includes:
  • mapping the N DCIs to REs of the TTIs After performing rate matching processing on the N DCIs and performing layer mapping and precoding processing on the N DCIs, mapping the N DCIs to REs of the TTIs.
  • the first DCI mapping is performed after performing rate matching processing on the N DCIs and before performing layer mapping and precoding processing on the N DCIs.
  • To the RE of the first symbol in the TTI including:
  • the RE of the first symbol is subjected to scrambling processing, modulation processing, power control processing, layer mapping and precoding processing, and IFFT processing in the time of the current symbol.
  • mapping the first DCI to the RE of the first symbol in the TTI includes:
  • the RE of the first symbol is subjected to modulation processing, power control processing, layer mapping and precoding processing, and IFFT processing.
  • mapping the first DCI to the RE of the first symbol in the TTI includes:
  • the RE of the first symbol is subjected to power control processing, layer mapping and precoding processing, and IFFT processing.
  • mapping the first DCI to the RE of the first symbol in the TTI includes:
  • the EPDCCH transmission processing method and device provided by the embodiment of the present invention map the first DCI to the first after performing rate matching processing on the N DCIs and performing layer mapping and precoding processing on the N DCIs.
  • the first processing of the RE of the first symbol is performed as follows, so that the layer mapping of the N DCIs in the TTI does not need to be completed before the IFFT processing is performed on the RE of each symbol.
  • the ITR of each symbol in this TTI can be IFFT processed, which solves the technical problem of delay in EPDCCH processing delay.
  • FIG. 1 is a schematic diagram of an EPDCCH transmission process in the prior art
  • Embodiment 1 of a network device according to the present invention is a schematic structural diagram of Embodiment 1 of a network device according to the present invention.
  • Embodiment 2 of a network device according to the present invention is a schematic structural diagram of Embodiment 2 of a network device according to the present invention.
  • FIG. 5 is a schematic diagram of a first implementation manner of an EPDCCH transmission processing method according to the present invention.
  • FIG. 6 is a schematic diagram of a second implementation manner of an EPDCCH transmission processing method according to the present invention.
  • FIG. 7 is a schematic diagram of a third implementation manner of an EPDCCH transmission processing method according to the present invention.
  • FIG. 8 is a schematic diagram of a fourth implementation manner of an EPDCCH transmission processing method according to the present invention.
  • FIG. 9 is a flowchart of Embodiment 2 of an EPDCCH transmission processing method according to the present invention.
  • FIG. 10 is a flowchart of Embodiment 3 of an EPDCCH transmission processing method according to the present invention.
  • FIG. 11 is a schematic diagram of an RE in a TTI according to an embodiment of the present invention.
  • the network device provided by the present invention may be, for example, an evolved base station (English: Evolved NodeB, eNB for short) in the LTE system, and the present invention is not limited thereto.
  • an evolved base station English: Evolved NodeB, eNB for short
  • eNB evolved NodeB
  • the network device in this embodiment may include: a memory 11 and a processor 12, where the memory 11 is configured to store and perform terminal working mode setting.
  • the code of the method; the memory 11 may include a non-volatile memory.
  • the processor 12 may be a central processing unit (English: Central Processing Unit, CPU for short), or an application specific integrated circuit (ASIC), or configured to implement the embodiments of the present invention.
  • One or more integrated circuits may be a central processing unit (English: Central Processing Unit, CPU for short), or an application specific integrated circuit (ASIC), or configured to implement the embodiments of the present invention.
  • ASIC application specific integrated circuit
  • the processor 12 is configured to invoke the code, and perform the following operations: mapping the first DCI to the TTI after performing rate matching processing on the N DCIs and performing layer mapping and precoding processing on the N DCIs On the RE of the first symbol, where N is an integer greater than or equal to 1, the N DCIs are transmitted in the TTI, and the first symbol is any one of the TTIs, the first
  • the DCI includes at least one of the N DCIs; performing, in a time of the current symbol, a first process on the RE of the first symbol, where the first process includes: a scrambling process, a modulation process, a power control process, Layer mapping and precoding processing, processing in addition to the second processing in the inverse fast Fourier transform IFFT processing, the first symbol is any symbol after the current symbol, and the second processing is in the Processing performed after the rate matching process before the first DCI is mapped to the RE of the first symbol.
  • the processor 12 is configured to map the first DCI to the RE of the first symbol in the TTI, where the processor 12 is specifically configured to: during the time of the current symbol, acquire, to be mapped to the first a portion of the first DCI data on a symbolized RE; and mapping the acquired portion of the first DCI data to the RE of the first symbol.
  • the first symbol is a next symbol of the current symbol.
  • the processor 12 is configured to map the first DCI to after performing rate matching processing on the N downlink control signals DCI and performing layer mapping and precoding processing on the N DCIs.
  • the processor 12 On the RE of the first symbol in the TTI, the processor 12 is specifically configured to: after performing rate matching processing on the N DCIs, and performing layer mapping and precoding processing on the N DCIs, The N DCIs are mapped to the RE of the TTI.
  • the processor 12 is configured to map the first DCI to the RE of the first symbol in the TTI after performing rate matching processing on the N DCIs and performing layer mapping and precoding processing on the N DCIs.
  • the processor 12 is specifically configured to map the first DCI to the first symbol after performing rate matching processing on the N DCIs and performing scrambling processing on the N DCIs.
  • the processor 12 is configured to perform the first processing on the RE of the first symbol in the time of the current symbol, including: the processor 12 is specifically configured to: during the time of the current symbol, the first symbol
  • the RE performs scrambling processing, modulation processing, power control processing, layer mapping and precoding processing, and IFFT processing.
  • the processor 12 is configured to map the first DCI to the RE of the first symbol in the TTI after performing rate matching processing on the N DCIs and performing layer mapping and precoding processing on the N DCIs.
  • the processor 12 is specifically configured to map the first DCI to the first symbol after performing the scrambling process on the N DCIs and before performing modulation processing on the N DCIs.
  • the processor 12 is configured to perform the first processing on the RE of the first symbol in the time of the current symbol, including: the processor 12 is specifically configured to: during the time of the current symbol, the first symbol
  • the RE performs modulation processing, power control processing, layer mapping and precoding processing, and IFFT processing.
  • the processor 12 is configured to map the first DCI to the RE of the first symbol in the TTI after performing rate matching processing on the N DCIs and performing layer mapping and precoding processing on the N DCIs.
  • the processor 12 is specifically configured to map the first DCI to the RE of the first symbol after performing modulation processing on the N DCIs and performing power control processing on the N DCIs. ;
  • the processor 12 is configured to perform the first processing on the RE of the first symbol in the time of the current symbol, including: the processor 12 is specifically configured to: during the time of the current symbol, the first symbol
  • the RE performs power control processing, layer mapping and precoding processing, and IFFT processing.
  • the processor 12 is configured to map the first DCI to the first one in the TTI after performing rate matching processing on the N DCIs and performing layer mapping and precoding processing on the N DCIs.
  • the processor 12 is specifically configured to map the first DCI to the N DCI after performing the power control processing on the N DCI and performing layer mapping and precoding processing on the N DCIs.
  • the RE of the first symbol On the RE of the first symbol;
  • the processor 12 is configured to perform the first processing on the RE of the first symbol in the time of the current symbol, including: the processor 12 is specifically configured to: during the time of the current symbol, the first symbol
  • the RE performs layer mapping and precoding processing, and IFFT processing.
  • the network device of this embodiment may be used to implement the technical solution of the following method embodiments of the present invention, and the implementation principle and technical effects thereof are similar, and details are not described herein again.
  • the network device in this embodiment may include: a mapping unit 21 and a processing unit 22, where the mapping unit 21 is configured to perform N downlinks.
  • the control signal DCI performs the rate matching process and performs layer mapping and precoding processing on the N DCIs
  • the first DCI is mapped to the resource element RE of the first symbol in the transmission time interval TTI, where N is an integer greater than or equal to 1.
  • the NTIs are transmitted in the TTI, the first symbol is any one of the TTIs, and the first DCI includes at least one of the N DCIs.
  • the processing unit 22 is configured to perform a first process on the RE of the first symbol in a time of a current symbol, where the first process includes: a scrambling process, a modulation process, a power control process, a layer mapping, and a precoding Processing, inverse fast Fourier transform IFFT processing, except for the second processing, the first symbol is any symbol after the current symbol, and the second processing is in the first DCI Mapping to the RE of the first symbol , The process performed after rate matching process.
  • the mapping unit 21 is configured to map the first DCI to the RE of the first symbol in the TTI, where the mapping unit 21 is specifically configured to: during the time of the current symbol, acquire a to-be-mapped to the a portion of the first DCI data on a symbolized RE; and mapping the acquired portion of the first DCI data to the RE of the first symbol.
  • the first symbol is a next symbol of the current symbol.
  • the mapping unit 21 is configured to map the first DCI to the first one of the TTIs after performing rate matching processing on the N downlink control signals DCI and performing layer mapping and precoding processing on the N DCIs.
  • the mapping unit 21 is specifically configured to map the N DCIs after performing rate matching processing on the N DCIs and performing layer mapping and precoding processing on the N DCIs. Up to the RE of the TTI.
  • the mapping unit 21 is configured to map the first DCI to the RE of the first symbol in the TTI after performing rate matching processing on the N DCIs and before performing layer mapping and precoding processing on the N DCIs.
  • the mapping unit 21 is specifically configured to map the first DCI to the first symbol after performing rate matching processing on the N DCIs and performing scrambling processing on the N DCIs.
  • the processing unit 22 is configured to perform the first processing on the RE of the first symbol in the time of the current symbol, including: the processing unit 22 is specifically configured to: during the time of the current symbol, the first symbol
  • the RE performs scrambling processing, modulation processing, power control processing, layer mapping and precoding processing, and IFFT processing.
  • the mapping unit 21 is configured to map the first DCI to the RE of the first symbol in the TTI after performing rate matching processing on the N DCIs and before performing layer mapping and precoding processing on the N DCIs.
  • the mapping unit 21 is specifically configured to map the first DCI to the first symbol after performing the scrambling process on the N DCIs and before performing modulation processing on the N DCIs.
  • the processing unit 22 is configured to perform the first processing on the RE of the first symbol in the time of the current symbol, including: the processing unit 22 is specifically configured to: during the time of the current symbol, the first symbol
  • the RE performs modulation processing, power control processing, layer mapping and precoding processing, and IFFT processing.
  • the mapping unit 21 is configured to map the first DCI to the RE of the first symbol in the TTI after performing rate matching processing on the N DCIs and before performing layer mapping and precoding processing on the N DCIs.
  • the mapping unit 21 is specifically configured to map the first DCI to the RE of the first symbol after performing modulation processing on the N DCIs and performing power control processing on the N DCIs. ;
  • the processing unit 22 is configured to perform the first processing on the RE of the first symbol in the time of the current symbol, including: the processing unit 22 is specifically configured to: during the time of the current symbol, the first symbol
  • the RE performs power control processing, layer mapping and precoding processing, and IFFT processing.
  • the mapping unit 21 is configured to map the first DCI to the RE of the first symbol in the TTI after performing rate matching processing on the N DCIs and before performing layer mapping and precoding processing on the N DCIs.
  • the mapping unit 21 is specifically configured to: before performing the power control processing on the N DCIs, and before performing layer mapping and precoding processing on the N DCIs, mapping the first DCI to the first Symbol of RE;
  • the processing unit 22 is configured to perform the first processing on the RE of the first symbol in the time of the current symbol, including: the processing unit 22 is specifically configured to: during the time of the current symbol, the first symbol
  • the RE performs layer mapping and precoding processing, and IFFT processing.
  • the network device of this embodiment may be used to implement the technical solution of the following method embodiments of the present invention, and the implementation principle and technical effects thereof are similar, and details are not described herein again.
  • Embodiment 1 of an EPDCCH transmission processing method is a network device, and the method in this embodiment may include:
  • S101 Before performing rate matching processing on the N DCIs, and performing layer mapping and precoding processing on the N DCIs, mapping the first DCI to the RE of the first symbol in the TTI, where the N For an integer greater than or equal to 1, the N DCIs are transmitted in the TTI, the first symbol is any one of the TTIs, and the first DCI includes at least one of the N DCIs.
  • S102 Perform a first process on the RE of the first symbol in a time of a current symbol, where the first process includes: a scrambling process, a modulation process, a power control process, a layer mapping, and a precoding process, and an IFFT process. a process other than the second process, the first symbol being any symbol after the current symbol, and the second processing being before mapping the first DCI to the RE of the first symbol, The processing performed after the rate matching process.
  • N DCIs are transmitted in the TTI, that is, the N DCIs are transmitted in the same TTI, and after the rate matching processing is performed on the N DCIs, layer mapping and precoding are performed on the N DCIs.
  • mapping the first DCI to the RE of the first symbol in the TTI transmitting the N DCIs the process may also be referred to as subcarrier mapping, where the first DCI is an RE that needs to be mapped to the first symbol.
  • the first symbol is any one of the 14 symbols of the TTI.
  • At least one DCI of the N DCIs is called a first DCI; after mapping the first DCI to the RE of the first symbol, performing a first process on the RE of the first symbol at a current time, that is, a time of the current symbol, where the first processing includes : scrambling processing, modulation processing, power control processing, layer mapping, and precoding processing, and IFFT processing, before the rate matching processing, before the mapping of the first DCI to the RE of the first symbol Processing other than the processing performed, the first symbol being after the current symbol Any of the symbols, for example, the first symbol is the next symbol of the current symbol, or the first symbol is the next two symbols of the current symbol, etc.; the second processing is in the sub Processing performed after the carrier mapping process and after the rate matching process.
  • the specific process of mapping the first DCI to the RE of the first symbol in the TTI may be: storing the first DCI on the RE that needs to be mapped to the first symbol into the memory of the network device. The corresponding position of a symbol RE.
  • Mapping a DCI to the RE of the first symbol in the TTI includes: mapping the first DCI to after performing rate matching processing on the N DCIs and performing scrambling processing on the N DCIs On the RE of the first symbol, the first processing of the RE of the first symbol in the time of the current symbol, including: the RE of the first symbol in the time of the current symbol Perform scrambling processing, modulation processing, power control processing, layer mapping and precoding processing, and IFFT processing.
  • mapping the first DCI to the RE of the first symbol in the TTI After performing CRC addition processing, CRC masking processing, encoding processing, and rate matching processing on the N DCIs, mapping the first DCI to the RE of the first symbol in the TTI, then mapping the first DCI
  • the processing performed after the rate matching processing to the RE of the first symbol in the TTI is none, and therefore, the first processing includes: scrambling processing, modulation processing, power control processing, layer mapping, and precoding processing, IFFT Processing; thus, when the RE of the first symbol needs to be processed (ie, the time of the current symbol), the RE of the first symbol is subjected to scrambling processing, modulation processing, power control processing, layer mapping, and precoding processing. , IFFT processing.
  • the process of this implementation may be as shown in FIG. 5.
  • the IFFT processing is not shown in FIG. 5.
  • the subcarrier mapping processing shown in FIG. 5 indicates that the first DCI is mapped to the RE of the first symbol.
  • the first Mapping the DCI to the RE of the first symbol in the TTI includes: mapping the first DCI to the to-be after performing the scrambling process on the N DCIs and performing modulation processing on the N DCIs The first symbol of the RE;
  • Performing the first processing on the RE of the first symbol in the time of the current symbol including: performing modulation processing, power control processing, and layer on the RE of the first symbol in the time of the current symbol Mapping and precoding processing, IFFT processing.
  • the first processing includes: modulation processing, power control processing, layer mapping, and precoding processing, and IFFT processing; thus, when the arrival reaches the first symbol
  • the RE is processed (that is, the time of the current symbol)
  • the RE of the first symbol is subjected to modulation processing, power control processing, layer mapping, precoding processing, and IFFT processing.
  • the process of this implementation may be as shown in FIG. 6.
  • the IFFT processing is not shown in FIG. 6.
  • the subcarrier mapping processing shown in FIG. 6 indicates that the first DCI is mapped to the RE of the first symbol.
  • the first Mapping the DCI to the RE of the first symbol in the TTI includes: mapping the first DCI to the TTI after performing modulation processing on the N DCIs and performing power control processing on the N DCIs a symbol of RE;
  • Performing the first processing on the RE of the first symbol in the time of the current symbol including: performing power control processing, layer mapping, and pre-processing on the RE of the first symbol in the time of the current symbol Encoding processing, IFFT processing.
  • the first process includes: power control processing, layer mapping, and Precoding processing, IFFT processing; thus, when the RE of the first symbol needs to be processed (ie, the time of the current symbol), the RE of the first symbol is subjected to power control processing, layer mapping and precoding processing, and IFFT deal with.
  • the process of this implementation may be as shown in FIG. 7.
  • the IFFT processing is not shown in FIG. 7, and the subcarrier mapping processing shown in FIG. 7 indicates that the first DCI is mapped to the RE of the first symbol.
  • the first Mapping the DCI to the RE of the first symbol in the TTI includes: mapping the first DCI to the N DCI after performing the power control processing and performing layer mapping and precoding processing on the N DCIs On the RE of the first symbol in the TTI;
  • the first processing of the RE of the first symbol including: performing layer mapping and precoding processing on the RE of the first symbol, IFFT in a time of the current symbol deal with.
  • the first process includes: layer mapping and precoding processing, IFFT processing; thus, when the RE that needs to process the first symbol is reached (ie, the time of the current symbol), the first symbol is The RE performs layer mapping and precoding processing, and IFFT processing.
  • the process of this implementation may be as shown in FIG. 8.
  • the IFFT processing is not shown in FIG. 8.
  • the subcarrier mapping processing shown in FIG. 8 indicates that the first DCI is mapped to the RE of the first symbol.
  • mapping the first DCI to the RE of the first symbol performs the first processing as described above, so that the TTI of the N DCIs in the TTI does not need to be completed before the IFFT processing of the RE of each symbol can be performed on the TTI.
  • the RE of each symbol in the IFFT processing performs the technical problem of delay in EPDCCH processing delay.
  • FIG. 9 is a flowchart of Embodiment 2 of the EPDCCH transmission processing method of the present invention.
  • the execution entity of this embodiment is a network device, and the method in this embodiment may include:
  • the N is an integer greater than or equal to 1.
  • the NTIs are transmitted in the TTI, the first symbol is any one of the TTIs, and the first DCI includes the N DCIs. At least one of them.
  • S201 and S202 are used to complete mapping the first DCI to the RE of the first symbol; respectively, processing is performed on each symbol in the TTI, and one of the symbols in the TTI is as follows.
  • the number hereinafter referred to as the first symbol
  • the other symbols of the TTI are processed in accordance with the processing of the symbol.
  • all processing before the transmission of the RE of the first symbol is completed before the time of the first symbol, and therefore, among the N DCIs, which are determined during the current symbol time.
  • the DCI needs to be mapped to the RE of the first symbol, where all DCIs mapped to the RE of the first symbol are referred to as the first DCI; since one DCI is mapped onto the symbol of the TTI, it is mapped into the symbol of the TTI On each symbol of the symbol is a part of the data of the DCI, so it is also necessary to obtain which data in the first DCI needs to be mapped to the RE of the first symbol. Then, the acquired part of the data of the first DCI is mapped to the RE of the first symbol.
  • the first processing is performed on the RE of the first symbol in the current symbol.
  • the specific implementation process refer to the method embodiment of the present invention. The related description in S102 will not be described here.
  • the first symbol is the next symbol of the current symbol; and the RE of the first symbol of the TTI is in the time of the last symbol of the last TTI of the TTI.
  • the first symbol is the next two symbols of the current symbol; and the first one of the TTI is in the time of the second to last symbol of the last TTI of the TTI.
  • the RE of the symbol performs the above S201-S203; then, in the time of the last symbol of the last TTI of the TTI, the above S201-S203 is performed on the RE of the second symbol of the TTI; and then, the first one of the TTI In the time of the symbol, the above S201-S203 is performed on the RE of the third symbol of the TTI; and so on, in the time of the twelfth symbol of the TTI, the above S201 is performed on the RE of the fourteenth symbol of the TTI.
  • the M is an integer greater than or equal to 1, and less than or equal to 13.
  • determining the RE to be mapped to the first symbol in the current symbol time Part of the first DCI data, and the obtained part of the first DCI data is mapped to the RE of the first symbol, and then the first symbol RE is first performed as described above. Processing, such that before performing IFFT processing on the RE of each symbol, the IFFT processing can be performed on each symbol in the TTI after the layer mapping and precoding processing of the N DCIs in the TTI are not completed, and the EPDCCH processing is solved. Technical problems with tight schedules.
  • FIG. 10 is a flowchart of Embodiment 3 of an EPDCCH transmission processing method according to the present invention.
  • the execution entity of this embodiment is a network device, and the method in this embodiment may include:
  • mapping the N DCIs to REs of the TTI After performing rate matching processing on the N DCIs and performing layer mapping and precoding processing on the N DCIs, mapping the N DCIs to REs of the TTI.
  • the N DCIs are transmitted on the same TTI, and after the rate matching processing is performed on the N DCIs, and the layer mapping and precoding processing are performed on the N DCIs, the N TTIs are performed on the TTIs.
  • Subcarrier mapping of the DCI that is, mapping the N DCIs to the REs of the symbols of the TTI.
  • This execution step performs subcarrier mapping in units of DCI, that is, mapping one DCI to the corresponding symbol of the TTI.
  • the next DCI is mapped to the corresponding RE in the symbol of the TTI, and so on, until the Nth DCI is mapped to the corresponding RE in the symbol of the TTI, thereby completing mapping the first DCI to
  • the first symbol is any one of the TTIs, and the first DCI includes at least one of the N DCIs.
  • the DCI data is divided into nine parts of data, and the first part of the DCI data is mapped to the No. 0 RE of the first symbol of the TTI. The second part of the DCI data is mapped to the No.
  • the third part of the DCI data is mapped to the No. 0 RE of the third symbol
  • the fourth part of the DCI data is mapped to the fifth.
  • the fifth part of the DCI data will be mapped to the No. 0 RE of the sixth symbol
  • the sixth part of the DCI data will be mapped to the No. 0 RE of the eighth symbol
  • the seventh of the DCI Part of the data will be mapped to the 0th RE of the 10th symbol
  • the eighth part of the DCI will be mapped to
  • the No. 0 RE of the eleventh symbol and the ninth part of the DCI data are mapped to the No. 0 RE of the twelfth symbol.
  • mapping the N DCIs to the REs of the TTI after performing rate matching processing on the N DCIs and performing layer mapping and precoding processing on the N DCIs, mapping the N DCIs to the REs of the TTI, and then Performing a first process on the RE of the first symbol in a time of the current symbol; thus, before performing IFFT processing on the RE of each symbol, layer mapping and precoding processing of N DCIs in the TTI need not be completed. After that, IFFT processing can be performed on each symbol in this TTI, and the technical problem of delay in EPDCCH processing delay is solved.
  • the foregoing program may be stored in a computer readable storage medium, and the program is executed when executed.
  • the foregoing storage medium includes: read-only memory (English: Read-Only Memory, ROM for short), random access memory (English: Random Access Memory, RAM), disk or A variety of media such as optical discs that can store program code.

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  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
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Abstract

Conformément à des modes de réalisation, la présente invention concerne un procédé et un dispositif de traitement de transmission pour un canal de commande de liaison descendante physique amélioré. Le procédé consiste : après un traitement de mise en correspondance de débits sur N éléments d'informations de commande de liaison descendante (DCI) et avant un traitement de mappage et de précodage de couches sur les N éléments de DCI, à mapper des premières DCI à un RE d'un premier symbole dans un intervalle de temps de transmission (TTI), N ≥ 1, les N éléments de DCI étant transmis dans le TTI, le premier symbole étant un symbole quelconque dans le TTI, et les premières DCI comprenant au moins l'un des N éléments de DCI ; et dans le temps d'un symbole courant, à réaliser un premier traitement sur le RE du premier symbole, le premier traitement comprenant un traitement d'embrouillage, un traitement de modulation, un traitement de commande d'alimentation, un traitement de mappage et de précodage de couches, et un traitement dans un traitement d'IFFT à l'exception d'un second traitement, le premier symbole étant un symbole quelconque, dans le TH, suivant le symbole courant, et le second traitement étant un traitement réalisé avant que les premières DCI ne soient mappées au RE du premier symbole et après le traitement de mise en correspondance de débits. Le problème technique d'insuffisance de retard dans un traitement d'EPDCCH est résolu.
PCT/CN2014/093974 2014-12-16 2014-12-16 Procédé et dispositif de traitement de transmission pour un canal de commande de liaison descendante physique amélioré WO2016095109A1 (fr)

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CN201480083862.3A CN107005303B (zh) 2014-12-16 2014-12-16 增强下行物理控制信道发送处理方法和设备
PCT/CN2014/093974 WO2016095109A1 (fr) 2014-12-16 2014-12-16 Procédé et dispositif de traitement de transmission pour un canal de commande de liaison descendante physique amélioré

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WO2020220371A1 (fr) * 2019-05-01 2020-11-05 Qualcomm Incorporated Omission d'informations d'état de canal (csi) sur la base d'une couche pour une rétroaction de csi de type 2 compressée
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