WO2016090248A1 - High gain load circuit for a differential pair using depletion mode transistors - Google Patents

High gain load circuit for a differential pair using depletion mode transistors Download PDF

Info

Publication number
WO2016090248A1
WO2016090248A1 PCT/US2015/063996 US2015063996W WO2016090248A1 WO 2016090248 A1 WO2016090248 A1 WO 2016090248A1 US 2015063996 W US2015063996 W US 2015063996W WO 2016090248 A1 WO2016090248 A1 WO 2016090248A1
Authority
WO
WIPO (PCT)
Prior art keywords
differential pair
depletion mode
transistor
transistors
gain stage
Prior art date
Application number
PCT/US2015/063996
Other languages
French (fr)
Inventor
Yogesh Jayaraman Sharma
James Fiorenza
Original Assignee
Analog Devices, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Analog Devices, Inc. filed Critical Analog Devices, Inc.
Priority to EP15825667.7A priority Critical patent/EP3228002A1/en
Publication of WO2016090248A1 publication Critical patent/WO2016090248A1/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H03F3/45188—Non-folded cascode stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45376—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using junction FET transistors as the active amplifying circuit
    • H03F3/45381—Long tailed pairs
    • H03F3/45385—Non-folded cascode stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/303—Indexing scheme relating to amplifiers the loading circuit of an amplifying stage comprising a diode or diode coupled transistor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/75—Indexing scheme relating to amplifiers the amplifier stage being a common source configuration MOSFET
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45036—Indexing scheme relating to differential amplifiers the differential amplifier amplifying transistors are single transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45182—Indexing scheme relating to differential amplifiers the differential amplifier contains one or more cascode current mirrors in the load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45184—Indexing scheme relating to differential amplifiers the differential amplifier has one or more cascode current sources in the load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45188—Indexing scheme relating to differential amplifiers the differential amplifier contains one or more current sources in the load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45202—Indexing scheme relating to differential amplifiers the differential amplifier contains only resistors in the load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45208—Indexing scheme relating to differential amplifiers the dif amp being of the long tail pair type, one current source being coupled to the common emitter of the amplifying transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45224—One output of the differential amplifier being taken into consideration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45656—Indexing scheme relating to differential amplifiers the LC comprising one diode of a current mirror, i.e. forming an asymmetrical load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45674—Indexing scheme relating to differential amplifiers the LC comprising one current mirror
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45676—Indexing scheme relating to differential amplifiers the LC comprising one cascode current mirror
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45701—Indexing scheme relating to differential amplifiers the LC comprising one resistor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45702—Indexing scheme relating to differential amplifiers the LC comprising two resistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45722—Indexing scheme relating to differential amplifiers the LC comprising one or more source followers, as post buffer or driver stages, in cascade in the LC

Definitions

  • the invention generally relates to depletion mode transistors and, more particularly, the invention relates to a differential pair gain stage using depletion mode transistors, such as, gallium nitride transistors.
  • depletion mode field effect transistors are in an "on” state when the gate voltage is equal to the source voltage of the transistor, such that current will flow through the drain source juncture of the transistor.
  • a depletion mode device can be turned “off” when the gate voltage is taken below the source voltage by the threshold voltage when current stops flowing through the drain source junction of the transistor.
  • GaN Gallium Nitride
  • Si silicon
  • GaN transistor device choices are limited. While n- type depletion and enhancement mode devices are available, p-type GaN devices are not available as they have poor performance due to fundamental device physics issues. Hence the challenge is to make analog circuits using only n-type depletion and enhancement mode devices.
  • Fig. 1 schematically shows one prior art elementary analog circuit— a gain block that has of a differential pair 100, 101 driving load devices 105, 106.
  • This block provides a differential signal gain while rejecting common mode signals. Getting the highest differential gain out of this circuit is important for building a wide array of high performance analog circuits.
  • One choice uses load resistors 220, 221 and is schematically shown in Fig. 2.
  • This circuit has poor gain because the resistors 220, 221 cannot be made sufficiently large as the resistor has to conduct the DC bias current, thus the resistors need to be small.
  • this circuit could have a current mirror (made of a current sense 331 and a current source device 332) for the load devices of the differential pair 300, 301 as shown in Fig. 3.
  • the high output impedance of the current source 332 normally provides good differential gain while the current source can provide the DC bias current as needed.
  • p-type transistors 400, 401 typically are easily used to design the current mirror ( Figure 4). Undesirably, this option currently is not available in the GaN fabrication process.
  • Embodiments of the invention include a depletion mode differential pair gain stage.
  • the gain stage includes a differential pair of depletion-mode transistors, including a first and a second n-type transistor.
  • the depletion mode transistor may be GaN (gallium nitride) field effect transistors.
  • the transistors have a gate, source, and a drain and the differential pair coupled at the source of each transistor forming a common node.
  • the gain stage also includes an active load including one or more depletion mode transistors electrically coupled to at least one of the drains of depletion mode transistors of the differential pair.
  • the differential pair may also include a constant current source coupled to a common node of the differential pair.
  • the current source can be used for biasing the differential pair.
  • the active load includes a current source formed from a third depletion mode transistor coupled to a resistor.
  • the current source of the active load electrically couples the gate of the third depletion mode transistor to the drain of the second n-type depletion mode transistor of the differential pair.
  • the active load include a buffer formed from at least a fourth depletion mode transistors electrically coupling the drains of the first and second n-type depletion mode transistors of the differential pair.
  • the buffer ideally has a substantially unity gain, which causes the output impedance to increase.
  • the gain of the buffer may be substantially unity such that any gain between .5 and 1 would at least double the output impedance and increase the overall gain.
  • the buffer of the active load may be formed as a source follower in which a depletion mode transistor has its gate electrically coupled to the current source formed from the third depletion mode transistor.
  • the source follower of the buffer causes the AC voltage at the drains of the differential pair to remain at the same potential. By having the AC voltage at the drains remain at the same potential the biasing current from the common node will be split between the two sides of the differential pair.
  • the gain stage may be further enhanced by increasing the output impedance of the circuit.
  • a cascade stage can be added to the active load to maintain a fixed voltage above the threshold voltage of the depletion mode transistor across the drain of at least the source the depletion mode transistor that forms the source follower.
  • Depletion mode transistors of any fabrication type may be used with the circuit topology described herein to create a differential pair gain stage and this gain stage can be used in the formation of an operational amplified.
  • Fabrication techniques may include silicon and gallium nitride for example.
  • Embodiments of the present invention can be used in high bandwidth, high gain applications and can be employed with high voltage supplies >50V and operate at high temperatures, such as the temperatures that GaN circuits have been known to function.
  • the differential pair is made up of n-type enhancement mode transistors and the active load includes only n- type depletion mode transistors.
  • Gain enhancement may be achieved with an n- type depletion mode transistor as a source follower so that the AC voltage of the drains of the differential pair are equal.
  • the differential pair gain stage may further be enhanced with a cascode stage that causes the drain/ source junction of at least one n-type depletion mode transistor in the active load to have a constant voltage. The constant voltage causes the output impedance to be increased.
  • Fig. 1 schematically shows a prior art elementary analog circuit in silicon— a gain block that has a differential pair driving load devices.
  • Fig. 2 schematically shows a prior art silicon-based differential circuit loaded with resistors.
  • Fig. 3 schematically shows a silicon-based prior art differential circuit with a current mirror.
  • Fig. 4 schematically shows a silicon-based prior art circuit with a current mirror using p-type transistors.
  • Fig. 5A schematically shows an exemplary depletion mode transistor having a gate, a drain, and a source.
  • Fig. 5B schematically shows an exemplary depletion mode transistor converted into a resistor by removing the gate.
  • Fig. 5C schematically shows an exemplary current source created from a depletion mode transistor in combination with a resistor coupled to the gate of the transistor;
  • Fig. 5D schematically shows one embodiment of the present invention using depletion mode transistors to form a differential pair with an active load such that the current is equal in both sides of the differential pair.
  • Figure 5E schematically shows an embodiment of a depletion mode transistor circuit having a buffer with gain K close to unity for causing the current to be equal in both sides of the differential pair and the drain voltage to be equal for both sides of the differential pair;
  • Fig. 6 schematically shows an embodiment of a depletion mode transistor circuit with a source-follower transistor forcing the AC voltage at the drains of two transistors of the differential pair to be equal;
  • Fig. 7 illustratively shows the design of the high side current mirror using depletion mode devices in accordance with illustrative embodiments of the invention
  • Fig. 8 schematically shows a full gain stage showing the differential pair with the high side current mirror using depletion mode devices in accordance with illustrative embodiments of the invention
  • Fig. 9 is a graph that shows that a tested version of the circuit of Fig. 8 has has a gain bandwidth product of 40 MHz.
  • Fig. 10 is a graph that shows that a tested version of the circuit of Fig. 8 has a differential DC open loop gain of approximately 400. DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
  • Embodiments of the present invention are implemented using depletion mode field effect transistors such as n-type gallium nitride (GaN) field effect transistors.
  • GaN transistors will be referenced within the specification, embodiments of the circuit topology are not limited to GaN transistors. Rather, embodiments of the present invention are directed to depletion mode transistors and the creation of a high gain differential pair stage that includes depletion mode transistors that operates over a wide frequency band and can be used as a gain stage in the creation of an operational amplifier.
  • Fig. 5A schematically shows a depletion mode transistor (e.g. a GaN n-type depletion transistor).
  • the transistor is a field effect transistor that contains a source, a drain, and a gate.
  • depletion mode field effect transistors are in an "on” state when the gate voltage is equal to the source voltage of the transistor, such that current will flow through the drain source juncture of the transistor.
  • a depletion mode device can be turned “off” when the gate voltage is taken below the source voltage by the threshold voltage when current stops flowing through the drain source junction of the transistor.
  • a resistor can be created from a GaN transistor by eliminating the gate, which produces a diffusion resistor.
  • a current source can be formed out of GaN n-type transistors by forcing a threshold voltage across a GaN diffusion resistor by coupling one side of the resistor to the gate of an n-type transistor while the other side of the resistor is connected to the source of the transistor.
  • the GaN current source between the drain and gate of the transistor behaves as current source up to approximately 150V at the drain of the transistor. Variations in the current source are due mainly to the variation in the threshold voltage of the GaN transistors.
  • the output impedance of a GaN current source is approximately 3 ⁇ and can be increased with a set of cascoded transistors to greater than 20 ⁇ .
  • the current source is formed by forcing the threshold voltage across the diffusion resistor.
  • the gate of depletion mode transistor Jl is at ground and the potential at the source of transistor Jl is approximately 3.5V assuming that the transistor is a GaN n-type depletion transistor.
  • the transistor draws a constant current equal to 3.5 V/ depletion mode resistor value.
  • a current source with a set of cascoded transistors is shown in Fig. 7 These cascoded transistors help increase the output impedance of the gain stage.
  • the behavior of the current source can be
  • Figure 5D schematically shows one embodiment of the present invention where the output impedance of a single ended depletion mode differential pair is r ds and the transconductance of the differential pair is g m ⁇ .
  • the differential voltage gain is g ml x r ds .
  • the output impedance of the differential pair is limited by the output impedance of the device 501.
  • the output impedance of one side of the differential pair can be increased further by keeping the two drains of the differential pair at the same potential.
  • a buffer 503 with gain K close to unity keeps the AC drain voltages close to each other.
  • K close to 1 the output impedance can be increased significantly.
  • the voltage gain is doubled as the output impedance is doubled.
  • illustrative embodiments further enhance this design by double cascoding the current source, as explained below.
  • the source-follower transistor Q3 forces the AC voltage at the drain of Ql (601) and Q2 (600) to be equal.
  • the AC source voltage of Q3 (603) (which is also the AC drain voltage of Ql (601) follows the AC voltage at the gate of the transistor Q3.
  • the voltage gain is:
  • gml is the transconductance of device Ql
  • rdsl is the drain to source impedance of device Ql
  • gm2 is the transconductance of device Q2
  • rds2 is the drain to source impedance of device Q2
  • gm3 is the transconductance of device Q3
  • rds3 is the drain to source impedance of device Q3
  • Q1-Q3 and J1-J4 are n-type depletion mode GaN FETs.
  • Figure 7 shows the design of the high side current mirror using GaN depletion mode devices in accordance with illustrative embodiments of the invention.
  • the top rail of the circuit is coupled to a voltage source, such as a constant voltage source that is typically designated Vdd.
  • Device Jl and resistor Rl are used to realize a simple current source as explained earlier.
  • Device J2 implements the gain enhancement for the differential pair.
  • Device J3 and J4 are used to maintain a fixed voltage (e.g., about 2 VT) across the drain-source of J2 and Jl to further improve the output impedance. From Fig. 7 the output voltage is fed back to the gate of transistor Jl. Due to the threshold voltage of the depletion mode transistor being approximately 3V the voltage at the source of Jl is Vo plus approximately 3V. This voltage is also seen at the gate of transistor J2. Thus, the voltage at the source of J2 is Vo plus 2Vt, which is Vo ⁇ +6V. This voltage feeds the gate of transistor J4 which is part of the cascode circuit. The voltage at the source of J4 is Vo— I-9V. The source voltage of the J4 transistor is the same voltage as the gate voltage of transistor J3. Therefore, the source voltage of transistor J3 is Vo— I-12V. As a result, the drain to source voltages of transistors Jl and J2 are substantially constant at 2Vt or 6V independent of the output voltage.
  • the threshold voltage of the depletion mode transistor being approximately 3V the
  • the output impedance of the high side current mirror at the output is g m r ds 2
  • Figure 8 schematically shows the full gain stage showing the differential pair (Ql, Q2) with the high side current mirror (J1-J4 and R) in accordance with illustrative embodiments of the invention.
  • the differential pair Ql and Q2 may both be n-type transistors.
  • the differential pair Ql and Q2 may be constructed from n-type enhancement mode devices. All of the remaining transistors in such an embodiment (J1-J4) would remain n-type depletion mode transistors. This embodiment would function similarly to the circuit that uses only n-type depletion mode transistors.
  • the circuit of Fig. 8 was fabricated and measurements showed that this input stage has a differential DC gain of 400 as show in Fig. 10 and a gain bandwidth product of 40MHz at 150V power supply as shown in Fig. 9.
  • the above circuit is one of the important ways of enhancing the differential gain of a differential pair using n-type GaN depletion mode devices only in a GaN fabrication process.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Amplifiers (AREA)

Abstract

A differential pair gain stage is disclosed. In one embodiment, the gain stage includes a differential pair of depletion-mode transistors, including a first and a second n-type transistor. In certain embodiments of the invention, the depletion mode transistor may be GaN (gallium nitride) field effect transistors. The gain stage includes an active load including one or more depletion mode transistors electrically coupled to at least one of the drains of depletion mode transistors of the differential pair. The active load may include a source follower for maintaining the AC voltages at the drains of the differential pair at a constant value and may further include a casocde stage for setting a fixed drain source voltage across the output transistors to increase the output impedance and gain of the stage.

Description

HIGH GAIN LOAD CIRCUIT FOR A DIFFERENTIAL PAIR
USING DEPLETION MODE TRANSISTORS
PRIORITY
The present application claims the benefit of U.S. Provisional Patent Application 62/ 087,987 filed on December 5, 2014, which is incorporated herein by reference in its entirety.
FIELD OF THE INVENTION
The invention generally relates to depletion mode transistors and, more particularly, the invention relates to a differential pair gain stage using depletion mode transistors, such as, gallium nitride transistors.
BACKGROUND OF THE INVENTION
As should be understood by one of ordinary skill in the art, depletion mode field effect transistors are in an "on" state when the gate voltage is equal to the source voltage of the transistor, such that current will flow through the drain source juncture of the transistor. A depletion mode device can be turned "off" when the gate voltage is taken below the source voltage by the threshold voltage when current stops flowing through the drain source junction of the transistor.
Some fabrication technologies are either technically limited or cost limited to fabricating only depletion mode field effect transistors. For example, Gallium Nitride (GaN) is presently one such fabrication technology. Design of analog integrated circuits in Gallium Nitride (GaN) fabrication technology is beginning to gain traction due to its significant benefits over silicon. Specifically, among other things, GaN fabrication technology benefits include high bandwidth, high temperature operation and high breakdown voltages. This is largely due to the fact that GaN has a higher bandgap voltage than silicon (3.49eV vs l.leV) and higher critical breakdown field (3MV/cm vs 0.3MV/ cm). At the same time, the fabrication of GaN circuits on a silicon (Si) substrate has made the technology affordable and applicable for a wider range of applications.
The variety of GaN transistor device choices, however, is limited. While n- type depletion and enhancement mode devices are available, p-type GaN devices are not available as they have poor performance due to fundamental device physics issues. Hence the challenge is to make analog circuits using only n-type depletion and enhancement mode devices.
Fig. 1 schematically shows one prior art elementary analog circuit— a gain block that has of a differential pair 100, 101 driving load devices 105, 106. This block provides a differential signal gain while rejecting common mode signals. Getting the highest differential gain out of this circuit is important for building a wide array of high performance analog circuits.
A differential pair of two transistors 100 and 101 when formed in silicon and operating in enhancement mode, such as that shown in Figure 1, can be loaded with a wide array of load device choices. One choice uses load resistors 220, 221 and is schematically shown in Fig. 2. This circuit has poor gain because the resistors 220, 221 cannot be made sufficiently large as the resistor has to conduct the DC bias current, thus the resistors need to be small. Ideally this circuit could have a current mirror (made of a current sense 331 and a current source device 332) for the load devices of the differential pair 300, 301 as shown in Fig. 3.
The high output impedance of the current source 332 normally provides good differential gain while the current source can provide the DC bias current as needed. In silicon, p-type transistors 400, 401 typically are easily used to design the current mirror (Figure 4). Undesirably, this option currently is not available in the GaN fabrication process.
SUMMARY OF THE EMBODIMENTS
Embodiments of the invention include a depletion mode differential pair gain stage. The gain stage includes a differential pair of depletion-mode transistors, including a first and a second n-type transistor. In certain
embodiments of the invention, the depletion mode transistor may be GaN (gallium nitride) field effect transistors. The transistors have a gate, source, and a drain and the differential pair coupled at the source of each transistor forming a common node. The gain stage also includes an active load including one or more depletion mode transistors electrically coupled to at least one of the drains of depletion mode transistors of the differential pair.
The differential pair may also include a constant current source coupled to a common node of the differential pair. The current source can be used for biasing the differential pair.
In embodiments of the invention, the active load includes a current source formed from a third depletion mode transistor coupled to a resistor. The current source of the active load electrically couples the gate of the third depletion mode transistor to the drain of the second n-type depletion mode transistor of the differential pair.
In yet another embodiment of the invention the active load include a buffer formed from at least a fourth depletion mode transistors electrically coupling the drains of the first and second n-type depletion mode transistors of the differential pair. The buffer ideally has a substantially unity gain, which causes the output impedance to increase. The gain of the buffer may be substantially unity such that any gain between .5 and 1 would at least double the output impedance and increase the overall gain.
The buffer of the active load may be formed as a source follower in which a depletion mode transistor has its gate electrically coupled to the current source formed from the third depletion mode transistor. The source follower of the buffer causes the AC voltage at the drains of the differential pair to remain at the same potential. By having the AC voltage at the drains remain at the same potential the biasing current from the common node will be split between the two sides of the differential pair.
The gain stage may be further enhanced by increasing the output impedance of the circuit. A cascade stage can be added to the active load to maintain a fixed voltage above the threshold voltage of the depletion mode transistor across the drain of at least the source the depletion mode transistor that forms the source follower.
Depletion mode transistors of any fabrication type may be used with the circuit topology described herein to create a differential pair gain stage and this gain stage can be used in the formation of an operational amplified. Fabrication techniques may include silicon and gallium nitride for example. Embodiments of the present invention can be used in high bandwidth, high gain applications and can be employed with high voltage supplies >50V and operate at high temperatures, such as the temperatures that GaN circuits have been known to function.
In yet another embodiment of the invention, the differential pair is made up of n-type enhancement mode transistors and the active load includes only n- type depletion mode transistors. Gain enhancement may be achieved with an n- type depletion mode transistor as a source follower so that the AC voltage of the drains of the differential pair are equal. The differential pair gain stage may further be enhanced with a cascode stage that causes the drain/ source junction of at least one n-type depletion mode transistor in the active load to have a constant voltage. The constant voltage causes the output impedance to be increased.
BRIEF DESCRIPTION OF THE DRAWINGS
Those skilled in the art should more fully appreciate advantages of various embodiments of the invention from the following "Description of Illustrative Embodiments," discussed with reference to the drawings
summarized immediately below.
Fig. 1 schematically shows a prior art elementary analog circuit in silicon— a gain block that has a differential pair driving load devices.
Fig. 2 schematically shows a prior art silicon-based differential circuit loaded with resistors.
Fig. 3 schematically shows a silicon-based prior art differential circuit with a current mirror.
Fig. 4 schematically shows a silicon-based prior art circuit with a current mirror using p-type transistors. Fig. 5A schematically shows an exemplary depletion mode transistor having a gate, a drain, and a source.
Fig. 5B schematically shows an exemplary depletion mode transistor converted into a resistor by removing the gate.
Fig. 5C schematically shows an exemplary current source created from a depletion mode transistor in combination with a resistor coupled to the gate of the transistor;
Fig. 5D schematically shows one embodiment of the present invention using depletion mode transistors to form a differential pair with an active load such that the current is equal in both sides of the differential pair.
Figure 5E schematically shows an embodiment of a depletion mode transistor circuit having a buffer with gain K close to unity for causing the current to be equal in both sides of the differential pair and the drain voltage to be equal for both sides of the differential pair;
Fig. 6 schematically shows an embodiment of a depletion mode transistor circuit with a source-follower transistor forcing the AC voltage at the drains of two transistors of the differential pair to be equal;
Fig. 7 illustratively shows the design of the high side current mirror using depletion mode devices in accordance with illustrative embodiments of the invention;
Fig. 8 schematically shows a full gain stage showing the differential pair with the high side current mirror using depletion mode devices in accordance with illustrative embodiments of the invention;
Fig. 9 is a graph that shows that a tested version of the circuit of Fig. 8 has has a gain bandwidth product of 40 MHz; and
Fig. 10 is a graph that shows that a tested version of the circuit of Fig. 8 has a differential DC open loop gain of approximately 400. DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
Embodiments of the present invention are implemented using depletion mode field effect transistors such as n-type gallium nitride (GaN) field effect transistors. Although GaN transistors will be referenced within the specification, embodiments of the circuit topology are not limited to GaN transistors. Rather, embodiments of the present invention are directed to depletion mode transistors and the creation of a high gain differential pair stage that includes depletion mode transistors that operates over a wide frequency band and can be used as a gain stage in the creation of an operational amplifier. Fig. 5A schematically shows a depletion mode transistor (e.g. a GaN n-type depletion transistor). The transistor is a field effect transistor that contains a source, a drain, and a gate. As explained above, depletion mode field effect transistors are in an "on" state when the gate voltage is equal to the source voltage of the transistor, such that current will flow through the drain source juncture of the transistor. A depletion mode device can be turned "off" when the gate voltage is taken below the source voltage by the threshold voltage when current stops flowing through the drain source junction of the transistor.
As shown in Fig. 5B, a resistor can be created from a GaN transistor by eliminating the gate, which produces a diffusion resistor. As shown in Fig. 5C a current source can be formed out of GaN n-type transistors by forcing a threshold voltage across a GaN diffusion resistor by coupling one side of the resistor to the gate of an n-type transistor while the other side of the resistor is connected to the source of the transistor. The GaN current source between the drain and gate of the transistor behaves as current source up to approximately 150V at the drain of the transistor. Variations in the current source are due mainly to the variation in the threshold voltage of the GaN transistors. The output impedance of a GaN current source is approximately 3ΜΩ and can be increased with a set of cascoded transistors to greater than 20ΜΩ.
As shown in the exemplary current source in Fig. 5C, the current source is formed by forcing the threshold voltage across the diffusion resistor. In this example the gate of depletion mode transistor Jl is at ground and the potential at the source of transistor Jl is approximately 3.5V assuming that the transistor is a GaN n-type depletion transistor. Thus, the transistor draws a constant current equal to 3.5 V/ depletion mode resistor value.
Examples of a current source with a set of cascoded transistors is shown in Fig. 7 These cascoded transistors help increase the output impedance of the gain stage. The behavior of the current source can
Figure 5D schematically shows one embodiment of the present invention where the output impedance of a single ended depletion mode differential pair is rds and the transconductance of the differential pair is gm\. The differential voltage gain is gml x rds. The output impedance of the differential pair is limited by the output impedance of the device 501.
The output impedance of one side of the differential pair can be increased further by keeping the two drains of the differential pair at the same potential. In Fig. 5E, a buffer 503 with gain K (close to unity) keeps the AC drain voltages close to each other. In this configuration:
Figure imgf000010_0001
For K close to 1, the output impedance can be increased significantly. The term substantially unity is used in this specification and the appended claims and the term refers to values of K close to 1 including K=.5 up to K=l. At K=.5 the voltage gain is doubled as the output impedance is doubled. In addition, illustrative embodiments further enhance this design by double cascoding the current source, as explained below.
In one illustrative implementation, shown in Figure 6, the source-follower transistor Q3 (603) forces the AC voltage at the drain of Ql (601) and Q2 (600) to be equal. As is known to one of ordinary skill in the art, in a source follower circuit the AC source voltage of Q3 (603) (which is also the AC drain voltage of Ql (601) follows the AC voltage at the gate of the transistor Q3. In this configuration, the voltage gain is:
V ml (1 + 9mlrdsl _ 9m3rds3
(1 + 9m2rds2) (1 + 9m3rds3)
Where gml is the transconductance of device Ql
rdsl is the drain to source impedance of device Ql
gm2 is the transconductance of device Q2
rds2 is the drain to source impedance of device Q2
gm3 is the transconductance of device Q3
rds3 is the drain to source impedance of device Q3
This expression reduces to (gmrds)2 assuming that the transistors are all equally sized. Thus, this technique has squared the differential gain of the block. In illustrative embodiments, Q1-Q3 and J1-J4 are n-type depletion mode GaN FETs. Figure 7 shows the design of the high side current mirror using GaN depletion mode devices in accordance with illustrative embodiments of the invention. The top rail of the circuit is coupled to a voltage source, such as a constant voltage source that is typically designated Vdd. Device Jl and resistor Rl are used to realize a simple current source as explained earlier. Device J2 implements the gain enhancement for the differential pair. Device J3 and J4 are used to maintain a fixed voltage (e.g., about 2 VT) across the drain-source of J2 and Jl to further improve the output impedance. From Fig. 7 the output voltage is fed back to the gate of transistor Jl. Due to the threshold voltage of the depletion mode transistor being approximately 3V the voltage at the source of Jl is Vo plus approximately 3V. This voltage is also seen at the gate of transistor J2. Thus, the voltage at the source of J2 is Vo plus 2Vt, which is Vo~+6V. This voltage feeds the gate of transistor J4 which is part of the cascode circuit. The voltage at the source of J4 is Vo— I-9V. The source voltage of the J4 transistor is the same voltage as the gate voltage of transistor J3. Therefore, the source voltage of transistor J3 is Vo— I-12V. As a result, the drain to source voltages of transistors Jl and J2 are substantially constant at 2Vt or 6V independent of the output voltage.
It should be recognized by holding the voltage across the drain-source junction to a constant value, the output impedance is further increased. When the devices are biased roughly at the same current density, the output impedance of the high side current mirror at the output is gmrds 2
Figure 8 schematically shows the full gain stage showing the differential pair (Ql, Q2) with the high side current mirror (J1-J4 and R) in accordance with illustrative embodiments of the invention. The differential pair Ql and Q2 may both be n-type transistors. In an alternative embodiment, the differential pair Ql and Q2 may be constructed from n-type enhancement mode devices. All of the remaining transistors in such an embodiment (J1-J4) would remain n-type depletion mode transistors. This embodiment would function similarly to the circuit that uses only n-type depletion mode transistors.
The circuit of Fig. 8 was fabricated and measurements showed that this input stage has a differential DC gain of 400 as show in Fig. 10 and a gain bandwidth product of 40MHz at 150V power supply as shown in Fig. 9. The above circuit is one of the important ways of enhancing the differential gain of a differential pair using n-type GaN depletion mode devices only in a GaN fabrication process.
Although the above discussion discloses various exemplary embodiments of the invention, it should be apparent that those skilled in the art can make various modifications that will achieve some of the advantages of the invention without departing from the true scope of the invention.

Claims

We claim:
1. A depletion mode differential pair gain stage comprising:
a differential pair of depletion-mode transistors, including a first and a second transistor, the transistors having a gate, source, and a drain, the differential pair coupled at the source of each transistor forming a common node; and an active load including one or more depletion mode transistors electrically coupled to at least one of the drains of depletion mode transistors of the differential pair.
2. A depletion mode differential pair gain stage according to claim 1 further comprising:
a constant current source coupled to the common node of the differential pair.
3. A depletion mode differential pair gain stage according to claim 2 wherein the active load includes a current source formed from a third depletion mode transistor coupled to a resistor, the current source electrically coupling the gate of the third depletion mode transistor to the drain of the second depletion mode transistor.
4. A depletion mode differential pair gain stage according to claim 3,
wherein the active load includes a buffer formed from at least a fourth depletion mode transistor electrically coupling the drains of the first and second depletion mode transistors of the differential pair.
5. A depletion mode differential pair gain stage according to claim 1 wherein the transistors are field effect transistors
6. A depletion mode differential pair gain stage according to claim 4 wherein the buffer has a substantially unity gain.
7. A depletion mode differential pair gain stage according to claim 6 wherein the fourth depletion mode transistor has its gate electrically coupled to the current source formed from the third depletion mode transistor forming a source follower.
8. A depletion mode differential pair gain stage according to claim 7 wherein during operation of the gain stage the buffer keeps AC voltage at the drains of the differential pair at the same potential.
9. A depletion mode differential pair gain stage according to claim 8 wherein the active load includes a cascode stage formed from at least two additional depletion mode transistors.
10. A depletion mode differential pair gain stage according to claim 9 wherein the cascode stage maintains a fixed voltage above the threshold voltage of the depletion mode transistor at the source of at least the fourth depletion mode transistor that forms the source follower.
11. A depletion mode differential pair gain stage according to claim 1 wherein each depletion mode transistor is an n-type gallium nitride depletion mode transistor.
12. A gallium nitride differential pair gain stage comprising:
a differential pair of n-type gallium nitride transistors, including a first and a second transistor, the transistors having a gate, source, and a drain, the differential pair coupled at the source of each transistor forming a common node;
and
an active load including a current source formed from a third n-type gallium nitride transistor coupled to a resistor, the current source electrically coupling the gate of the third n-type gallium nitride transistor to the drain of the second n-type gallium nitride transistor and a buffer formed from at least a fourth n-type gallium nitride transistor electrically coupling the drains of the first and second n-type gallium nitride transistors of the differential pair to the same AC voltage.
13. A gallium nitride differential pair gain stage according to claim 12
wherein the active load includes a cascode stage formed from at least two additional n-type gallium nitride transistors.
14. A gallium nitride differential pair gain stage according to claim 13
wherein the cascode stage maintains a fixed voltage across the drain and source of the fourth depletion mode transistor that forms the source follower thereby increasing the output impedance of the gallium nitride differential pair gain stage as compared to differential pair gain stage without the cascade stage.
15. A differential pair gain stage comprising:
a differential pair of n-type enhancement-mode transistors, including a first and a second transistor, the transistors having a gate, source, and a drain, the differential pair coupled at the source of each transistor forming a common node; and
an active load electrically coupled to at least one of the drains of the n- type enhancement mode transistors of the differential pair, the active load containing only n-type depletion mode transistors.
16. A differential pair gain stage according to claim 15 wherein the active load includes a current source formed from an n-type depletion mode transistor coupled to a resistor.
17. A differential pair gain stage according to claim 16, wherein the active load includes a buffer having an n-type depletion mode transistor to couple the drains of the transistors of the differential pair to have the same AC voltage.
18. A differential pair gain stage according to claim 17 wherein the buffer has a substantially unity gain.
19. A differential pair gain stage according to claim 18 wherein the active load includes a cascode stage formed from at least two n-type depletion mode transistors.
20. A differential pair gain stage according to claim 19 wherein the cascode stage maintains a fixed voltage across a drain source junction of the depletion mode transistor in the buffer.
PCT/US2015/063996 2014-12-05 2015-12-04 High gain load circuit for a differential pair using depletion mode transistors WO2016090248A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP15825667.7A EP3228002A1 (en) 2014-12-05 2015-12-04 High gain load circuit for a differential pair using depletion mode transistors

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201462087987P 2014-12-05 2014-12-05
US62/087,987 2014-12-05

Publications (1)

Publication Number Publication Date
WO2016090248A1 true WO2016090248A1 (en) 2016-06-09

Family

ID=55168357

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2015/063996 WO2016090248A1 (en) 2014-12-05 2015-12-04 High gain load circuit for a differential pair using depletion mode transistors

Country Status (4)

Country Link
US (1) US10284194B2 (en)
EP (1) EP3228002A1 (en)
DE (1) DE202015009751U1 (en)
WO (1) WO2016090248A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102019120355B3 (en) * 2019-07-04 2020-10-29 Elmos Semiconductor Se HV amplifier for controlling data lines
DE102019120354B3 (en) * 2019-07-04 2020-10-29 Elmos Semiconductor Se Input stage of an HV amplifier for controlling data lines
CN111404529B (en) * 2020-04-03 2023-04-25 电子科技大学 Segmented direct gate driving circuit of depletion type GaN power device
US11489441B2 (en) * 2020-06-02 2022-11-01 Texas Instruments Incorporated Reference voltage generation circuits and related methods

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5132560A (en) * 1990-09-28 1992-07-21 Siemens Corporate Research, Inc. Voltage comparator with automatic output-level adjustment
US6320429B1 (en) * 1991-06-28 2001-11-20 Fuji Electric Co., Ltd. Integrated circuit having a comparator circuit including at least one differential amplifier
JP3347615B2 (en) * 1996-11-28 2002-11-20 富士通株式会社 Semiconductor integrated circuit and optical transmission module
US5966005A (en) * 1997-12-18 1999-10-12 Asahi Corporation Low voltage self cascode current mirror
JP2001036186A (en) 1999-07-16 2001-02-09 Sony Corp Semiconductor laser drive circuit
US7019590B1 (en) * 2004-09-20 2006-03-28 National Semiconductor Corporation Self-stabilizing differential load circuit with well controlled impedance
US7236011B2 (en) * 2004-09-20 2007-06-26 Analog Devices, Inc. High-speed differential logic buffer
KR100693821B1 (en) * 2005-10-31 2007-03-12 삼성전자주식회사 Differential amplifier and active load for the same
US8090334B1 (en) * 2007-09-11 2012-01-03 Marvell International Ltd. High accuracy programmable gain amplifier
JP5543059B2 (en) * 2007-10-10 2014-07-09 ピーエスフォー ルクスコ エスエイアールエル Differential amplifier circuit
US8766720B2 (en) 2012-06-29 2014-07-01 Siemens Energy, Inc. Hybrid load differential amplifier operable in a high temperature environment of a turbine engine
US9105752B2 (en) 2008-11-14 2015-08-11 Kulite Semiconductor Products, Inc. High temperature transducer using SOI, silicon carbide or gallium nitride electronics
US8859337B2 (en) 2009-12-15 2014-10-14 Soitec Thermal matching in semiconductor devices using heat distribution structures
JP2011155488A (en) * 2010-01-27 2011-08-11 Ricoh Co Ltd Differential input stage circuit, operational amplifier including the same, and voltage regulator circuit
JP2013239898A (en) * 2012-05-15 2013-11-28 Ps4 Luxco S A R L Differential amplifier circuit and semiconductor device provided with the same

Non-Patent Citations (6)

* Cited by examiner, † Cited by third party
Title
ABIDI A A: "ON THE OPERATION OF CASCODE GAIN STAGES", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE SERVICE CENTER, PISCATAWAY, NJ, USA, vol. 23, no. 6, 1 December 1988 (1988-12-01), pages 1434 - 1437, XP000608528, ISSN: 0018-9200, DOI: 10.1109/4.90043 *
ASSAD A ABIDI: "An Analysis of Bootstrapped Gain Enhancement Techniques", 6 December 1987 (1987-12-06), pages 1200 - 1204, XP055259756, Retrieved from the Internet <URL:http://ieeexplore.ieee.org/ielx5/4/22617/01052875.pdf?tp=&arnumber=1052875&isnumber=22617> [retrieved on 20160318] *
LAWRENCE E LARSON ET AL: "SESSION 111: SAMPLED-DATA ANALOG CIRCUITS WAM 3.1: GaAs Switched-Capacitor Circuits for Video Signal Processing*", 25 February 1987 (1987-02-25), pages 40 - 41, XP055259752, Retrieved from the Internet <URL:http://ieeexplore.ieee.org/ielx6/8303/25935/01157146.pdf?tp=&arnumber=1157146&isnumber=25935> [retrieved on 20160318] *
MARALANI A ET AL: "Design of a Silicon Carbide JFET based operational amplifier for gain and CMRR performance", CIRCUITS AND SYSTEMS, 2009. ISCAS 2009. IEEE INTERNATIONAL SYMPOSIUM ON, IEEE, PISCATAWAY, NJ, USA, 24 May 2009 (2009-05-24), pages 1953 - 1956, XP031573276, ISBN: 978-1-4244-3827-3 *
XIAO S ET AL: "IMPROVED DOUBLE CASCODE SELF-BOOTSTRAPPING TECHNIQUE FOR GAIN ENHANCEMENT IN GAAS MESFET OPAMPS", ELECTRONICS LETTERS, IEE STEVENAGE, GB, vol. 28, no. 12, 4 June 1992 (1992-06-04), pages 1128 - 1129, XP000304632, ISSN: 0013-5194 *
XIAOSEN LIU ET AL: "GaN Single-Polarity Power Supply Bootstrapped Comparator for High-Temperature Electronics", IEEE ELECTRON DEVICE LETTERS, IEEE SERVICE CENTER, NEW YORK, NY, US, vol. 32, no. 1, 1 January 2011 (2011-01-01), pages 27 - 29, XP011340562, ISSN: 0741-3106, DOI: 10.1109/LED.2010.2088376 *

Also Published As

Publication number Publication date
US10284194B2 (en) 2019-05-07
US20160164517A1 (en) 2016-06-09
DE202015009751U1 (en) 2019-11-26
EP3228002A1 (en) 2017-10-11

Similar Documents

Publication Publication Date Title
US4048575A (en) Operational amplifier
US3947778A (en) Differential amplifier
US8138839B2 (en) Wideband CMOS gain stage
US6433637B1 (en) Single cell rail-to-rail input/output operational amplifier
US10284194B2 (en) High gain load circuit for a differential pair using depletion mode transistors
US3956708A (en) MOSFET comparator
US20170047897A1 (en) Dc bias regulator for cascode amplifier
US20080007338A1 (en) Regulated cascode circuit, an amplifier including the same, and method of regulating a cascode circuit
JP5083845B2 (en) Semiconductor differential amplifier
US20150207468A1 (en) Amplifier circuit
US11742812B2 (en) Output pole-compensated operational amplifier
US8432226B1 (en) Amplifier circuits and methods for cancelling Miller capacitance
TWI699966B (en) Operational amplifier
JP3841652B2 (en) Amplifier circuit
US7167053B2 (en) Integrated circuit amplifier device and method using FET tunneling gate current
US20150015326A1 (en) Bulk-modulated current source
KR20200048583A (en) Low noise amplifier using differential superposition circuit
CA1180773A (en) Differential amplifier with differential to single- ended conversion function
US20240056044A1 (en) Precision operational amplifier using floating input stage
TWI681622B (en) Power amplifier and compound semiconductor device
JP3500544B2 (en) Amplifier circuit
JPH0257721B2 (en)
JPH09294026A (en) Semiconductor circuit
Raj et al. Multifunction filter design using BDQFG miller OTA
JP2021507595A (en) High voltage, high speed GaN drive circuit

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15825667

Country of ref document: EP

Kind code of ref document: A1

REEP Request for entry into the european phase

Ref document number: 2015825667

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: DE