WO2016088220A1

WO2016088220A1 - Computer and control method for logical processors

Info

Publication number: WO2016088220A1
Application number: PCT/JP2014/081967
Authority: WO
Inventors: 周平松本; 仁川嶋; 栄一郎大岩
Original assignee: 株式会社日立製作所
Priority date: 2014-12-03
Filing date: 2014-12-03
Publication date: 2016-06-09

Abstract

A computer provided with physical CPUs and a physical memory that stores a program for implementing a virtualization unit, wherein said virtualization unit: divides the physical CPUs into a plurality of logical CPUs and allocates a first logical CPU and a second logical CPU to a first LPAR on which a first OS operates; retains management information for managing associations between the identifiers of the logical CPUs and the addresses of monitored regions in an address space managed by the OS; registers, in the management information, information associating the identifier of the first logical CPU with the address of a monitored region for the first logical CPU, in the address space managed by the first OS, if the virtualization unit detects a MONITOR command for the first logical CPU issued from the first OS; and causes the first logical CPU to transition into a dormant state if the virtualization unit detects an MWAIT command for the first logical CPU issued from the first OS, or causes the first logical CPU to transition into a running state if the virtualization unit detects a WRITE command and this WRITE command is determined, by reference to the management information, to be a WRITE command for the monitored region for the first logical CPU.

Description

Computer and logical processor control method

The present invention relates to suspension control of a logical CPU in a virtual machine.

Currently, in order to effectively use computer resources of a physical computer having a physical CPU (Central Processing Unit), a physical memory, an IO device, and the like, the use of virtualization technology is generalized. In the virtualization technology, a virtualization unit such as a hypervisor logically divides a computer resource of a physical computer, assigns it to each of a plurality of virtual computers, and operates an OS (Operating System) on the virtual computer. Are known. Here, the virtual machine is also referred to as LPAR (Logical Partition).

The virtualization unit dynamically allocates a plurality of physical CPUs according to the states of the logical CPUs of the plurality of LPARs on the physical computer (see, for example, Patent Document 1). Patent Document 1 describes that when a logical CPU transitions from an execution state to a dormant state, the virtualization unit releases the physical CPU assignment assigned to the logical CPU. The released physical CPU can be assigned to another logical CPU. By the control as described above, the limited computer resources possessed by the physical computer can be effectively utilized.

The MONITOR / MWAIT system is known as a conventional physical CPU sleep control system. A physical CPU that implements the MONITOR / MWAIT system includes an instruction execution unit that executes an instruction and a MONITOR unit. The MONITOR unit periodically monitors the value of a specific memory area (hereinafter referred to as a monitor area) on the physical memory registered in advance for each physical CPU. Note that a MONITOR instruction issued by the OS is used for registering the monitor area.

In the MONITOR / MWAIT system, the physical CPU can be put into a sleep state by the MWAIT command issued from the OS. The physical CPU that has entered the hibernation state operates in a power saving state by stopping the instruction execution unit. On the other hand, the MONITOR section monitors the value in the monitor area even while the physical CPU is in the dormant state. Further, the OS writes a value in the monitor area via a CPU other than the CPU in the power saving state in order to release the power saving state. When the MONITOR unit of the physical CPU in the dormant state detects writing to the monitor area, the MONITOR unit releases the dormant state of the physical CPU by operating the instruction execution unit. As a result, the operation of the instruction execution unit is resumed.

As described above, in the control of the physical CPU by the MONITOR / MWAIT system, the MONITOR unit that changes the physical CPU from the execution state to the hibernation state in response to a request from the OS, and that operates even when the physical CPU is in the hibernation state, In response to a request from, the physical CPU can be quickly transitioned from the sleep state to the execution state.

JP 2013-250949 A

There are various correspondences between the logical CPU of the LPAR and the physical CPU of the physical computer depending on the setting. For example, there are associations in which one physical CPU is shared by a plurality of logical CPUs, associations in which a plurality of physical CPUs are assigned to one logical CPU, and the like. In the association as described above, the same physical CPU is not always assigned to the logical CPU, but the physical CPU is dynamically assigned to the logical CPU.

On the other hand, the MONITOR part of the physical CPU monitors only one monitor area. Therefore, the guest OS on each LPAR cannot register the monitor area of the logical CPU. Therefore, when the guest OS writes a value to the monitor area of the logical CPU, the MONITOR part of the physical CPU cannot detect writing to the monitor area. Accordingly, the logical CPU cannot realize the MONITOR / MWAIT control similar to the physical CPU.

A typical example of the invention disclosed in the present application is as follows. That is, as a computer resource, a computer including a plurality of physical processors and a physical memory connected to each of the plurality of physical processors, wherein the physical memory is logically divided into a plurality of logical partitions. An operating system that stores a program that realizes a virtualization unit that allocates the computer resources, manages a plurality of logical processors and a logical memory in each of the plurality of logical partitions, and the virtualization unit The plurality of physical processors manage the allocation of the plurality of physical processors so that the plurality of logical processors included in each of the logical partitions share the same plurality of physical processors. Two physical processors, and the operating system includes: A MONITOR instruction that designates a monitor area that is a memory area to be monitored in order to transition the processor to be managed from the hibernation state to the execution state; The plurality of logical partitions includes a first logical partition having a first logical processor, a second logical processor, and a first logical memory, and running a first operating system; The virtualization unit holds monitor area management information for managing an association between an identifier of a logical processor that is a target of the MONITOR instruction and an address of the monitor area in an address space managed by the operating system. The first physical processor assigned to the logical processor of When a MONITOR instruction for the first logical processor is detected by the first operating system, the identifier of the first logical processor and the first space in the address space managed by the first operating system are detected. Information that associates the address of the monitor area of the logical processor is registered in the monitor area management information, and the first logical processor assigns the first logical processor to the first logical processor. When a MWAIT instruction for a processor is detected, the first logical processor is transitioned from an execution state to a sleep state, the first physical processor is unassigned from the first logical processor, and the second logical processor is released. Said first assigned to a processor When a WRITE instruction for the monitor area of the first logical processor is detected by the second physical processor from the first operating system, the monitor area of the first logical processor is referred to by referring to the monitor area management information WRITE instruction is specified, and the first logical processor is changed from the sleep state to the execution state.

According to the present invention, the virtualization unit can realize suspension control of the MONITOR / MWAIT system even in the logical processor of the logical partition by emulating various instructions in the MONITOR / MWAIT system.

Issues, configurations, and effects other than those described above will be clarified by the description of the following examples.

FIG. 3 is an explanatory diagram illustrating an example of a configuration of a physical computer according to the first embodiment. It is explanatory drawing which shows the correspondence of the guest physical address space of Example 1, and a kernel virtual address space. FIG. 3 is an explanatory diagram illustrating an example of CPU configuration information according to the first embodiment. FIG. 3 is an explanatory diagram illustrating an example of memory configuration information according to the first embodiment. FIG. 6 is an explanatory diagram illustrating an example of monitor area management information according to the first embodiment. FIG. 10 is a sequence diagram illustrating a flow of instruction emulation processing in the MONITOR / MWAIT system of the shared mode logical CPU according to the first embodiment. 6 is a flowchart illustrating an example of a monitor area registration process executed by the hypervisor according to the first embodiment. 6 is a flowchart for explaining hibernation state transition processing executed by the hypervisor according to the first embodiment. 6 is a flowchart illustrating an execution state transition process executed by the hypervisor according to the first embodiment. 10 is a flowchart illustrating an execution state transition process executed by a hypervisor according to the second embodiment.

Hereinafter, embodiments will be described with reference to the drawings.

FIG. 1 is an explanatory diagram illustrating an example of the configuration of the physical computer according to the first embodiment.

The physical computer 100 includes a plurality of physical CPUs 101 and one or more physical memories 102 as computer resources. In the example illustrated in FIG. 1, the physical computer 100 includes four physical CPUs 101, a physical CPU 1 (101-1), a physical CPU 2 (101-2), a physical CPU 3 (101-3), and a physical CPU 4 (101-4). . The plurality of physical CPUs 101 and one or more physical memories 102 are connected via a bus or the like.

The physical computer 100 includes, as computer resources, storage devices such as NIC (Network Interface Card) and IO devices such as HBA (Host Bus Adapter), HDD (Hard Disk Drive), and SSD (Solid State Drive). May be.

The physical CPU 101 executes a program stored in the physical memory 102. The physical CPU 101 of this embodiment includes an instruction execution unit 110 and a MONITOR unit 111. The instruction execution unit 110 executes various arithmetic processes according to a program. The MONITOR unit 111 controls the MONITOR / MWAIT system.

Various functions of the physical computer 100 can be realized by the instruction execution unit 110 of the physical CPU 101 executing the program. In the following description, when a program is mainly described, it indicates that the program is being executed by the physical CPU 101.

When the MONITOR unit 111 receives an MWAIT command from the OS, the MONITOR unit 111 causes the physical CPU 101 to transition from the execution state to the sleep state, and periodically monitors the value of a predetermined memory area of the physical memory 102. Also, the MONITOR unit 111 cancels the sleep state of the physical CPU 101 when detecting a WRITE command for a predetermined memory area. Here, the MWAIT instruction is an instruction for causing the processor managed by the OS to transition from the execution state to the hibernation state.

In the following description, a predetermined memory area monitored by the MONITOR unit 111 is also referred to as a monitor area. The monitor area is set by a MONITOR instruction issued by the OS. Here, the MONITOR instruction is an instruction for designating a monitor area for transitioning the CPU managed by the OS from the sleep state to the execution state.

A virtual environment is constructed on the physical computer 100 using the computer resources described above. The virtual environment is managed by the hypervisor 120. Specifically, the hypervisor 120 logically divides computer resources and allocates the divided computer resources to a plurality of virtual computers (LPARs 130). Each LPAR 130 includes one or more logical CPUs 131 and one or more logical memories 132, and a guest OS 140 runs on each LPAR 130.

In the example shown in FIG. 1, the computer resource of the physical computer 100 is allocated to each of three LPAR1 (130-1), LPAR2 (130-2), and LPAR3 (130-3). In addition, the guest OS1 (140-1) operates in the LPAR1 (130-1), the guest OS2 (140-2) operates in the LPAR2 (130-2), and the guest OS3 (130-3) in the LPAR3 (130-3). 140-3) operates.

The LPAR1 (130-1) includes a logical CPU1 (131-1), a logical CPU2 (131-2), and a logical memory 1 (132-1). The LPAR2 (130-2) includes the logical CPU3 (131-). 3), logical CPU 4 (131-4), and logical memory 2 (132-2), and LPAR 3 (130-3) includes logical CPU 5 (131-5), logical CPU 6 (131-6), And a logical memory 1 (132-3).

The hypervisor 120 has a physical CPU 1 (101-1) and a physical CPU 2 for the logical CPU 1 (131-1), the logical CPU 2 (131-2), the logical CPU 3 (131-3), and the logical CPU 4 (131-4). (101-2) is assigned. Specifically, the hypervisor 120 dynamically assigns the physical CPU 101 according to the usage state of the logical CPU 131. In the following description, a plurality of physical CPUs 101 are dynamically allocated according to the usage state of one logical CPU 131, that is, an allocation mode in which physical CPUs 101 are dynamically allocated to the logical CPU 131 is described as “shared mode”. To do.

The hypervisor 120 uniquely assigns the physical CPU 3 (101-3) to the logical CPU 5 (131-5) and uniquely assigns the physical CPU 4 (101-4) to the logical CPU 6 (131-6). assign. In the following description, an allocation mode in which one physical CPU 101 is uniquely assigned to one logical CPU 131 is referred to as an “occupancy mode”.

The hypervisor 120 also allocates a part of the memory area of the physical memory 102 as the memory area of the logical memory 132. Specifically, the hypervisor 120 manages the correspondence between the address space of the physical memory 102 and the address space of the logical memory 132. In the following description, the address space of the physical memory 102 is described as a hypervisor physical address space, and the address space of the logical memory 132 is described as a guest physical address space.

The guest OS 140 manages the logical memory 132 as a physical memory, and manages the correspondence between the address space and the virtual address space of the guest OS 140.

The hypervisor 120 according to the first embodiment includes a process scheduler 121, a memory write protection unit 122, and an instruction trap unit 123 in order to manage the configuration of the LPAR 130 and the computer resources allocated to the LPAR 130, and the LPAR configuration information 124, And monitor area management information 125 is held.

The process scheduler 121 manages the memory areas of the physical CPU 101 assigned to each logical CPU 131 of each LPAR 130 and the physical memory 102 assigned to each logical memory 132. The memory write protector 122 prohibits writing to a part of the memory area of the physical memory 102. The instruction trap unit 123 traps an instruction that matches a predetermined condition among the instructions issued from the guest OS 140.

The LPAR configuration information 124 is information for managing the configuration of the LPAR 130 and the computer resources allocated to the LPAR 130. The LPAR configuration information 124 includes CPU configuration information 126 and memory configuration information 127. Details of the CPU configuration information 126 and the memory configuration information 127 will be described later with reference to FIGS. 3A and 3B. The monitor area management information 125 is information for realizing the MONITOR / MWAIT system in the LPAR 130. Details of the monitor area management information 125 will be described later with reference to FIG.

Here, a method for realizing the MONITOR / MWAIT system in the logical CPU 131 of the LPAR 130 will be described.

When one physical CPU 101 is uniquely assigned to one logical CPU 131, that is, in the “occupied mode”, the LPAR 130 is set so that the physical CPU 101 can be used directly without going through the hypervisor 120. Thus, the MONITOR / MWAIT system in the logical CPU 131 can be realized.

On the other hand, in the “shared mode”, the hypervisor 120 realizes the setting of the monitor area of each logical CPU 131 in order to realize the MONITOR / MWAIT method in the logical CPU 131 of the LPAR 130, and (2) each monitor area. It is necessary to implement monitoring of the issuance of WRITE instructions for Therefore, the hypervisor 120 solves the above two problems (1) and (2) using the memory write protector 122.

Specifically, when the issuance of a MONITOR instruction instructing the setting of the monitor area of the logical CPU 131 from the guest OS 140 is detected, the memory write protection unit 122 writes to the memory area related to the designated monitor area. Ban. That is, the memory write protection unit 122 sets write protection for the memory area. Furthermore, the hypervisor 120 sets the logical CPU 131 to a dormant state and cancels the assignment of the physical CPU 101 to the logical CPU 131. In addition, the hypervisor 120 monitors the issuance of a WRITE instruction to a memory area for which write protection is set via the physical CPU 101.

When it is detected that a WRITE instruction is issued from the guest OS 140 to the memory area for which write protection has been set, the hypervisor 120 identifies the logical CPU 131 whose state is to be changed, and changes the identified logical CPU 131 from the sleep state to the execution state. Transition. Further, the hypervisor 120 assigns the physical CPU 101 to the logical CPU 131 according to the schedule. At this time, the memory write protection unit 122 cancels the write protection setting of the memory area where the WRITE instruction is issued.

By the control as described above, the MONITOR / MWAIT control in the logical CPU 131 can be realized. However, in order to realize the setting and monitoring of the monitor area using the memory write protector 122, there are the following problems. This problem will be described using the correspondence between the physical address space (guest physical address space 210) of the logical memory 132 managed by the LPAR 130 and the kernel virtual address space 220 managed by the guest OS 140.

FIG. 2 is an explanatory diagram illustrating a correspondence relationship between the guest physical address space 210 and the kernel virtual address space 220 according to the first embodiment.

The guest physical address space 210 is managed in units of pages, and the hypervisor 120 allocates a page of the guest physical address space 210 to a page of the kernel virtual address space 220 in response to a request from the guest OS 140.

As shown in FIG. 2, the size of the monitor area designated by the conventional OS (guest OS 140) for the MONITOR unit 111 is 64 bytes corresponding to the size of the cache line. On the other hand, the memory write protection unit 122 sets write protection for a memory area in units of pages (4 kilobytes).

Therefore, in order to realize the MONITOR / MWAIT method in the logical CPU 131 of the LPAR 130, the hypervisor 120 needs to monitor the issuance of a WRITE instruction for a memory area (page) larger than the monitor area specified by the guest OS 140.

When using the MONITOR instruction and the MWAIT instruction, software such as an OS needs to ensure that no data variable unrelated to the MONITOR / MWAIT system exists in the monitor area. For this reason, in this embodiment, the same condition must be satisfied for a memory area (page) larger than the monitor area that can be guaranteed by software.

However, the memory area excluding the monitor area among the pages for which writing is prohibited includes data variables not related to the MONITOR / MWAIT system. When the memory write protection function is used as it is, when the issuance (noise) of the WRITE instruction to the memory area other than the monitor area is detected among the memory areas (pages) described above, the hibernation state of the logical CPU 131 is released. .

(3) Write protection is set on a page basis. Therefore, one page is the minimum unit for setting write protection. The page size depends on the physical CPU 101, but generally the size of one page is 4 kilobytes. Therefore, the detection of noise as described above cannot be excluded. Therefore, the MONITOR / MWAIT method similar to that of the physical CPU 101 cannot be realized. Therefore, it is necessary to eliminate the detection of noise as described above.

(4) When the monitor areas of the plurality of logical CPUs 131 are registered in the same page, the hypervisor 120 can determine which logical CPU 131 for the same reason as described above even if the memory write protection function is used as it is. It cannot be determined whether to cancel the hibernation state.

The following two methods are conceivable as solutions for the above problems (3) and (4).

In the first method, the hypervisor 120 manages the guest physical address of the monitor area specified by the guest OS 140, and when the issuance of the WRITE instruction to the memory area including the monitor area is detected, the guest included in the WRITE instruction Based on the physical address, the monitor area set for which logical CPU 131 is specified. In the first method, the problems (3) and (4) can be solved.

In the second method, the hypervisor 120 previously sets the monitor area size (64 bytes) to the page size (4 kilobytes) for the guest OS 140. In the second method, since the size of the monitor area matches the size of the memory area where the write protection is set, the occurrence of the problems (3) and (4) can be suppressed. In the second method, it is necessary for the software operating on the guest OS 140 to ensure that there is no unrelated data variable in the monitor area of 4 kilobytes.

Example 1 describes the first method. The second method will be described in Example 2.

FIG. 3A is an explanatory diagram illustrating an example of the CPU configuration information 126 according to the first embodiment.

The CPU configuration information 126 stores information for managing the logical CPU 131 included in each LPAR 130. The CPU configuration information 126 has one entry for one LPAR 130, and each entry includes an LPAR number 301, a scheduling mode 302, a logical CPU number 303, a physical CPU number 304, and a state 305.

The LPAR number 301 stores the identification number of the LPAR 130. The scheduling mode 302 stores information related to the allocation mode of the physical CPU 101 in the logical CPU 131 included in the LPAR 130. Specifically, the scheduling mode 302 stores either “shared” indicating “shared mode” or “occupied” indicating “occupied mode”.

The logical CPU number 303 stores the identification number of the logical CPU 131 that the LPAR 130 has. The entry of one LPAR 130 includes the same number of rows as the number of logical CPUs 131 included in the LPAR 130.

The physical CPU number 304 stores information indicating the allocation state of the physical CPU 101 to the logical CPU 131. Specifically, when the physical CPU 101 is assigned to the logical CPU 131, the physical CPU number 304 stores the identification number of the assigned physical CPU 101. If the physical CPU 101 is not assigned to the logical CPU 131, “no assignment” is stored in the physical CPU number 304.

The state 305 stores information indicating the state of the logical CPU 131. Specifically, the state 305 stores any one of “pause”, “running”, and “waiting for allocation”. “Suspended” indicates that the logical CPU 131 is in a suspended state, and “in execution” indicates that the logical CPU 131 is in an executing state and the physical CPU 101 is assigned to the logical CPU 131. “Waiting for allocation” indicates a state in which the logical CPU 131 is in an execution state but the physical CPU 101 is not allocated to the logical CPU 131.

FIG. 3B is an explanatory diagram illustrating an example of the memory configuration information 127 according to the first embodiment.

The memory configuration information 127 stores information for managing the memory area of the physical memory 102 allocated to the logical memory 132 included in the LPAR 130. The memory configuration information 127 has one entry for one page of the physical memory 102, and each entry includes a hypervisor physical address 311, an allocation destination LPAR number 312, a guest physical address 313, and an attribute 314.

The hypervisor physical address 311 stores the start address of a page in the hypervisor physical address space. The allocation LPAR number 312 stores the identification number of the LPAR 130 to which the page of the physical memory 102 is allocated. The identification number of the logical CPU 131 stored in the allocation destination LPAR number 312 is the same as that stored in the LPAR number 301. The guest physical address 313 stores the start address of the page of the logical memory 132 to which the page of the physical memory 102 in the guest physical address space 210 is allocated.

The attribute 314 stores information indicating the page attribute of the physical memory 102. In this embodiment, the attribute 314 stores information indicating that the write protection is set by the memory write protection unit 122. Specifically, when “write protection” is stored in the attribute 314, it indicates that the write protection is set for the page. When the attribute 314 is blank, the page is protected for write protection. Indicates that it has not been set. The attribute 314 may store attribute information other than write protection.

FIG. 4 is an explanatory diagram illustrating an example of the monitor area management information 125 according to the first embodiment.

The monitor area management information 125 stores information for monitoring the monitor area designated for each logical CPU 131. The monitor area management information 125 includes one entry for one logical CPU 131 for which a monitor area is set, and each entry includes a logical CPU number 401 and a monitor area address 402.

The logical CPU number 401 stores the identification number of the logical CPU 131 in which the monitor area is set. The identification number of the logical CPU 131 stored in the logical CPU number 401 is the same as that stored in the LPAR number 301.

The monitor area address 402 stores the address of the monitor area of the logical CPU 131 in the address space managed by the guest OS 140. The monitor area address 402 includes a virtual address 403 and a guest physical address 404.

The virtual address 403 stores a virtual address in the kernel virtual address space 220 of the monitor area specified by the guest OS 140. The guest physical address 404 stores a guest physical address in the guest physical address space 210 of the monitor area. In the first embodiment, the size of the monitor area is the same as the size of the conventional monitor area. That is, the size of the monitor area is 64 bytes.

The monitor area management information 125 manages information related to the monitor area of the logical CPU 131 in the “shared mode”. On the other hand, the monitor area of the logical CPU 131 in the “occupied mode” is not managed using the monitor area management information 125. This is because the logical CPU 131 and the physical CPU 101 in the “occupied mode” are associated one-to-one and the physical CPU 101 can be used as it is.

FIG. 5 is a sequence diagram illustrating the flow of instruction emulation processing in the MONITOR / MWAIT system of the shared mode logical CPU 131 according to the first embodiment.

In the following description, the LPAR1 (130-1) having the logical CPU1 (131-1) and the logical CPU2 (131-2) in the shared mode will be described as an example. It is assumed that the physical CPU 1 (101-1) is assigned to the logical CPU 1 (131-1), and the physical CPU 2 (101-2) is assigned to the logical CPU 2 (131-2).

In this case, “pCPU1” is stored in the physical CPU number 304 of the row corresponding to the logical CPU1 (131-1) in the CPU configuration information 126, and “running” is stored in the state 305. In addition, “pCPU2” is stored in the physical CPU number 304 of the row corresponding to the logical CPU2 (131-2), and “running” is stored in the state 305.

Guest OS1 (140-1) issues a MONITOR instruction to logical CPU1 (131-1) (step S501).

When the physical CPU 1 (101-1) assigned to the logical CPU 1 (131-1) detects the issuance of the MONITOR instruction, it shifts from the processing mode of the guest OS 140 to the processing mode of the hypervisor 120 using the virtualization support function. Let As virtualization support functions, “Intel VT-x” and “AMD-V” are known.

The hypervisor 120 refers to the CPU configuration information 126 and determines whether or not the logical CPU 1 (131-1) that sets the monitor area is in the “shared mode”. Since the logical CPU 1 (131-1) is in the “shared mode”, the instruction trap unit 123 of the hypervisor 120 traps the instruction (step S502) and executes the monitor area registration process (step S503).

Thereby, write protection is set to the page including the monitor area designated by the guest OS1 (140-1). Details of the monitor area registration processing will be described later with reference to FIG. Note that the physical CPU 1 (101-1) shifts the processing mode of the hypervisor 120 to the processing mode of the guest OS 140 using the virtualization support function after the monitor area registration processing is completed.

The guest OS1 (140-1) issues an MWAIT command for the logical CPU1 (131-1) (step S504).

At this time, when the physical CPU 1 (101-1) assigned to the logical CPU 1 (131-1) detects the issuance of the MWAIT instruction, the processing of the hypervisor 120 from the processing mode of the guest OS 140 is performed using the virtualization support function. Switch to mode.

The hypervisor 120 refers to the CPU configuration information 126 and determines whether or not the logical CPU 1 (131-1) that sets the monitor area is in the “shared mode”. Since the logical CPU 1 (131-1) is in the “shared mode”, the instruction trap unit 123 of the hypervisor 120 traps the instruction (step S505) and executes a dormant state transition process (step S506).

As a result, the logical CPU 1 (131-1) transitions from the execution state to the dormant state, and the assignment of the physical CPU 1 (101-1) to the logical CPU 1 (131-1) is released. Details of the dormant state transition process will be described later with reference to FIG. The physical CPU 1 (101-1) shifts from the processing mode of the hypervisor 120 to the processing mode of the guest OS 140 using the virtualization support function after the hibernation state transition processing is completed.

The guest OS1 (140-1) issues a WRITE command to the monitor area of the logical CPU1 (131-1) using the logical CPU2 (131-2) (step S507).

The physical CPU 2 (101-2) assigned to the logical CPU 2 (131-2) receives the WRITE command. When the physical CPU 2 (101-2) detects an exception process due to the issuance of the WRITE instruction to the memory area where the write protection is set including the monitor area, the process of the guest OS 140 is performed using the virtualization support function. The mode is changed to the processing mode of the hypervisor 120.

The instruction trap unit 123 of the hypervisor 120 traps the WRITE instruction to the monitor area (step S508) and executes the execution state transition process (step S509).

As a result, the logical CPU 1 (131-1) transitions from the sleep state to the execution state. Details of the execution state transition process will be described later with reference to FIG. The physical CPU 2 (101-2) shifts from the processing mode of the hypervisor 120 to the processing mode of the guest OS 140 using the virtualization support function after the execution state transition processing is completed.

Thereafter, the process scheduler 121 of the hypervisor 120 assigns the physical CPU 1 (101-1) to the logical CPU 1 (131-1) according to the schedule (step S510), and further updates the CPU configuration information 126 (step S511).

There is a possibility that the physical CPU 1 (101-1) has already been assigned to the logical CPU 3 (131-3) or the like. In this case, the hypervisor 120 compares the priorities of the logical CPU 1 (131-1) and the logical CPU 3 (131-3).

When the priority of the logical CPU 1 (131-1) is higher than the priority of the logical CPU 3 (131-3), the hypervisor 120 forcibly assigns the physical CPU 1 (101-1) to the logical CPU 3 (131-3). The physical CPU 1 (101-1) is assigned to the logical CPU 1 (131-1). When the priority of the logical CPU 1 (131-1) is lower than the priority of the logical CPU 3 (131-3), the hypervisor 120 deallocates the physical CPU 1 (101-1) to the logical CPU 3 (131-3). Wait for

Next, details of processing executed by the hypervisor 120 will be described with reference to FIGS.

FIG. 6 is a flowchart for explaining an example of the monitor area registration process executed by the hypervisor 120 according to the first embodiment.

Here, it is assumed that the MONITOR instruction includes “Ad_mon10” as a virtual address of the monitor area. The guest physical address corresponding to the virtual address “Ad_mon10” is assumed to be “L1_Ad_mon10”.

The hypervisor 120 refers to the CPU configuration information 126 based on the identification number of the logical CPU 131, and determines whether or not the allocation mode of the logical CPU 131 is “shared mode” (step S601). Specifically, the following processing is executed.

The hypervisor 120 searches for a line in which the logical CPU number 303 matches the identification number of the logical CPU 131 that is the target of the MONITOR instruction. The hypervisor 120 determines whether or not the scheduling mode 302 of the retrieved row is “shared”. When the scheduling mode 302 of the retrieved row is “shared”, the hypervisor 120 determines that the allocation mode of the logical CPU 131 is “shared mode”.

When it is determined that the allocation mode of the logical CPU 131 is not “shared mode”, the hypervisor 120 shifts from the processing mode of the hypervisor 120 to the processing mode of the guest OS 140 using the virtualization support function, and ends the processing. In this case, since the allocation mode of the logical CPU 131 is “occupied mode”, the MONITOR instruction is directly executed on the physical CPU 101. That is, emulation by the hypervisor 120 is not performed.

When it is determined that the allocation mode of the logical CPU 131 is the “shared mode”, the hypervisor 120 refers to the monitor area management information 125 (step S602), and the monitor area specified by the MONITOR instruction is specified in the monitor area management information 125. It is determined whether it is registered (step S603).

Specifically, the hypervisor 120 searches for an entry in which the logical CPU number 401 matches the identification number of the logical CPU 131 that is the target of the MONITOR instruction. If the entry does not exist, the hypervisor 120 determines that the monitor area specified by the MONITOR instruction is not registered in the monitor area management information 125.

When it is determined that the monitor area specified by the MONITOR instruction is not registered in the monitor area management information 125, the hypervisor 120 registers the monitor area in the monitor area management information 125 (step S606). Thereafter, the hypervisor 120 proceeds to step S607.

Specifically, the hypervisor 120 adds a new entry to the monitor area management information 125 and sets the identification number of the logical CPU 131 that is the target of the MONITOR instruction in the logical CPU number 401. Further, the hypervisor 120 sets the virtual address of the monitor area in the virtual address 403 of the added entry, and sets the guest physical address of the monitor area in the guest physical address 404. For example, “Ad_mon10” is set in the virtual address 403, and “L1_Ad_mon10” is set in the guest physical address 404.

When it is determined that the monitor area specified by the MONITOR instruction is registered in the monitor area management information 125, the hypervisor 120 determines whether or not the registered monitor area matches the monitor area specified by the MONITOR instruction. Is determined (step S604).

Specifically, the hypervisor 120 determines whether or not the virtual address 403 of the entry searched in step S603 matches the virtual address included in the MONITOR instruction. For example, the hypervisor 120 searches for an entry in which “Ad_mon10” is stored in the virtual address 403.

When it is determined that the registered monitor area matches the monitor area specified by the MONITOR instruction, the hypervisor 120 ends the process.

If it is determined that the registered monitor area does not match the monitor area specified by the MONITOR instruction, the hypervisor 120 cancels the write protection setting of the memory area including the registered monitor area (step S605). ). Specifically, the following processing is executed.

The hypervisor 120 refers to the memory configuration information 127 and searches for an entry in which the guest physical address 313 matches the guest physical address 404 of the entry searched in step S603. For example, the hypervisor 120 searches for an entry whose guest physical address 313 is “L1_Ad_mon10”.

The memory write protection unit 122 of the hypervisor 120 cancels the write protection setting of the memory area including the monitor area based on the address set as the hypervisor physical address 311 of the retrieved entry. Further, the hypervisor 120 rewrites the attribute 314 of the searched entry to a blank.

The hypervisor 120 registers the monitor area in the monitor area management information 125 (step S606).

Specifically, the hypervisor 120 changes the values of the virtual address 403 and guest physical address 404 of the entry searched in step S603 to the virtual address and guest physical address of the monitor area included in the MONITOR instruction. For example, the virtual address 403 is changed to “Ad_mon10”, and the guest physical address 404 is changed to “L1_Ad_mon10”.

The memory write protection unit 122 of the hypervisor 120 sets write protection for the page including the monitor area (step S607). Also, the memory configuration information 127 is updated (step S608). Thereafter, the hypervisor 120 ends the process.

Specifically, the hypervisor 120 refers to the memory configuration information 127 and searches for an entry that matches the guest physical address 404 of the entry corresponding to the monitor area in which the guest physical address 313 is registered. The hypervisor 120 sets “write protection” to the attribute 314 of the retrieved entry.

FIG. 7 is a flowchart for explaining hibernation state transition processing executed by the hypervisor 120 according to the first embodiment.

The hypervisor 120 refers to the CPU configuration information 126 based on the identification number of the logical CPU 131 included in the MWAIT instruction, and determines whether or not the allocation mode of the logical CPU 131 is “shared mode” (step S701). The process in step S701 is the same as the process in step S601.

When it is determined that the allocation mode of the logical CPU 131 is not “shared mode”, the hypervisor 120 shifts from the processing mode of the hypervisor 120 to the processing mode of the guest OS 140 using the virtualization support function, and ends the processing. In this case, since the allocation mode of the logical CPU 131 is “occupied mode”, the MWAIT instruction is directly executed to the physical CPU 101. That is, emulation by the hypervisor 120 is not performed.

When it is determined that the allocation mode of the logical CPU 131 is the “shared mode”, the hypervisor 120 updates the CPU configuration information 126 (step S702).

Specifically, the hypervisor 120 sets “pause” in the state 305 of the row of the logical CPU 131 searched in step S701.

The hypervisor 120 changes the state of the logical CPU 131 that is the target of the MWAIT instruction to the sleep state (step S703), and releases the physical CPU 101 assigned to the logical CPU 131 (step S704). Further, the hypervisor 120 updates the CPU configuration information 126 (step S705), and thereafter ends the process.

Specifically, the hypervisor 120 sets “not assigned” to the physical CPU number 304 in the row of the logical CPU 131 searched in step S701.

FIG. 8 is a flowchart for explaining execution state transition processing executed by the hypervisor 120 according to the first embodiment.

When the physical CPU 101 detects an exception process by the WRITE instruction for the memory area where the write protection is set, the physical CPU 101 shifts from the processing mode of the guest OS 140 to the processing mode of the hypervisor 120 using the virtualization support function.

Note that since write protection is set in the memory area only when the logical CPU 131 is in the “shared mode”, no exception processing occurs when the logical CPU 131 is in the “occupied mode”, and thus the emulation by the hypervisor 120 is not performed. .

The hypervisor 120 detects that it is a WRITE command for the memory area where the write protection is set by the transition of the processing mode described above (step S801).

The hypervisor 120 determines based on the monitor area management information 125 whether or not the WRITE instruction for the memory area for which write protection is set is a WRITE instruction for the monitor area (step S802). Specifically, the following processing is executed.

The hypervisor 120 searches for an entry in which the virtual address 403 matches the virtual address included in the WRITE instruction. If there is an entry in which the virtual address 403 matches the virtual address included in the WRITE instruction, the hypervisor 120 determines that the WRITE instruction for the memory area for which write protection is set is a WRITE instruction for the monitor area.

If it is determined that the WRITE instruction for the memory area for which write protection is set is a WRITE instruction for the monitor area, the hypervisor 120 identifies the logical CPU 131 that is the target of the WRITE instruction, and the state of the identified logical CPU 131 Is transitioned from the sleep state to the execution state (step S803).

The hypervisor 120 cancels the write protection setting set for the page including the monitor area (step S804). Specifically, the following processing is executed.

The hypervisor 120 identifies the logical CPU 131 that is the target of the WRITE instruction based on the logical CPU number 401 of the entry searched in step S802. The hypervisor 120 refers to the CPU configuration information 126 and searches for a line in which the logical CPU number 303 matches the logical CPU number 401 of the searched entry. The hypervisor 120 identifies the LPAR 130 having the logical CPU 131 that is the target of the WRITE instruction from the LPAR number 301 of the entry including the retrieved line.

The hypervisor 120 refers to the memory configuration information 127 and searches for an entry whose allocation destination LPAR number 312 matches the identification number of the specified LPAR 130. Further, the hypervisor 120 refers to the guest physical address 313 of the searched entry, and specifies a memory area including the guest physical address 404 of the entry searched in step S802. The memory write protection unit 122 of the hypervisor 120 cancels the write protection setting of the memory area.

The hypervisor 120 updates the CPU configuration information 126 and the memory configuration information 127 (step S805), and thereafter ends the processing. Specifically, the following processing is executed.

The hypervisor 120 refers to the CPU configuration information 126 and changes the state 305 of the line where the logical CPU number 303 matches the logical CPU number 401 of the retrieved entry to “waiting for allocation”. The hypervisor 120 refers to the memory configuration information 127 and changes the row attribute 314 corresponding to the memory area specified in step S804 to a blank.

If it is determined that the WRITE command for the memory area for which write protection is set is not a WRITE command for the monitor area, proxy WRITE processing is executed for the memory area for which write protection is set (step S806).

That is, the hypervisor 120 writes data in a memory area where write protection is set instead of the guest OS 140.

Example 2 will be described with a focus on differences from Example 1.

Since the configurations of the physical computer 100, the hypervisor 120, and the LPAR 130 of the second embodiment are the same as those of the first embodiment, description thereof is omitted. However, in the second embodiment, the hypervisor 120 has an interface that notifies the guest OS 140 of the size of the monitor area.

When the guest OS 140 is operated on the LPAR 130, the hypervisor 120 notifies the guest OS 140 that the size of the monitor area is “4 kilobytes” in advance via the interface. As a result, the size of the memory area where the memory write protection unit 122 sets the write protection matches the size of the monitor area. Therefore, in the second embodiment, noise as in the first embodiment does not occur.

Since the flow of emulation processing of the MONITOR / MWAIT instruction in the logical CPU 131 in the shared mode of the second embodiment is the same as that of the first embodiment, the description thereof is omitted. Further, the monitor area registration process and the dormant state transition process of the second embodiment are the same as those of the first embodiment, and thus the description thereof is omitted.

In the second embodiment, a part of the execution state transition process is different from the execution state transition process of the first embodiment. FIG. 9 is a flowchart for explaining execution state transition processing executed by the hypervisor 120 according to the second embodiment.

The hypervisor 120 detects that it is a WRITE command for the memory area where the write protection is set, that is, the monitor area, by the transition of the processing mode described above (step S901).

The hypervisor 120 identifies the logical CPU 131 that is the target of the WRITE instruction based on the monitor area management information 125, and changes the state of the identified logical CPU 131 from the sleep state to the execution state (step S902). The process in step S902 is the same as the process in step S803.

The hypervisor 120 cancels the write protection setting set in the monitor area (step S903). Specifically, the following processing is executed.

The hypervisor 120 identifies the logical CPU 131 that is the target of the WRITE instruction based on the logical CPU number 401 of the entry searched in step S902. The hypervisor 120 refers to the CPU configuration information 126 and searches for a line in which the logical CPU number 303 matches the logical CPU number 401. The hypervisor 120 identifies the LPAR 130 including the logical CPU 131 that is the target of the WRITE instruction from the LPAR number 301 of the entry including the retrieved line.

The hypervisor 120 refers to the memory configuration information 127 and searches for an entry whose allocation destination LPAR number 312 matches the identification number of the specified LPAR 130. Further, the hypervisor 120 refers to the guest physical address 313 of the searched entry, and specifies a memory area corresponding to the guest physical address 404 of the entry searched in step S802. The memory write protection unit 122 of the hypervisor 120 cancels the write protection setting of the memory area.

The hypervisor 120 updates the CPU configuration information 126 and the memory configuration information 127 (step S904), and then ends the processing. The process in step S904 is the same as the process in step S806.

In the second embodiment, since the size of the memory area in which the write protection is set matches the size of the monitor area, the processes in steps S802 and S806 are not necessary.

As described in the first and second embodiments, the hypervisor 120 uses the memory write protector 122 and the monitor area management information 125 to monitor the MONITOR instruction, the MWAIT instruction, and the monitor for each logical CPU 131 in the shared mode. A WRITE instruction to the area can be emulated. Further, when emulating a WRITE instruction to the monitor area, the hypervisor 120 performs control so as to hide the difference between the size of the memory area to which the write protection is set and the size of the monitor area.

Therefore, the MONITOR / MWAIT system control similar to that of the physical CPU 101 can also be realized in the logical CPU 131. Even if the physical CPU 101 does not support the MONITOR / MWAIT system, the MONITOR / MWAIT system can be controlled on the LPAR 130. Further, by releasing the assignment of the physical CPU 101 to the logical CPU 131 that has transitioned to the hibernation state, it can be assigned to another logical CPU 131. Therefore, computer resources can be used effectively.

In addition, this invention is not limited to the above-mentioned Example, Various modifications are included. Further, for example, the above-described embodiments are described in detail for easy understanding of the present invention, and are not necessarily limited to those provided with all the described configurations. Further, a part of the configuration of each embodiment can be added to, deleted from, or replaced with another configuration.

In addition, each of the above-described configurations, functions, processing units, processing means, and the like may be realized by hardware by designing a part or all of them with, for example, an integrated circuit. The present invention can also be realized by software program codes that implement the functions of the embodiments. In this case, a storage medium in which the program code is recorded is provided to the computer, and a CPU included in the computer reads the program code stored in the storage medium. In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiments, and the program code itself and the storage medium storing it constitute the present invention. Examples of storage media for supplying such program codes include flexible disks, CD-ROMs, DVD-ROMs, hard disks, SSDs (Solid State Drives), optical disks, magneto-optical disks, CD-Rs, magnetic tapes, A non-volatile memory card, ROM, or the like is used.

Further, the program code for realizing the functions described in this embodiment can be implemented by a wide range of programs or script languages such as assembler, C / C ++, Perl, Shell, PHP, Java, and the like.

Furthermore, by distributing the program code of the software that realizes the functions of the embodiments via a network, the program code is stored in a storage means such as a hard disk or memory of a computer or a storage medium such as a CD-RW or CD-R. The CPU included in the computer may read and execute the program code stored in the storage unit or the storage medium.

In the above-described embodiments, the control lines and information lines indicate those that are considered necessary for the explanation, and do not necessarily indicate all the control lines and information lines on the product. All the components may be connected to each other.

Claims

As a computer resource, a computer comprising a plurality of physical processors and a physical memory connected to each of the plurality of physical processors,
The physical memory stores a program for realizing a virtualization unit that allocates the computer resources logically divided into a plurality of logical partitions,
In each of the plurality of logical partitions, an operating system for managing a plurality of logical processors and a logical memory operates,
The virtualization unit manages allocation of the plurality of physical processors so that the plurality of logical processors included in each of the plurality of logical partitions share the same plurality of physical processors;
The plurality of physical processors includes a first physical processor and a second physical processor,
The operating system is
A MONITOR instruction that designates a monitor area that is a memory area to be monitored in order to transition the processor managed by the operating system from the sleep state to the execution state;
Issuing a MWAIT instruction for transitioning a processor managed by the operating system from an execution state to a dormant state;
The plurality of logical partitions includes a first logical partition having a first logical processor, a second logical processor, and a first logical memory, and running a first operating system;
The virtualization unit
Holding monitor area management information for managing the association of the address of the monitor area in the address space managed by the operating system, and the identifier of the logical processor that is the target of the MONITOR instruction;
When a MONITOR instruction for the first logical processor is detected from the first operating system by the first physical processor assigned to the first logical processor, an identifier of the first logical processor; and Registering, in the monitor area management information, information associated with the address of the monitor area of the first logical processor in the address space managed by the first operating system;
When the MWAIT instruction for the first logical processor is detected from the first operating system by the first physical processor assigned to the first logical processor, the first logical processor is changed from the execution state to the sleep state. To deallocate the first physical processor to the first logical processor,
When a WRITE instruction for the monitor area of the first logical processor is detected from the first operating system by the second physical processor allocated to the second logical processor, the monitor area management information is referred to. A computer that identifies a WRITE instruction for the monitor area of the first logical processor and causes the first logical processor to transition from a sleep state to an execution state.
The computer according to claim 1,
The virtualization unit includes a memory write protection unit that sets a write protection that prohibits writing to the memory area of the physical memory related to the monitor area when the issuance of the MONITOR instruction is detected;
The second physical processor assigned to the second logical processor calls the virtualization unit by detecting exception processing of a WRITE instruction for the memory area of the physical memory to which the write protection is set. Calculator.
The computer according to claim 2,
The size of the monitor area is smaller than the size of the memory area where the memory write protection unit sets write protection,
The virtualization unit
When called by the second processor assigned to the second logical processor, referring to the monitor area management information, the address of the memory area targeted by the WRITE instruction matches the address of the monitor area. Determine whether or not
When it is determined that the address of the memory area subject to the WRITE instruction matches the address of the monitor area, it is detected that the address is a WRITE instruction for the monitor area of the first logical processor. calculator.
The computer according to claim 3, wherein
When the virtualization unit determines that the address of the memory area targeted by the WRITE instruction does not match the address of the monitor area, the virtualization unit includes the memory area of the physical memory in which the write protection is set. A computer which writes data into a memory area designated by a WRITE instruction.
The computer according to claim 2,
The size of the monitor area is smaller than the size of the memory area where the memory write protection unit sets write protection,
When the virtualization unit operates the operating system on the logical partition, the size of the monitor area is set in the operating system, and the size of the memory area in which the memory write protection unit sets write protection. A computer characterized by having an interface for notifying.
A method of controlling a logical processor in a logical partition on a computer,
The computer has, as computer resources, a plurality of physical processors and a physical memory connected to each of the plurality of physical processors,
The physical memory stores a program for realizing a virtualization unit that allocates the computer resources logically divided into a plurality of logical partitions,
In each of the plurality of logical partitions, an operating system for managing a plurality of logical processors and a logical memory operates,
The virtualization unit manages allocation of the plurality of physical processors so that the plurality of logical processors included in each of the plurality of logical partitions share the same plurality of physical processors;
The plurality of physical processors includes a first physical processor and a second physical processor,
The operating system is
A MONITOR instruction that designates a monitor area that is a memory area to be monitored in order to transition the processor managed by the operating system from the sleep state to the execution state;
Issuing a MWAIT instruction for transitioning a processor managed by the operating system from an execution state to a dormant state;
The plurality of logical partitions includes a first logical partition having a first logical processor, a second logical processor, and a first logical memory, and running a first operating system;
The virtualization unit holds monitor area management information for managing an association between an identifier of a logical processor that is a target of the MONITOR instruction and an address of the monitor area in an address space managed by the operating system,
The logical processor control method includes:
When the virtualization unit detects a MONITOR instruction for the first logical processor from the first operating system by the first physical processor assigned to the first logical processor, the first logical processor A first step of registering, in the monitor area management information, information associating a processor identifier and an address of the monitor area of the first logical processor in an address space managed by the first operating system;
When the virtualization unit detects an MWAIT instruction for the first logical processor from the first operating system by a first physical processor assigned to the first logical processor, the first logical processor Transition from an execution state to a dormant state, and deallocating the first physical processor to the first logical processor;
When the virtualization unit detects a WRITE instruction for the monitor area of the first logical processor from the first operating system by the second physical processor allocated to the second logical processor, the monitor A third step of referring to the area management information to identify a WRITE instruction for the monitor area of the first logical processor and causing the first logical processor to transition from a sleep state to an execution state. A control method for a logical processor.
A method of controlling a logical processor according to claim 6,
The virtualization unit includes a memory write protection unit that sets a write protection that prohibits writing to the memory area of the physical memory related to the monitor area when the issuance of the MONITOR instruction is detected;
In the third step, the second physical processor assigned to the second logical processor detects the exception processing of the WRITE instruction for the memory area of the physical memory in which the write protection is set, thereby causing the virtual process. A control method for a logical processor, comprising a step of calling an allocating unit.
A method of controlling a logical processor according to claim 7,
The size of the monitor area is smaller than the size of the memory area where the memory write protection unit sets write protection,
The third step includes
When the virtualization unit is called by the second processor allocated to the second logical processor, the virtualization unit refers to the monitor area management information and stores the memory area that is the target of the WRITE instruction. Determining whether the address matches the address of the monitor area;
When it is determined that the address of the memory area targeted by the WRITE instruction matches the address of the monitor area, the virtualization unit detects that the address is a WRITE instruction for the monitor area of the first logical processor. And a logical processor control method.
A method of controlling a logical processor according to claim 8,
In the third step, when it is determined that the address of the memory area targeted by the WRITE instruction does not match the address of the monitor area, the virtualization unit sets the physical memory in which the write protection is set. A method for controlling a logical processor, wherein data is written into a memory area specified by the WRITE instruction in the memory area.
A method of controlling a logical processor according to claim 7,
The size of the monitor area is smaller than the size of the memory area where the memory write protection unit sets write protection,
When the virtualization unit operates the operating system on the logical partition, the size of the monitor area is set in the operating system, and the size of the memory area in which the memory write protection unit sets write protection. A control method for a logical processor, characterized by comprising an interface for notifying.