WO2016086446A1 - 一种发光二极管以及发光二极管的制造方法 - Google Patents

一种发光二极管以及发光二极管的制造方法 Download PDF

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Publication number
WO2016086446A1
WO2016086446A1 PCT/CN2014/093702 CN2014093702W WO2016086446A1 WO 2016086446 A1 WO2016086446 A1 WO 2016086446A1 CN 2014093702 W CN2014093702 W CN 2014093702W WO 2016086446 A1 WO2016086446 A1 WO 2016086446A1
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Prior art keywords
light emitting
electrode pad
circuit layer
layer
emitting chip
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English (en)
French (fr)
Inventor
周革革
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/426,455 priority Critical patent/US9780272B2/en
Publication of WO2016086446A1 publication Critical patent/WO2016086446A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/851—Wavelength conversion means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/036—Manufacture or treatment of packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/036—Manufacture or treatment of packages
    • H10H20/0362—Manufacture or treatment of packages of encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/036—Manufacture or treatment of packages
    • H10H20/0364—Manufacture or treatment of packages of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/8506—Containers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/851—Wavelength conversion means
    • H10H20/8511—Wavelength conversion means characterised by their material, e.g. binder
    • H10H20/8512—Wavelength conversion materials
    • H—ELECTRICITY
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    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/851—Wavelength conversion means
    • H10H20/8514—Wavelength conversion means characterised by their shape, e.g. plate or foil
    • H—ELECTRICITY
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    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/852—Encapsulations
    • H10H20/853—Encapsulations characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/852—Encapsulations
    • H10H20/854—Encapsulations characterised by their material, e.g. epoxy or silicone resins
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H10W72/07554—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5524—Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5525—Materials of bond wires comprising metals or metalloids, e.g. silver comprising copper [Cu]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings

Definitions

  • the present invention claims the priority of the prior application entitled “A Light Emitting Diode and a Method of Making a Light Emitting Diode”, filed on December 2, 2014, the disclosure of which is incorporated herein by reference. This.
  • the present invention relates to the field of light sources, and more particularly to a light emitting diode and a method of manufacturing the same.
  • LEDs Light Emitting Diodes
  • traditional light sources such as incandescent lamps and fluorescent lamps
  • LEDs Light Emitting Diodes
  • red and green phosphors may be coated in the encapsulation layer of the diode (for example, an epoxy layer), and the red color in the encapsulation layer is emitted when the blue chip in the LED emits blue light.
  • the green phosphor will produce red and green light, respectively, under the stimulation of blue light.
  • the resulting red and green light is mixed with the blue light that passes through the encapsulation layer to produce white light.
  • the shape of the encapsulation layer may be irregular, for example, some places are thicker and some are thinner, the optical path length of the light transmitted through the encapsulation layer is different, resulting in uneven white light emitted.
  • the technical problem to be solved by the embodiments of the present invention is to provide a method for manufacturing a light emitting diode and a light emitting diode, which realizes forming a uniform encapsulation layer such that the optical path length of the light transmitted through the encapsulation layer is uniform, thereby causing the emitted white light. Evenly.
  • a first aspect of the present invention provides a light emitting diode comprising: a bottom layer; a circuit layer formed on the bottom layer; a light emitting chip formed on the circuit layer; and an electrode pad formed on the bottom layer Electrically connecting with the light emitting chip, the electrode pad and the circuit layer and the light emitting chip have a predetermined first interval, such that the electrode pad and the circuit layer and the light emitting chip Room Forming a first trench, and a level of the electrode pad is equal to a level of the light emitting chip; an encapsulation layer containing a phosphor formed on the light emitting chip and the electrode pad, and filling the a first trench between the electrode pad and the circuit layer to form a uniform dome shape.
  • the height of the electrode pad is equal to the sum of the height of the circuit layer and the height of the light emitting chip.
  • the bottom layer is recessed inward to form a receiving groove
  • the circuit layer is disposed on the sidewall and the bottom of the receiving groove.
  • a predetermined second interval is formed between the circuit layer and the light emitting chip, so that a second trench is formed between the circuit layer and the light emitting chip.
  • the bottom layer comprises a conductive substrate and an insulating layer formed over the conductive substrate.
  • the conductive substrate is any one of aluminum, aluminum alloy, magnesium, magnesium alloy, titanium, and titanium alloy.
  • the thickness of the electrically conductive substrate is set to 0.1 mm.
  • the material of the encapsulation layer is silicone or epoxy resin.
  • the electrode pad and the circuit layer are made of gold or aluminum or copper.
  • a second aspect of the present invention provides a method of fabricating a light emitting diode, comprising: providing a bottom layer; forming a circuit layer and an electrode pad on the underlayer using a plating method; mounting a light emitting chip on the circuit layer, and causing The horizontal height of the electrode pad is equal to the horizontal height of the light emitting chip, wherein a first interval is preset between the electrode pad and the circuit layer and the light emitting chip, such that the electrode pad and the circuit layer Forming a first trench with the light emitting chip; filling a packaging material containing phosphor on the first trench between the light emitting chip, the electrode pad, and the electrode pad and the circuit layer, To form a uniform dome-shaped encapsulation layer.
  • the height of the electrode pad is equal to the sum of the height of the circuit layer and the height of the light emitting chip.
  • the step of providing the bottom layer is specifically: providing an underlayer that forms an accommodating groove inwardly recessed; forming a circuit layer on the bottom layer by using a plating method, specifically: using a plating method in the accommodating groove of the bottom layer
  • a plating method specifically: using a plating method in the accommodating groove of the bottom layer
  • a predetermined second interval is formed between the circuit layer and the light emitting chip, so that a second trench is formed between the circuit layer and the light emitting chip.
  • the step of providing a bottom layer is specifically: providing a conductive substrate; forming an insulating layer on the conductive substrate.
  • the conductive substrate is any one of aluminum, aluminum alloy, magnesium, magnesium alloy, titanium, and titanium alloy.
  • the thickness of the electrically conductive substrate is set to 0.1 mm.
  • the material of the encapsulation layer is silicone or epoxy resin.
  • the electrode pad and the circuit layer are made of gold or aluminum or copper.
  • the forming a circuit layer and the electrode pad on the underlayer by using a plating method is specifically: plating a conductor on the bottom layer by using a plating method; etching the conductor to the bottom layer A circuit layer and an electrode pad are formed on top.
  • the height of the plated conductor is between 35 and 300 microns.
  • a first trench is formed between the electrode pad and the circuit layer, and the spreadability of the encapsulation layer is reduced due to the presence of the first trench, so that the encapsulation layer has a uniform dome shape, so that the encapsulation layer is uniformly
  • the optical path length of the light passing through the encapsulation layer is uniform, thereby making the emitted white light uniform.
  • FIG. 1 is a schematic structural view of an embodiment of a light emitting diode of the present invention
  • FIG. 2 is a schematic structural view of another embodiment of a light emitting diode of the present invention.
  • FIG. 3 is a schematic structural view of an embodiment of a bottom layer of a light emitting diode of the present invention.
  • FIG. 4 is a flow chart showing an embodiment of a method of manufacturing a light emitting diode of the present invention
  • Fig. 5 is a flow chart showing another embodiment of a method of manufacturing a light emitting diode of the present invention.
  • FIG. 1 is a schematic structural view of an embodiment of a light emitting diode of the present invention.
  • the light emitting diode of the present embodiment includes a bottom layer 110, a circuit layer 120, a light emitting chip 130, an electrode pad 140, a conductive line 150, and an encapsulation layer 160.
  • the bottom layer 110 includes a conductive substrate 111 and an insulating layer 112.
  • the circuit layer 120 is disposed over the insulating layer 112, and the light emitting chip 130 is formed over the circuit layer 120.
  • the electrode pad 140 is also disposed on the insulating layer 112, and the electrode pad 140 has a predetermined first interval between the circuit layer 120 and the light emitting chip 130, so that the electrode pad 140 is formed between the circuit layer 120 and the light emitting chip 130.
  • the level of the electrode pad 140 is equal to the level of the light-emitting chip 130.
  • the height of the electrode pad 140 is equal to the sum of the height of the circuit layer 120 and the height of the light emitting chip 130.
  • the conductive line 150 electrically connects the electrode pad 140 and the light emitting chip 130.
  • the encapsulating layer 160 is mixed with a phosphor, and the encapsulation layer 160 is formed on the light emitting chip 130 and the electrode pad 140, and fills the first trench 151 between the electrode pad 140 and the circuit layer 120 to form a uniform dome shape. .
  • the conductive substrate 111 is a metal substrate and may be aluminum (Al), aluminum alloy (Al alloy), magnesium (Mg), magnesium alloy (Mg alloy), titanium (Ti), titanium alloy (Ti alloy), or the like.
  • the size and shape of the conductive substrate 111 are not limited and can be set according to the processing ability and actual needs.
  • the thickness of the conductive substrate 111 can be set to 0.1 mm in consideration of the process of processing, the reliability of the product, and the lightness and thinness of the product.
  • the insulating layer 112 may be formed on the conductive substrate 111 by an anodizing method, a plasma electrolytic oxidation (PEO) method, a dry oxidation method, a bonding process, or the like.
  • the insulating layer 112 is disposed on one side of the conductive substrate 111 adjacent to the circuit layer 120 and the electrode pad 140, and may be disposed on the entire surface of the conductive substrate 111.
  • the conductor is plated on the insulating layer 112 until the thickness of the light-emitting chip 130 can be sufficiently masked.
  • the conductor is then etched to form the circuit layer 120 and the electrode pads 140. Therefore, here, the height of the plated conductor may vary with the thickness of the light emitting chip 130, for example, the height of the plated conductor may be between 35 and 300 microns.
  • the covered conductor may be gold (Au), aluminum (Al) or copper (Cu) or the like.
  • the conductive wire 150 is a conductive wire, for example, a gold (Au) wire, an aluminum (Al) wire, or a copper (Cu) wire, or the like.
  • the encapsulation layer 160 is formed by solidification of a transparent resin material containing a phosphor.
  • the transparent resin material may be silicone resin or epoxy resin or the like.
  • the transparent resin material containing the phosphor is injected onto the light emitting chip 130 and the electrode pad 140, the resin material is intruded into the first trench 151 between the electrode pad 140 and the circuit layer 120.
  • the spreadability of the resin material to be injected is lowered, so that the resin material to be injected is formed into a uniform dome shape after hardening. Therefore, the optical path length of the light transmitted through the encapsulation layer 160 is uniform, so that the emitted white light is uniform.
  • FIG. 2 is a schematic structural view of another embodiment of a light emitting diode of the present invention.
  • the light emitting diode of the present embodiment includes a bottom layer 110, a circuit layer 120, a light emitting chip 130, an electrode pad 140, a conductive line 150, and an encapsulation layer 160.
  • the bottom layer 110 includes a conductive substrate 111 and an insulating layer 112.
  • the bottom layer 110 is recessed inward to form a receiving groove.
  • a circuit layer 120 is disposed on the sidewall 113 and the bottom portion 114 of the accommodating groove.
  • the circuit layer 120 is disposed over the insulating layer 112, and the light emitting chip 130 is formed over the circuit layer 120.
  • the electrode pad 140 is also disposed on the insulating layer 112, and the electrode pad 140 has a predetermined first interval between the circuit layer 120 and the light emitting chip 130, so that the electrode pad 140 is formed between the circuit layer 120 and the light emitting chip 130.
  • the level of the electrode pad 140 is equal to the level of the light-emitting chip 130.
  • a predetermined second interval is formed between the light emitting chip 130 and the circuit layer 120 such that a second trench 152 is formed between the light emitting chip 130 and the circuit layer 120.
  • the conductive line 150 electrically connects the electrode pad 140 and the light emitting chip 130.
  • the encapsulating layer 160 is mixed with a phosphor, and the encapsulating layer 160 is formed on the light emitting chip 130 and the electrode pad 140, and fills the first trench 151 and the light emitting chip 130 and the circuit layer 120 between the electrode pad 140 and the circuit layer 120.
  • the second groove 152 is formed to form a uniform dome shape.
  • the conductive substrate 111 is a metal substrate and may be aluminum (Al), aluminum alloy (Al alloy), magnesium (Mg), magnesium alloy (Mg alloy), titanium (Ti), titanium alloy (Ti alloy), or the like.
  • the size and shape of the conductive substrate 111 are not limited and can be set according to the processing ability and actual needs.
  • the thickness of the conductive substrate 111 can be set to 0.1 mm in consideration of the process of processing, the reliability of the product, and the lightness and thinness of the product.
  • the conductive substrate 111 is made by etching or the like to form a cavity on the conductive substrate 111.
  • the insulating layer 112 may be formed on the conductive substrate 111 by an anodizing method, a plasma electrolytic oxidation (PEO) method, a dry oxidation method, a bonding process, or the like.
  • the insulating layer 112 is disposed on one side of the conductive substrate 111 adjacent to the circuit layer 120 and the electrode pad 140, and may be disposed on the entire surface of the conductive substrate 111.
  • the insulating layer 112 covers the cavity of the conductive substrate 111 to Forming a receiving groove.
  • the conductor is plated on the insulating layer 112 until the thickness of the light-emitting chip 130 can be sufficiently masked.
  • the conductor is then etched to form the circuit layer 120 and the electrode pads 140. Therefore, here, the height of the plated conductor may vary with the thickness of the light emitting chip 130, for example, the height of the plated conductor may be between 35 and 300 microns.
  • the covered conductor may be gold (Au), aluminum (Al) or copper (Cu) or the like.
  • the conductive wire 150 is a conductive wire, for example, a gold (Au) wire, an aluminum (Al) wire, or a copper (Cu) wire, or the like.
  • the encapsulation layer 160 is formed by solidification of a transparent resin material containing a phosphor.
  • the transparent resin material may be silicone resin or epoxy resin or the like.
  • the resin material breaks into the first trench 151 and the light-emitting chip 130 and the circuit layer 120 between the electrode pad 140 and the circuit layer 120.
  • the second grooves 152 Between the second grooves 152. Also, due to the presence of the first groove 151 and the second groove 152, the spreadability of the injected resin material is lowered, thereby causing the injected resin material to form a uniform dome shape after hardening. Therefore, the optical path length of the light transmitted through the encapsulation layer 160 is uniform, so that the emitted white light is uniform.
  • FIG. 4 there is shown a flow chart of an embodiment of a method of fabricating a light emitting diode of the present invention.
  • the method of manufacturing the light emitting diode of the present embodiment includes:
  • a conductive substrate for manufacturing a light emitting diode wherein the conductive substrate is a metal substrate, which may be aluminum (Al), aluminum alloy (A1 alloy), magnesium (Mg), magnesium alloy (Mg alloy), titanium. (Ti), titanium alloy (Ti alloy), and the like.
  • the size and shape of the conductive substrate are not limited and can be set according to the processing ability and actual needs.
  • the thickness of the conductive substrate can be set to 0.1 mm in consideration of the processing technology, the reliability of the product, and the lightness and thinness of the product.
  • an insulating layer is formed over the conductive substrate by an anodizing method, a plasma electrolytic oxidation (PEO) method, a dry oxidation method, a bonding process, or the like.
  • the insulating layer may be disposed on one side of the conductive substrate adjacent to the circuit layer and the electrode pad, or may be disposed on the entire surface of the conductive substrate.
  • the conductor is plated on the insulating layer until the thickness of the light-emitting chip is sufficiently masked. Then guide The body is etched to form a circuit layer and an electrode pad. Therefore, here, the height of the plated conductor may vary with the thickness of the light-emitting chip, for example, the height of the plated conductor may be between 35 and 300 microns.
  • the covered conductor may be gold (Au), aluminum (Al) or copper (Cu) or the like.
  • the conductive wire is a wire that can conduct electricity, for example, a gold (Au) wire, an aluminum (Al) wire, or a copper (Cu) wire, or the like.
  • a transparent resin material containing a phosphor is injected onto the light emitting chip and the electrode pad, and the resin material is drawn into the first trench between the electrode pad and the circuit layer.
  • the transparent resin material may be silicone resin or epoxy resin or the like. Due to the presence of the first groove, the spreadability of the injected resin material is lowered, thereby causing the injected resin material to form a uniform dome shape after hardening. Therefore, the optical path length of the light transmitted through the encapsulation layer is uniform, so that the emitted white light is uniform.
  • FIG. 5 is a flow chart showing another embodiment of a method of manufacturing a light emitting diode of the present invention.
  • the method of manufacturing the light emitting diode of the present embodiment includes:
  • a conductive substrate for manufacturing a light emitting diode wherein the conductive substrate is a metal substrate, which may be aluminum (Al), aluminum alloy (A1 alloy), magnesium (Mg), magnesium alloy (Mg alloy), titanium. (Ti), titanium alloy (Ti alloy), and the like.
  • the size and shape of the conductive substrate are not limited and can be set according to the processing ability and actual needs.
  • the thickness of the conductive substrate can be set to 0.1 mm in consideration of the processing technology, the reliability of the product, and the lightness and thinness of the product.
  • the conductive substrate is made by etching or the like to form a cavity on the conductive substrate.
  • an insulating layer is formed over the conductive substrate by an anodizing method, a plasma electrolytic oxidation (PEO) method, a dry oxidation method, a bonding process, or the like.
  • the insulating layer may be disposed on one side of the conductive substrate adjacent to the circuit layer and the electrode pad, or may be disposed on the entire surface of the conductive substrate.
  • the insulating layer covers the cavity of the conductive substrate to form a receiving groove.
  • the conductor is plated on the insulating layer until the thickness of the light-emitting chip is sufficiently masked.
  • the conductor is then etched to form a circuit layer and an electrode pad, wherein the circuit layer is formed on the sidewall and the bottom of the accommodating groove. Therefore, here, the height of the plated conductor may vary with the thickness of the light-emitting chip, for example, the height of the plated conductor may be between 35 and 300 microns.
  • the covered conductor may be gold (Au), aluminum (Al) or copper (Cu) or the like.
  • the height of the electrode pads is made equal to the sum of the height of the circuit layer and the height of the light-emitting chip.
  • the first interval is preset between the electrode pad and the circuit layer and the light emitting chip, so that a first trench is formed between the electrode pad and the circuit layer and the light emitting chip.
  • a predetermined second interval is formed between the circuit layer and the light emitting chip, so that a second trench is formed between the circuit layer and the light emitting chip.
  • the light-emitting chip and the electrode pad are electrically connected by a conductive wire.
  • the conductive wire is a wire that can conduct electricity, for example, a gold (Au) wire, an aluminum (Al) wire, or a copper (Cu) wire, or the like.
  • the transparent resin material may be silicone resin or epoxy resin or the like. Due to the presence of the first groove and the second groove, the spreadability of the resin material to be injected is lowered, thereby causing the injected resin material to form a uniform dome shape after hardening. Therefore, the optical path length of the light transmitted through the encapsulation layer is uniform, so that the emitted white light is uniform.
  • a first trench is formed between the electrode pad and the circuit layer, and the spreadability of the encapsulation layer is reduced due to the presence of the first trench, so that the encapsulation layer has a uniform dome shape, so that the encapsulation layer is uniformly
  • the optical path length of the light passing through the encapsulation layer is uniform, thereby making the emitted white light uniform.
  • the storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

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Abstract

本发明公开了一种发光二极管以及发光二极管的制造方法。所述方法包括：底层；电路层，形成于底层之上；发光芯片，形成于电路层之上；电极垫，形成于底层之上，与发光芯片之间电连接，电极垫与电路层和发光芯片之间具有预设的第一间隔，使得电极垫与电路层和发光芯片之间形成第一沟槽，并且，电极垫的水平高度等于发光芯片的水平高度；包含荧光粉的封装层，形成于发光芯片以及电极垫之上，并填充了电极垫与电路层之间的第一沟槽，以形成均匀的圆顶状。

Description

一种发光二极管以及发光二极管的制造方法
本发明要求2014年12月02日递交的发明名称为“一种发光二极管以及发光二极管的制造方法”的申请号201410723053.6的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及发光源领域，尤其涉及一种发光二极管以及发光二极管的制造方法。
背景技术
由于与白炽灯、荧光灯等传统光源相比，发光二极管(LED，Light Emitting Diode)具有使用寿命长，低功耗以及高效率的特点，近年来，发光二极管的需求持续增加，并在整个照明市场上占据了主导地位。
为了使发光二极管能够产生白光，可以在二极管的封装层(例如，环氧树脂层)中涂布红色和绿色的荧光粉，当发光二极管中的蓝色芯片发出蓝光时，封装层中的红色和绿色荧光粉将在蓝光的刺激下分别产生红光和绿光。所产生的红光和绿光会和透过封装层的蓝光进行混合，从而产生白光。
但是，由于封装层的形状可能是不规则的，例如，有些地方厚些，有些地方薄些，所以，透过封装层的光的光程长度不一，造成所发出的白光不均匀。
发明内容
本发明实施例所要解决的技术问题在于，提供一种发光二极管以及发光二极管的制造方法，实现了形成均匀的封装层，使得透过封装层的光的光程长度一致，进而使得所发出的白光均匀。
本发明第一方面提供了一种发光二极管，包括：底层；电路层，形成于所述底层之上；发光芯片，形成于所述电路层之上；电极垫，形成于所述底层之上，与所述发光芯片之间电连接，所述电极垫与所述电路层和所述发光芯片之间具有预设的第一间隔，使得所述电极垫与所述电路层和所述发光芯片之间 形成第一沟槽，并且，所述电极垫的水平高度等于所述发光芯片的水平高度；包含荧光粉的封装层，形成于所述发光芯片以及所述电极垫之上，并填充了所述电极垫与所述电路层之间的第一沟槽，以形成均匀的圆顶状。
可选地，所述电极垫的高度等于所述电路层的高度与所述发光芯片的高度之和。
可选地，所述底层向内凹陷形成容置槽，所述容置槽的侧壁和底部上设置所述电路层。
可选地，所述电路层与所述发光芯片之间具有预设的第二间隔，使得所述电路层与所述发光芯片之间形成第二沟槽。
可选地，所述底层包括导电底材以及形成与所述导电底材之上的绝缘层。
可选地，所述导电底材为铝、铝合金、镁、镁合金、钛、钛合金中的任意一种。
可选地，所述导电底材的厚度设置为0.1毫米。
可选地，所述封装层的材料为硅树脂或者环氧树脂。
可选地，所述电极垫和所述电路层的材料为金或铝或铜。
本发明第二方面提供了一种发光二极管的制造方法，包括：提供底层；使用镀覆法在所述底层之上形成电路层以及电极垫；在所述电路层上安装发光芯片，并使得所述电极垫的水平高度等于所述发光芯片的水平高度，其中，在所述电极垫与所述电路层和所述发光芯片之间预设第一间隔，使得所述电极垫与所述电路层和所述发光芯片之间形成第一沟槽；在所述发光芯片、所述电极垫以及所述电极垫与所述电路层之间的第一沟槽之上填充包含荧光粉的封装材料，以形成均匀圆顶状的封装层。
可选地，所述电极垫的高度等于所述电路层的高度与所述发光芯片的高度之和。
可选地，提供底层的步骤具体为：提供向内凹陷形成容置槽的底层；使用镀覆法在所述底层之上形成电路层具体为：使用镀覆法在所述底层的容置槽的侧壁以及底部形成所述电路层。
可选地，所述电路层与所述发光芯片之间具有预设的第二间隔，使得所述电路层与所述发光芯片之间形成第二沟槽。
可选地，提供底层的步骤具体为：提供导电底材；在所述导电底材上形成绝缘层。
可选地，所述导电底材为铝、铝合金、镁、镁合金、钛、钛合金中的任意一种。
可选地，所述导电底材的厚度设置为0.1毫米。
可选地，所述封装层的材料为硅树脂或者环氧树脂。
可选地，所述电极垫和所述电路层的材料为金或铝或铜。
可选地，所述使用镀覆法在所述底层之上形成电路层以及电极垫具体为：使用镀覆法在所述底层之上镀覆导体；对所述导体进行腐蚀以在所述底层之上形成电路层以及电极垫。
可选地，所述镀覆导体的高度为35-300微米之间。
通过实施本发明实施例，在电极垫与电路层之间形成第一沟槽，由于第一沟槽的存在，使得封装层的可铺展性下降，从而封装层为均匀的圆顶状，使得透过封装层的光的光程长度一致，进而使得所发出的白光均匀。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明发光二极管一实施方式的结构示意图；
图2是本发明发光二极管另一实施方式的结构示意图；
图3是本发明发光二极管的底层的一实施方式的结构示意图；
图4是本发明发光二极管的制造方法一实施方式的流程图；
图5是本发明发光二极管的制造方法另一实施方式的流程图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是 全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
参阅图1，图1是本发明发光二极管一实施方式的结构示意图。本实施方式的发光二极管包括：底层110、电路层120、发光芯片130、电极垫140、导电线150以及封装层160。其中，底层110包括导电底材111以及绝缘层112。电路层120设置在绝缘层112之上，发光芯片130形成于电路层120之上。电极垫140同样设置在绝缘层112之上，并且，电极垫140与电路层120和发光芯片130之间具有预设的第一间隔，使得电极垫140与电路层120和发光芯片130之间形成第一沟槽151。并且，电极垫140的水平高度等于发光芯片130的水平高度。在一具体的实施方式中，电极垫140的高度等于电路层120的高度与发光芯片130的高度之和。导电线150将电极垫140和发光芯片130电连接起来。封装层160中混合有荧光粉，封装层160形成于发光芯片130以及电极垫140之上，并填充了电极垫140与电路层120之间的第一沟槽151，以形成均匀的圆顶状。
导电底材111为金属底材，可以是铝(Al)、铝合金(A1合金)、镁(Mg)、镁合金(Mg合金)、钛(Ti)、钛合金(Ti合金)等等。导电底材111的大小和形状不限，可根据加工能力和实际需要而进行设定。在综合考虑加工的工艺、产品的可靠性以及产品的轻薄要求，可将导电底材111的厚度设置为0.1毫米。
绝缘层112可以采用阳极化法、等离子体电解质氧化(PEO)法、干氧化方法、接合法(bonding process)等形成在导电底材111之上。其中，绝缘层112设置在导电底材111中接近电路层120以及电极垫140的一面，也可以设置在导电底材111的整个表面。
在绝缘层112上镀覆导体，直到能够使发光芯片130被充分掩盖的厚度。然后对导体进行腐蚀，从而形成了电路层120以及电极垫140。所以，此处，镀覆导体的高度可以随着发光芯片130的厚度而改变，例如，镀覆导体的高度可以为35-300微米之间。覆盖的导体可以是金(Au)、铝(Al)或铜(Cu)等等。
导电线150为能够导电的金属丝，例如，金(Au)丝、铝(Al)丝或铜(Cu)丝等等。
封装层160为由含有荧光粉的透明树脂材料凝固而成。其中，透明树脂材料可以是硅树脂或者环氧树脂等等。当含有荧光粉的透明树脂材料被注射到发光芯片130以及电极垫140之上时，树脂材料沁入到电极垫140与电路层120之间的第一沟槽151中。并且，由于第一沟槽151的存在，使得被注入的树脂材料的可铺展性下降，进而使得被注入的树脂材料在硬化后形成均匀的圆顶状。所以，透过封装层160的光的光程长度一致，使得所发出的白光均匀。
参阅图2，图2是本发明发光二极管另一实施方式的结构示意图。本实施方式的发光二极管包括：底层110、电路层120、发光芯片130、电极垫140、导电线150以及封装层160。请一并参阅图3，底层110包括导电底材111以及绝缘层112，底层110向内凹陷形成容置槽。容置槽的侧壁113和底部114上设置电路层120。电路层120设置在绝缘层112之上，发光芯片130形成于电路层120之上。电极垫140同样设置在绝缘层112之上，并且，电极垫140与电路层120和发光芯片130之间具有预设的第一间隔，使得电极垫140与电路层120和发光芯片130之间形成第一沟槽151。并且，电极垫140的水平高度等于发光芯片130的水平高度。发光芯片130与电路层120之间具有预设的第二间隔，使得发光芯片130与电路层120之间形成第二沟槽152。导电线150将电极垫140和发光芯片130电连接起来。封装层160中混合有荧光粉，封装层160形成于发光芯片130以及电极垫140之上，并填充了电极垫140与电路层120之间的第一沟槽151和发光芯片130与电路层120之间的第二沟槽152，以形成均匀的圆顶状。
导电底材111为金属底材，可以是铝(Al)、铝合金(A1合金)、镁(Mg)、镁合金(Mg合金)、钛(Ti)、钛合金(Ti合金)等等。导电底材111的大小和形状不限，可根据加工能力和实际需要而进行设定。在综合考虑加工的工艺、产品的可靠性以及产品的轻薄要求，可将导电底材111的厚度设置为0.1毫米。通过刻蚀等方法使得导电底材111，以在导电底材111上形成空腔。
绝缘层112可以采用阳极化法、等离子体电解质氧化(PEO)法、干氧化方法、接合法(bonding process)等形成在导电底材111之上。其中，绝缘层112设置在导电底材111中接近电路层120以及电极垫140的一面，也可以设置在导电底材111的整个表面。绝缘层112覆盖在导电底材111的空腔上，以 形成容置槽。
在绝缘层112上镀覆导体，直到能够使发光芯片130被充分掩盖的厚度。然后对导体进行腐蚀，从而形成了电路层120以及电极垫140。所以，此处，镀覆导体的高度可以随着发光芯片130的厚度而改变，例如，镀覆导体的高度可以为35-300微米之间。覆盖的导体可以是金(Au)、铝(Al)或铜(Cu)等等。
导电线150为能够导电的金属丝，例如，金(Au)丝、铝(Al)丝或铜(Cu)丝等等。
封装层160为由含有荧光粉的透明树脂材料凝固而成。其中，透明树脂材料可以是硅树脂或者环氧树脂等等。当含有荧光粉的透明树脂材料被注射到发光芯片130以及电极垫140之上时，树脂材料沁入到电极垫140与电路层120之间的第一沟槽151和发光芯片130与电路层120之间的第二沟槽152中。并且，由于第一沟槽151和第二沟槽152的存在，使得被注入的树脂材料的可铺展性下降，进而使得被注入的树脂材料在硬化后形成均匀的圆顶状。所以，透过封装层160的光的光程长度一致，使得所发出的白光均匀。
参阅图4，图4是本发明发光二极管的制造方法一实施方式的流程图。本实施方式的发光二极管的制造方法包括：
410：提供底层。
首先，提供用于制造发光二极管的导电底材，其中，导电底材为金属底材，可以是铝(Al)、铝合金(A1合金)、镁(Mg)、镁合金(Mg合金)、钛(Ti)、钛合金(Ti合金)等等。导电底材的大小和形状不限，可根据加工能力和实际需要而进行设定。在综合考虑加工的工艺、产品的可靠性以及产品的轻薄要求，可将导电底材的厚度设置为0.1毫米。
然后，通过阳极化法、等离子体电解质氧化(PEO)法、干氧化方法、接合法(bonding process)等在导电底材之上形成绝缘层。其中，绝缘层可以设置在导电底材中接近电路层以及电极垫的一面，也可以设置在导电底材的整个表面。
420：使用镀覆法在底层之上形成电路层以及电极垫。
在绝缘层上镀覆导体，直到能够使发光芯片被充分掩盖的厚度。然后对导 体进行腐蚀，从而形成了电路层以及电极垫。所以，此处，镀覆导体的高度可以随着发光芯片的厚度而改变，例如，镀覆导体的高度可以为35-300微米之间。覆盖的导体可以是金(Au)、铝(Al)或铜(Cu)等等。
430：在电路层上安装发光芯片，并使得电极垫的水平高度等于发光芯片的水平高度。在具体的实施方式中，使得电极垫的高度等于电路层的高度与发光芯片的高度之和。其中，在电极垫与电路层和发光芯片之间预设第一间隔，使得电极垫与电路层和发光芯片之间形成第一沟槽。再通过引线接合，使得发光芯片和电极垫之间通过导电线电连接。导电线为能够导电的金属丝，例如，金(Au)丝、铝(Al)丝或铜(Cu)丝等等。
440：在发光芯片、电极垫以及电极垫与电路层之间的第一沟槽之上填充包含荧光粉的封装材料，以形成均匀圆顶状的封装层。
将含有荧光粉的透明树脂材料注射到发光芯片以及电极垫之上，并使得树脂材料沁入到电极垫与电路层之间的第一沟槽中。其中，透明树脂材料可以是硅树脂或者环氧树脂等等。由于第一沟槽的存在，使得被注入的树脂材料的可铺展性下降，进而使得被注入的树脂材料在硬化后形成均匀的圆顶状。所以，透过封装层的光的光程长度一致，使得所发出的白光均匀。
参阅图5，图5是本发明发光二极管的制造方法另一实施方式的流程图。本实施方式的发光二极管的制造方法包括：
510：提供向内凹陷形成容置槽的底层。
首先，提供用于制造发光二极管的导电底材，其中，导电底材为金属底材，可以是铝(Al)、铝合金(A1合金)、镁(Mg)、镁合金(Mg合金)、钛(Ti)、钛合金(Ti合金)等等。导电底材的大小和形状不限，可根据加工能力和实际需要而进行设定。在综合考虑加工的工艺、产品的可靠性以及产品的轻薄要求，可将导电底材的厚度设置为0.1毫米。通过刻蚀等方法使得导电底材，以在导电底材上形成空腔。
然后，通过阳极化法、等离子体电解质氧化(PEO)法、干氧化方法、接合法(bonding process)等在导电底材之上形成绝缘层。其中，绝缘层可以设置在导电底材中接近电路层以及电极垫的一面，也可以设置在导电底材的整个表面。绝缘层覆盖在导电底材的空腔上，以形成容置槽。
520：使用镀覆法在底层的容置槽的侧壁以及底部形成电路层。
在绝缘层上镀覆导体，直到能够使发光芯片被充分掩盖的厚度。然后对导体进行腐蚀，从而形成了电路层以及电极垫，其中，电路层形成于容置槽的侧壁以及底部。所以，此处，镀覆导体的高度可以随着发光芯片的厚度而改变，例如，镀覆导体的高度可以为35-300微米之间。覆盖的导体可以是金(Au)、铝(Al)或铜(Cu)等等。
530：在电路层上安装发光芯片，并使得电极垫的水平高度等于发光芯片的水平高度。在具体的实施方式中，使得电极垫的高度等于电路层的高度与发光芯片的高度之和。其中，在电极垫与电路层和发光芯片之间预设第一间隔，使得电极垫与电路层和发光芯片之间形成第一沟槽。电路层与发光芯片之间具有预设的第二间隔，使得电路层与发光芯片之间形成第二沟槽。再通过引线接合，使得发光芯片和电极垫之间通过导电线电连接。导电线为能够导电的金属丝，例如，金(Au)丝、铝(Al)丝或铜(Cu)丝等等。
540：在发光芯片、电极垫以及电极垫与电路层之间的第一沟槽之上填充包含荧光粉的封装材料，以形成均匀圆顶状的封装层。
将含有荧光粉的透明树脂材料注射到发光芯片以及电极垫之上，并使得树脂材料沁入到电极垫与电路层之间的第一沟槽以及发光芯片与电路层之间的第二沟槽中。其中，透明树脂材料可以是硅树脂或者环氧树脂等等。由于第一沟槽和第二沟槽的存在，使得被注入的树脂材料的可铺展性下降，进而使得被注入的树脂材料在硬化后形成均匀的圆顶状。所以，透过封装层的光的光程长度一致，使得所发出的白光均匀。
通过实施本发明实施例，在电极垫与电路层之间形成第一沟槽，由于第一沟槽的存在，使得封装层的可铺展性下降，从而封装层为均匀的圆顶状，使得透过封装层的光的光程长度一致，进而使得所发出的白光均匀。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，是可以通过计算机程序来指令相关的硬件来完成，所述的程序可存储于一计算机可读取存储介质中，该程序在执行时，可包括如上述各方法的实施例的流程。其中，所述的存储介质可为磁碟、光盘、只读存储记忆体(Read-Only Memory，ROM)或随机存储记忆体(Random Access Memory，RAM)等。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (20)

  1. 一种发光二极管，其特征在于，包括：
    底层；
    电路层，形成于所述底层之上；
    发光芯片，形成于所述电路层之上；
    电极垫，形成于所述底层之上，与所述发光芯片之间电连接，所述电极垫与所述电路层和所述发光芯片之间具有预设的第一间隔，使得所述电极垫与所述电路层和所述发光芯片之间形成第一沟槽，并且，所述电极垫的水平高度等于所述发光芯片的水平高度；
    包含荧光粉的封装层，形成于所述发光芯片以及所述电极垫之上，并填充了所述电极垫与所述电路层之间的第一沟槽，以形成均匀的圆顶状。
  2. 根据权利要求1所述的发光二极管，其特征在于，所述电极垫的高度等于所述电路层的高度与所述发光芯片的高度之和。
  3. 根据权利要求1所述的发光二极管，其特征在于，所述底层向内凹陷形成容置槽，所述容置槽的侧壁和底部上设置所述电路层。
  4. 根据权利要求3所述的发光二极管，其特征在于，所述电路层与所述发光芯片之间具有预设的第二间隔，使得所述电路层与所述发光芯片之间形成第二沟槽。
  5. 根据权利要求1所述的发光二极管，其特征在于，所述底层包括导电底材以及形成与所述导电底材之上的绝缘层。
  6. 根据权利要求5所述的发光二极管，其特征在于，所述导电底材为铝、铝合金、镁、镁合金、钛、钛合金中的任意一种。
  7. 根据权利要求5所述的发光二极管，其特征在于，所述导电底材的厚度设置为0.1毫米。
  8. 根据权利要求1所述的发光二极管，其特征在于，所述封装层的材料为硅树脂或者环氧树脂。
  9. 根据权利要求1所述的发光二极管，其特征在于，所述电极垫和所述电路层的材料为金或铝或铜。
  10. 一种发光二极管的制造方法，其特征在于，包括：
    提供底层；
    使用镀覆法在所述底层之上形成电路层以及电极垫；
    在所述电路层上安装发光芯片，并使得所述电极垫的水平高度等于所述发光芯片的水平高度，其中，在所述电极垫与所述电路层和所述发光芯片之间预设第一间隔，使得所述电极垫与所述电路层和所述发光芯片之间形成第一沟槽；
    在所述发光芯片、所述电极垫以及所述电极垫与所述电路层之间的第一沟槽之上填充包含荧光粉的封装材料，以形成均匀圆顶状的封装层。
  11. 根据权利要求10所述的方法，其特征在于，所述电极垫的高度等于所述电路层的高度与所述发光芯片的高度之和。
  12. 根据权利要求10所述的方法，其特征在于，
    提供底层的步骤具体为：提供向内凹陷形成容置槽的底层；
    使用镀覆法在所述底层之上形成电路层具体为：使用镀覆法在所述底层的容置槽的侧壁以及底部形成所述电路层。
  13. 根据权利要求12所述的方法，其特征在于，所述电路层与所述发光芯片之间具有预设的第二间隔，使得所述电路层与所述发光芯片之间形成第二沟槽。
  14. 根据权利要求10所述的方法，其特征在于，提供底层的步骤具体为：
    提供导电底材；
    在所述导电底材上形成绝缘层。
  15. 根据权利要求14所述的方法，其特征在于，所述导电底材为铝、铝合金、镁、镁合金、钛、钛合金中的任意一种。
  16. 根据权利要求14所述的方法，其特征在于，所述导电底材的厚度设置为0.1毫米。
  17. 根据权利要求10所述的方法，其特征在于，所述封装层的材料为硅树脂或者环氧树脂。
  18. 根据权利要求10所述的方法，其特征在于，所述电极垫和所述电路层的材料为金或铝或铜。
  19. 根据权利要求10所述的方法，其特征在于，所述使用镀覆法在所述底层之上形成电路层以及电极垫具体为：
    使用镀覆法在所述底层之上镀覆导体；
    对所述导体进行腐蚀以在所述底层之上形成电路层以及电极垫。
  20. 根据权利要求19所述的方法，其特征在于，所述镀覆导体的高度为35-300微米之间。
PCT/CN2014/093702 2014-12-02 2014-12-12 一种发光二极管以及发光二极管的制造方法 Ceased WO2016086446A1 (zh)

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