WO2016086411A1 - 一种控制器、闪存装置、识别数据块稳定性的方法以及在闪存装置中存储数据的方法 - Google Patents

一种控制器、闪存装置、识别数据块稳定性的方法以及在闪存装置中存储数据的方法 Download PDF

Info

Publication number
WO2016086411A1
WO2016086411A1 PCT/CN2014/093139 CN2014093139W WO2016086411A1 WO 2016086411 A1 WO2016086411 A1 WO 2016086411A1 CN 2014093139 W CN2014093139 W CN 2014093139W WO 2016086411 A1 WO2016086411 A1 WO 2016086411A1
Authority
WO
WIPO (PCT)
Prior art keywords
data block
flash memory
memory device
reference count
time
Prior art date
Application number
PCT/CN2014/093139
Other languages
English (en)
French (fr)
Inventor
吴黎明
黄斌
赵万
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to DK14902279.0T priority Critical patent/DK3059679T3/en
Priority to ES14902279.0T priority patent/ES2691484T3/es
Priority to PCT/CN2014/093139 priority patent/WO2016086411A1/zh
Priority to KR1020167009885A priority patent/KR101784893B1/ko
Priority to EP14902279.0A priority patent/EP3059679B1/en
Priority to CN201480075497.1A priority patent/CN105980992B/zh
Priority to JP2016535211A priority patent/JP6147933B2/ja
Priority to US15/085,831 priority patent/US9772790B2/en
Publication of WO2016086411A1 publication Critical patent/WO2016086411A1/zh
Priority to US15/679,174 priority patent/US20170364300A1/en

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/064—Management of blocks
    • G06F3/0641—De-duplication techniques
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0253—Garbage collection, i.e. reclamation of unreferenced memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0868—Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0608—Saving storage space on storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0616—Improving the reliability of storage systems in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/064—Management of blocks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
    • G06F2212/1036—Life time enhancement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7205—Cleaning, compaction, garbage collection, erase control

Definitions

  • Embodiments of the present invention relate to the field of storage technologies, and in particular, to a controller, a flash memory device, a method of identifying data block stability, and a method of storing data in a flash memory device.
  • the Flash Memory device is a non-volatile memory whose storage medium is NAND Flash, which has the characteristics that the data does not disappear after power-off, and therefore is widely used as an external and internal memory.
  • a flash memory device using NAND Flash as a storage medium may be a solid state hard disk (full name: Solid State Device, SSD for short), also known as a solid state drive (full name: Solid State Drive, SSD for short), and may be other memory.
  • An SSD is usually composed of a plurality of flash chips, each of which contains a plurality of blocks. Since NAND Flash has an erasing feature, the data stored in the block is not directly modified like a normal mechanical hard disk. When it is necessary to modify the data pointed to by a certain logical address, it is necessary to find a free block to write the modified data to the free block, and then point the logical address to the newly written data, then the original block. The data in it becomes invalid data.
  • valid data refers to data stored in a block with a logical address, and this part of data may be read; invalid data refers to data stored in a block without a logical address. This part of data may not be Was read.
  • Garbage collection refers to moving the valid data in the block to the free block, and then erasing the old block. After the erased block, the block can be written again as an idle block.
  • garbage collection it will look for blocks containing more invalid data, because blocks containing more invalid data contain less valid data, so you need to move to free blocks. There will be less valid data.
  • the lifetime of the SSD is related to the number of erasures of the NAND Flash, the less data is moved during garbage collection, the smaller the write amplification of the SSD is. However, since the probability that the data saved by different blocks is modified is roughly equivalent, there is no significant difference in the amount of invalid data contained in each block.
  • a first aspect of the embodiments of the present invention provides a controller, where the controller is located in a storage system that supports deduplication, where the storage system includes a flash memory device, where the first data block is stored in the flash memory device;
  • the controller includes a processor, a cache, and a communication interface; the communication interface is configured to communicate with the flash memory device;
  • the cache stores information of the first data block, and the information of the first data block includes a reference count of the first data block, or a length of time in which the first data block is saved in the flash memory device, or a reference count of the first data block and the first data block are saved in the flash memory device The length of time, wherein the reference count of the first data block is equal to the number of the first data block received by the controller.
  • the processor is configured to read information of the first data block from the cache. Then, according to (1) the reference count of the first data block, and the correspondence between the reference count of the data block and the stability level, or (2) the length of time in which the first data block is stored in the flash memory device, and a data block holds a correspondence between a length of time of the flash memory device and a stable level, or (3) a reference count of the first data block and a length of time in which the first data block is stored in the flash memory device, and a data block
  • the reference count, the correspondence between the length of time of the data block and the stable level of the flash memory device determines the stability level of the first data block, and the stable level is used to indicate the stability of the data block. And transmitting the logical address of the first data block and the stability level of the first data block to the flash memory device through the communication interface.
  • the correspondence between the reference count of the data block and the stability level includes: a correspondence between the reference count interval and the stability level.
  • the processor is configured to determine a first reference counting interval according to a reference count of the first data block, where a reference count of the first data block is located in the first reference counting interval, and according to the first The reference count interval, and the correspondence between the reference count interval and the stability level determine the stability level of the first data block.
  • the correspondence between the time length of the data block and the stability level of the flash memory device includes: a correspondence between the time interval and the stability level.
  • the processor is configured to determine a first time interval according to a length of time that the first data block is saved in the flash memory device, where a length of time in which the first data block is stored in the flash memory device is located in the first time interval.
  • the stability level of the first data block is determined in the time interval, and according to the first time interval, and the correspondence between the time interval and the stability level.
  • the reference count of the data block, the correspondence between the length of time and the stability level of the data block stored in the flash memory device includes: a reference count interval, a correspondence between the time interval and the stability level.
  • the processor is configured to determine a first reference count interval according to a reference count of the first data block, where a reference count of the first data block is located in the first reference count interval.
  • the first reference count interval, the first time interval, and the reference count interval, the correspondence between the time interval and the stability level determine a stability level of the first data block.
  • a second aspect of the embodiments of the present invention provides a flash memory device including a main controller and a flash memory chip, the flash memory chip including a block, and the main controller including a processor.
  • the processor is configured to obtain a stability level corresponding to the target logical address, where the stability level is used to indicate the stability of the data block; and then, according to the stability level corresponding to the target logical address, the target logical address is used.
  • the corresponding data block is written in the block corresponding to the stable level.
  • the processor is further configured to search, in the flash memory chip, a block that contains the most invalid data, where the block that contains the most invalid data includes the target logical address. data block.
  • the processor is further configured to search, in the flash memory chip, a block that has not been erased for a long time, the block that has not been erased for the longest time.
  • a data block corresponding to the target logical address is included.
  • the main controller further includes a cache, where the processor is configured to: when determining that the number of logical addresses saved in the cache reaches a preset threshold, acquiring the A stable level corresponding to the target logical address, wherein the stable level corresponding to the logical address is the same as the stable level corresponding to the target logical address.
  • a third aspect of the embodiments of the present invention provides a method for identifying stability of a data block, the method being applied to a controller, the controller being located in a storage system supporting deduplication, the storage system including a flash memory device
  • the flash memory device stores a first data block
  • the controller includes a processor, a cache, and a communication interface
  • the communication interface is configured to communicate with the flash memory device
  • the first cache is stored in the cache Information of the data block, the information of the first data block including a reference count of the first data block, or a length of time in which the first data block is saved in the flash memory device, or a reference to the first data block Counting and a length of time in which the first data block is stored in the flash memory device, wherein a reference count of the first data block is equal to a number of the first data block received by the controller; the method is performed by the processing Execution.
  • the method includes: reading information of the first data block from the cache, and then, according to (1) a reference count of the first data block, and a correspondence between a reference count of the data block and a stability level, Or (2) the length of time in which the first data block is stored in the flash memory device, and the correspondence between the length of time in which the data block is stored in the flash memory device and the stable level, or (3) the reference count of the first data block And determining, by the first data block, the length of time of the flash memory device, and the reference count of the data block, the correspondence between the length of time of the data block and the stability level of the data block, and determining the stability level of the first data block.
  • the stability level is used to indicate the stability of the data block. And transmitting the logical address of the first data block and the stability level of the first data block to the flash memory device through the communication interface.
  • the correspondence between the reference count of the data block and the stability level includes: a correspondence between a reference count interval and a stability level. Determining the stability level of the first data block according to the reference count of the first data block according to (1), and the correspondence between the reference count of the data block and the stability level, including: referencing according to the first data block Counting determines a first reference count interval, the reference count of the first data block being located in the first reference count interval; And determining a stability level of the first data block according to the first reference counting interval and a correspondence between a reference counting interval and a stability level.
  • the correspondence between the time length of the data block and the stability level of the flash memory device includes: a correspondence between the time interval and the stability level. Determining, according to (2), a length of time in which the first data block is stored in the flash memory device, and a correspondence between a length of time in which the data block is stored in the flash memory device and a stable level, determining a stability level of the first data block includes Determining, according to a length of time that the first data block is saved in the flash memory device, a first time interval, where a length of time in which the first data block is stored in the flash memory device is located in the first time interval, and The first time interval, and the correspondence between the time interval and the stability level determine a stability level of the first data block.
  • the reference count of the data block, the correspondence between the length of time and the stability level of the data block stored in the flash memory device includes: a reference count interval, a correspondence between the time interval and the stability level.
  • the reference count of the first data block according to (3) and the length of time that the first data block is saved in the flash memory device, and the reference count of the data block, the length of time and stability of the data block stored in the flash memory device Determining a level of stability of the first data block, determining a first reference count interval according to a reference count of the first data block, where a reference count of the first data block is located in the first reference count And determining a first time interval according to a length of time in which the first data block is saved in the flash memory device, where a length of time in which the first data block is stored in the flash memory device is located in the first time interval And determining, according to the first reference counting interval, the first time interval, and the reference counting interval, the correspondence between the time interval and the stability level,
  • a fourth aspect of the embodiments of the present invention provides a method of storing data in a flash memory device, the flash memory device including a main controller and a flash memory chip, the flash memory chip including a block, the main controller including a processor; The method is performed by the processor. The method includes: obtaining a stability level corresponding to a target logical address, the stability level being used to indicate stability of a data block. Then, according to the stability level corresponding to the target logical address, the data block corresponding to the target logical address is written into the The block corresponding to the stability level.
  • the method further includes: searching, in the flash memory chip, a block that includes the most invalid data, where the block containing the most invalid data includes a data block corresponding to the target logical address. .
  • the method further includes: searching, in the flash memory chip, a block that has not been erased for a long time, and the block that has not been erased in the longest time includes the The data block corresponding to the target logical address.
  • the main controller further includes a cache
  • the obtaining a stable level corresponding to the target logical address includes: determining that the number of logical addresses saved in the cache reaches a preset threshold And obtaining a stable level corresponding to the target logical address, where a stable level corresponding to the logical address is the same as a stable level corresponding to the target logical address.
  • a fifth aspect of the embodiments of the present invention provides an apparatus for identifying stability of a data block, the apparatus being located in a controller, the controller being located in a storage system supporting deduplication, the storage system including a flash memory device,
  • the first data block is stored in the flash memory device.
  • the device includes: a storage module, configured to save information of the first data block, the information of the first data block includes a reference count of the first data block, or the first data block is saved in the a length of time of the flash memory device, or a reference count of the first data block and a length of time in which the first data block is stored in the flash memory device, wherein a reference count of the first data block is equal to the controller receiving station The number of first data blocks.
  • a reading module configured to read information of the first data block from the storage module.
  • a determining module configured to, according to (1), a reference count of the first data block, and a reference count of the data block and a stable level, or (2) a time at which the first data block is saved in the flash memory device a length, and a data block is stored in a correspondence between a length of time of the flash memory device and a stable level, or (3) a reference count of the first data block and a length of time in which the first data block is stored in the flash memory device, and The reference count of the data block, the correspondence between the length of time of the data block and the stable level of the data block is determined, and the stability level of the first data block is determined.
  • a sending module configured to send, to the flash memory, a logical address of the first data block and a stable level of the first data block Set.
  • the correspondence between the reference count of the data block and the stability level includes: a correspondence between the reference count interval and the stability level.
  • the determining module is configured to determine a first reference counting interval according to a reference count of the first data block, where a reference count of the first data block is located in the first reference counting interval; according to the first reference The counting interval, and the correspondence between the reference counting interval and the stability level, determines the stability level of the first data block.
  • the correspondence between the time length of the data block and the stability level of the flash memory device includes: a correspondence between the time interval and the stability level.
  • the determining module is configured to determine a first time interval according to a length of time that the first data block is saved in the flash memory device, where a length of time in which the first data block is stored in the flash memory device is located in the first time interval And determining a stability level of the first data block according to the first time interval and a correspondence between the time interval and the stability level.
  • the reference count of the data block, the correspondence between the length of time and the stability level of the data block stored in the flash memory device includes: a reference count interval, a correspondence between the time interval and the stability level.
  • the determining module is configured to determine a first reference counting interval according to a reference count of the first data block, where a reference count of the first data block is located in the first reference counting interval, and then, according to the Determining, in a first time interval, a length of time in which the data block is stored in the flash memory device, wherein a length of time in which the first data block is stored in the flash memory device is in the first time interval; and counting according to the first reference
  • the interval, the first time interval, and the reference count interval, the correspondence between the time interval and the stability level determines a stability level of the first data block.
  • a sixth aspect of the embodiments of the present invention provides an apparatus for storing data in a flash memory device, the apparatus being located in a main controller of the flash memory device, in which a block is stored.
  • the device includes: an obtaining module, configured to acquire a stable level corresponding to a target logical address, where the stable level is used to indicate stability of a data block.
  • a migration module configured to write, according to the stability level corresponding to the target logical address, a data block corresponding to the target logical address into a block corresponding to the stable level.
  • the acquiring module is further configured to search, in the flash memory chip, a block that contains the most invalid data, where the block that contains the most invalid data includes data corresponding to the target logical address. Piece.
  • the acquiring module is further configured to search, in the flash memory chip, a block that has not been erased for a long time, and the block that has not been erased for the longest time A data block corresponding to the target logical address is included.
  • the device further includes a storage module, where the storage module stores a logical address, and the stable level corresponding to the logical address is the same as the stable level corresponding to the target logical address.
  • the obtaining module is configured to obtain a stability level corresponding to the target logical address when the number of the logical addresses saved in the cache reaches a preset threshold.
  • a seventh aspect of the embodiments of the present invention provides a computer program product comprising a computer readable storage medium storing program code, the program code comprising instructions for performing a third implementation of the third to third aspects The method of any of the modes.
  • An eighth aspect of the embodiments of the present invention provides a computer program product, comprising: a computer readable storage medium storing program code, the program code comprising instructions for performing a third implementation of the fourth to fourth aspects The method of any of the modes.
  • the controller provided by the embodiment of the present invention may be based on (1) a reference count of the first data block, and a correspondence between a reference count of the data block and a stability level, or (2) the first data block is stored in the The length of time of the flash memory device, and the correspondence between the length of time of the data block stored in the flash memory device and the stable level, or (3) the reference count of the first data block and the first data block being stored in the flash memory device
  • the length of time, and the reference count of the data block, the correspondence between the length of time of the data block and the stability level of the data block, determining the stability level of the first data block, the stability level may reflect the stability of the data block, And transmitting the stable level and logical address of the data block to the flash memory device 22, so that the flash memory device 22 centrally stores the data blocks of the same stable level.
  • the flash memory device provided by the embodiment of the present invention can store data blocks of the same stable level in one In the block. Then, for a block storing a data block with a higher stable level, the stored data block becomes less likely to be invalid data. As a whole, the block does not contain invalid data or only a small amount of invalid data, such a block. A block having a relatively high utilization rate does not collect such a block when garbage collection is performed on the flash memory device 22; it is highly likely that a stored data block becomes invalid data for a block storing a data block having a lower stable level.
  • the block contains less valid data, less data needs to be migrated during garbage collection, and the write amplification is reduced.
  • the effect of the embodiment mainly reflects that the effective data moved during the subsequent garbage collection is reduced. It can be seen that whether the block storing the data block with higher stability level or the block storing the data block with lower stability level can reduce the write amplification of the flash memory device 22, thus extending the flash memory device 22 to some extent. Life expectancy.
  • FIG. 1 is a structural diagram of a storage system according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a controller according to an embodiment of the present invention.
  • FIG. 3A is a schematic structural diagram of a storage medium of a flash memory device according to an embodiment of the present invention.
  • 3B is a schematic structural diagram of a main controller of a flash memory device according to an embodiment of the present invention.
  • FIG. 4 is a schematic flowchart of a method for identifying data block stability according to an embodiment of the present invention
  • FIG. 5 is a schematic flowchart of a method for storing data in a flash memory device according to an embodiment of the present invention
  • FIG. 6 is a schematic flowchart diagram of another method for storing data in a flash memory device according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of an apparatus for identifying stability of a data block according to an embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of an apparatus for storing data in a flash memory device according to an embodiment of the present invention.
  • Embodiments of the present invention provide a controller, a flash memory device, a method for identifying data block stability, and a method for storing data in a flash memory device, which are capable of storing data blocks of the same stable level in a centralized manner, so that the flash memory device performs subsequent garbage.
  • the block selected during the recycle operation contains as little valid data as possible, thereby reducing the write amplification of the flash device.
  • a data object is an object that contains actual data, and can be block data, or it can be a file or other form of data.
  • a data block is a data unit that is divided by data objects.
  • a data object can be divided into several data blocks, each of which is the same size.
  • the metadata of a data block refers to information for describing a data block, such as a logical address of a data block, a physical address of a data block, a correspondence between a logical address and a physical address, a write time of a data block, and the like.
  • Stable data refers to data that is relatively less likely to be modified.
  • the logical block address also known as the logical address (English full name: Logical Block Address, English abbreviation: LBA), refers to the storage address of the data block, which is not the actual address of the data block stored in the SSD, but the SSD is externally presented. The address of the visit.
  • LBA Logical Block Address
  • the physical block address also known as the physical address (English full name: Physical Block Address, English abbreviation: PBA) refers to the actual address of the data block stored in the SSD.
  • the reference count of the data block (reference count or reference counting) is applied to the storage system supporting the deduplication function to indicate the number of repetitions of the data block in the storage system. For storage systems that support deduplication, the same block does not need to be in storage. The system stores multiple times, so the number of repetitions of the data block in the storage system is equal to the number of data blocks received by the controller, but only one copy is actually stored.
  • the reference count of the data block may also indicate the number of times the physical address of the data block is referenced.
  • the valid data in the SSD refers to the data block pointed to by the logical address in the block of the SSD, that is to say, the physical address has a corresponding logical address.
  • Invalid data in the SSD usually refers to a data block that is not stored in the SSD block and has no logical address, that is, its physical address does not have a corresponding logical address.
  • FIG. 1 depicts a composition diagram of a storage system provided by an embodiment of the present invention.
  • the storage system illustrated in FIG. 1 includes a controller 11 and a plurality of flash memory devices 22.
  • the flash device 22 is a storage device that uses NAND Flash as a storage medium, and may include a solid state drive (full name: Solid State Device, SSD for short), and is also called a solid state drive (full name: Solid State Drive, SSD for short). Includes other storage.
  • the flash memory device 22 is described by taking an SSD as an example.
  • FIG. 1 is only an exemplary description, and is not limited to a specific networking manner, such as a cascading tree network or a ring network. As long as the controller 11 and the flash memory device 22 can communicate with each other.
  • Controller 11 may comprise any computing device known in the art, such as a server, desktop computer, or the like.
  • the controller 11 can receive the data object transmitted by the host (not shown in FIG. 1) and send a write data request to the flash device 22 such that the flash device 22 writes the data object carried in the write data request into its flash chip.
  • FIG. 2 is a schematic structural diagram of the controller 11 according to an embodiment of the present invention.
  • the controller 11 mainly includes a processor 118, a cache 120, a memory 122, a communication bus (abbreviated as bus) 126, and a communication interface 128.
  • the processor 118, the cache 120, the memory 122, and the communication interface 128 communicate with each other via the communication bus 126.
  • the processor 118 may be a central processing unit CPU, or an application specific integrated circuit (ASIC), or configured to implement the embodiments of the present invention. One or more integrated circuits. In the embodiment of the present invention, the processor 118 is configured to receive a data object from the host, and send the data object to the flash device 22 after a certain process.
  • ASIC application specific integrated circuit
  • Communication interface 128 is for communicating with a host or flash device 22.
  • the memory 122 is configured to store the program 124.
  • the memory 122 may include a high speed RAM memory, and may also include a non-volatile memory, such as at least one disk memory. It can be understood that the memory 122 can be a random access memory (full name: Random-Access Memory, RAM for short), a magnetic disk, a hard disk, an optical disk, a solid state hard disk (full name: Solid State Disk, SSD for short) or a non-volatile memory.
  • RAM Random-Access Memory
  • SSD Solid State Disk
  • a cache 120 is used to temporarily store data objects received from the host or data objects read from the flash device 22.
  • the cache 120 can be RAM, storage-level memory (full name: Storage-Class Memory, SCM for short), non-volatile storage (full name: Non-Volatile Memory, NVM for short), flash memory (Flash memory) or solid state hard disk (full name: A non-transitory machine readable medium that can store data, such as a Solid State Disk (SSD), is not limited herein.
  • the cache 120 and the memory 122 may be provided in combination or separately, which is not limited by the embodiment of the present invention.
  • Program 124 can include program code, the program code including computer operating instructions.
  • the program code can include a deduplication module and a stability determination module.
  • the deduplication module is configured to perform deduplication before transmitting data objects received from the host to the flash device 22.
  • the data object can be divided into several data blocks of the same size.
  • the size of each data block is 4KB.
  • the processor 118 determines whether the same data block is stored in each of the flash memory devices 22, and if not, writes the data block to the flash memory device 22 while setting the reference count of the data block to an initial value (for example, , equal to 1); if so, there is no need to write the saved data block to the flash device 22 again, but to increment the reference count of the data block by one.
  • the reference count reflects the stability of the data block to some extent. The higher the reference count, the higher the probability that it will be used for a relatively long period of time. The smaller the probability that a data block is deleted, the more stable the data block will be.
  • the flash device 22 For how to determine whether the flash device 22 stores the same data block, it is common practice to pre-store the fingerprint information of each data block stored in the flash device 22, wherein the fingerprint information of each data block is according to a preset hash function pair. Each data block is calculated and obtained. Then, calculating, according to the hash function, the data block to be stored, obtaining fingerprint information of the data block to be stored; matching the fingerprint information with fingerprint information of each data block saved in advance, if there is the same fingerprint The information indicates that the flash device 22 has saved the same data block, otherwise it indicates that the data block to be stored is not saved.
  • the fingerprint information of the respective data blocks may be stored in the cache 120 or may be stored in the flash memory device 22. In addition, other methods can be used to determine whether the flash device 22 stores the same data block, which will not be enumerated here.
  • the controller 11 can save the correspondence relationship between the fingerprint information of the data block and the LBA of the data block.
  • the LBA may be found according to the fingerprint information of the data block and the corresponding relationship.
  • the LBA of the data block may be sent to the controller 11 after the flash device 22 stores the data block, or may be an LBA allocated by the controller 11 for the data block, because the LBA is stored in the flash device 22.
  • the flash device 22 can write the data block into the storage space corresponding to the PBA according to the allocated LBA.
  • the reference count can be a reference factor in determining the stability of the data block, and another reference factor that can affect the stability of the data block is the long time that the data block is stored in the flash memory device 22. degree.
  • the length of time that the data block is stored in flash memory device 22 may be equal to the difference between the current time of the system minus the time the data block was written to the flash memory device.
  • the time at which the data block is written to the flash memory device may be part of the metadata of the data block, stored in the cache 120 or the flash memory device 22. It can be understood that the longer the time period in which the data block is stored in the flash memory device 22, the more stable the data block is; on the contrary, the more unstable.
  • the length of time may also be a value reflecting the length of time that the data block is stored in the flash memory device 22, and is not strictly equal to the current time of the system minus the time when the data block is written into the flash memory device. The difference obtained.
  • the main function of the stability determination module is to determine the length based on the reference count, or based on the length of time in which the data block is stored in the flash memory device 22, or based on the reference count and the length of time the data block is stored in the flash memory device 22.
  • the stability of the data block resulting in a stable level of the data block.
  • the stability level is a value that reflects the stability of the data block. The larger the value, the higher the stability, and vice versa. Alternatively, the stability level can also be defined as the smaller the value, the higher the stability, and vice versa.
  • the controller 11 may send the LBA and the stability level of the data block to the flash memory device 22, so that the flash memory device 22 stores the same level of data blocks in one. Or multiple blocks.
  • the structure and function of the flash memory device 22 will be described below.
  • FIG. 3A is a schematic structural diagram of a flash memory device 22 according to an embodiment of the present invention.
  • the flash memory device 22 is described by taking an SSD as an example.
  • the flash memory device 22 includes a main controller 220 and a storage medium 221.
  • the main controller 220 is configured to receive an I/O request sent by the controller 11 to the flash device 22, or other information, such as a logical address and a stable level of the data block, and the main controller 220 is further configured to execute the received I.
  • the /O request for example, writes a data block carried in the I/O request to the storage medium 221, or reads the data block from the storage medium 221 and returns it to the controller 11.
  • the main controller 220 here is the main controller of the SSD.
  • the storage medium 221 is usually composed of a plurality of flash chips. Each flash chip includes a number of blocks. Each block includes a number of pages, and the main controller 220 writes in units of pages when writing data blocks into the block.
  • NAND Flash Since NAND Flash has an erasing feature, the data stored in the block is not directly modified like a normal mechanical hard disk. When it is necessary to modify the data in a block, it is necessary to find an idle block to write the modified data to the free block, and then the data in the original block becomes invalid data. As more and more data is stored in the SSD, fewer free blocks are available, so it is necessary to garbage collect the SSDs to generate free blocks that are available for use. In this embodiment, when garbage collection is performed, a block containing the most invalid data is usually selected in order to be collected.
  • the trigger condition for garbage collection is that the number of free blocks included in the flash chip is lower than a first threshold, and the first threshold may be an integer greater than 10 and less than 100.
  • Patrol inspection refers to the operation of periodically shifting the data stored in the flash chip to prevent data loss caused by some blocks in the flash chip being erased for a long time.
  • NAND Flash its ability to maintain data can only be maintained for a certain period of time, so it is necessary to periodically move the data stored in it to other blocks.
  • the blocks that have not been erased for the longest time are usually selected in order, the valid data in the block is moved to the free block, and the original block is erased.
  • the trigger condition of the patrol may be when the preset patrol period arrives.
  • the data movement inside the SSD mainly refers to the movement of the valid data in the block during garbage collection or inspection. It can be understood that for the block to be recycled, if there is less valid data, the less data needs to be moved. Therefore, the object of the present invention is mainly to centrally store data blocks in an SSD according to a stable level, so that the effective data moved during the subsequent garbage collection operation is as small as possible.
  • FIG. 3B is a schematic structural diagram of the main controller 220 in the flash memory device 22 according to the embodiment of the present invention.
  • the main controller 220 mainly includes a processor 218, a memory 230, a communication bus (abbreviated as bus) 226, and a communication interface 228.
  • processor 218, cache 230, and communication interface 228 communicate with one another via communication bus 226.
  • the processor 218 may be a central processing unit CPU, or an Application Specific Integrated Circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present invention.
  • the processor 218 can be configured to receive information such as an I/O request from the controller 11, a logical address of the data block, and a stable level of the data block.
  • the processor 218 is further configured to perform I/O. request.
  • the communication interface 228 is configured to communicate with the controller 11 and the storage medium 221.
  • the cache 230 (Cache) is used to buffer information received from the controller 11, such as the logical address of the data block and the stability level of the data block, and the like.
  • the cache 230 may be a non-transitory or transitory machine readable medium that can store data, such as a RAM, an SCM, an NVM, and the like, which is not limited herein.
  • the cache 230 may also be placed outside the main controller 220 in some application scenarios.
  • a mapping table may be saved in the cache 230 for holding the correspondence between the LBA of the data block received from the controller 11 and the stable level of the data block.
  • the cache 230 also stores a mapping table for recording the mapping relationship between the LBA and the PBA.
  • the correspondence between the LBA and the stability level can be increased based on the mapping table. .
  • a plurality of arrays are saved in the cache 230, each array corresponding to a stable level, and the logical addresses of the plurality of data blocks corresponding to the stable level may be saved in the array.
  • the cache 230 may store the logical addresses of the data blocks of the same stable level in a buffer space of the cache 230.
  • the controller 11 may send the buffer area division information to the flash memory device 22 in advance, and the cache area division information includes no The same stability level (for example, 10 stable levels of 1-10 respectively), after receiving the cache area division information, the flash device 22 divides the cache 230 into 10 cache areas according to 10 stable levels, each cache. The area corresponds to a stable level, and is specifically used to store the logical address of the data block corresponding to the stable level.
  • the controller 11 may transmit the logical address of the data block and the stable level of the data block to the flash memory device 22 without directly transmitting to the flash memory device 22 the buffer area division information.
  • the flash memory device 22 divides a buffer area in the cache 230 according to the stability level of the data block, and associates the buffer area with the stable level (saves a correspondence between the cache area and the stable level), Thereafter, the divided cache area may be dedicated to save a logical address of the data block corresponding to the stable level.
  • the logical addresses of the data blocks with the same stable level can be collectively stored in a buffer space of the cache 230.
  • FIG. 4 is a schematic flowchart diagram of the method for identifying the stability of a data block. The method may be applied to the storage system shown in FIG. 1 and the controller 11 shown in FIG. Processor 118 in controller 11. The method includes:
  • Step S201 reading information of the first data block from the cache 120, the information of the first data block includes a reference count of the first data block, or a time when the first data block is saved in the flash memory device a length, or a reference count of the first data block and a length of time in which the first data block is stored in the flash memory device, wherein a reference count of the first data block is equal to the controller receiving the first data The number of blocks.
  • the first data block is one of a plurality of data blocks stored in the flash memory device 22.
  • the first data block is taken as an example for description.
  • the first data block in this embodiment refers to a data block included in the valid data. For invalid data, the reference count of the data block included therein is 0, and the controller 11 will information the data block whose reference count is 0. Slow Save 120 to delete.
  • the trigger condition of step S201 may be set such that the size of all data blocks received by the controller 11 exceeds a preset capacity threshold, or a preset time interval arrives, or one of the above two trigger conditions is satisfied.
  • the preset capacity threshold may be equal to the available capacity presented by the storage system shown in FIG. 1 to the user, or an integer multiple of the available capacity.
  • Step S202 Determine a stability level of the first data block according to the information of the first data block.
  • the controller 11 can preset the number of stable levels.
  • an implementation manner is: since each data block saved in the flash device 22 has a reference count, the reference counts can be divided into multiple reference count intervals, wherein each reference count interval corresponds to one Stability level. For example, assuming 10 stable levels are set in advance, the correspondence between the reference count interval and the stable level can be as shown in Table 1:
  • determining the stability level of the first data block according to the information of the first data block may be: determining a first reference counting area according to a reference count of the first data block.
  • the reference count of the first data block is located in the first reference count interval; determining the stability level of the first data block according to the first reference count interval and the correspondence relationship shown in Table 1. For example, if the reference count of the first data block is 3, then its corresponding stability level is 9.
  • another implementation manner is: dividing a time length of storing the plurality of data blocks in the flash memory device into a plurality of time intervals, wherein each time interval corresponds to one stable level. For example, if 10 stable levels are preset, the correspondence between the time interval and the stable level can be as shown in Table 2:
  • determining the stability level of the first data block according to the information of the first data block may be: determining a first time interval according to a length of time in which the first data block is stored in the flash memory device, where The length of time in which the first data block is stored in the flash memory device is located in the first time interval; and the stability level of the first data block is determined according to the first time interval and the correspondence relationship shown in Table 2. For example, the length of time that the first data block is saved in the flash memory device is 12, and its corresponding stable level is 7.
  • the multiple time lengths are divided into at least two time intervals, and the multiple reference counts are also divided into at least two reference counting intervals; the time interval, the reference counting interval, and the stability level three.
  • the time length may be greater than the threshold T as a criterion for dividing into two time intervals, one time interval is (0, T), and the other time interval is [T, + ⁇ ).
  • the stability level of the data block whose time length belongs to [T, + ⁇ ) is greater than the stability level of the data block whose time length belongs to (0, T), and the reference count is further divided into multiple reference count intervals in each time interval.
  • the data blocks belonging to the same reference count interval have the same level of stability. For data blocks belonging to different reference count intervals, the stability level of the data block with a large reference count is greater than the stability level of the data block with a small reference count. Assuming 10 stable levels are set in advance, the correspondence between time interval, reference counting interval and stability level can be as shown in Table 3:
  • multiple reference counts can be divided into two reference count intervals, one reference count interval is (0, 10) and the other reference count interval is [10, + ⁇ ).
  • the stability level of the data block whose reference count belongs to [10, + ⁇ ) is greater than the stability level of the data block whose reference count belongs to (0, 10).
  • a plurality of time lengths are further divided into a plurality of time intervals, and the data blocks belonging to the same time interval have the same stable level.
  • the stability level of the data block with a large time length is greater than the stability level of the data block with a small time length. Assuming 10 stable levels are set in advance, the correspondence between time interval, reference counting interval and stability level can be as shown in Table 4:
  • determining the stability level of the first data block according to the information of the first data block may be: determining a first reference counting interval according to a reference count of the first data block, where the first data block is a reference count is located in the first reference count interval; determining a first time interval according to a length of time in which the first data block is saved in the flash memory device, where the first data block is located at a time length of the flash memory device And determining, according to the first reference counting interval, the first time interval, the reference time interval, the correspondence between the time interval and the stability level, the stability level of the first data block. It can be understood that whether the correspondence relationship shown in Table 3 or the correspondence relationship shown in Table 4 is utilized, the stability level can be determined as long as the time length of the first data block is saved in the flash memory device and the reference count is determined. .
  • the controller 11 processes each data block saved in the cache 120, the task is completed, and the length of time for storing each data block in the flash memory device is reduced. Go to a fixed value so that the next time the task starts, the length of time can start to increase with a smaller base.
  • Step S203 Send the logical address of the first data block and the stability level of the first data block to the flash memory device 22.
  • the controller 11 may separately send the logical address and the stable level of the first data block to the flash device 22, and may also send the logical address and the stable level of the first data block together with the logical address and the stability level of other data blocks.
  • the logical address and stability level can be carried to the flash device 22 in a custom command.
  • the controller 11 may according to (1) the reference count of the first data block, and the correspondence between the reference count of the data block and the stability level, or (2) the first data block is saved in the The length of time of the flash memory device, and the correspondence between the length of time of the data block stored in the flash memory device and the stable level, or (3) the reference count of the first data block and the first data block being stored in the flash memory device
  • the length of time, and the reference count of the data block, the correspondence between the length of time of the data block and the stability level of the data block, determining the stability level of the first data block, the stability level may reflect the stability of the data block, And transmitting the stable level and logical address of the data block to the flash memory device 22, so that the flash memory device 22 centrally stores the data blocks of the same stable level.
  • FIG. 5 is a schematic flowchart diagram of the method for storing data in a flash memory device. The method may be applied to the storage system shown in FIG. 1 and the flash memory device 22 shown in FIG. 3A and FIG. 3B. Its execution body is the processor 218 in the flash memory device 22. The method includes:
  • Step S301 Acquire a stability level corresponding to the target logical address, where the stability level is used to indicate the stability of the data block.
  • the flash memory device 22 receives a plurality of logical addresses sent by the controller 11 and a stable level corresponding to the logical addresses before step S301, and may store the plurality of logical addresses and their corresponding stable levels in the cache. 230.
  • the target logical address is one of a plurality of logical addresses stored in the cache 230.
  • the stable level corresponding to the target logical address may be obtained from the cache 230.
  • Step S302 Write, according to the stability level corresponding to the target logical address, the data block corresponding to the target logical address into the block corresponding to the stable level.
  • the correspondence between the blocks in the flash chip and the stability level can be established.
  • the data block corresponding to the target logical address can be read from the original block and written into the block corresponding to the stable level.
  • the correspondence between the block and the stable level in the flash chip may be pre-established, or may be recorded after the first time a block of data or a plurality of blocks of the same stable level are written into a block. The correspondence between blocks.
  • the data block corresponding to the target logical address is read from the original block.
  • the cache 230 of the flash device 22 or the flash chip stores a mapping table, where the mapping table is used to save each data. The correspondence between the logical address and the physical address of the block, so that the data block can be read from the storage space where the corresponding physical address is located according to the logical address received in step S301 and the mapping table.
  • data blocks of the same stable level can be stored in one block. Then, for a block storing a data block with a higher stable level, the stored data block becomes less likely to be invalid data. As a whole, the block does not contain invalid data or only a small amount of invalid data, such a block.
  • a block having a relatively high utilization rate does not collect such a block when garbage collection is performed on the flash memory device 22; it is highly likely that a stored data block becomes invalid data for a block storing a data block having a lower stable level. Assuming that most of the data in a block or most of the data becomes invalid data, then correspondingly, the block contains less valid data, less data needs to be migrated during garbage collection, and the write amplification is reduced.
  • the effect of the embodiment mainly reflects that the effective data moved during the subsequent garbage collection is reduced. It can be seen that whether the block storing the data block with higher stability level or the block storing the data block with lower stability level can reduce the write amplification of the flash memory device 22, thus extending the flash memory device 22 to some extent. Life expectancy.
  • a preferred embodiment is to combine the steps S301-S302 described above with the garbage collection operation, that is, when the flash memory device 22 needs to perform garbage collection, according to the steps S301-S302.
  • the method performs garbage collection. Specifically, when it is determined that the number of free blocks included in the flash chip is lower than the first threshold, the blocks containing the most invalid data are sequentially searched from the flash chip, and the to-be-moved is obtained from the blocks. The logical address of the data block is then searched according to the logical address in the correspondence between the logical address and the stable level, and the stable level corresponding to the logical address is acquired (in combination with the embodiment shown in FIG. 5, the logical address That is, the target logical address), and then the data block corresponding to the logical address is written into the corresponding block.
  • Another preferred embodiment is to combine the steps S301-S302 described above with the patrol operation, that is, when the flash memory device 22 needs to perform the patrol, according to the manner described in steps S301-S302.
  • Performing a patrol Specifically, when the preset patrol period arrives, the blocks that have not been erased for the longest time are sequentially searched from the flash chip, and the logical addresses of the data blocks to be moved are obtained from the blocks, and then Searching, according to the logical address, a correspondence between the logical address and the stable level, and acquiring a stable level corresponding to the logical address (in conjunction with the embodiment shown in FIG. 5, the logical address is the target logical address) And writing the data block corresponding to the logical address into the corresponding block.
  • the logical address sent by the controller 11 received by the flash memory device 22 is the logical address of the data block included in the valid data (refer to the description of step S201 in the embodiment shown in FIG. 4), so the flash memory device 22 The received data block corresponding to the logical address sent by the controller 11 needs to be moved.
  • FIG. 6 is a schematic flowchart of a method for storing data in a flash memory device, and the method can be applied to FIG. In the storage system.
  • steps S101 to S104 describe the process in which the controller 11 stores the received data block in the flash memory device 22. Steps S101 to S104 may be applied to the controller 11 shown in FIG. 2, the execution subject of which is the processor 118 in the controller 11.
  • step S101 the controller 11 receives a write data request sent by the host, where the write data request includes a data object and address information of the data object, and the address information may include a logical unit number (English full name: Logical Unit Number) , English abbreviation: LUN) ID and the starting address offset of the LUN; or the ID of the file and the starting address offset of the file, etc.; or when the storage system has multiple file systems, the address information can This includes the file system ID, the file ID, and the file's starting address offset.
  • the address information may include a logical unit number (English full name: Logical Unit Number) , English abbreviation: LUN) ID and the starting address offset of the LUN; or the ID of the file and the starting address offset of the file, etc.; or when the storage system has multiple file systems, the address information can This includes the file system ID, the file ID, and the file's starting address offset.
  • the data object is block data or a file to be written to the flash memory device 22.
  • step S102 the controller 11 divides the data object into a plurality of data blocks of the same size.
  • step S103 the controller 11 determines one target data block from the plurality of data blocks, and determines whether the target data block has been saved in the flash memory device 22.
  • the controller 11 transmits the split data block to the flash memory device 22 for storage, it is necessary to sequentially determine whether each data block has been saved in the flash memory device 22, and if so, it is not necessary to save again.
  • the determination method refer to the previous description of the function of the deduplication module, and details are not described herein again.
  • step S104 if the same data block as the target data block is not stored in the flash memory device 22, the controller 11 transmits the target data block to the flash memory device 22 for storage, and the reference count of the target data block An initial value, and the reference count of the target data block and the target data block are written into the logical address of the flash device 22 in the cache 120; if the flash device 22 is stored in the same manner as the target data block The data block is incremented by the reference count of the same data block as the target data block.
  • the logical address of the target data block written to the flash memory device 22 may be a logical address allocated by the controller 11 for the target data block, and after the controller 11 allocates, the logical address is sent to the flash memory device 22, and the flash memory
  • the device 22 searches for the physical address corresponding to the logical address according to the correspondence between the logical address and the physical address, and writes the target data block into the storage space corresponding to the physical address; or
  • the controller 11 can split the received data object into a plurality of data blocks and store them in the flash memory device 22. It can be understood that since the controller 11 has the function of data deduplication, the data blocks stored in the flash memory device 22 are different data blocks. The information of these multiple different data blocks can be stored in the cache 120.
  • Steps S105 to S107 describe the process in which the controller 11 recognizes the stabilization level of each data block stored in the flash memory device 22 and transmits it to the flash memory device 22. Steps S105 - S107 can be applied to the controller 11 shown in FIG. 2, the execution subject of which is the processor 118 in the controller 11. It should be noted that the process of identifying the stable level is not in the order of the process of storing the received data block in the flash memory device 22 described in steps S101 to S104.
  • step S105 when the task is triggered, the controller 11 reads the information of the target data block from the cache 120.
  • the task herein refers to the task of the controller 11 identifying the level of stability of each data block in the flash device 22.
  • the controller 11 may scan information of the plurality of data blocks and sequentially read Information for each data block.
  • the processing manner of the target data block is still taken as an example. It can be understood that other data blocks are processed in a similar manner to the target data block.
  • the information of the target data block includes a reference count of the target data block, or a length of time in which the target data block is saved in the flash memory device, or a reference count of the target data block and the target data block are saved in The length of time of the flash memory device.
  • step S106 the controller 11 determines the stabilization level of the target data block based on the information of the target data block.
  • Step S106 is similar to step S202 in the embodiment shown in FIG. 5, please refer to the description of step S202.
  • step S107 the controller 11 transmits the logical address of the target data block and the stable level of the target data block to the flash memory device 22.
  • the controller 11 can transmit the logical addresses of the plurality of data blocks and the stabilization level to the flash memory device 22 in the manner described in steps S105 to S107.
  • Steps S108 to S110 describe a process in which the flash memory device 22 stores the data blocks of the same stable level after receiving the stable level of the data block transmitted by the controller 11.
  • Steps S108 to S110 may be applied to the flash memory device (for example, SSD) shown in FIGS. 3A and 3B, and the execution subject thereof is the processor 218 in the flash memory device 22.
  • step S108 the flash memory device 22 stores the logical address of the plurality of data blocks and a stabilization level corresponding to the logical address.
  • a saving mode is to establish a mapping table in the cache 230 of the flash memory device 22 for storing the correspondence between the logical address of the data block received from the controller 11 and the stable level of the data block.
  • Another way to save is to save multiple arrays in the cache 230, each array corresponding to a stable level.
  • the logical addresses of the plurality of data blocks are respectively stored in their corresponding arrays.
  • another storage method is to divide the cache 230 into a plurality of cache areas in advance.
  • Each cache area corresponds to a stable level.
  • the logical addresses of the plurality of data blocks are respectively recorded in their corresponding cache areas.
  • step S109 the flash memory device 22 determines whether the number of logical addresses corresponding to the same stable level reaches a preset threshold, and if so, reads the data block according to the logical address corresponding to the same stable level.
  • the logical address corresponding to the same stable level may include the logical address of the target data block in steps S105-S107.
  • the trigger condition for data block transfer and FIG. 5 are shown.
  • the implementation manner is different, and the triggering condition is that the number of logical addresses corresponding to the same stable level saved in the cache reaches a preset threshold.
  • the mapping table saved in the cache 230 it is determined according to the mapping table saved in the cache 230 whether the number of logical addresses having the same stable level reaches a preset threshold.
  • the second implementation manner is to determine whether the number of logical addresses saved in an array in the cache 230 reaches a preset threshold.
  • the third implementation manner is to determine whether the number of logical addresses saved in one cache area in the cache 230 reaches a preset threshold.
  • the preset threshold may be set to a ratio between the capacity of the block and the size of the data block. According to this implementation manner, after the number of logical addresses reaches the threshold, the multiple logical addresses correspond to The data block just fills up a free block.
  • step S110 the flash memory device 22 looks up a free block and writes the read data block into a free block.
  • data blocks of the same stable level may be sequentially stored in one or more free blocks.
  • the preset threshold may also be set to a value greater than 2, but smaller than the ratio between the capacity of the block and the size of the data block.
  • the flash memory device 22 concentrates the data blocks of the same stable level in one or more free blocks, so that the effective data moved during the subsequent garbage collection operation is reduced, thereby reducing the writing. Enlarging, to a certain extent, extends the life of the flash memory device 22.
  • the embodiment of the present invention further provides an apparatus 40 for identifying the stability of a data block, the apparatus 40 being located in the controller 11, the controller being located in the storage system shown in FIG. 1, the storage system including a flash memory device 22, the first data block is stored in the flash memory device 22; as shown in FIG. 7, the device 40 includes:
  • a storage module 401 configured to save information of the first data block, where the information of the first data block includes a reference count of the first data block, or a time when the first data block is saved in the flash memory device a length, or a reference count of the first data block and a length of time in which the first data block is stored in the flash memory device, wherein a reference count of the first data block is equal to the controller receiving the first data The number of blocks;
  • the reading module 402 is configured to read information of the first data block from the storage module
  • a determining module 403 configured to: according to (1) a reference count of the first data block, and a correspondence between a reference count of the data block and a stable level, or (2) the first data block is saved in the flash memory device a length of time, and a correspondence between a length of time in which the data block is stored in the flash memory device and a stable level, or (3) a reference count of the first data block and a length of time in which the first data block is stored in the flash memory device, And a reference count of the data block, the correspondence between the length of time of the data block and the stability level of the data block is determined, and determining a stability level of the first data block;
  • the sending module 404 is configured to send the logical address of the first data block and the stability level of the first data block to the flash memory device 22.
  • the means 40 for identifying the stability of the data block may be according to (1) a reference count of a data block, and a correspondence between a reference count of the data block and a stable level, or (2) a length of time in which the first data block is stored in the flash memory device, and a length of time in which the data block is stored in the flash memory device a correspondence with a stable level, or (3) a reference count of the first data block and a length of time in which the first data block is stored in the flash memory device, and a reference count of the data block, the data block being saved in the flash memory device Determining a stability level of the first data block, the stability level may reflect stability of the data block, and transmitting the stable level and the logical address of the data block to the flash memory device 22 The flash device 22 causes the data blocks of the same stable level to be collectively stored.
  • the correspondence between the reference count of the data block and the stability level includes: a correspondence between the reference counting interval and the stability level;
  • the determining module 403 is specifically configured to determine, according to the reference count of the first data block, a first reference counting interval, where a reference count of the first data block is located in the first reference counting interval; The first reference count interval, and the correspondence between the reference count interval and the stability level determine a stability level of the first data block.
  • the correspondence between the length of time and the stability level of the data block stored in the flash memory device includes: a correspondence between a time interval and a stability level;
  • the determining module 403 is specifically configured to determine, according to a length of time that the first data block is saved in the flash memory device, a first time interval, where a length of time in which the first data block is stored in the flash memory device is located In the first time interval, determining a stability level of the first data block according to the first time interval and a correspondence between the time interval and the stability level.
  • the reference count of the data block, the correspondence between the length of time and the stability level of the data block stored in the flash memory device includes: a reference counting interval, a correspondence between the time interval and the stability level. relationship;
  • the determining module 403 is specifically configured to determine, according to the reference count of the first data block, a first reference counting interval, where a reference count of the first data block is located in the first reference counting interval; Determining the first time zone by the length of time in which the first data block is stored in the flash memory device Between the first time interval, the first time interval, and the reference counting interval The correspondence between the interval and the stability level determines the stability level of the first data block.
  • each module of the device 40 for a specific implementation manner of each module of the device 40, reference may be made to the method embodiment shown in FIG. 5 or FIG. 7 , and details are not described herein again.
  • the embodiment of the present invention further provides a device 50 for storing data in a flash memory device.
  • the device 50 is located in a main controller of the flash memory device 22.
  • the flash memory device 22 stores a block.
  • the device 50 includes:
  • the obtaining module 501 is configured to acquire a stability level corresponding to the target logical address, where the stability level is used to indicate stability of the data block;
  • the migrating module 502 is configured to write, according to the stability level corresponding to the target logical address, a data block corresponding to the target logical address into a block corresponding to the stable level.
  • data blocks of the same stable level can be stored in one block.
  • the obtaining module 501 is further configured to search, in the flash memory chip, a block that contains the most invalid data, where the block that contains the most invalid data includes a data block corresponding to the target logical address.
  • the obtaining module 501 is further configured to search, in the flash chip, a block that has not been erased for a long time, and the block that is not erased in the longest time includes the target logical address corresponding to Data block.
  • the device 50 further includes a storage module 503, where the storage module 503 stores a logical address, and the stable level corresponding to the logical address is the same as the stable level corresponding to the target logical address;
  • the obtaining module 501 is configured to obtain a stability level corresponding to the target logical address when the number of the logical addresses saved in the cache reaches a preset threshold.
  • the preset threshold is equal to the quotient of the capacity of the block divided by the size of the data block.
  • the embodiment of the invention further provides a computer program product for data processing, comprising a computer readable storage medium storing program code, the program code comprising instructions for executing the method flow described in any one of the foregoing method embodiments.
  • the foregoing storage medium includes: a USB flash drive, a mobile hard disk, a magnetic disk, an optical disk, a random access memory (RAM), a solid state disk (SSD), or a nonvolatile.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)

Abstract

一种控制器（11），包括处理器（118）、缓存（120）和通信接口（128），所述处理器（118），用于从所述缓存（120）中读取第一数据块的信息；根据所述第一数据块的引用计数和所述第一数据块保存在闪存装置（22）的时间长度，和数据块的引用计数，数据块保存在闪存装置（22）的时间长度与稳定级别的对应关系，确定所述第一数据块的稳定级别，所述稳定级别用于表示数据块的稳定性；将所述第一数据块的逻辑地址以及所述第一数据块的稳定级别通过所述通信接口（128）发送给所述闪存装置（22），使得闪存装置（22）将相同稳定级别的数据块进行集中存储。

Description

一种控制器、闪存装置、识别数据块稳定性的方法以及在闪存装置中存储数据的方法 技术领域
本发明实施例涉及存储技术领域，特别是一种控制器、闪存装置、识别数据块稳定性的方法以及在闪存装置中存储数据的方法。
背景技术
Flash Memory(闪存)装置是一种非易失性存储器，其存储介质是NAND Flash，具有断电后数据不消失的特点，因此，被广泛的作为外部和内部存储器使用。以NAND Flash为存储介质的闪存装置可能是固态硬盘(全称：Solid State Device，简称：SSD)，又名固态驱动器(全称：Solid State Drive，简称：SSD)，还可能是其他存储器。
一个SSD通常由多个闪存芯片组成，每个闪存芯片包含若干个块(block)。由于NAND Flash具有擦除特性，保存在block中的数据不会像普通机械硬盘那样直接被修改。当需要对某个逻辑地址指向的数据进行修改时，需要查找一个空闲的block将修改后的数据写入该空闲的block，然后将所述逻辑地址指向新写入的数据，那么，原来的block中的数据则变为无效数据。对于SSD而言，有效数据是指block中保存的有逻辑地址指向的数据，这部分数据可能会被读取；无效数据是指block中保存的没有逻辑地址指向的数据，这部分数据不可能会被读取。
随着SSD中存储的数据越来越多，可利用的空闲的block越来越少，因此有必要对SSD进行垃圾回收以便产生可供利用的空闲的block。垃圾回收是指将block中的有效数据搬移到空闲的block中去，然后将旧的block进行擦除，经过擦除之后的block又可以作为空闲的block再次写入数据。通常情况下，SSD在进行垃圾回收时，会查找包含无效数据较多的block，因为包含无效数据较多的block包含的有效数据较少，那么需要搬移到空闲block 的有效数据会较少。在SSD的寿命跟NAND Flash的擦除次数相关的情况下，垃圾回收时搬移的数据越少，SSD的写放大就越小。然而，由于不同block保存的数据被修改的可能性大致相当，因此每个block包含的无效数据的多少也无明显差别。
发明内容
本发明实施例第一方面提供了一种控制器，所述控制器位于支持重复数据删除的存储系统中，所述存储系统包括闪存装置，所述闪存装置中保存有第一数据块；所述控制器包括处理器、缓存和通信接口；所述通信接口，用于与所述闪存装置通信；所述缓存中保存有所述第一数据块的信息，所述第一数据块的信息包括所述第一数据块的引用计数，或所述第一数据块保存在所述闪存装置的时间长度，或所述第一数据块的引用计数和所述第一数据块保存在所述闪存装置的时间长度，其中所述第一数据块的引用计数等于所述控制器接收所述第一数据块的数量。所述处理器，用于从所述缓存中读取所述第一数据块的信息。然后，根据(1)所述第一数据块的引用计数，和数据块的引用计数与稳定级别的对应关系，或(2)所述第一数据块保存在所述闪存装置的时间长度，和数据块保存在闪存装置的时间长度与稳定级别的对应关系，或(3)所述第一数据块的引用计数和所述第一数据块保存在所述闪存装置的时间长度，和数据块的引用计数，数据块保存在闪存装置的时间长度与稳定级别的对应关系，确定所述第一数据块的稳定级别，所述稳定级别用于表示数据块的稳定性。再将所述第一数据块的逻辑地址以及所述第一数据块的稳定级别通过所述通信接口发送给所述闪存装置。
在第一方面的第一实施方式中，所述数据块的引用计数与稳定级别的对应关系包括：引用计数区间与稳定级别的对应关系。所述处理器，具体用于根据所述第一数据块的引用计数确定第一引用计数区间，所述第一数据块的引用计数位于所述第一引用计数区间中，以及根据所述第一引用计数区间，以及引用计数区间与稳定级别的对应关系确定所述第一数据块的稳定级别。
在第一方面的第二种实施方式中，所述数据块保存在闪存装置的时间长度与稳定级别的对应关系包括：时间区间与稳定级别的对应关系。所述处理器，具体用于根据所述第一数据块保存在所述闪存装置的时间长度确定第一时间区间，所述第一数据块保存在所述闪存装置的时间长度位于所述第一时间区间中，以及根据所述第一时间区间，以及时间区间与稳定级别的对应关系确定所述第一数据块的稳定级别。
在第一方面的第三种实施方式中，所述数据块的引用计数，数据块保存在闪存装置的时间长度与稳定级别的对应关系包括：引用计数区间，时间区间与稳定级别的对应关系。所述处理器，具体用于根据所述第一数据块的引用计数确定第一引用计数区间，所述第一数据块的引用计数位于所述第一引用计数区间中。然后，根据所述第一数据块保存在所述闪存装置的时间长度确定第一时间区间，所述第一数据块保存在所述闪存装置的时间长度位于所述第一时间区间中；再根据所述第一引用计数区间，所述第一时间区间，以及所述引用计数区间，时间区间与稳定级别的对应关系确定所述第一数据块的稳定级别。
本发明实施例第二方面提供了一种闪存装置，包括主控制器和闪存芯片，所述闪存芯片包括块，所述主控制器包括处理器。其中，所述处理器，用于获取目标逻辑地址对应的稳定级别，所述稳定级别用于表示数据块的稳定性；然后，根据所述目标逻辑地址对应的稳定级别，将所述目标逻辑地址对应的数据块写入所述稳定级别对应的块中。
在第二方面的第一种实施方式中，所述处理器，还用于在所述闪存芯片中查找包含无效数据最多的块，所述包含无效数据最多的块包括所述目标逻辑地址对应的数据块。
在第二方面的第二种实施方式中，所述处理器，还用于在所述闪存芯片中查找最长时间内未被擦除的块，所述最长时间内未被擦除的块包括所述目标逻辑地址对应的数据块。
在第二方面的第三种实施方式中，所述主控制器还包括缓存；所述处理器，具体用于确定所述缓存中保存的逻辑地址的个数达到预设阈值时，获取所述目标逻辑地址对应的稳定级别，其中，所述逻辑地址对应的稳定级别与所述目标逻辑地址对应的稳定级别相同。
本发明实施例第三方面提供了一种识别数据块的稳定性的方法，所述方法应用于控制器中，所述控制器位于支持重复数据删除的存储系统中，所述存储系统包括闪存装置，所述闪存装置中保存有第一数据块；所述控制器包括处理器、缓存和通信接口；所述通信接口，用于与所述闪存装置通信；所述缓存中保存有所述第一数据块的信息，所述第一数据块的信息包括所述第一数据块的引用计数，或所述第一数据块保存在所述闪存装置的时间长度，或所述第一数据块的引用计数和所述第一数据块保存在所述闪存装置的时间长度，其中所述第一数据块的引用计数等于所述控制器接收所述第一数据块的数量；所述方法由所述处理器执行。所述方法包括：从所述缓存中读取所述第一数据块的信息，然后，根据(1)所述第一数据块的引用计数，和数据块的引用计数与稳定级别的对应关系，或(2)所述第一数据块保存在所述闪存装置的时间长度，和数据块保存在闪存装置的时间长度与稳定级别的对应关系，或(3)所述第一数据块的引用计数和所述第一数据块保存在所述闪存装置的时间长度，和数据块的引用计数，数据块保存在闪存装置的时间长度与稳定级别的对应关系，确定所述第一数据块的稳定级别，所述稳定级别用于表示数据块的稳定性。再将所述第一数据块的逻辑地址以及所述第一数据块的稳定级别通过所述通信接口发送给所述闪存装置。
在第三方面的第一种实施方式中，所述数据块的引用计数与稳定级别的对应关系包括：引用计数区间与稳定级别的对应关系。所述根据(1)所述第一数据块的引用计数，和数据块的引用计数与稳定级别的对应关系，确定所述第一数据块的稳定级别包括：根据所述第一数据块的引用计数确定第一引用计数区间，所述第一数据块的引用计数位于所述第一引用计数区间中； 以及根据所述第一引用计数区间，以及引用计数区间与稳定级别的对应关系确定所述第一数据块的稳定级别。
在第三方面的第二种实施方式中，所述数据块保存在闪存装置的时间长度与稳定级别的对应关系包括：时间区间与稳定级别的对应关系。所述根据(2)所述第一数据块保存在所述闪存装置的时间长度，和数据块保存在闪存装置的时间长度与稳定级别的对应关系，确定所述第一数据块的稳定级别包括：根据所述第一数据块保存在所述闪存装置的时间长度确定第一时间区间，所述第一数据块保存在所述闪存装置的时间长度位于所述第一时间区间中，以及根据所述第一时间区间，以及时间区间与稳定级别的对应关系确定所述第一数据块的稳定级别。
在第三方面的第三种实施方式中，所述数据块的引用计数，数据块保存在闪存装置的时间长度与稳定级别的对应关系包括：引用计数区间，时间区间与稳定级别的对应关系。所述根据(3)所述第一数据块的引用计数和所述第一数据块保存在所述闪存装置的时间长度，和数据块的引用计数，数据块保存在闪存装置的时间长度与稳定级别的对应关系，确定所述第一数据块的稳定级别包括：根据所述第一数据块的引用计数确定第一引用计数区间，所述第一数据块的引用计数位于所述第一引用计数区间中；然后，根据所述第一数据块保存在所述闪存装置的时间长度确定第一时间区间，所述第一数据块保存在所述闪存装置的时间长度位于所述第一时间区间中；再根据所述第一引用计数区间，所述第一时间区间，以及所述引用计数区间，时间区间与稳定级别的对应关系确定所述第一数据块的稳定级别。
本发明实施例第四方面提供了一种在闪存装置中存储数据的方法，所述闪存装置包括主控制器和闪存芯片，所述闪存芯片包括块，所述主控制器包括处理器；所述方法由所述处理器执行。所述方法包括：获取目标逻辑地址对应的稳定级别，所述稳定级别用于表示数据块的稳定性。然后，根据所述目标逻辑地址对应的稳定级别，将所述目标逻辑地址对应的数据块写入所述 稳定级别对应的块中。
在第四方面的第一种实施方式中，所述方法还包括：在所述闪存芯片中查找包含无效数据最多的块，所述包含无效数据最多的块包括所述目标逻辑地址对应的数据块。
在第四方面的第二种实施方式中，所述方法还包括：在所述闪存芯片中查找最长时间内未被擦除的块，所述最长时间内未被擦除的块包括所述目标逻辑地址对应的数据块。
在第四方面的第三种实施方式中，所述主控制器还包括缓存；所述获取目标逻辑地址对应的稳定级别包括：确定所述缓存中保存的逻辑地址的个数达到预设阈值时，获取所述目标逻辑地址对应的稳定级别，其中，所述逻辑地址对应的稳定级别与所述目标逻辑地址对应的稳定级别相同。
本发明实施例第五方面提供了一种识别数据块的稳定性的装置，所述装置位于控制器中，所述控制器位于支持重复数据删除的存储系统中，所述存储系统包括闪存装置，所述闪存装置中保存有第一数据块。所述装置包括：存储模块，用于保存所述第一数据块的信息，所述第一数据块的信息包括所述第一数据块的引用计数，或所述第一数据块保存在所述闪存装置的时间长度，或所述第一数据块的引用计数和所述第一数据块保存在所述闪存装置的时间长度，其中所述第一数据块的引用计数等于所述控制器接收所述第一数据块的数量。读取模块，用于从所述存储模块中读取所述第一数据块的信息。确定模块，用于根据(1)所述第一数据块的引用计数，和数据块的引用计数与稳定级别的对应关系，或(2)所述第一数据块保存在所述闪存装置的时间长度，和数据块保存在闪存装置的时间长度与稳定级别的对应关系，或(3)所述第一数据块的引用计数和所述第一数据块保存在所述闪存装置的时间长度，和数据块的引用计数，数据块保存在闪存装置的时间长度与稳定级别的对应关系，确定所述第一数据块的稳定级别。发送模块，用于将所述第一数据块的逻辑地址以及所述第一数据块的稳定级别发送给所述闪存装 置。
在第五方面的第一种实施方式中，所述数据块的引用计数与稳定级别的对应关系包括：引用计数区间与稳定级别的对应关系。所述确定模块，具体用于根据所述第一数据块的引用计数确定第一引用计数区间，所述第一数据块的引用计数位于所述第一引用计数区间中；根据所述第一引用计数区间，以及引用计数区间与稳定级别的对应关系确定所述第一数据块的稳定级别。
在第五方面的第二种实施方式中，所述数据块保存在闪存装置的时间长度与稳定级别的对应关系包括：时间区间与稳定级别的对应关系。所述确定模块，具体用于根据所述第一数据块保存在所述闪存装置的时间长度确定第一时间区间，所述第一数据块保存在所述闪存装置的时间长度位于所述第一时间区间中；然后，根据所述第一时间区间，以及时间区间与稳定级别的对应关系确定所述第一数据块的稳定级别。
在第五方面的第三种实施方式中，所述数据块的引用计数，数据块保存在闪存装置的时间长度与稳定级别的对应关系包括：引用计数区间，时间区间与稳定级别的对应关系。所述确定模块，具体用于根据所述第一数据块的引用计数确定第一引用计数区间，所述第一数据块的引用计数位于所述第一引用计数区间中，然后，根据所述第一数据块保存在所述闪存装置的时间长度确定第一时间区间，所述第一数据块保存在所述闪存装置的时间长度位于所述第一时间区间中；再根据所述第一引用计数区间，所述第一时间区间，以及所述引用计数区间，时间区间与稳定级别的对应关系确定所述第一数据块的稳定级别。
本发明实施例第六方面提供了一种在闪存装置中存储数据的装置，所述装置位于所述闪存装置的主控制器中，所述闪存装置中存储有块。所述装置包括：获取模块，用于获取目标逻辑地址对应的稳定级别，所述稳定级别用于表示数据块的稳定性。迁移模块，用于根据所述目标逻辑地址对应的稳定级别，将所述目标逻辑地址对应的数据块写入所述稳定级别对应的块中。在 第六方面的第一种实施方式中，所述获取模块，还用于在所述闪存芯片中查找包含无效数据最多的块，所述包含无效数据最多的块包括所述目标逻辑地址对应的数据块。
在第六方面的第二种实施方式中，所述获取模块，还用于在所述闪存芯片中查找最长时间内未被擦除的块，所述最长时间内未被擦除的块包括所述目标逻辑地址对应的数据块。
在第六方面的第三种实施方式中，所述装置还包括存储模块，所述存储模块中保存有逻辑地址，所述逻辑地址对应的稳定级别与所述目标逻辑地址对应的稳定级别相同。所述获取模块，具体用于确定所述缓存中保存的逻辑地址的个数达到预设阈值时，获取所述目标逻辑地址对应的稳定级别。
本发明实施例第七方面提供了一种计算机程序产品，包括存储了程序代码的计算机可读存储介质，所述程序代码包括的指令用于执行如第三方面至第三方面的第三种实施方式中的任意一种所述的方法。
本发明实施例第八方面提供了一种计算机程序产品，包括存储了程序代码的计算机可读存储介质，所述程序代码包括的指令用于执行如第四方面至第四方面的第三种实施方式中的任意一种所述的方法。
本发明实施例提供的控制器，可以根据(1)所述第一数据块的引用计数，和数据块的引用计数与稳定级别的对应关系，或(2)所述第一数据块保存在所述闪存装置的时间长度，和数据块保存在闪存装置的时间长度与稳定级别的对应关系，或(3)所述第一数据块的引用计数和所述第一数据块保存在所述闪存装置的时间长度，和数据块的引用计数，数据块保存在闪存装置的时间长度与稳定级别的对应关系，确定所述第一数据块的稳定级别，所述稳定级别可以反映数据块的稳定性，并且将所述数据块的稳定级别和逻辑地址发送给闪存装置22，使得闪存装置22将相同稳定级别的数据块进行集中存储。
本发明实施例提供的闪存装置，可以将相同稳定级别的数据块存储在一 个block中。那么，对于存放稳定级别较高的数据块的block，其存储的数据块成为无效数据的可能性较小，整体来看，该block中不含无效数据或仅含少量的无效数据，这样的block属于利用率比较高的block，在对闪存装置22进行垃圾回收时不会回收这样的block；对于存放稳定级别较低的数据块的block，其存储的数据块成为无效数据的可能性较大，假设一个block中的大部分数据或者绝大部分数据都变成了无效数据，那么相应地，这个block中包含的有效数据较少，垃圾回收时需要迁移的数据也较少，减小了写放大。需要说明的是，本实施例的效果主要体现在之后的垃圾回收时搬移的有效数据会减少。由此可见，无论是存放稳定级别较高的数据块的block，还是存放稳定级别较低的数据块的block，都可以减小闪存装置22的写放大，因此在一定程度上延长了闪存装置22的寿命。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对现有技术或实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例提供的存储系统的组成图；
图2是本发明实施例提供的控制器的结构示意图；
图3A是本发明实施例提供的闪存装置的存储介质的结构示意图；
图3B是本发明实施例提供的闪存装置的主控制器的结构示意图；
图4是本发明实施例提供的识别数据块稳定性的方法的流程示意图；
图5是本发明实施例提供的一种在闪存装置中存储数据的方法的流程示意图；
图6是本发明实施例提供的另一种在闪存装置中存储数据的方法的流程示意图；
图7是本发明实施例提供的识别数据块稳定性的装置的结构示意图；
图8是本发明实施例提供的在闪存装置中存储数据的装置的结构示意图。
具体实施方式
本发明实施例提出了一种控制器、闪存装置、识别数据块稳定性的方法以及在闪存装置中存储数据的方法，能够将稳定级别相同的数据块集中存储，使得闪存装置在进行后续的垃圾回收操作时选择到的块所包含的有效数据尽可能得少，从而减小闪存装置的写放大。
在描述本发明实施例之前，首先对下面将要出现的术语进行说明：
数据对象是指包含实际数据的对象，可以是块数据，也可以是文件或者其他形式的数据。
数据块是指由数据对象划分而成的数据单元。为了方便管理，一个数据对象可以被划分为若干个数据块，每个数据块的尺寸相同。
数据块的元数据是指用于描述数据块的信息，例如数据块的逻辑地址、数据块的物理地址、逻辑地址与物理地址之间的对应关系、数据块的写入时间等等。
稳定数据是指被修改的可能性相对较低的数据。
逻辑块地址，又称逻辑地址(英文全称：Logical Block Address，英文简称：LBA)，是指数据块的存放地址，该地址并非数据块存储在SSD中的实际地址，而是SSD对外呈现的可访问的地址。
物理块地址，又称物理地址(英文全称：Physical Block Address，英文简称：PBA)是指数据块存储在SSD中的实际地址。
数据块的引用计数(reference count或reference counting)，应用于支持重复数据删除功能的存储系统，用来表示数据块在存储系统中的重复数量。对于支持重复数据删除功能的存储系统来说，同一个数据块并不需要在存储 系统中存储多次，所以数据块在存储系统中的重复数量等于控制器接收所述数据块的数量，而实际上只存储了一份。另外，数据块的引用计数也可以表示所述数据块的物理地址被引用的次数。
SSD中的有效数据是指在SSD的block中有逻辑地址指向的数据块，也就是说其物理地址有对应的逻辑地址。
SSD中的无效数据通常是指在SSD的block中保存的没有逻辑地址指向的数据块，也就是说其物理地址没有对应的逻辑地址。
图1描绘了本发明实施例提供的存储系统的组成图，图1所示的存储系统包括控制器11和多个闪存装置22。其中，闪存装置22是以NAND Flash为存储介质的存储装置，可以包括固态硬盘(全称：Solid State Device，简称：SSD)，又名固态驱动器(全称：Solid State Drive，简称：SSD)，还可能包括其他存储器。本实施例中，闪存装置22以SSD为例说明。
图1仅是示例性说明，并不限定具体的组网方式，如：级联树形组网、环状组网都可以。只要控制器11和闪存装置22之间能够相互通信。
控制器11可以包括当前技术已知的任何计算设备，如服务器、台式计算机等等。控制器11可以接收主机(图1中未示出)发送的数据对象，并且向闪存装置22发送写数据请求，使得闪存装置22将写数据请求中携带的数据对象写入其闪存芯片中。
请参考图2，图2是本发明实施例控制器11的结构示意图。如图2所示，控制器11主要包括处理器(processor)118、缓存(cache)120、存储器(memory)122、通信总线(简称总线)126以及通信接口(Communication Interface)128。处理器118、缓存120、存储器122以及通信接口128通过通信总线126进行相互间的通信。
处理器118可能是一个中央处理器CPU，或者是特定集成电路ASIC(Application Specific Integrated Circuit)，或者是被配置成实施本发明实施例 的一个或多个集成电路。在本发明实施例中，处理器118用于接收来自主机的数据对象，将所述数据对象经过一定的处理后再发送给闪存装置22。
通信接口128，用于与主机或闪存装置22通信。
存储器122，用于存放程序124，存储器122可能包含高速RAM存储器，也可能还包括非易失性存储器(non-volatile memory)，例如至少一个磁盘存储器。可以理解的是，存储器122可以为随机存储器(全称：Random-Access Memory，简称：RAM)、磁碟、硬盘、光盘、固态硬盘(全称：Solid State Disk，简称：SSD)或者非易失性存储器等各种可以存储程序代码的非短暂性的(non-transitory)机器可读介质。
缓存120(Cache)用于暂时存放从主机接收的数据对象或从闪存装置22读取的数据对象。另外，由于Cache读写数据的速度较快，为了方便读取也可以将一些经常使用的信息存放在Cache中，例如数据块的逻辑地址，写入时间等信息。缓存120可以是RAM、储存级内存(全称：Storage-Class Memory，简称：SCM)、非易失存储(全称：Non-Volatile Memory，简称：NVM)、闪存(Flash memory)或固态硬盘(全称：Solid State Disk，简称：SSD)等各种可以存储数据的非短暂性的(non-transitory)机器可读介质，在此不做限定。
缓存120和存储器122可以合设或者分开设置，本发明实施例对此不做限定。
程序124可以包括程序代码，所述程序代码包括计算机操作指令。对于具有重复数据删除功能的存储系统，程序代码可以包括重复数据删除模块和稳定性判断模块。重复数据删除模块用于在将从主机接收的数据对象发送给闪存装置22之前进行重复数据删除。
下面对重复数据删除功能进行简要地介绍：
当控制器11接收主机发送的数据对象之后，可以将所述数据对象划分为尺寸相同的若干个数据块。为了描述方便，以每个数据块的尺寸为4KB 为例来进行说明，可以理解的是，数据块的尺寸并不限于4KB。对于每个数据块，处理器118分别判断各个闪存装置22中是否保存有相同的数据块，如果没有，则将数据块写入闪存装置22，同时将数据块的引用计数设置为初始值(例如，等于1)；如果有，则不需要将所述已保存的数据块再次写入闪存装置22，而是将数据块的引用计数加1。由此可见，引用计数在一定程度上反映了数据块的稳定性。引用计数越高的数据块，在相当长的时间内被使用的可能性就越高。数据块被删除的概率越小，数据块就越稳定。
对于如何判断闪存装置22是否保存有相同的数据块，通常的做法是预先保存闪存装置22中存储的各个数据块的指纹信息，其中每个数据块的指纹信息是根据预设的哈希函数对每个数据块进行计算获得的。然后，根据所述哈希函数对待存储的数据块进行计算，获得该待存储的数据块的指纹信息；将所述指纹信息与预先保存的各个数据块的指纹信息进行匹配，如果有相同的指纹信息则说明闪存装置22已经保存有相同的数据块，否则说明没有保存所述待存储的数据块。所述各个数据块的指纹信息可以保存在缓存120中，也可以保存在闪存装置22中。除此之外，还可以采用其他方式判断闪存装置22是否保存有相同的数据块，这里不再一一列举。
另外，对于第一次写入闪存装置22的数据块，控制器11可以保存所述数据块的指纹信息与所述数据块的LBA之间的对应关系。当控制器11需要将所述数据块的LBA发送给闪存装置22时，可以根据所述数据块的指纹信息和所述对应关系查找到所述LBA。具体的，所述数据块的LBA可以是闪存装置22存储所述数据块之后发送给控制器11的，也可以是控制器11为所述数据块分配的LBA，由于闪存装置22中保存有LBA与PBA之间的对应关系，因此闪存装置22可以根据分配的LBA将所述数据块写入PBA对应的存储空间中。
然而，引用计数可以是决定数据块的稳定性的一个参考因素，另外一个可以影响数据块稳定性的参考因素是数据块保存在闪存装置22中的时间长 度。所述数据块保存在闪存装置22中的时间长度可以等于所述系统当前时间减去所述数据块写入所述闪存装置的时间所得的差值。所述数据块写入所述闪存装置的时间可以是所述数据块的元数据的一部分，保存在缓存120或者闪存装置22中。可以理解的是，数据块保存在闪存装置22中的时间长度越长，所述数据块越稳定；反之，越不稳定。可以理解的是，所述时间长度也可以是一个反映数据块保存在闪存装置22中时间长短的数值，并不严格等于所述系统当前时间减去所述数据块写入所述闪存装置的时间所得的差值。
所述稳定性判断模块的主要功能是，基于引用计数，或基于数据块保存在闪存装置22中的时间长度，或基于引用计数和数据块保存在闪存装置22中的时间长度，来判断所述数据块的稳定性，从而得到所述数据块的稳定级别。稳定级别是一个反映数据块稳定性的数值，数值越大稳定性越高，反之越低。或者，也可以将稳定级别定义为数值越小稳定性越高，反之越低。
控制器11在通过所述稳定性判断模块获得数据块的稳定级别之后，可以将所述数据块的LBA与稳定级别发送给闪存装置22，使得闪存装置22将相同级别的数据块集中存储在一个或多个block中。
下面介绍闪存装置22的结构与功能。
请参考图3A，图3A是本发明实施例闪存装置22的结构示意图。本实施例中，闪存装置22以SSD为例说明。
如图3A所示，闪存装置22包括主控制器220和存储介质221。其中，主控制器220用于接收控制器11发送给闪存装置22的I/O请求，或者其他信息，例如数据块的逻辑地址和稳定级别，并且主控制器220还用于执行接收到的I/O请求，例如将I/O请求中携带的数据块写入存储介质221，或者从存储介质221中读取数据块并返回给控制器11。这里的主控制器220是SSD的主控制器。
存储介质221通常由若干个闪存(Flash)芯片组成。每个闪存芯片包括若干个块(block)。每个block包括若干个页(page)，主控制器220在将数据块写入block中时是以page为单位写入的。
由于NAND Flash具有擦除特性，保存在block中的数据不会像普通机械硬盘那样直接被修改。当需要对某个block中的数据进行修改时，需要查找一个空闲的block将修改后的数据写入该空闲的block，那么，原来的block中的数据则变为无效数据。随着SSD中存储的数据越来越多，可利用的空闲的block越来越少，因此有必要对SSD进行垃圾回收以便产生可供利用的空闲的block。本实施例中，在进行垃圾回收时通常会依次选择包含无效数据最多的块进行回收。而垃圾回收的触发条件是所述闪存芯片中包含的空闲的块的数量低于第一阈值，所述第一阈值可以是大于10并且小于100的整数。
另外，在闪存装置22内部还需要定期进行巡检。巡检是指为防止闪存芯片中某些block较长时间内未被擦除导致数据丢失，周期性地对闪存芯片中存储的数据进行搬移的操作。对于NAND Flash来说，其保持数据的能力只能维持一定时间，因此需要定期将其中存储的数据搬移到其他block。本实施例中，在进行巡检时通常会依次选择最长时间内未被擦除的块，将所述块中的有效数据搬移到空闲的块中，再擦除原来的块。而巡检的触发条件可以是当预设的巡检周期到达。
由于SSD的寿命与NAND Flash的擦除次数相关，所以尽量减少SSD内部的数据搬移有利于减小写放大，从而延长SSD的寿命。在本实施例中，SSD内部的数据搬移主要是指垃圾回收或者巡检时对block中有效数据的搬移。可以理解的是，对于待回收的block来说，如果其包含的有效数据越少，需要搬移的数据也越少。因此本发明的目的主要在于将SSD中的数据块按照稳定级别来进行集中存储，使得在进行以后的垃圾回收操作时搬移的有效数据尽可能得少。
图3B是本发明实施例描述的闪存装置22中主控制器220的结构示意图。
主控制器220主要包括处理器(processor)218、内存(cache)230、通信总线(简称总线)226以及通信接口(Communication Interface)228。处理器218、缓存230以及通信接口228通过通信总线226进行相互间的通信。
处理器218可能是一个中央处理器CPU，或者是特定集成电路ASIC(Application Specific Integrated Circuit)，或者是被配置成实施本发明实施例的一个或多个集成电路。在本发明实施例中，处理器218可以用于接收来自控制器11的I/O请求、数据块的逻辑地址以及数据块的稳定级别等信息，另外，处理器218还用于执行I/O请求。
通信接口228，用于与控制器11及存储介质221通信。
缓存230(Cache)用于缓存从控制器11接收的信息，例如数据块的逻辑地址以及数据块的稳定级别等。缓存230可以是RAM、SCM、NVM等各种可以存储数据的非短暂性的(non-transitory)或者短暂性的(transitory)机器可读介质，在此不做限定。另外，在某些应用场景下，缓存230也可以置于主控制器220的外部。
在本实施例中，可以在缓存230中保存一张映射表，用于保存从控制器11接收的数据块的LBA与数据块的稳定级别之间的对应关系。通常情况下，缓存230中还保存有一张记录LBA与PBA之间映射关系的映射表，在本发明实施例中，可以在这张映射表的基础上，增加LBA与稳定级别之间的对应关系。
或者，在缓存230中保存多个数组，每个数组对应一个稳定级别，所述数组中可以保存对应所述稳定级别的多个数据块的逻辑地址。
或者，缓存230中也可以不保存映射表，而是将稳定级别相同的数据块的逻辑地址集中存储到缓存230的一块缓存空间中。例如，控制器11可以事先发送给闪存装置22缓存区域划分信息，所述缓存区域划分信息包括不 同的稳定级别(例如，分别为1-10的10个稳定级别)，闪存装置22接收到所述缓存区域划分信息后，按照10个稳定级别将缓存230划分为10个缓存区域，每个缓存区域对应一个稳定级别，专门用于存储对应所述稳定级别的数据块的逻辑地址。或者，控制器11也可以不事先发送给闪存装置22缓存区域划分信息，而是直接将数据块的逻辑地址与数据块的稳定级别发送给闪存装置22。闪存装置22根据所述数据块的稳定级别在缓存230中划分出一段缓存区域，将所述缓存区域与所述稳定级别对应(保存所述缓存区域与所述稳定级别之间的对应关系)，之后，所述划分出的缓存区域可以专门用于保存对应所述稳定级别的数据块的逻辑地址。以上两种方式都可以实现将稳定级别相同的数据块的逻辑地址集中存储到缓存230的一块缓存空间中。
下面介绍本发明实施例一种识别数据块稳定性的方法，所述方法从控制器11的角度描述根据数据块的引用计数，或者时间长度，或者引用计数和时间长度获得该数据块的稳定级别，并发送给闪存装置22的过程。请参考图4，图4是所述识别数据块稳定性的方法的流程示意图，所述方法可以应用在图1所示的存储系统中以及图2所示的控制器11中，其执行主体是控制器11中的处理器118。所述方法包括：
步骤S201：从缓存120中读取第一数据块的信息，所述第一数据块的信息包括所述第一数据块的引用计数，或所述第一数据块保存在所述闪存装置的时间长度，或所述第一数据块的引用计数和所述第一数据块保存在所述闪存装置的时间长度，其中所述第一数据块的引用计数等于所述控制器接收所述第一数据块的数量。
需要说明的是，在本实施例中，所述第一数据块是闪存装置22中保存的多个数据块中的其中一个，这里是以第一数据块为例进行说明。并且，本实施例中的第一数据块是指有效数据包含的数据块，对于无效数据，其包含的数据块的引用计数为0，控制器11会将引用计数为0的数据块的信息从缓 存120中删除。
另外，步骤S201的触发条件可以设置为控制器11接收的所有数据块的大小超过预设的容量阈值，或者预设的时间间隔到达，或者上述两个触发条件的其中一个满足时。其中，所述预设的容量阈值可以等于图1所示的存储系统对用户呈现的可用容量，或者所述可用容量的整数倍。
步骤S202：根据所述第一数据块的信息确定所述第一数据块的稳定级别。
其中，控制器11可以预先设定稳定级别的个数。
可选的，一种实施方式是：由于闪存装置22中保存的每个数据块都有一个引用计数，因此可以将这些引用计数划分为多个引用计数区间，其中，每个引用计数区间对应一个稳定级别。举例来说，假设预先设定10个稳定级别，那么引用计数区间和稳定级别之间的对应关系可以如表1所示：
引用计数 稳定级别
+∞>引用计数≥35 1
35>引用计数≥30 2
30>引用计数≥25 3
25>引用计数≥20 4
20>引用计数≥15 5
20>引用计数≥15 6
15>引用计数≥10 7
10>引用计数≥5 8
5>引用计数≥2 9
引用计数＝1 10
表1
那么，相应地，根据所述第一数据块的信息确定所述第一数据块的稳定级别具体可以是：根据所述第一数据块的引用计数确定第一引用计数区 间，所述第一数据块的引用计数位于所述第一引用计数区间中；根据所述第一引用计数区间，以及表1所示的对应关系确定所述第一数据块的稳定级别。例如，第一数据块的引用计数是3，那么其对应的稳定级别为9。
可选的，另一种实施方式是：将多个数据块保存在闪存装置的时间长度划分为多个时间区间，其中，每个时间区间对应一个稳定级别。举例来说，假设预先设定10个稳定级别，那么时间区间和稳定级别之间的对应关系可以如表2所示：
数据块保存在闪存装置中的时间长度(单位：天) 稳定级别
+∞>时间长度≥35 1
35>时间长度≥30 2
30>时间长度≥25 3
25>时间长度≥20 4
20>时间长度≥15 5
20>时间长度≥15 6
15>时间长度≥10 7
10>时间长度≥5 8
5>时间长度≥2 9
时间长度＝1 10
表2
那么，相应地，根据所述第一数据块的信息确定所述第一数据块的稳定级别具体可以是：根据所述第一数据块保存在闪存装置中的时间长度确定第一时间区间，所述第一数据块保存在闪存装置中的时间长度位于所述第一时间区间中；根据所述第一时间区间，以及表2所示的对应关系确定所述第一数据块的稳定级别。例如，第一数据块保存在闪存装置中的时间长度是12，那么其对应的稳定级别为7。
可选的，再一种实施方式是：将多个时间长度划分为至少两个时间区间，同时也将多个引用计数划分为至少两个引用计数区间；时间区间、引用计数区间和稳定级别三者之间存在一个对应关系。
举例来说，可以以时间长度是否大于阈值T为判断标准划分为两个时间区间，一个时间区间是(0，T)，另一个时间区间是[T，+∞)。时间长度属于[T，+∞)的数据块的稳定级别大于时间长度属于(0，T)的数据块的稳定级别，在每个时间区间内，进一步地将引用计数划分为多个引用计数区间，属于相同引用计数区间的数据块的稳定级别相同。对于属于不同引用计数区间的数据块，引用计数大的数据块的稳定级别大于引用计数小的数据块的稳定级别。假设预先设定10个稳定级别，那么时间区间、引用计数区间和稳定级别之间的对应关系可以如表3所示：
数据块保存在闪存装置中的时间长度 引用计数 稳定级别
≥T ∞>引用计数≥20 1
≥T 20>引用计数≥10 2
≥T 10>引用计数≥5 3
≥T 5>引用计数≥2 4
≥T 引用计数＝1 5
<T ∞>引用计数≥20 6
<T 20>引用计数≥10 7
<T 10>引用计数≥5 8
<T 5>引用计数≥2 9
<T 引用计数＝1 10
表3
或者，也可以将多个引用计数划分为两个引用计数区间，一个引用计数区间是(0，10)，另一个引用计数区间是[10，+∞)。引用计数属于[10，+∞)的数据块的稳定级别大于引用计数属于(0，10)的数据块的稳定级别， 在每个引用计数区间内，进一步地将多个时间长度划分为多个时间区间，属于相同时间区间的数据块的稳定级别相同。对于属于不同时间区间的数据块，时间长度大的数据块的稳定级别大于时间长度小的数据块的稳定级别。假设预先设定10个稳定级别，那么时间区间、引用计数区间和稳定级别之间的对应关系可以如表4所示：
引用计数 数据块保存在闪存装置中的时间长度(单位：天) 稳定级别
≥10 ∞>时间长度≥20 1
≥10 20>时间长度≥10 2
≥10 10>时间长度≥5 3
≥10 5>时间长度≥2 4
≥10 时间长度＝1 5
<10 ∞>时间长度≥20 6
<10 20>时间长度≥10 7
<10 10>时间长度≥5 8
<10 5>时间长度≥2 9
<10 时间长度＝1 10
表4
相应地，根据所述第一数据块的信息确定所述第一数据块的稳定级别具体可以是：根据所述第一数据块的引用计数确定第一引用计数区间，所述第一数据块的引用计数位于所述第一引用计数区间中；根据所述第一数据块保存在所述闪存装置的时间长度确定第一时间区间，所述第一数据块保存在所述闪存装置的时间长度位于所述第一时间区间中；根据所述第一引用计数区间，所述第一时间区间，以及所述引用计数区间，时间区间与稳定级别的对应关系确定所述第一数据块的稳定级别。可以理解的是，无论是利用表3所示的对应关系还是利用表4所示的对应关系，只要第一数据块保存在所述闪存装置的时间长度和引用计数确定，其稳定级别也可以确定。
可选的，在上述两种实施方式中，当控制器11处理完缓存120中保存的每个数据块后，本次任务完成，可以将各个数据块的保存在闪存装置中的时间长度均减去一个固定值，使得下次任务开始时，时间长度可以以一个较小的基数开始递增。
步骤S203：将所述第一数据块的逻辑地址以及所述第一数据块的稳定级别发送给闪存装置22。
具体地，控制器11可以单独发送第一数据块的逻辑地址和稳定级别给闪存装置22，也可以将第一数据块的逻辑地址和稳定级别，与其他数据块的逻辑地址和稳定级别一起发送给闪存装置22。举例来说，逻辑地址和稳定级别可以携带在自定义的命令中发送给所述闪存装置22。
在本实施例中，控制器11可以根据(1)所述第一数据块的引用计数，和数据块的引用计数与稳定级别的对应关系，或(2)所述第一数据块保存在所述闪存装置的时间长度，和数据块保存在闪存装置的时间长度与稳定级别的对应关系，或(3)所述第一数据块的引用计数和所述第一数据块保存在所述闪存装置的时间长度，和数据块的引用计数，数据块保存在闪存装置的时间长度与稳定级别的对应关系，确定所述第一数据块的稳定级别，所述稳定级别可以反映数据块的稳定性，并且将所述数据块的稳定级别和逻辑地址发送给闪存装置22，使得闪存装置22将相同稳定级别的数据块进行集中存储。
下面介绍本发明实施例一种在闪存装置中存储数据的方法，所述方法从闪存装置22的角度描述将稳定级别相同的数据块集中存储的过程。请参考图5，图5是所述在闪存装置中存储数据的方法的流程示意图，所述方法可以应用在图1所示的存储系统中以及图3A，图3B所示的闪存装置22中，其执行主体是闪存装置22中的处理器218。所述方法包括：
步骤S301：获取目标逻辑地址对应的稳定级别，所述稳定级别用于表示数据块的稳定性。
具体地，闪存装置22在步骤S301之前接收控制器11发送的多个逻辑地址，和与所述逻辑地址对应的稳定级别，并且可以将所述多个逻辑地址及其对应的稳定级别存储在缓存230中。所述目标逻辑地址是缓存230中保存的多个逻辑地址的其中一个，当数据搬移的任务触发时，可以从缓存230中获取所述目标逻辑地址对应的稳定级别。
步骤S302：根据所述目标逻辑地址对应的稳定级别，将所述目标逻辑地址对应的数据块写入所述稳定级别对应的块中。
在本实施例中，为了将相同稳定级别的数据块搬移到同样的block中，可以建立闪存芯片中的block与稳定级别的对应关系。按照这种对应关系，可以将目标逻辑地址对应的数据块从原来的block中读取出来，写入与其稳定级别对应的block中。所述闪存芯片中的block与稳定级别的对应关系可以是预先建立的，也可以是第一次将一个数据块或者多个稳定级别相同的数据块写入一个block后便记录所述稳定级别与block之间的对应关系。
对于将目标逻辑地址对应的数据块从原来的block中读取出来具体可以是：通常情况下，闪存装置22的缓存230或者闪存芯片中保存有一张映射表，所述映射表用于保存各个数据块的逻辑地址和物理地址之间的对应关系，所以可以根据步骤S301中接收到的逻辑地址和所述映射表，从对应的物理地址所在的存储空间中读取出所述数据块。
采用本实施例提供的方式，可以将相同稳定级别的数据块存储在一个block中。那么，对于存放稳定级别较高的数据块的block，其存储的数据块成为无效数据的可能性较小，整体来看，该block中不含无效数据或仅含少量的无效数据，这样的block属于利用率比较高的block，在对闪存装置22进行垃圾回收时不会回收这样的block；对于存放稳定级别较低的数据块的block，其存储的数据块成为无效数据的可能性较大，假设一个block中的大部分数据或者绝大部分数据都变成了无效数据，那么相应地，这个block中包含的有效数据较少，垃圾回收时需要迁移的数据也较少，减小了写放大。 需要说明的是，本实施例的效果主要体现在之后的垃圾回收时搬移的有效数据会减少。由此可见，无论是存放稳定级别较高的数据块的block，还是存放稳定级别较低的数据块的block，都可以减小闪存装置22的写放大，因此在一定程度上延长了闪存装置22的寿命。
另外，一种较优的实施方式是：将上面描述的步骤S301-步骤S302与垃圾回收操作结合在一起，也就是说，当闪存装置22需要进行垃圾回收时，按照步骤S301-步骤S302描述的方式进行垃圾回收，具体的，确定所述闪存芯片中包含的空闲的块的数量低于第一阈值时，依次从闪存芯片中查找出包含无效数据最多的块，从这些块中获取待搬移的数据块的逻辑地址，然后根据所述逻辑地址，在所述逻辑地址与稳定级别的对应关系中查找，获取所述逻辑地址对应的稳定级别(结合图5所示的实施方式，所述逻辑地址即所述目标逻辑地址)，再将所述逻辑地址对应的数据块写入对应的块中。
另一种较优的实施方式是：将上面描述的步骤S301-步骤S302与巡检操作结合在一起，也就是说，当闪存装置22需要进行巡检时，按照步骤S301-步骤S302描述的方式进行巡检，具体的，当预设的巡检周期到达时，依次从闪存芯片中查找出最长时间内未被擦除的块，从这些块中获取待搬移的数据块的逻辑地址，然后根据所述逻辑地址，在所述逻辑地址与稳定级别的对应关系中查找，获取所述逻辑地址对应的稳定级别(结合图5所示的实施方式，所述逻辑地址即所述目标逻辑地址)，再将所述逻辑地址对应的数据块写入对应的块中。
本领域技术人员可以理解的是，无论是垃圾回收还是巡检，搬移的数据都是有效数据，无效数据由于不可能再被读取所以不用再做搬移，搬移完成之后以block为单位擦除所有的无效数据即可。在本实施例中，由于闪存装置22接收到的控制器11发送的逻辑地址均是有效数据包含的数据块的逻辑地址(可参见图4所示实施例中步骤S201的描述)，因此闪存装置22接收到的控制器11发送的逻辑地址对应的数据块都需要进行搬移。
按照上面提供的两种较优的实施方式，可以在闪存装置22进行垃圾回收或者巡检时实现将稳定级别相同的数据块集中存储，由于闪存装置22在进行垃圾回收或者巡检时原本会进行数据搬移，因此本实施例并没有额外的数据搬移操作，可以进一步减小写放大。
下面介绍本发明实施例另一种在闪存装置中存储数据的方法，请参考图6，图6是所述在闪存装置中存储数据的方法的流程示意图，所述方法可以应用在图1所示的存储系统中。
在本实施例中，步骤S101-步骤S104描述的是控制器11将接收到的数据块存储在闪存装置22的过程。步骤S101-步骤S104可以应用在图2所示的控制器11中，其执行主体是控制器11中的处理器118。
在步骤S101中，控制器11接收主机发送的写数据请求，所述写数据请求中包括数据对象以及所述数据对象的地址信息，所述地址信息可以包括逻辑单元号(英文全称：Logical Unit Number，英文简称：LUN)的ID以及LUN的起始地址偏移量；或者文件的ID以及文件的起始地址偏移量等等；或者当存储系统具有多个文件系统时，所述地址信息可以包括文件系统的ID、文件的ID以及文件的起始地址偏移量等等。
所述数据对象是待写入闪存装置22的块数据或者文件。
在步骤S102中，控制器11将所述数据对象划分为尺寸相同的多个数据块。
在步骤S103中，控制器11从所述多个数据块中确定一个目标数据块，判断所述目标数据块是否已经保存在闪存装置22中。
具体地，控制器11在将拆分后的数据块发送给闪存装置22存储之前，需要依次判断每个数据块是否已经保存在闪存装置22，如果是，则不需要再次进行保存。其判断方式可参考前面对重复数据删除模块功能的描述，这里不再赘述。
在步骤S104中，若所述闪存装置22中没有保存与所述目标数据块相同的数据块，控制器11将所述目标数据块发送给闪存装置22进行存储，所述目标数据块的引用计数为初始值，并且将所述目标数据块的引用计数以及所述目标数据块写入闪存装置22的逻辑地址写入缓存120中；若所述闪存装置22中保存有与所述目标数据块相同的数据块，则增加所述与所述目标数据块相同的数据块的引用计数。
具体地，所述目标数据块写入闪存装置22的逻辑地址可以是控制器11为所述目标数据块分配的逻辑地址，控制器11分配之后，将所述逻辑地址发送给闪存装置22，闪存装置22根据所述逻辑地址与物理地址之间的对应关系查找到所述逻辑地址对应的物理地址，将所述目标数据块写入所述物理地址对应的存储空间中；或者，也可以是闪存装置22存储所述数据块之后，反馈给控制器11的逻辑地址。
按照步骤S101-步骤S104描述的方式，控制器11可以将接收到数据对象拆分成若干个数据块存储在闪存装置22中。可以理解的是，由于控制器11具有重复数据删除的功能，保存在闪存装置22中的数据块都是不同的数据块。这些多个不同的数据块的信息可以保存在缓存120中。
步骤S105-步骤S107描述的是控制器11识别闪存装置22中存储的每个数据块的稳定级别，并发送给闪存装置22的过程。步骤S105-步骤S107可以应用在图2所示的控制器11中，其执行主体是控制器11中的处理器118。需要说明的是，所述稳定级别的识别过程与步骤S101-步骤S104描述的将接收到的数据块存储在闪存装置22的过程没有先后顺序之分。
在步骤S105中，任务触发时，控制器11从缓存120中读取所述目标数据块的信息。
这里的任务是指控制器11识别闪存装置22中每个数据块的稳定级别的任务。
具体地，控制器11可以对所述多个数据块的信息进行扫描，依次读取 每个数据块的信息。为了方便描述，在下面的步骤中仍以目标数据块的处理方式为例来进行说明，可以理解的是，其他数据块的处理方式和目标数据块类似。
所述目标数据块的信息包括所述目标数据块的引用计数，或所述目标数据块保存在所述闪存装置的时间长度，或所述目标数据块的引用计数和所述目标数据块保存在所述闪存装置的时间长度。
在步骤S106中，控制器11根据所述目标数据块的信息确定所述目标数据块的稳定级别。
步骤S106与图5所示实施例中的步骤S202类似，请参考步骤S202的描述。
在步骤S107中，控制器11将所述目标数据块的逻辑地址以及所述目标数据块的稳定级别发送给闪存装置22。
按照步骤S105-步骤S107描述的方式，控制器11可以将多个数据块的逻辑地址以及稳定级别发送给闪存装置22。
步骤S108-步骤S110描述的是闪存装置22接收控制器11发送的数据块的稳定级别之后，将稳定级别相同的数据块集中存储的过程。步骤S108-步骤S110可以应用在图3A、图3B所示的闪存装置(例如，SSD)中，其执行主体是闪存装置22中的处理器218。
在步骤S108中，闪存装置22保存所述多个数据块的逻辑地址，以及与所述逻辑地址对应的稳定级别。
可选的，一种保存方式是在闪存装置22的缓存230中建立一张映射表，用于保存从控制器11接收的数据块的逻辑地址与数据块的稳定级别之间的对应关系。
可选的，另一种保存方式是在缓存230中保存多个数组，每个数组对应一个稳定级别。所述多个数据块的逻辑地址分别保存在其对应的数组中。
可选的，再一种保存方式是预先将缓存230划分为若干个缓存区域， 每个缓存区域对应一个稳定级别。将所述多个数据块的逻辑地址分别记录在其对应的缓存区域中。
在步骤S109中，闪存装置22判断是否有相同稳定级别对应的逻辑地址的个数达到预设阈值，如果是，则根据所述相同稳定级别对应的逻辑地址读取数据块。
所述相同稳定级别对应的逻辑地址可以包括步骤S105-步骤S107中的目标数据块的逻辑地址。
需要说明的是，在图6所示的实施方式中，可以不和垃圾回收或者巡检操作结合，也就是说，在这种实施方式中，进行数据块搬移的触发条件和图5所示的实施方式有所不同，其触发条件是缓存中保存的相同稳定级别对应的逻辑地址的个数达到预设阈值。
那么，对于如何判断是否有相同稳定级别对应的逻辑地址的个数达到预设阈值，可以有如下三种实施方式：
第一种实施方式是，根据缓存230中保存的映射表确定是否有相同稳定级别的逻辑地址的个数达到预设阈值。
第二种实施方式是判断缓存230中是否有一个数组中保存的逻辑地址的个数达到预设阈值。
第三种实施方式是判断缓存230中是否有一个缓存区域中保存的逻辑地址的个数达到预设阈值。
其中，可以将所述预设阈值设置成块的容量与数据块的尺寸之间的比值，按照这种实施方式，当逻辑地址的个数达到所述阈值后，所述多个逻辑地址对应的数据块正好将一个空闲的block填满。
在步骤S110中，闪存装置22查找一个空闲的块，将所述读取出的数据块写入一个空闲的块中。
依次类推，按照步骤S109-步骤S110描述的方式，可以依次将稳定级别相同的数据块存储在一个或多个空闲的块中。
另外，所述预设阈值也可以设置成大于2，但小于块的容量与数据块的尺寸之间的比值的一个数值，此时，在步骤S110中，则可以查找一个未被写满的块，将稳定级别相同的数据块存储到所述未被写满的块中。
在图6所示的实施例中，闪存装置22将稳定级别相同的数据块集中在一个或多个空闲的block中，使得在进行之后的垃圾回收操作时搬移的有效数据减少，从而减小写放大，在一定程度上延长闪存装置22的寿命。
本发明实施例还提供了一种识别数据块的稳定性的装置40，所述装置40位于控制器11中，所述控制器位于图1所示的存储系统中，所述存储系统包括闪存装置22，所述闪存装置22中保存有第一数据块；如图7所示，所述装置40包括：
存储模块401，用于保存所述第一数据块的信息，所述第一数据块的信息包括所述第一数据块的引用计数，或所述第一数据块保存在所述闪存装置的时间长度，或所述第一数据块的引用计数和所述第一数据块保存在所述闪存装置的时间长度，其中所述第一数据块的引用计数等于所述控制器接收所述第一数据块的数量；
读取模块402，用于从所述存储模块中读取所述第一数据块的信息；
确定模块403，用于根据(1)所述第一数据块的引用计数，和数据块的引用计数与稳定级别的对应关系，或(2)所述第一数据块保存在所述闪存装置的时间长度，和数据块保存在闪存装置的时间长度与稳定级别的对应关系，或(3)所述第一数据块的引用计数和所述第一数据块保存在所述闪存装置的时间长度，和数据块的引用计数，数据块保存在闪存装置的时间长度与稳定级别的对应关系，确定所述第一数据块的稳定级别；
发送模块404，用于将所述第一数据块的逻辑地址以及所述第一数据块的稳定级别发送给所述闪存装置22。
在本实施例中，识别数据块的稳定性的装置40可以根据(1)所述第 一数据块的引用计数，和数据块的引用计数与稳定级别的对应关系，或(2)所述第一数据块保存在所述闪存装置的时间长度，和数据块保存在闪存装置的时间长度与稳定级别的对应关系，或(3)所述第一数据块的引用计数和所述第一数据块保存在所述闪存装置的时间长度，和数据块的引用计数，数据块保存在闪存装置的时间长度与稳定级别的对应关系，确定所述第一数据块的稳定级别，所述稳定级别可以反映数据块的稳定性，并且将所述数据块的稳定级别和逻辑地址发送给闪存装置22，使得闪存装置22将相同稳定级别的数据块进行集中存储。
可选的，在图7所示的实施方式中，所述数据块的引用计数与稳定级别的对应关系包括：引用计数区间与稳定级别的对应关系；
那么，所述确定模块403，具体用于根据所述第一数据块的引用计数确定第一引用计数区间，所述第一数据块的引用计数位于所述第一引用计数区间中；根据所述第一引用计数区间，以及引用计数区间与稳定级别的对应关系确定所述第一数据块的稳定级别。
可选的，在图7所示的实施方式中，所述数据块保存在闪存装置的时间长度与稳定级别的对应关系包括：时间区间与稳定级别的对应关系；
那么，所述确定模块403，具体用于根据所述第一数据块保存在所述闪存装置的时间长度确定第一时间区间，所述第一数据块保存在所述闪存装置的时间长度位于所述第一时间区间中；根据所述第一时间区间，以及时间区间与稳定级别的对应关系确定所述第一数据块的稳定级别。
可选的，在图7所示的实施方式中，所述数据块的引用计数，数据块保存在闪存装置的时间长度与稳定级别的对应关系包括：引用计数区间，时间区间与稳定级别的对应关系；
那么，所述确定模块403，具体用于根据所述第一数据块的引用计数确定第一引用计数区间，所述第一数据块的引用计数位于所述第一引用计数区间中；根据所述第一数据块保存在所述闪存装置的时间长度确定第一时间区 间，所述第一数据块保存在所述闪存装置的时间长度位于所述第一时间区间中；根据所述第一引用计数区间，所述第一时间区间，以及所述引用计数区间，时间区间与稳定级别的对应关系确定所述第一数据块的稳定级别。
另外，装置40各个模块的具体实现方式可参考图5或图7所示的方法实施例，这里不再赘述。
本发明实施例还提供了一种在闪存装置中存储数据的装置50，装置50位于所述闪存装置22的主控制器中，所述闪存装置22中存储有块，所述装置50包括：
获取模块501，用于获取目标逻辑地址对应的稳定级别，所述稳定级别用于表示数据块的稳定性；
迁移模块502，用于根据所述目标逻辑地址对应的稳定级别，将所述目标逻辑地址对应的数据块写入所述稳定级别对应的块中。
采用本实施例提供的装置50，可以将相同稳定级别的数据块存储在一个block中。
可选的，所述获取模块501，还用于在所述闪存芯片中查找包含无效数据最多的块，所述包含无效数据最多的块包括所述目标逻辑地址对应的数据块。
可选的，所述获取模块501，还用于在所述闪存芯片中查找最长时间内未被擦除的块，所述最长时间内未被擦除的块包括所述目标逻辑地址对应的数据块。
可选的，所述装置50还包括存储模块503，所述存储模块503中保存有逻辑地址，所述逻辑地址对应的稳定级别与所述目标逻辑地址对应的稳定级别相同；
所述获取模块501，具体用于确定所述缓存中保存的逻辑地址的个数达到预设阈值时，获取所述目标逻辑地址对应的稳定级别。
其中，所述预设阈值等于块的容量除以数据块的尺寸所得的商。
另外，装置50各个模块的具体实现方式可参考图6或图7所示的方法实施例，这里不再赘述。
本发明实施例还提供一种数据处理的计算机程序产品，包括存储了程序代码的计算机可读存储介质，所述程序代码包括的指令用于执行前述任意一个方法实施例所述的方法流程。
本领域普通技术人员可以理解，前述的存储介质包括：U盘、移动硬盘、磁碟、光盘、随机存储器(Random-Access Memory，RAM)、固态硬盘(Solid State Disk，SSD)或者非易失性存储器(non-volatile memory)等各种可以存储程序代码的非短暂性的(non-transitory)机器可读介质。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制。

Claims (33)

  1. 一种控制器，其特征在于，所述控制器位于支持重复数据删除的存储系统中，所述存储系统包括闪存装置，所述闪存装置中保存有第一数据块；所述控制器包括处理器、缓存和通信接口；所述通信接口，用于与所述闪存装置通信；所述缓存中保存有所述第一数据块的信息，所述第一数据块的信息包括所述第一数据块的引用计数，或所述第一数据块保存在所述闪存装置的时间长度，或所述第一数据块的引用计数和所述第一数据块保存在所述闪存装置的时间长度，其中所述第一数据块的引用计数等于所述控制器接收所述第一数据块的数量；
    所述处理器，用于从所述缓存中读取所述第一数据块的信息；
    根据(1)所述第一数据块的引用计数，和数据块的引用计数与稳定级别的对应关系，或(2)所述第一数据块保存在所述闪存装置的时间长度，和数据块保存在闪存装置的时间长度与稳定级别的对应关系，或(3)所述第一数据块的引用计数和所述第一数据块保存在所述闪存装置的时间长度，和数据块的引用计数，数据块保存在闪存装置的时间长度与稳定级别的对应关系，确定所述第一数据块的稳定级别，所述稳定级别用于表示数据块的稳定性；
    将所述第一数据块的逻辑地址以及所述第一数据块的稳定级别通过所述通信接口发送给所述闪存装置。
  2. 根据权利要求1所述的控制器，其特征在于，所述数据块的引用计数与稳定级别的对应关系包括：引用计数区间与稳定级别的对应关系；
    所述处理器，具体用于根据所述第一数据块的引用计数确定第一引用计数区间，所述第一数据块的引用计数位于所述第一引用计数区间中；
    根据所述第一引用计数区间，以及引用计数区间与稳定级别的对应关系确定所述第一数据块的稳定级别。
  3. 根据权利要求1所述的控制器，其特征在于，所述数据块保存在闪存装置的时间长度与稳定级别的对应关系包括：时间区间与稳定级别的对应关系；
    所述处理器，具体用于根据所述第一数据块保存在所述闪存装置的时间长度确定第一时间区间，所述第一数据块保存在所述闪存装置的时间长度位于所述第一时间区间中；
    根据所述第一时间区间，以及时间区间与稳定级别的对应关系确定所述第一数据块的稳定级别。
  4. 根据权利要求1所述的控制器，其特征在于，所述数据块的引用计数，数据块保存在闪存装置的时间长度与稳定级别的对应关系包括：引用计数区间，时间区间与稳定级别的对应关系；
    所述处理器，具体用于根据所述第一数据块的引用计数确定第一引用计数区间，所述第一数据块的引用计数位于所述第一引用计数区间中；
    根据所述第一数据块保存在所述闪存装置的时间长度确定第一时间区间，所述第一数据块保存在所述闪存装置的时间长度位于所述第一时间区间中；
    根据所述第一引用计数区间，所述第一时间区间，以及所述引用计数区间，时间区间与稳定级别的对应关系确定所述第一数据块的稳定级别。
  5. 根据权利要求1，2或4任一所述的控制器，其特征在于，所述第一数据块的信息还包括所述第一数据块的指纹信息，所述第一数据块的指纹信息是根据预设的哈希函数对所述第一数据块进行计算获得的；
    所述处理器，还用于接收所述第一数据块；
    根据所述哈希函数和所述第一数据块计算所述第一数据块的指纹信息；
    确定所述闪存装置中没有包含指纹信息与所述第一数据块的指纹信息相同的数据块；
    将所述第一数据块发送给所述闪存装置，所述第一数据块的引用计数等于初始值；
    将所述第一数据块的引用计数写入所述缓存。
  6. 根据权利要求5所述的控制器，其特征在于，
    所述处理器，还用于接收第二数据块；
    根据所述哈希函数和所述第二数据块计算所述第二数据块的指纹信息；
    确定所述第一数据块的指纹信息与所述第二数据块的指纹信息相同；
    增加所述初始值，第一数据块的引用计数等于所述初始值增加后的值。
  7. 一种闪存装置，其特征在于，所述闪存装置包括主控制器和闪存芯片，所述闪存芯片包括块，所述主控制器包括处理器；
    所述处理器，用于获取目标逻辑地址对应的稳定级别，所述稳定级别用于表示数据块的稳定性；
    根据所述目标逻辑地址对应的稳定级别，将所述目标逻辑地址对应的数据块写入所述稳定级别对应的块中。
  8. 根据权利要求7所述的闪存装置，其特征在于，
    所述处理器，还用于在所述闪存芯片中查找包含无效数据最多的块，所述包含无效数据最多的块包括所述目标逻辑地址对应的数据块。
  9. 根据权利要求7所述的闪存装置，其特征在于，
    所述处理器，还用于在所述闪存芯片中查找最长时间内未被擦除的块，所述最长时间内未被擦除的块包括所述目标逻辑地址对应的数据块。
  10. 根据权利要求7所述的闪存装置，其特征在于，所述主控制器还包括缓存；所述处理器，具体用于确定所述缓存中保存的逻辑地址的个数达到预设阈值时，获取所述目标逻辑地址对应的稳定级别，其中，所述逻辑地址对应的稳定级别与所述目标逻辑地址对应的稳定级别相同。
  11. 根据权利要求10所述的闪存装置，其特征在于，所述预设阈值等于块的容量除以数据块的尺寸所得的商。
  12. 一种识别数据块的稳定性的方法，其特征在于，所述方法应用于控制器中，所述控制器位于支持重复数据删除的存储系统中，所述存储系统包括闪存装置，所述闪存装置中保存有第一数据块；所述控制器包括处理器、缓存和通信接口；所述通信接口，用于与所述闪存装置通信；所述缓存中保存有所述第一数据块的信息，所述第一数据块的信息包括所述第一数据块的引用计数，或所述第一数据块保存在所述闪存装置的时间长度，或所述第一数据块的引用计数和所述第一数据块保存在所述闪存装置的时间长度，其中所述第一数据块的引用计数等于所述控制器接收所述第一数据块的数量；所述方法由所述处理器执行，包括：
    从所述缓存中读取所述第一数据块的信息；
    根据(1)所述第一数据块的引用计数，和数据块的引用计数与稳定级别的对应关系，或(2)所述第一数据块保存在所述闪存装置的时间长度，和数据块保存在闪存装置的时间长度与稳定级别的对应关系，或(3)所述第一数据块的引用计数和所述第一数据块保存在所述闪存装置的时间长度，和数据块的引用计数，数据块保存在闪存装置的时间长度与稳定级别的对应关系，确定所述第一数据块的稳定级别，所述稳定级别用于表示数据块的稳定性；
    将所述第一数据块的逻辑地址以及所述第一数据块的稳定级别通过所 述通信接口发送给所述闪存装置。
  13. 根据权利要求12所述的方法，其特征在于，所述数据块的引用计数与稳定级别的对应关系包括：引用计数区间与稳定级别的对应关系；
    所述根据(1)所述第一数据块的引用计数，和数据块的引用计数与稳定级别的对应关系，确定所述第一数据块的稳定级别包括：
    根据所述第一数据块的引用计数确定第一引用计数区间，所述第一数据块的引用计数位于所述第一引用计数区间中；
    根据所述第一引用计数区间，以及引用计数区间与稳定级别的对应关系确定所述第一数据块的稳定级别。
  14. 根据权利要求12所述的方法，其特征在于，所述数据块保存在闪存装置的时间长度与稳定级别的对应关系包括：时间区间与稳定级别的对应关系；
    所述根据(2)所述第一数据块保存在所述闪存装置的时间长度，和数据块保存在闪存装置的时间长度与稳定级别的对应关系，确定所述第一数据块的稳定级别包括：
    根据所述第一数据块保存在所述闪存装置的时间长度确定第一时间区间，所述第一数据块保存在所述闪存装置的时间长度位于所述第一时间区间中；
    根据所述第一时间区间，以及时间区间与稳定级别的对应关系确定所述第一数据块的稳定级别。
  15. 根据权利要求12所述的方法，其特征在于，所述数据块的引用计数，数据块保存在闪存装置的时间长度与稳定级别的对应关系包括：引用计数区间，时间区间与稳定级别的对应关系；
    所述根据(3)所述第一数据块的引用计数和所述第一数据块保存在所 述闪存装置的时间长度，和数据块的引用计数，数据块保存在闪存装置的时间长度与稳定级别的对应关系，确定所述第一数据块的稳定级别包括：
    根据所述第一数据块的引用计数确定第一引用计数区间，所述第一数据块的引用计数位于所述第一引用计数区间中；
    根据所述第一数据块保存在所述闪存装置的时间长度确定第一时间区间，所述第一数据块保存在所述闪存装置的时间长度位于所述第一时间区间中；
    根据所述第一引用计数区间，所述第一时间区间，以及所述引用计数区间，时间区间与稳定级别的对应关系确定所述第一数据块的稳定级别。
  16. 根据权利要求12，13或15任一所述的方法，其特征在于，所述第一数据块的信息还包括所述第一数据块的指纹信息，所述第一数据块的指纹信息是根据预设的哈希函数对所述第一数据块进行计算获得的；
    所述方法还包括：接收所述第一数据块；
    根据所述哈希函数和所述第一数据块计算所述第一数据块的指纹信息；
    确定所述闪存装置中没有包含指纹信息与所述第一数据块的指纹信息相同的数据块；
    将所述第一数据块发送给所述闪存装置，所述第一数据块的引用计数等于初始值；
    将所述第一数据块的引用计数写入所述缓存。
  17. 根据权利要求16所述的方法，其特征在于，所述方法还包括：
    接收第二数据块；
    根据所述哈希函数和所述第二数据块计算所述第二数据块的指纹信息；
    确定所述第一数据块的指纹信息与所述第二数据块的指纹信息相同；
    增加所述初始值，第一数据块的引用计数等于所述初始值增加后的值。
  18. 一种在闪存装置中存储数据的方法，其特征在于，所述闪存装置包括主控制器和闪存芯片，所述闪存芯片包括块，所述主控制器包括处理器；所述方法由所述处理器执行，包括：
    获取目标逻辑地址对应的稳定级别，所述稳定级别用于表示数据块的稳定性；
    根据所述目标逻辑地址对应的稳定级别，将所述目标逻辑地址对应的数据块写入所述稳定级别对应的块中。
  19. 根据权利要求18所述的方法，其特征在于，所述方法还包括：
    在所述闪存芯片中查找包含无效数据最多的块，所述包含无效数据最多的块包括所述目标逻辑地址对应的数据块。
  20. 根据权利要求18所述的方法，其特征在于，所述方法还包括：
    在所述闪存芯片中查找最长时间内未被擦除的块，所述最长时间内未被擦除的块包括所述目标逻辑地址对应的数据块。
  21. 根据权利要求18所述的方法，其特征在于，所述主控制器还包括缓存；
    所述获取目标逻辑地址对应的稳定级别包括：确定所述缓存中保存的逻辑地址的个数达到预设阈值时，获取所述目标逻辑地址对应的稳定级别，其中，所述逻辑地址对应的稳定级别与所述目标逻辑地址对应的稳定级别相同。
  22. 根据权利要求21所述的方法，其特征在于，所述预设阈值等于块 的容量除以数据块的尺寸所得的商。
  23. 一种识别数据块的稳定性的装置，其特征在于，所述装置位于控制器中，所述控制器位于支持重复数据删除的存储系统中，所述存储系统包括闪存装置，所述闪存装置中保存有第一数据块；所述装置包括：
    存储模块，用于保存所述第一数据块的信息，所述第一数据块的信息包括所述第一数据块的引用计数，或所述第一数据块保存在所述闪存装置的时间长度，或所述第一数据块的引用计数和所述第一数据块保存在所述闪存装置的时间长度，其中所述第一数据块的引用计数等于所述控制器接收所述第一数据块的数量；
    读取模块，用于从所述存储模块中读取所述第一数据块的信息；
    确定模块，用于根据(1)所述第一数据块的引用计数，和数据块的引用计数与稳定级别的对应关系，或(2)所述第一数据块保存在所述闪存装置的时间长度，和数据块保存在闪存装置的时间长度与稳定级别的对应关系，或(3)所述第一数据块的引用计数和所述第一数据块保存在所述闪存装置的时间长度，和数据块的引用计数，数据块保存在闪存装置的时间长度与稳定级别的对应关系，确定所述第一数据块的稳定级别；
    发送模块，用于将所述第一数据块的逻辑地址以及所述第一数据块的稳定级别发送给所述闪存装置。
  24. 根据权利要求23所述的装置，其特征在于，所述数据块的引用计数与稳定级别的对应关系包括：引用计数区间与稳定级别的对应关系；
    所述确定模块，具体用于根据所述第一数据块的引用计数确定第一引用计数区间，所述第一数据块的引用计数位于所述第一引用计数区间中；
    根据所述第一引用计数区间，以及引用计数区间与稳定级别的对应关系确定所述第一数据块的稳定级别。
  25. 根据权利要求23所述的装置，其特征在于，所述数据块保存在闪存装置的时间长度与稳定级别的对应关系包括：时间区间与稳定级别的对应关系；
    所述确定模块，具体用于根据所述第一数据块保存在所述闪存装置的时间长度确定第一时间区间，所述第一数据块保存在所述闪存装置的时间长度位于所述第一时间区间中；
    根据所述第一时间区间，以及时间区间与稳定级别的对应关系确定所述第一数据块的稳定级别。
  26. 根据权利要求23所述的装置，其特征在于，所述数据块的引用计数，数据块保存在闪存装置的时间长度与稳定级别的对应关系包括：引用计数区间，时间区间与稳定级别的对应关系；
    所述确定模块，具体用于根据所述第一数据块的引用计数确定第一引用计数区间，所述第一数据块的引用计数位于所述第一引用计数区间中；
    根据所述第一数据块保存在所述闪存装置的时间长度确定第一时间区间，所述第一数据块保存在所述闪存装置的时间长度位于所述第一时间区间中；
    根据所述第一引用计数区间，所述第一时间区间，以及所述引用计数区间，时间区间与稳定级别的对应关系确定所述第一数据块的稳定级别。
  27. 一种在闪存装置中存储数据的装置，其特征在于，所述装置位于所述闪存装置的主控制器中，所述闪存装置中存储有块，所述装置包括：
    获取模块，用于获取目标逻辑地址对应的稳定级别，所述稳定级别用于表示数据块的稳定性；
    迁移模块，用于根据所述目标逻辑地址对应的稳定级别，将所述目标逻辑地址对应的数据块写入所述稳定级别对应的块中。
  28. 根据权利要求27所述的装置，其特征在于，
    所述获取模块，还用于在所述闪存芯片中查找包含无效数据最多的块，所述包含无效数据最多的块包括所述目标逻辑地址对应的数据块。
  29. 根据权利要求27所述的装置，其特征在于，
    所述获取模块，还用于在所述闪存芯片中查找最长时间内未被擦除的块，所述最长时间内未被擦除的块包括所述目标逻辑地址对应的数据块。
  30. 根据权利要求27所述的装置，其特征在于，所述装置还包括存储模块，所述存储模块中保存有逻辑地址，所述逻辑地址对应的稳定级别与所述目标逻辑地址对应的稳定级别相同；
    所述获取模块，具体用于确定所述缓存中保存的逻辑地址的个数达到预设阈值时，获取所述目标逻辑地址对应的稳定级别。
  31. 根据权利要求30所述的装置，其特征在于，所述预设阈值等于块的容量除以数据块的尺寸所得的商。
  32. 一种计算机程序产品，包括存储了程序代码的计算机可读存储介质，所述程序代码包括的指令用于执行如权利要求12-17任意一项所述的方法。
  33. 一种计算机程序产品，包括存储了程序代码的计算机可读存储介质，所述程序代码包括的指令用于执行如权利要求18-22任意一项所述的方法。
PCT/CN2014/093139 2014-12-05 2014-12-05 一种控制器、闪存装置、识别数据块稳定性的方法以及在闪存装置中存储数据的方法 WO2016086411A1 (zh)

Priority Applications (9)

Application Number Priority Date Filing Date Title
DK14902279.0T DK3059679T3 (en) 2014-12-05 2014-12-05 CONTROL UNIT, FLASH MEMORY UNIT, PROCEDURE FOR IDENTIFICATION OF DATA BLOCK STABILITY, AND PROCEDURE FOR STORING DATA ON THE FLASH MEMORY UNIT
ES14902279.0T ES2691484T3 (es) 2014-12-05 2014-12-05 Controlador, dispositivo de memoria flash, método para identificar la estabilidad de bloques de datos y método para almacenar datos en un dispositivo de memoria flash
PCT/CN2014/093139 WO2016086411A1 (zh) 2014-12-05 2014-12-05 一种控制器、闪存装置、识别数据块稳定性的方法以及在闪存装置中存储数据的方法
KR1020167009885A KR101784893B1 (ko) 2014-12-05 2014-12-05 컨트롤러, 플래시 메모리 장치, 데이터 블록 안정성을 확인하는 방법, 그리고 플래시 메모리 장치에 데이터를 저장하는 방법
EP14902279.0A EP3059679B1 (en) 2014-12-05 2014-12-05 Controller, flash memory device, method for identifying data block stability and method for storing data on flash memory device
CN201480075497.1A CN105980992B (zh) 2014-12-05 2014-12-05 一种存储系统、识别数据块稳定性的方法以及装置
JP2016535211A JP6147933B2 (ja) 2014-12-05 2014-12-05 コントローラ、フラッシュメモリ装置、データブロック安定性を識別する方法、及びデータをフラッシュメモリ装置に記憶する方法
US15/085,831 US9772790B2 (en) 2014-12-05 2016-03-30 Controller, flash memory apparatus, method for identifying data block stability, and method for storing data in flash memory apparatus
US15/679,174 US20170364300A1 (en) 2014-12-05 2017-08-17 Controller, flash memory apparatus, method for identifying data block stability, and method for storing data in flash memory apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2014/093139 WO2016086411A1 (zh) 2014-12-05 2014-12-05 一种控制器、闪存装置、识别数据块稳定性的方法以及在闪存装置中存储数据的方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US15/085,831 Continuation US9772790B2 (en) 2014-12-05 2016-03-30 Controller, flash memory apparatus, method for identifying data block stability, and method for storing data in flash memory apparatus

Publications (1)

Publication Number Publication Date
WO2016086411A1 true WO2016086411A1 (zh) 2016-06-09

Family

ID=56090853

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/093139 WO2016086411A1 (zh) 2014-12-05 2014-12-05 一种控制器、闪存装置、识别数据块稳定性的方法以及在闪存装置中存储数据的方法

Country Status (8)

Country Link
US (2) US9772790B2 (zh)
EP (1) EP3059679B1 (zh)
JP (1) JP6147933B2 (zh)
KR (1) KR101784893B1 (zh)
CN (1) CN105980992B (zh)
DK (1) DK3059679T3 (zh)
ES (1) ES2691484T3 (zh)
WO (1) WO2016086411A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107193758A (zh) * 2017-05-19 2017-09-22 记忆科技(深圳)有限公司 一种固态硬盘的映射表管理方法及固态硬盘

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9917894B2 (en) * 2014-08-06 2018-03-13 Quest Software Inc. Accelerating transfer protocols
KR102306672B1 (ko) * 2016-11-23 2021-09-29 삼성전자주식회사 데이터 중복 제거를 수행하는 스토리지 시스템, 스토리지 시스템 및 데이터 처리 시스템의 동작방법
US11644992B2 (en) 2016-11-23 2023-05-09 Samsung Electronics Co., Ltd. Storage system performing data deduplication, method of operating storage system, and method of operating data processing system
US10416899B2 (en) * 2018-02-13 2019-09-17 Tesla, Inc. Systems and methods for low latency hardware memory management
US11256628B2 (en) * 2019-08-02 2022-02-22 EMC IP Holding Company LLC Volatile read cache in a content addressable storage system
KR102234886B1 (ko) * 2019-11-07 2021-04-02 숭실대학교산학협력단 플래시 메모리에서 장치 지문을 추출하는 방법 및 장치
KR20220049397A (ko) * 2020-10-14 2022-04-21 삼성전자주식회사 메모리 장치, 이를 포함하는 스토리지 장치 및 스토리지 장치의 동작 방법
KR102545465B1 (ko) * 2021-11-17 2023-06-21 삼성전자주식회사 스토리지 컨트롤러 및 이를 포함하는 스토리지 장치

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102981969A (zh) * 2012-11-21 2013-03-20 记忆科技(深圳)有限公司 重复数据删除的方法及其固态硬盘
CN103019887A (zh) * 2012-12-12 2013-04-03 华为技术有限公司 数据备份方法及装置
CN103455435A (zh) * 2013-08-29 2013-12-18 华为技术有限公司 数据写入方法及装置
US20140013032A1 (en) * 2012-07-03 2014-01-09 Research & Business Foundation Sungkyunkwan University Method and apparatus for controlling writing data in storage unit based on nand flash memory
CN103577336A (zh) * 2013-10-23 2014-02-12 华为技术有限公司 一种存储数据处理方法及装置

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4679581B2 (ja) * 2005-07-29 2011-04-27 パナソニック株式会社 メモリコントローラ、不揮発性記憶装置、不揮発性記憶システム及び不揮発性メモリのアドレス管理方法
JP4439569B2 (ja) * 2008-04-24 2010-03-24 株式会社東芝 メモリシステム
US8447915B2 (en) * 2009-07-23 2013-05-21 Hitachi, Ltd. Flash memory device for allocating physical blocks to logical blocks based on an erase count
US8452932B2 (en) * 2010-01-06 2013-05-28 Storsimple, Inc. System and method for efficiently creating off-site data volume back-ups
US8438361B2 (en) * 2010-03-10 2013-05-07 Seagate Technology Llc Logical block storage in a storage device
JP2011203916A (ja) * 2010-03-25 2011-10-13 Toshiba Corp メモリコントローラ、および半導体記憶装置
US9183134B2 (en) * 2010-04-22 2015-11-10 Seagate Technology Llc Data segregation in a storage device
JP2012014400A (ja) * 2010-06-30 2012-01-19 Toshiba Corp 半導体メモリ装置および半導体メモリシステム
US20120023144A1 (en) * 2010-07-21 2012-01-26 Seagate Technology Llc Managing Wear in Flash Memory
US20120159098A1 (en) * 2010-12-17 2012-06-21 Microsoft Corporation Garbage collection and hotspots relief for a data deduplication chunk store
EP2681691A4 (en) 2011-03-03 2015-06-03 Cypher Llc SYSTEM FOR AUTONOMOUS DETECTION AND SEPARATION OF COMMON ELEMENTS IN DATA, AND METHODS AND DEVICES RELATED THERETO
US8782370B2 (en) * 2011-05-15 2014-07-15 Apple Inc. Selective data storage in LSB and MSB pages
US9176864B2 (en) * 2011-05-17 2015-11-03 SanDisk Technologies, Inc. Non-volatile memory and method having block management with hot/cold data sorting
US9141528B2 (en) * 2011-05-17 2015-09-22 Sandisk Technologies Inc. Tracking and handling of super-hot data in non-volatile memory systems
US20120317337A1 (en) * 2011-06-09 2012-12-13 Microsoft Corporation Managing data placement on flash-based storage by use
US9021203B2 (en) 2012-05-07 2015-04-28 International Business Machines Corporation Enhancing tiering storage performance
KR101929584B1 (ko) * 2012-06-29 2018-12-17 에스케이하이닉스 주식회사 데이터 저장 장치 및 그 동작 방법
US9395924B2 (en) * 2013-01-22 2016-07-19 Seagate Technology Llc Management of and region selection for writes to non-volatile memory
CN103455436B (zh) * 2013-09-23 2016-09-14 北京经纬恒润科技有限公司 一种ram检测方法及系统
US9390116B1 (en) * 2013-09-26 2016-07-12 Emc Corporation Insertion and eviction schemes for deduplicated cache system of a storage system
US9529546B2 (en) * 2014-01-08 2016-12-27 Netapp, Inc. Global in-line extent-based deduplication

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140013032A1 (en) * 2012-07-03 2014-01-09 Research & Business Foundation Sungkyunkwan University Method and apparatus for controlling writing data in storage unit based on nand flash memory
CN102981969A (zh) * 2012-11-21 2013-03-20 记忆科技(深圳)有限公司 重复数据删除的方法及其固态硬盘
CN103019887A (zh) * 2012-12-12 2013-04-03 华为技术有限公司 数据备份方法及装置
CN103455435A (zh) * 2013-08-29 2013-12-18 华为技术有限公司 数据写入方法及装置
CN103577336A (zh) * 2013-10-23 2014-02-12 华为技术有限公司 一种存储数据处理方法及装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107193758A (zh) * 2017-05-19 2017-09-22 记忆科技(深圳)有限公司 一种固态硬盘的映射表管理方法及固态硬盘

Also Published As

Publication number Publication date
EP3059679A1 (en) 2016-08-24
JP6147933B2 (ja) 2017-06-14
EP3059679B1 (en) 2018-08-22
US20170364300A1 (en) 2017-12-21
ES2691484T3 (es) 2018-11-27
EP3059679A4 (en) 2017-03-01
KR20160084370A (ko) 2016-07-13
US20160216915A1 (en) 2016-07-28
DK3059679T3 (en) 2018-12-17
CN105980992A (zh) 2016-09-28
US9772790B2 (en) 2017-09-26
CN105980992B (zh) 2018-02-13
KR101784893B1 (ko) 2017-10-12
JP2017501489A (ja) 2017-01-12

Similar Documents

Publication Publication Date Title
WO2016086411A1 (zh) 一种控制器、闪存装置、识别数据块稳定性的方法以及在闪存装置中存储数据的方法
US10713161B2 (en) Memory system and method for controlling nonvolatile memory
US10789162B2 (en) Memory system and method for controlling nonvolatile memory
CN107346290B (zh) 使用并行化日志列表重放分区逻辑到物理数据地址转换表
US10761731B2 (en) Array controller, solid state disk, and method for controlling solid state disk to write data
CN105917303B (zh) 一种控制器、识别数据块稳定性的方法和存储系统
US9229876B2 (en) Method and system for dynamic compression of address tables in a memory
US11630767B2 (en) Garbage collection—automatic data placement
US9122586B2 (en) Physical-to-logical address map to speed up a recycle operation in a solid state drive
CN108027764B (zh) 可转换的叶的存储器映射
US20200110555A1 (en) Write control method, associated data storage device and controller thereof
US11614885B2 (en) Data processing method for improving access performance of memory device and data storage device utilizing the same
JP6167646B2 (ja) 情報処理装置、制御回路、制御プログラム、および制御方法
CN111159059A (zh) 一种垃圾回收方法、装置及非易失性的存储设备
CN112306898A (zh) 存储设备、其操作方法及包括其的电子设备
US20170271022A1 (en) Determination of a read voltage to be applied to a page based on read voltages of other pages
TW201624491A (zh) 資訊處理裝置及非暫態電腦可讀取記錄媒體
US11886335B2 (en) Memory system and controlling method of performing rewrite operation at maximum rewrite speed
JP5253471B2 (ja) メモリコントローラ

Legal Events

Date Code Title Description
REEP Request for entry into the european phase

Ref document number: 2014902279

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2014902279

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 20167009885

Country of ref document: KR

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 2016535211

Country of ref document: JP

Kind code of ref document: A

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14902279

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE