WO2016082205A1 - 一种多级缓存的功耗控制方法、装置及设备 - Google Patents

一种多级缓存的功耗控制方法、装置及设备 Download PDF

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Publication number
WO2016082205A1
WO2016082205A1 PCT/CN2014/092545 CN2014092545W WO2016082205A1 WO 2016082205 A1 WO2016082205 A1 WO 2016082205A1 CN 2014092545 W CN2014092545 W CN 2014092545W WO 2016082205 A1 WO2016082205 A1 WO 2016082205A1
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cache
specified
interval
buffer interval
buffer
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PCT/CN2014/092545
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English (en)
French (fr)
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魏孔刚
杨同增
彭钰
陈伟
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华为技术有限公司
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Priority to PCT/CN2014/092545 priority Critical patent/WO2016082205A1/zh
Priority to CN201480055990.7A priority patent/CN105849707B/zh
Publication of WO2016082205A1 publication Critical patent/WO2016082205A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to the field of computer technologies, and in particular, to a power consumption control method, apparatus, and device for a multi-level cache.
  • multi-level cache is usually used in the prior art to buffer the speed difference between the processor operation speed and the memory read/write speed, and the space of the multi-level cache is getting larger and larger.
  • the secondary or secondary caches in the multi-level cache are controlled by a unified power consumption related parameter, wherein the power consumption related parameter is a parameter related to the cache power consumption, that is, the cache power consumption can be generated.
  • Parameters that affect such as power supply voltage, clock frequency, etc.
  • the L2 cache in the multi-level cache shown in Figure 1 all L2 caches use the same power supply voltage and the same clock frequency, that is, unified by one power domain and one clock domain, and to ensure access to the L2 cache. Performance, power supply voltage, and clock frequency are both set high, requiring real-time flushing of the cache to ensure data is not lost. Therefore, multi-level cache brings power consumption problems while improving computer performance, especially in mobile terminal devices with limited battery capacity.
  • Embodiments of the present invention provide a power consumption control method, apparatus, device, and computer program product for a multi-level cache, which can reduce power consumption of a multi-level cache.
  • a power consumption control method for a multi-level cache including:
  • the to-be-controlled level cache is a secondary or secondary cache in the multi-level cache; and the to-be-controlled level cache includes at least Two buffer intervals, each buffer interval including at least one cache block;
  • the power consumption related parameters of each buffer section are controlled according to the access rate of each buffer section.
  • the power consumption related parameter includes Source voltage and / or clock frequency
  • Controlling power consumption related parameters of each buffer interval according to the access rate of each buffer interval including:
  • Each buffer interval in each buffer interval is a specified buffer interval, and when the access rate of the specified buffer interval is higher than a first preset threshold, adjusting a power supply voltage and/or a clock frequency of the specified buffer interval is increased. ;
  • the first preset threshold is greater than the second preset threshold.
  • the method before adjusting the power supply voltage of the specified buffer interval, the method further includes:
  • the method further includes:
  • the preset voltage adjustment period is greater than the preset frequency adjustment period.
  • each cache interval is controlled according to the access rate of each buffer interval.
  • the power consumption related parameters also include:
  • the first possible implementation manner of the first aspect, the second possible implementation manner of the first aspect, or the third possible implementation manner of the first aspect, in the fourth possible implementation manner Specifically, the specified data in the memory is written into the to-be-controlled level cache in the following manner:
  • index bit included in a corresponding memory address of the specified data in the memory, where the index bit is a specified index bit; wherein, the memory address of the memory and the cache address of the to-be-controlled level cache Each includes an index bit, and each cache address corresponds to one cache block;
  • the specified data in the memory is written to the determined available cache block.
  • the method further includes:
  • the specified data in the memory is written in the order of the preset cache interval.
  • the buffer address of the to-be-controlled level cache further includes an interval bit
  • the interval bit is a high bit in the cache address, and the index bit is a low bit in the cache address.
  • a power consumption control apparatus for a multi-level cache including:
  • An obtaining unit configured to obtain an access rate of each buffer interval included in the to-be-controlled cache of the multi-level cache, where the to-be-controlled level cache is a secondary or secondary cache in the multi-level cache;
  • the control level cache includes at least two buffer intervals, each buffer interval including at least one cache block;
  • the control unit is configured to control power consumption related parameters of each buffer interval according to the access rate of each buffer interval.
  • the power consumption related parameter includes a power supply voltage and/or a clock frequency
  • the control unit is configured to: in each of the buffering intervals, each of the buffering intervals is a specified buffering interval, and when the access rate of the specified buffering interval is higher than a first preset threshold, adjusting the power of the specified buffering interval.
  • the voltage and/or the clock frequency is increased; when the access rate of the specified buffer interval is lower than the second preset threshold, the power supply voltage and/or the clock frequency of the specified buffer interval is adjusted to decrease; wherein the first pre- The threshold is set to be greater than the second predetermined threshold.
  • control unit is further configured to determine that the current time has arrived before the power supply voltage of the specified buffer interval is adjusted. Setting a voltage adjustment period to adjust a time of the power supply voltage of the specified buffer interval; before adjusting a clock frequency of the specified buffer interval, determining that the current time has reached a time when the clock frequency of the specified buffer interval is adjusted by using a preset frequency adjustment period The preset voltage adjustment period is greater than the preset frequency adjustment period.
  • control unit is further configured to: when the specified buffer interval The power and/or clock of the specified buffer interval is turned off when the number of times the access rate is lower than the second preset threshold reaches a preset number of times and the number of available cache blocks in the specified buffer interval reaches a preset number.
  • the device further includes a writing unit, configured to specifically write the specified data in the memory to the to-be-controlled level cache in the following manner:
  • an index bit included in the corresponding memory address of the specified data in the memory where the index bit is a specified index bit; wherein the memory address of the memory and the cache address of the to-be-controlled level cache both include an index bit, and each The cache address corresponds to a cache block; determining, according to a preset cache interval sequence, whether the cache block corresponding to the cache address of the specified index bit in the cache interval is an available cache block, until the available cache block is determined. The specified data in the memory is written to the determined available cache block.
  • the writing unit is further configured to: when the cache interval is included, the cache address corresponding to the specified index bit is corresponding to When the cache blocks are not available cache blocks, the specified data in the memory is written into the cache buffer corresponding to the specified index bit according to the preset cache interval order. Piece.
  • the buffer address of the to-be-controlled level cache further includes an interval bit
  • the interval bit is a high bit in the cache address, and the index bit is a low bit in the cache address.
  • a mobile terminal device comprising the above-described multi-level cache power consumption control device.
  • a fourth aspect provides a mobile terminal device, including a processor and a memory, the processor running a preset program stored in the memory, for:
  • the to-be-controlled level cache is a secondary or secondary cache in the multi-level cache; and the to-be-controlled level cache includes at least Two buffer intervals, each buffer interval includes at least one cache block; and control power consumption related parameters of each buffer interval according to the access rate of each buffer interval.
  • the power consumption related parameter includes a power supply voltage and/or a clock frequency
  • the processor is specifically configured to:
  • Each buffer interval in each buffer interval is a specified buffer interval, and when the access rate of the specified buffer interval is higher than a first preset threshold, adjusting a power supply voltage and/or a clock frequency of the specified buffer interval is increased. Adjusting a power supply voltage and/or a clock frequency of the specified buffer interval when the access rate of the specified buffer interval is lower than a second preset threshold; wherein the first preset threshold is greater than the second pre- Set the threshold.
  • the processor is further configured to:
  • the processor is further configured to:
  • the processor is further configured to write specified data in the memory to the to-be-controlled level cache in the following manner:
  • an index bit included in the corresponding memory address of the specified data in the memory where the index bit is a specified index bit; wherein the memory address of the memory and the cache address of the to-be-controlled level cache both include an index bit, and each The cache address corresponds to a cache block; determining, according to a preset cache interval sequence, whether the cache block corresponding to the cache address of the specified index bit in the cache interval is an available cache block, until the available cache block is determined. The specified data in the memory is written to the determined available cache block.
  • the processor is further configured to:
  • the specified data in the memory is written in the order of the preset cache interval.
  • the buffer address of the to-be-controlled level cache further includes an interval bit
  • the interval bit is a high bit in the cache address, and the index bit is a low bit in the cache address.
  • a computer program product comprising a readable storage medium for storing computer program code, the computer level code running on a processor, the computer program code comprising:
  • the access rate of each cache interval included in the to-be-controlled cache of the multi-level cache is obtained; wherein the to-be-controlled level cache is a secondary or secondary cache in the multi-level cache; the to-be-controlled level cache
  • the method includes at least two buffer intervals, each buffer interval includes at least one cache block, and is configured to control power consumption related parameters of each buffer interval according to the access rate of each buffer interval.
  • the power consumption related parameter includes a power supply voltage and/or a clock frequency
  • the computer program code includes:
  • each buffer interval in each buffer interval is a specified buffer interval, and when the access rate of the specified buffer interval is higher than a first preset threshold, adjusting a power voltage and/or a clock of the specified buffer interval.
  • the frequency is increased; when the access rate of the specified buffer interval is lower than the second preset threshold, the power supply voltage and/or the clock frequency of the specified buffer interval is decreased; wherein the first preset threshold is greater than the The second preset threshold.
  • the computer program code includes:
  • the computer program code includes:
  • the specified buffer interval is closed. Power and / or clock.
  • the computer program code includes:
  • an index bit included in the corresponding memory address of the specified data in the memory where the index bit is a specified index bit; wherein the memory address of the memory and the cache address of the to-be-controlled level cache both include an index bit, and each The cache address corresponds to a cache block; determining, according to a preset cache interval sequence, whether the cache block corresponding to the cache address of the specified index bit in the cache interval is an available cache block, until the available cache block is determined. The specified data in the memory is written to the determined available cache block.
  • the computer program code includes:
  • the specified data in the memory is in the order of the preset cache interval. Writes to the cache block corresponding to the cache address of the specified index bit in the first buffer interval.
  • the buffer address of the to-be-controlled level cache further includes an interval bit
  • the interval bit is a high bit in the cache address, and the index bit is a low bit in the cache address.
  • the power consumption control method of the multi-level cache provided by the first aspect, the power consumption control apparatus of the multi-level cache provided by the second aspect, the mobile terminal device provided by the third aspect, the fourth aspect, and the computer program product provided by the fifth aspect For the secondary or secondary cache in the multi-level cache, the cache is divided into multiple buffer intervals, and the power consumption related parameters of the buffer interval are controlled according to the access rate of each buffer interval;
  • the low buffer interval which has little effect on the performance of the computer, can reduce the power consumption of the buffer interval by adjusting the power-related parameters of the buffer interval, thereby reducing the power consumption of the multi-level cache.
  • FIG. 1 is a schematic diagram of a control scheme of a secondary cache in a multi-level cache in the prior art
  • FIG. 2 is a schematic flowchart of a power consumption control method for a multi-level cache according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a control scheme of a secondary cache in a multi-level cache according to an embodiment of the present invention
  • FIG. 4 is a schematic flowchart of a method for controlling power consumption of a secondary cache in a multi-level cache according to an embodiment of the present invention
  • FIG. 5 is a schematic flowchart of a method for writing data of a secondary cache in a multi-level cache according to an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of data writing results according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a multi-core asynchronous processor system
  • Figure 8 is a schematic diagram of a large and small core architecture
  • FIG. 9 is a schematic structural diagram of a power consumption control apparatus for a multi-level cache according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a mobile terminal device according to an embodiment of the present invention.
  • the embodiment of the present invention provides a power consumption control method, apparatus, device, and computer program product.
  • the preferred embodiment of the present invention will be described below with reference to the accompanying drawings.
  • the preferred embodiments described herein are for illustrative purposes only and are not intended to limit the invention. And in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.
  • An embodiment of the present invention provides a power consumption control method for a multi-level cache, as shown in FIG. 2, which may specifically include:
  • Step 201 Obtain an access rate of each buffer interval included in the to-be-controlled cache of the multi-level cache, where the to-be-controlled level cache is a secondary or secondary cache in the multi-level cache;
  • the storage includes at least two buffer intervals, each buffer interval including at least one cache block.
  • the buffer to be controlled is divided into multiple buffer intervals (Region) for the to-be-controlled level cache (secondary or higher level cache) in the multi-level cache.
  • the partitioning method is not specifically limited in the present invention; each buffer interval includes at least one buffer block, and the cache block is a minimum unit of the buffer space.
  • the existing SCU (Snoop Control Unit) and other modules can monitor the access rate of each buffer interval. Therefore, in actual implementation, the access rate of each buffer interval can be directly obtained from the SCU or other modules.
  • Step 202 Control power consumption related parameters of each buffer interval according to an access rate of each buffer interval.
  • the power consumption related parameter is a parameter related to the cache power consumption, that is, a parameter that can affect the cache power consumption.
  • the power supply voltage and the lower the power supply voltage, the smaller the power consumption of the cache, that is, the power supply voltage is a power-related parameter that is positively related to the cache power consumption; similarly, the clock frequency is also a type and the buffer power consumption is positive.
  • Related power related parameters are a parameter related to the cache power consumption, that is, a parameter that can affect the cache power consumption.
  • the power consumption related parameter is a parameter that is positively related to the cache power consumption
  • the lower the access rate of the buffer interval is, the smaller the power consumption related parameter that controls the buffer interval is, so that the function of the buffer interval is smaller.
  • the power consumption related parameter is a parameter that is negatively correlated with the cache power consumption
  • the lower the access rate of the buffer interval the larger the power consumption related parameter that controls the buffer interval, so that the buffer interval is The lower the power consumption.
  • the specific values of the power consumption related parameters may be different for different buffer intervals of the to-be-controlled level cache (secondary or higher level cache) in the multi-level cache.
  • different buffer intervals may use different power supply voltages and clock frequencies, that is, each buffer interval is controlled by one power domain and one clock domain.
  • the foregoing power supply voltage and clock frequency are only examples.
  • the power consumption related parameter in the power consumption control method provided by the embodiment of the present invention may also be other parameters that can affect the cache power consumption, and will not be exemplified herein.
  • the power consumption related parameter includes at least one of a power supply voltage and a clock frequency.
  • the power consumption related parameter is specifically the power supply voltage
  • the power consumption related parameter is specifically a clock frequency
  • the clock frequency of each buffer interval is controlled according to the access rate of each buffer interval; preferably, the power consumption related parameter
  • the power supply voltage and the clock frequency can be simultaneously included.
  • the power supply voltage and the clock frequency of each buffer section are controlled according to the access rate of each buffer section, and the power consumption can be more effectively controlled.
  • the specific control method follows the principle of low access rate and low power consumption, and is not specifically limited in the present invention.
  • the following takes the power consumption related parameters including the power supply voltage and the clock frequency as an example to illustrate the specific control method.
  • the power consumption related parameter may also be only the power supply voltage or the clock frequency, that is, only the power supply voltage or the clock frequency is controlled.
  • Each buffer interval in the buffer interval of the to-be-controlled level cache (secondary or higher level cache) in the multi-level cache is a specified buffer interval, and if the power consumption related parameter includes both the power supply voltage and the clock frequency, when the specified cache
  • the power supply voltage and the clock frequency of the specified buffer interval are adjusted to meet the performance requirement; when the access rate of the specified buffer interval is lower than the second preset threshold, the adjustment is performed.
  • the power supply voltage and the clock frequency of the specified buffer interval are reduced to reduce power consumption loss; wherein the first preset threshold is greater than the second preset threshold.
  • the number of times that the access rate of the specified buffer interval is lower than the second preset threshold is recorded, and the number of times the access rate of the specified buffer interval is lower than the second preset threshold reaches a preset number of times, and the specified cache is used.
  • the preset number may be half of the number of cache blocks in the specified buffer interval. That is, at this time, the specified cache interval has a lower access rate and less stored data, and the specified buffer interval can be turned off to further reduce power consumption loss.
  • the available cache block includes a free cache block, and may further include a cache block that is not accessed by a preset duration.
  • Step 401 Acquire an access rate of each buffer interval included in the second level cache in the multi-level cache.
  • Step 402 Each buffer interval of each buffer interval is a specified buffer interval, and the specified buffer area is determined. Whether the access rate between the two is higher than the first preset threshold T1.
  • Step 403 Adjust a power supply voltage and a clock frequency of the specified buffer interval.
  • control process ends and proceeds directly to step 409.
  • Step 404 Determine whether the access rate of the specified buffer interval is lower than a second preset threshold T2.
  • Step 405 Lower the power supply voltage and the clock frequency of the specified buffer interval.
  • Step 406 Record the number of times that the access rate of the specified buffer interval is lower than the second preset threshold T2, and determine whether the number of times the access rate of the specified buffer interval is lower than the second preset threshold T2 reaches the preset number of times M.
  • Step 407 Determine whether the number of available cache blocks in the specified buffer interval reaches a preset number.
  • the preset number may be half of the total number of cache blocks in the specified buffer interval.
  • Step 408 Turn off the power and clock of the specified buffer interval.
  • the specified buffer interval is turned off; when the data to be written subsequently exists, the specified buffer interval can be turned on again, that is, the power and clock of the specified buffer interval are turned on.
  • Step 409 Determine whether the access rate of each buffer interval is acquired next time and the time when the next control flow is executed.
  • the access rate monitoring period can be set, the access rate is periodically acquired, and the power supply voltage and the clock cycle are controlled and adjusted. That is, at this time, the access rate monitoring period is the voltage adjustment period and the frequency adjustment period. At this time, the access rate monitoring period should select an appropriate value according to the actual situation to prevent frequent adjustment of the power supply voltage and clock frequency.
  • the access rate monitoring period set for the power supply voltage at this time is the voltage adjustment period
  • the access rate monitoring period set for the clock frequency is the clock frequency adjustment period
  • the adjustment period may be preset for the power supply voltage and the clock frequency, and the relationship between the preset voltage adjustment period and the preset frequency adjustment period is not specifically limited.
  • the preset voltage adjustment period should be greater than the preset frequency adjustment period, and a better control effect can be achieved. That is, before adjusting the power supply voltage of the specified buffer interval, determining that the current time has reached the time when the power supply voltage of the specified buffer interval is adjusted by using the preset voltage adjustment period; before adjusting the clock frequency of the specified buffer interval, determining that the current time has arrived at the adoption pre-
  • the frequency adjustment period is set to adjust the timing of the clock frequency of the specified buffer interval.
  • the access rate monitoring period may be set to be equal to the preset frequency adjustment period, so that in each control flow, before the clock frequency is adjusted, it is not necessary to determine whether the current time has arrived.
  • the clock frequency is adjusted by the preset frequency adjustment period, it is only necessary to determine whether the current time has reached the time when the power supply voltage is adjusted by the preset voltage adjustment period before adjusting the power supply voltage.
  • the specific method for controlling the power consumption related parameters of the buffer interval according to the access rate of the buffer interval is merely an example and is not intended to limit the present invention. Other methods may be employed in other embodiments of the present invention.
  • the correspondence between the access rate interval and the power consumption related parameter may be preset, and the power consumption related parameter corresponding to the interval with the lower access rate can make the cache power consumption more Small, determine each buffer interval
  • the access rate interval in which the access rate is located, that is, the corresponding power consumption related parameter can be determined according to the preset correspondence relationship, and the control is performed.
  • the power consumption control method of the multi-level cache separately performs dynamics of power consumption related parameters for each buffer interval in the to-be-controlled level cache (secondary or higher level cache) in the multi-level cache. Control, for some cache intervals with low access rate, this part of the buffer interval has little impact on computer performance. You can reduce the power consumption of this part of the buffer interval by adjusting the power-related parameters of this part of the buffer interval, and even close part of the buffer interval. , reducing unnecessary cache flushes, thereby reducing the power consumption of the multi-level cache.
  • the data is written into one or several buffer intervals in the buffer to be controlled as much as possible, so that the access rate of the one or several buffer intervals is compared. High; while other buffer intervals write less data, even no data is written, the access rate is naturally lower; that is, this can greatly increase the number of buffer intervals with low access rate, and thus can be adjusted by adjusting the power consumption related parameters.
  • the power consumption of the smaller buffer interval further reduces the power consumption of the multi-level cache.
  • the memory address of the memory may include an index bit
  • the cache address of the control level cache also includes an index bit, wherein each cache address corresponds to a cache block, and the specified data in the memory may be written in the following manner.
  • the to-be-controlled level cache :
  • the index bit is a specified index bit; determining, according to a preset buffer interval sequence, a cache corresponding to the cache address of the specified index bit in each buffer interval Whether the block is an available cache block until an available cache block is determined; the specified data in memory is written to the determined available cache block.
  • the specified data in the memory is in the order of the preset cache interval. Writes to the cache block corresponding to the cache address of the specified index bit in the first buffer interval.
  • the data in the memory is concentrated in the preset buffer interval order, and the cache interval in the previous order.
  • the method may include the following steps:
  • Step 501 Obtain an index bit in a memory address corresponding to the specified data to be written into the second level cache.
  • Step 502 Determine whether the cache block corresponding to the index bit acquired in step 501 is an available cache block in the first buffer interval in the preset buffer interval sequence.
  • step 501 When the cache block corresponding to the index bit acquired in step 501 is not an available cache block in the first buffer interval, the process proceeds to step 503 to continue searching for an available cache block.
  • step 501 When the cache block corresponding to the index bit acquired in step 501 is an available cache block in the first buffer interval, the process proceeds directly to step 506.
  • Step 503 Determine, according to a preset buffer interval sequence, whether the cache block corresponding to the index bit acquired in step 501 is an available cache block in the next buffer interval.
  • next buffer interval is off, the next buffer interval is turned on.
  • step 504 when the cache block corresponding to the index bit obtained in step 501 is an available cache block, proceed to step 504;
  • step 501 When the cache block corresponding to the index bit acquired in step 501 is not an available cache block in the next buffer interval, the process proceeds to step 505.
  • Step 504 Write the designated data into the available cache block determined in step 503, and the current data writing process ends.
  • Step 505 Determine whether the next buffer interval in step 503 is the last buffer interval in the preset buffer interval sequence.
  • step 503 When the next buffer interval in step 503 is not the last buffer interval, return to step 503 to continue searching for available caches;
  • step 503 When the next buffer interval in step 503 is already the last buffer interval, the process proceeds to step 506.
  • Step 506 Write the specified data into the corresponding cache block in the first buffer interval.
  • the buffer address may further include an interval bit for identifying a buffer interval to which each cache block belongs.
  • n 2, 4, 8, 16...2 L2 , L2 ⁇ 1, in this case, the number of bits of the interval bit is the logarithm of n at base 2.
  • the interval bit can be used as the upper bit in the cache address, and the index bit is used as the lower bit in the cache address.
  • the to-be-controlled level cache (secondary or higher level cache) in the multi-level cache is divided into two buffer intervals, and the number of bits in the interval bits is 1 bit; each buffer interval includes 4 buffers. Block, the number of bits in the index bit is 2 bits.
  • the number of bits of the index bit contained in the memory address should be the same as the number of bits of the index bit contained in the cache address. Further, the memory address may also include an identifier bit.
  • the flag bit can be used as the upper bit in the memory address, and the index bit is used as the low bit in the memory address.
  • the memory address can be as shown in the following table:
  • the cache blocks in the buffer segments of the current control level cache are available cache blocks, and the data in the memory memory addresses of 00011, 01000, and 11001 are written by the above data writing method.
  • the control level is cached, the result of the writing is as shown in FIG. 6.
  • the above data is written into the cache block with the cache address of 011, 000, and 001, and the data in different positions in the memory is written in the buffer interval 0.
  • the access rate of buffer interval 0 is high, and the power consumption related parameters can be adjusted to meet performance requirements, such as setting a higher power supply voltage and clock frequency; and buffer interval 1 can adjust power consumption related parameters to reduce Power loss, such as setting a lower supply voltage and clock frequency, can even turn off the power and clock in buffer interval 1.
  • the LUT (Look-Up Table) may be used to record the mapping relationship between the memory address and the cache address. Preferably, the LUT (Look-Up Table) may be used. The available bits are used to identify whether the corresponding cache block is available. Cache block.
  • interval bit + index bit cache address
  • flag bit + index bit memory address
  • control method provided by the embodiment of the present invention is to be controlled in a multi-level cache.
  • level cache secondary or above cache
  • the access rate and usage rate of each buffer interval are comprehensively considered, and power consumption loss can be avoided while ensuring performance.
  • the power consumption control method of the multi-level cache provided by the above embodiments of the present invention is applicable to various system architectures, for example, a single core processor system, a multi-core processor system, and the like.
  • the second-level cache is taken as an example, and the power consumption control method of the multi-level cache provided by the embodiment of the present invention can be used for the second level cache 0, the second level cache 1 ... Cache n as a whole to divide and manage the buffer interval; it is also possible to separately divide and manage the buffer interval for the second cache 0, the second cache 1 ... the second cache n, preferably, the second cache is different at this time
  • the upper buffer interval number is continuous.
  • the secondary buffer 0 includes a buffer interval number of 1, 2, and 3.
  • the secondary cache 1 includes a buffer interval number starting from 4.
  • the power consumption control method of the multi-level cache provided by the foregoing embodiment of the present invention can also be applied to the size and core architecture shown in FIG. 8 , for the secondary or secondary cache in the multi-level cache of the large core, and the small core.
  • the secondary or secondary cache in the multi-level cache can be partitioned separately.
  • the embodiment of the present invention further provides a multi-level cache power consumption control device, and the structure diagram thereof is as shown in FIG. Specifically, including:
  • the obtaining unit 901 is configured to obtain an access rate of each buffer interval included in the to-be-controlled level cache in the multi-level cache, where the to-be-controlled level cache is a secondary or secondary cache in the multi-level cache; the to-be-controlled level cache Include at least two buffer intervals, each buffer interval including at least one cache block;
  • the control unit 902 is configured to control power consumption related parameters of each buffer interval according to an access rate of each buffer interval.
  • the power consumption related parameter is a parameter related to the cache power consumption, that is, a parameter that can affect the cache power consumption. Specifically, when the power consumption related parameter is a parameter that is positively related to the buffer power consumption, the lower the access rate of the buffer interval, the smaller the power consumption related parameter that controls the buffer interval, so that the power consumption of the buffer interval is smaller; Cache interval when the power-related parameter is a parameter that is negatively related to the cache power consumption The lower the access rate, the larger the power-related parameter that controls the buffer interval, so that the power consumption of the buffer interval is smaller.
  • the specific values of the power consumption related parameters may be different for different buffer intervals of the to-be-controlled level cache (secondary or higher level cache) in the multi-level cache.
  • the power consumption related parameter may include a power supply voltage and/or a clock frequency; the power supply voltage and the clock frequency are power consumption related parameters that are positively related to the buffer power consumption;
  • control unit 902 is specifically configured to: each buffer interval in each buffer interval is a specified buffer interval, and when the access rate of the specified buffer interval is higher than a first preset threshold, adjust the The power supply voltage and/or the clock frequency of the specified buffer interval are increased to meet the performance requirement; when the access rate of the specified buffer interval is lower than the second preset threshold, the power supply voltage and/or the clock frequency of the specified buffer interval are adjusted to decrease. To reduce power consumption loss; wherein the first preset threshold is greater than the second preset threshold.
  • control unit 902 is further configured to: before adjusting the power voltage of the specified buffer interval, determine that the current time has reached a time when the power voltage of the specified buffer interval is adjusted by using the preset voltage adjustment period; and adjusting the specified buffer interval. Before the clock frequency, it is determined that the current time has reached the time when the clock frequency of the specified buffer interval is adjusted by the preset frequency adjustment period.
  • the relationship between the preset voltage adjustment period and the preset frequency adjustment period is not limited in the present invention.
  • the preset voltage adjustment period may be greater than the preset. Set the frequency adjustment period to achieve better control results.
  • control unit 902 is further configured to record the number of times that the access rate of the specified buffer interval is lower than the second preset threshold, when the number of times the access rate of the specified buffer interval is lower than the second preset threshold reaches a preset number of times, When the number of available cache blocks in the specified buffer interval reaches a preset number, the power and/or clock of the specified buffer interval is turned off.
  • the available cache block includes a free cache block, and may further include a cache block that is not accessed by a preset duration.
  • the preset number may be half of the number of cache blocks in the specified buffer interval. That is When the specified buffer interval has a lower access rate and less stored data, the specified buffer interval can be turned off to further reduce power consumption loss.
  • the power consumption related parameter may also be other parameters that can affect the power consumption of the cache, and will not be exemplified herein.
  • the specific manner of controlling the power consumption related parameters of the buffer interval according to the access rate of the buffer interval is merely an example, and is not intended to limit the present invention.
  • the data is written into the buffer to be controlled, the data is written into one or several buffer intervals in the buffer to be controlled as much as possible, so that the access rate of the one or several buffer intervals is high; However, other buffer intervals write less data, even no data is written, and the access rate is naturally lower; that is, the number of buffer intervals with low access rate can be greatly increased, and the power consumption related parameters can be adjusted to reduce The power consumption of the multi-buffer interval further reduces the power consumption of the multi-level cache.
  • the power consumption control device of the multi-level cache further includes a writing unit, configured to write the specified data in the memory into the to-be-controlled level cache in the following manner:
  • each cache address corresponds to a cache Blocking, according to the preset buffer interval order, sequentially determining whether the cache block corresponding to the cache address containing the specified index bit in each buffer interval is an available cache block until determining an available cache block; writing the specified data in the memory Enter the determined available cache block.
  • the writing unit is further configured to: after traversing all the buffering intervals, when the cache block corresponding to the cached address including the specified index bit is not an available cache block in each buffering interval, according to a preset buffering interval In the order, the specified data in the memory is written into the cache block corresponding to the cache address of the specified index bit in the first buffer interval.
  • the data in the memory is concentrated in the preset buffer interval order, and the cache interval in the previous order.
  • the cache address of the control level cache further includes an interval bit; the interval bit is a high bit in the cache address, and the index bit is a low bit in the cache address.
  • the memory address of the memory also contains an identifier bit; the flag bit is the high bit in the memory address, and the index bit is the low bit in the memory address.
  • the embodiment of the invention further provides a mobile terminal device, which comprises the above-mentioned multi-level cache power consumption control device.
  • the embodiment of the present invention further provides a mobile terminal device, and a schematic structural diagram thereof is shown in FIG. 10, including the processor 1001. And the memory 1002, the processor 1001 runs a preset program stored in the memory 1002 for:
  • the to-be-controlled level cache is a secondary or secondary cache in the multi-level cache; the to-be-controlled level cache includes at least two buffer intervals Each buffer interval includes at least one cache block; and the power consumption related parameters of each buffer interval are controlled according to the access rate of each buffer interval.
  • the power consumption related parameter includes a power supply voltage and/or a clock frequency
  • the processor 1001 is specifically configured to:
  • Each buffer interval in each buffer interval is a specified buffer interval.
  • adjusting a power supply voltage and/or a clock frequency of the specified buffer interval is increased;
  • the access rate of the buffer interval is lower than the second preset threshold, the power supply voltage and/or the clock frequency of the specified buffer interval is decreased; wherein the first preset threshold is greater than the second preset threshold.
  • the processor 1001 is further configured to:
  • the frequency adjustment period is adjusted to adjust the clock frequency of the buffer interval; wherein the preset voltage adjustment period is greater than the preset frequency adjustment period.
  • processor 1001 is further configured to:
  • the access rate of the specified buffer interval is lower than the second preset threshold, the preset number of times reaches, and When the number of available cache blocks in the specified buffer interval reaches a preset number, the power and/or clock of the specified buffer interval is turned off.
  • the processor 1001 is further configured to write the specified data in the memory into the to-be-controlled level cache in the following manner:
  • each cache address corresponds to a cache Blocking, according to the preset buffer interval order, sequentially determining whether the cache block corresponding to the cache address containing the specified index bit in each buffer interval is an available cache block until determining an available cache block; writing the specified data in the memory Enter the determined available cache block.
  • processor 1001 is further configured to:
  • the specified data in the memory is written into the first buffer interval according to a preset cache interval sequence.
  • a cache block corresponding to the cache address of the specified index bit is not an available cache block in each buffer interval.
  • the cache address of the control level cache further includes an interval bit
  • the interval bit is the high bit in the cache address, and the index bit is the low bit in the cache address.
  • the functions of the foregoing processor may correspond to the corresponding processing steps in the process shown in FIG. 2, FIG. 4 or FIG. 5, and details are not described herein again.
  • the mobile terminal device provided by the embodiment of the invention can reduce the power consumption of the device and extend the battery life of the device, thereby improving the user experience.
  • the embodiment of the present invention further provides a computer program product, the computer program product comprising a readable storage medium for storage a computer program code, the computer program code is run on a processor, the computer program code includes: an access rate of each cache interval included in the to-be-controlled level cache in the multi-level cache; wherein the to-be-controlled level cache is Level 2 or above cache in the level cache; the to-be-controlled level cache includes at least two buffer intervals, each buffer interval includes at least one cache block; and is used to control the work of each buffer interval according to the access rate of each buffer interval Consumption related parameters.
  • the power consumption related parameter includes a power supply voltage and/or a clock frequency
  • the computer program code includes: each cache interval in each buffer interval is a specified buffer interval, and when the access rate of the specified buffer interval is higher than a first preset threshold, adjusting a power voltage of the specified buffer interval and/or Or the clock frequency is increased; when the access rate of the specified buffer interval is lower than the second preset threshold, the power supply voltage and/or the clock frequency of the specified buffer interval is decreased; wherein the first preset threshold is greater than the second preset Threshold.
  • the computer program code is further configured to: before adjusting the power voltage of the specified buffer interval, determine that the current time has reached a time when the power voltage of the specified buffer interval is adjusted by using the preset voltage adjustment period; and the specified cache is adjusted. Before the clock frequency of the interval, it is determined that the current time has reached a time when the clock frequency of the specified buffer interval is adjusted by using the preset frequency adjustment period; wherein the preset voltage adjustment period is greater than the preset frequency adjustment period.
  • the computer program code is further configured to: when the access rate of the specified buffer interval is lower than the second preset threshold by a preset number of times, and the number of available cache blocks in the specified buffer interval reaches a preset number , turn off the power and/or clock for the specified buffer interval.
  • the computer program code is further configured to: write the specified data in the memory into the control-level cache by using the following manner:
  • each cache address corresponds to a cache Blocking, according to the preset buffer interval order, sequentially determining whether the cache block corresponding to the cache address containing the specified index bit in each buffer interval is an available cache block until determining an available cache block; writing the specified data in the memory Enter the determined available cache block.
  • the computer program code is further configured to: when each of the cache intervals, the cache block corresponding to the cache address including the specified index bit is not an available cache block, according to a preset cache interval order, the memory The specified data is written into the cache block corresponding to the cache address of the specified index bit in the first buffer interval.
  • the cache address of the control level cache further includes an interval bit
  • the interval bit is the high bit in the cache address, and the index bit is the low bit in the cache address.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.
  • computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements a particular function in a block or blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing a particular function in a block or blocks of a flow or a flow and/or block diagram of a flowchart.

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Abstract

一种多级缓存的功耗控制方法、装置及设备，能够减小多级缓存的功耗。该方法包括：获取多级缓存中待控制级缓存包括的各缓存区间的访问率；其中，该待控制级缓存为该多级缓存中的二级或二级以上缓存；所述待控制级缓存包括至少两个缓存区间，每个缓存区间包括至少一个缓存块；根据该各缓存区间的访问率，控制各缓存区间的功耗相关参数。

Description

一种多级缓存的功耗控制方法、装置及设备 技术领域
本发明涉及计算机技术领域，特别涉及一种多级缓存的功耗控制方法、装置及设备。
背景技术
随着计算机技术的发展，现有技术中通常会采用多级缓存来缓冲处理器运算速度与内存读写速度之间的速度差，且多级缓存的空间越来越大。目前，针对多级缓存中的二级或二级以上缓存，均采用统一的功耗相关参数进行控制，其中，该功耗相关参数为和缓存功耗相关的参数，即能够对缓存功耗产生影响的参数，如电源电压、时钟频率等。例如图1所示的多级缓存中的二级缓存，所有二级缓存采用同一个电源电压和同一个时钟频率，即统一由一个电源域和一个时钟域控制，并且为了保证二级缓存的访问性能，电源电压和时钟频率均设置得较高，需要实时刷新缓存以保证数据不丢失。因此，多级缓存在提高计算机性能的同时也带来了功耗的问题，尤其是在电池容量有限的移动终端设备中。
发明内容
本发明实施例提供一种多级缓存的功耗控制方法、装置、设备及计算机程序产品，能够减小多级缓存的功耗。
第一方面，提供一种多级缓存的功耗控制方法，包括：
获取多级缓存中待控制级缓存包括的各缓存区间的访问率；其中，所述待控制级缓存为所述多级缓存中的二级或二级以上缓存；所述待控制级缓存包括至少两个缓存区间，每个缓存区间包括至少一个缓存块；
根据所述各缓存区间的访问率，控制各缓存区间的功耗相关参数。
结合第一方面，在第一种可能的实现方式中，所述功耗相关参数包括电 源电压和/或时钟频率；
根据所述各缓存区间的访问率，控制各缓存区间的功耗相关参数，包括：
所述各缓存区间中的每个缓存区间为指定缓存区间，当所述指定缓存区间的访问率高于第一预设阈值时，调整所述指定缓存区间的电源电压和/或时钟频率升高；
当所述指定缓存区间的访问率低于第二预设阈值时，调整所述指定缓存区间的电源电压和/或时钟频率降低；
其中，所述第一预设阈值大于所述第二预设阈值。
结合第一方面的第一种可能的实现方式，在第二种可能的实现方式中，在调整所述指定缓存区间的电源电压之前，还包括：
确定当前时刻已到达采用预设电压调整周期调整所述指定缓存区间的电源电压的时刻；
在调整所述指定缓存区间的时钟频率之前，还包括：
确定当前时刻已到达采用预设频率调整周期调整所述指定缓存区间的时钟频率的时刻；
其中，所述预设电压调整周期大于所述预设频率调整周期。
结合第一方面的第一种可能的实现方式，或者第一方面的第二种可能的实现方式，在第三种可能的实现方式中，根据所述各缓存区间的访问率，控制各缓存区间的功耗相关参数，还包括：
当所述指定缓存区间的访问率低于第二预设阈值的次数达到预设次数、且所述指定缓存区间中可用缓存块的数量达到预设数量时，关闭所述指定缓存区间的电源和/或时钟。
结合第一方面，第一方面的第一种可能的实现方式，第一方面的第二种可能的实现方式，或者第一方面的第三种可能的实现方式，在第四种可能的实现方式中，具体采用如下方式将内存中的指定数据写入所述待控制级缓存：
获取所述指定数据在内存中对应的内存地址包含的索引位，所述索引位为指定索引位；其中，所述内存的内存地址和所述待控制级缓存的缓存地址 均包含索引位，每个缓存地址对应一个缓存块；
按照预设的缓存区间顺序，依次确定所述各缓存区间中、包含所述指定索引位的缓存地址对应的缓存块是否为可用缓存块，直至确定出可用缓存块；
将内存中的所述指定数据写入确定出的可用缓存块。
结合第一方面的第四种可能的实现方式，在第五种可能的实现方式中，还包括：
当所述各缓存区间中，包含所述指定索引位的缓存地址对应的缓存块均不为可用缓存块时，按照所述预设的缓存区间顺序，将内存中的所述指定数据写入第一个缓存区间中、包含所述指定索引位的缓存地址对应的缓存块。
结合第一方面的第四种可能的实现方式，或者第一方面的第五种可能的实现方式，在第六种可能的实现方式中，所述待控制级缓存的缓存地址还包含区间位；
所述区间位为所述缓存地址中的高位，所述索引位为所述缓存地址中的低位。
第二方面，提供一种多级缓存的功耗控制装置，包括：
获取单元，用于获取多级缓存中待控制级缓存包括的各缓存区间的访问率；其中，所述待控制级缓存为所述多级缓存中的二级或二级以上缓存；所述待控制级缓存包括至少两个缓存区间，每个缓存区间包括至少一个缓存块；
控制单元，用于根据所述各缓存区间的访问率，控制各缓存区间的功耗相关参数。
结合第二方面，在第一种可能的实现方式中，所述功耗相关参数包括电源电压和/或时钟频率；
所述控制单元，具体用于所述各缓存区间中的每个缓存区间为指定缓存区间，当所述指定缓存区间的访问率高于第一预设阈值时，调整所述指定缓存区间的电源电压和/或时钟频率升高；当所述指定缓存区间的访问率低于第二预设阈值时，调整所述指定缓存区间的电源电压和/或时钟频率降低；其中，所述第一预设阈值大于所述第二预设阈值。
结合第二方面的第一种可能的实现方式，在第二种可能的实现方式中，所述控制单元，还用于在调整所述指定缓存区间的电源电压之前，确定当前时刻已到达采用预设电压调整周期调整所述指定缓存区间的电源电压的时刻；在调整所述指定缓存区间的时钟频率之前，确定当前时刻已到达采用预设频率调整周期调整所述指定缓存区间的时钟频率的时刻；其中，所述预设电压调整周期大于所述预设频率调整周期。
结合第二方面的第一种可能的实现方式，或者第二方面的第二种可能的实现方式，在第三种可能的实现方式中，所述控制单元，还用于当所述指定缓存区间的访问率低于第二预设阈值的次数达到预设次数、且所述指定缓存区间中可用缓存块的数量达到预设数量时，关闭所述指定缓存区间的电源和/或时钟。
结合第二方面，第二方面的第一种可能的实现方式，第二方面的第二种可能的实现方式，或者第二方面的第三种可能的实现方式，在第四种可能的实现方式中，所述装置还包括写入单元，用于具体采用如下方式将内存中的指定数据写入所述待控制级缓存：
获取所述指定数据在内存中对应的内存地址包含的索引位，所述索引位为指定索引位；其中，所述内存的内存地址和所述待控制级缓存的缓存地址均包含索引位，每个缓存地址对应一个缓存块；按照预设的缓存区间顺序，依次确定所述各缓存区间中、包含所述指定索引位的缓存地址对应的缓存块是否为可用缓存块，直至确定出可用缓存块；将内存中的所述指定数据写入确定出的可用缓存块。
结合第二方面的第四种可能的实现方式，在第五种可能的实现方式中，所述写入单元，还用于当所述各缓存区间中，包含所述指定索引位的缓存地址对应的缓存块均不为可用缓存块时，按照所述预设的缓存区间顺序，将内存中的所述指定数据写入第一个缓存区间中、包含所述指定索引位的缓存地址对应的缓存块。
结合第二方面的第四种可能的实现方式，或者第二方面的第五种可能的 实现方式，在第六种可能的实现方式中，所述待控制级缓存的缓存地址还包含区间位；
所述区间位为所述缓存地址中的高位，所述索引位为所述缓存地址中的低位。
第三方面，提供一种移动终端设备，包括上述多级缓存的功耗控制装置。
第四方面，提供一种移动终端设备，包括处理器和存储器，所述处理器运行所述存储器中存储的预设程序，用于：
获取多级缓存中待控制级缓存包括的各缓存区间的访问率；其中，所述待控制级缓存为所述多级缓存中的二级或二级以上缓存；所述待控制级缓存包括至少两个缓存区间，每个缓存区间包括至少一个缓存块；根据所述各缓存区间的访问率，控制各缓存区间的功耗相关参数。
结合第四方面，在第一种可能的实现方式中，所述功耗相关参数包括电源电压和/或时钟频率；
所述处理器，具体用于：
所述各缓存区间中的每个缓存区间为指定缓存区间，当所述指定缓存区间的访问率高于第一预设阈值时，调整所述指定缓存区间的电源电压和/或时钟频率升高；当所述指定缓存区间的访问率低于第二预设阈值时，调整所述指定缓存区间的电源电压和/或时钟频率降低；其中，所述第一预设阈值大于所述第二预设阈值。
结合第四方面的第一种可能的实现方式，在第二种可能的实现方式中，所述处理器，还用于：
在调整所述指定缓存区间的电源电压之前，确定当前时刻已到达采用预设电压调整周期调整所述指定缓存区间的电源电压的时刻；在调整所述指定缓存区间的时钟频率之前，确定当前时刻已到达采用预设频率调整周期调整所述指定缓存区间的时钟频率的时刻；其中，所述预设电压调整周期大于所述预设频率调整周期。
结合第四方面的第一种可能的实现方式，或者第四方面的第二种可能的 实现方式，在第三种可能的实现方式中，所述处理器，还用于：
当所述指定缓存区间的访问率低于第二预设阈值的次数达到预设次数、且所述指定缓存区间中可用缓存块的数量达到预设数量时，关闭所述指定缓存区间的电源和/或时钟。
结合第四方面，第四方面的第一种可能的实现方式，第四方面的第二种可能的实现方式，或者第四方面的第三种可能的实现方式，在第四种可能的实现方式中，所述处理器，还用于具体采用如下方式将内存中的指定数据写入所述待控制级缓存：
获取所述指定数据在内存中对应的内存地址包含的索引位，所述索引位为指定索引位；其中，所述内存的内存地址和所述待控制级缓存的缓存地址均包含索引位，每个缓存地址对应一个缓存块；按照预设的缓存区间顺序，依次确定所述各缓存区间中、包含所述指定索引位的缓存地址对应的缓存块是否为可用缓存块，直至确定出可用缓存块；将内存中的所述指定数据写入确定出的可用缓存块。
结合第四方面的第四种可能的实现方式，在第五种可能的实现方式中，所述处理器，还用于：
当所述各缓存区间中，包含所述指定索引位的缓存地址对应的缓存块均不为可用缓存块时，按照所述预设的缓存区间顺序，将内存中的所述指定数据写入第一个缓存区间中、包含所述指定索引位的缓存地址对应的缓存块。
结合第四方面的第四种可能的实现方式，或者第四方面的第五种可能的实现方式，在第六种可能的实现方式中，所述待控制级缓存的缓存地址还包含区间位；
所述区间位为所述缓存地址中的高位，所述索引位为所述缓存地址中的低位。
第五方面，提供一种计算机程序产品，所述计算机程序产品包括可读取存储介质用于存储计算机程序代码，所述计算机程度代码运行在一个处理器上，所述计算机程序代码包括：
用于获取多级缓存中待控制级缓存包括的各缓存区间的访问率；其中，所述待控制级缓存为所述多级缓存中的二级或二级以上缓存；所述待控制级缓存包括至少两个缓存区间，每个缓存区间包括至少一个缓存块；用于根据所述各缓存区间的访问率，控制各缓存区间的功耗相关参数。
结合第五方面，在第一种可能的实现方式中，所述功耗相关参数包括电源电压和/或时钟频率；
所述计算机程序代码包括：
具体用于所述各缓存区间中的每个缓存区间为指定缓存区间，当所述指定缓存区间的访问率高于第一预设阈值时，调整所述指定缓存区间的电源电压和/或时钟频率升高；当所述指定缓存区间的访问率低于第二预设阈值时，调整所述指定缓存区间的电源电压和/或时钟频率降低；其中，所述第一预设阈值大于所述第二预设阈值。
结合第五方面的第一种可能的实现方式，在第二种可能的实现方式中，所述计算机程序代码包括：
还用于在调整所述指定缓存区间的电源电压之前，确定当前时刻已到达采用预设电压调整周期调整所述指定缓存区间的电源电压的时刻；在调整所述指定缓存区间的时钟频率之前，确定当前时刻已到达采用预设频率调整周期调整所述指定缓存区间的时钟频率的时刻；其中，所述预设电压调整周期大于所述预设频率调整周期。
结合第五方面的第一种可能的实现方式，或者第五方面的第二种可能的实现方式，在第三种可能的实现方式中，所述计算机程序代码包括：
还用于当所述指定缓存区间的访问率低于第二预设阈值的次数达到预设次数、且所述指定缓存区间中可用缓存块的数量达到预设数量时，关闭所述指定缓存区间的电源和/或时钟。
结合第五方面，第五方面的第一种可能的实现方式，第五方面的第二种可能的实现方式，或者第五方面的第三种可能的实现方式，在第四种可能的实现方式中，所述计算机程序代码包括：
还用于具体采用如下方式将内存中的指定数据写入所述待控制级缓存：
获取所述指定数据在内存中对应的内存地址包含的索引位，所述索引位为指定索引位；其中，所述内存的内存地址和所述待控制级缓存的缓存地址均包含索引位，每个缓存地址对应一个缓存块；按照预设的缓存区间顺序，依次确定所述各缓存区间中、包含所述指定索引位的缓存地址对应的缓存块是否为可用缓存块，直至确定出可用缓存块；将内存中的所述指定数据写入确定出的可用缓存块。
结合第五方面的第四种可能的实现方式，在第五种可能的实现方式中，所述计算机程序代码包括：
还用于当所述各缓存区间中，包含所述指定索引位的缓存地址对应的缓存块均不为可用缓存块时，按照所述预设的缓存区间顺序，将内存中的所述指定数据写入第一个缓存区间中、包含所述指定索引位的缓存地址对应的缓存块。
结合第五方面的第四种可能的实现方式，或者第五方面的第五种可能的实现方式，在第六种可能的实现方式中，所述待控制级缓存的缓存地址还包含区间位；
所述区间位为所述缓存地址中的高位，所述索引位为所述缓存地址中的低位。
根据第一方面提供的多级缓存的功耗控制方法，第二方面提供的多级缓存的功耗控制装置，第三方面、第四方面提供的移动终端设备，第五方面提供的计算机程序产品，针对多级缓存中的二级或二级以上缓存，将该级缓存划分为多个缓存区间，根据每个缓存区间的访问率，控制该缓存区间的功耗相关参数；对于一些访问率较低的缓存区间，这部分缓存区间对计算机性能影响较小，可以通过调整这部分缓存区间的功耗相关参数减小缓存区间的功耗，进而减小了多级缓存的功耗。
附图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明实施例一起用于解释本发明，并不构成对本发明的限制。在附图中：
图1为现有技术中多级缓存中的二级缓存的控制方案的示意图；
图2为本发明实施例提供的多级缓存的功耗控制方法的流程示意图；
图3为本发明实施例提供的多级缓存中的二级缓存的控制方案的示意图；
图4为本发明实施例提供的多级缓存中的二级缓存的功耗控制方法的详细流程示意图；
图5为本发明实施例提供的多级缓存中的二级缓存的数据写入方法的详细流程示意图；
图6为本发明实施例提供的数据写入结果的示意图；
图7为多核异步处理器系统的示意图；
图8为大小核架构的示意图；
图9为本发明实施例提供的多级缓存的功耗控制装置的结构示意图；
图10为本发明实施例提供的移动终端设备的示意图。
具体实施方式
为了给出减小多级缓存功耗的实现方案，本发明实施例提供了一种功耗控制方法、装置、设备及计算机程序产品，以下结合说明书附图对本发明的优选实施例进行说明，应当理解，此处所描述的优选实施例仅用于说明和解释本发明，并不用于限定本发明。并且在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
本发明实施例提供了一种多级缓存的功耗控制方法，如图2所示，具体可以包括：
步骤201、获取多级缓存中待控制级缓存包括的各缓存区间的访问率；其中，该待控制级缓存为多级缓存中的二级或二级以上缓存；所述待控制级缓 存包括至少两个缓存区间，每个缓存区间包括至少一个缓存块。
即本发明实施例提供的功耗控制方法中，针对多级缓存中的待控制级缓存(二级或二级以上缓存)，将该待控制级缓存划分为多个缓存区间(Region)，具体划分方法本发明不作具体限定；每个缓存区间包括至少一个缓存块(Block)，缓存块为缓存空间的最小单位。
现有的SCU(Snoop Control Unit，窥探控制器)等多种模块都可以监控各缓存区间的访问率，因此实际实施时，可以从SCU或其它模块直接获取各缓存区间的访问率。
步骤202、根据各缓存区间的访问率，控制各缓存区间的功耗相关参数。
其中，该功耗相关参数为和缓存功耗相关的参数，即能够对缓存功耗产生影响的参数。例如电源电压，并且，电源电压越低，缓存功耗越小，即电源电压为一种和缓存功耗正相关的功耗相关的参数；同理，时钟频率也为一种和缓存功耗正相关的功耗相关的参数。
具体的，当功耗相关参数为和缓存功耗正相关的参数时，步骤202中，缓存区间的访问率越低，控制该缓存区间的该功耗相关参数越小，使得该缓存区间的功耗越小；当功耗相关参数为和缓存功耗负相关的参数时，步骤202中，缓存区间的访问率越低，控制该缓存区间的该功耗相关参数越大，使得该缓存区间的功耗越小。
即针对多级缓存中的待控制级缓存(二级或二级以上缓存)的不同缓存区间，功耗相关参数的具体值可以不同。例如图3所示的多级缓存中的二级缓存，不同缓存区间可以采用不同的电源电压和时钟频率，即每个缓存区间由一个电源域和一个时钟域控制。
上述电源电压和时钟频率仅为示例，本发明实施例提供的功耗控制方法中功耗相关参数也可以为其它能够对缓存功耗产生影响的参数，在此不再进行举例说明。在本发明下述具体实施例中，功耗相关参数包括电源电压和时钟频率中的至少一个。
当功耗相关参数具体为电源电压时，此时，根据各缓存区间的访问率， 对各缓存区间的电源电压进行控制；当功耗相关参数具体为时钟频率时，此时，根据各缓存区间的访问率，对各缓存区间的时钟频率进行控制；较佳的，功耗相关参数可以同时包括电源电压和时钟频率，此时，根据各缓存区间的访问率，对各缓存区间的电源电压和时钟频率均进行控制，能够更有效的控制功耗。
具体的控制方法遵循低访问率低功耗的原则，本发明不作具体限定。下面以功耗相关参数同时包括电源电压和时钟频率为例，对具体的控制方法进行举例说明。当然，下述具体的控制方法中，功耗相关参数也可以仅为电源电压或时钟频率，即仅对电源电压或时钟频率进行控制。
多级缓存中的待控制级缓存(二级或二级以上缓存)的各缓存区间中的每个缓存区间为指定缓存区间，若功耗相关参数同时包括电源电压和时钟频率，当该指定缓存区间的访问率高于第一预设阈值时，调整该指定缓存区间的电源电压和时钟频率升高，以满足性能需求；当该指定缓存区间的访问率低于第二预设阈值时，调整该指定缓存区间的电源电压和时钟频率降低，以减小功耗损失；其中，该第一预设阈值大于该第二预设阈值。
较佳的，可以同时记录该指定缓存区间的访问率低于第二预设阈值的次数，当该指定缓存区间的访问率低于第二预设阈值的次数达到预设次数、且该指定缓存区间中的可用缓存块的数量达到预设数量时，关闭该指定缓存区间的电源和时钟。具体的，预设数量可以为该指定缓存区间中缓存块的数量的一半。即此时，该指定缓存区间的访问率较低，存储的数据较少，可以关闭该指定缓存区间以进一步减小功耗损失。
其中，可用缓存块包括空闲缓存块，也可以进一步包括超过预设时长未被访问的缓存块。
下面以多级缓存中的二级缓存为例，结合附图，对上述功耗控制方法进行详细说明。如图4所示，具体可以包括如下步骤：
步骤401、获取多级缓存中的二级缓存包括的各缓存区间的访问率。
步骤402、各缓存区间每个缓存区间为指定缓存区间，判断该指定缓存区 间的访问率是否高于第一预设阈值T1。
当该指定缓存区间的访问率高于第一预设阈值T1时，进入步骤403；
当该指定缓存区间的访问率不高于第一预设阈值T1时，直接进入步骤404。
步骤403、上调该指定缓存区间的电源电压和时钟频率。
本次控制流程结束，直接进入步骤409。
步骤404、判断该指定缓存区间的访问率是否低于第二预设阈值T2。
当该指定缓存区间的访问率低于第二预设阈值T2时，进入步骤405；
当该指定缓存区间的访问率不低于第二预设阈值T2时，电源电压和时钟频率无需进行调整，直接进入步骤409。
步骤405、下调该指定缓存区间的电源电压和时钟频率。
步骤406、记录该指定缓存区间的访问率低于第二预设阈值T2的次数，判断该指定缓存区间的访问率低于第二预设阈值T2的次数是否达到预设次数M。
当该指定缓存区间的访问率低于第二预设阈值T2的次数达到预设次数M时，进入步骤407；
当该指定缓存区间的访问率低于第二预设阈值T2的次数未达到预设次数M时，本次控制流程结束，直接进入步骤409。
步骤407、判断该指定缓存区间中可用缓存块的数量是否达到预设数量。
其中，该预设数量可以为该指定缓存区间中缓存块总数量的一半。
当该指定缓存区间中可用缓存块的数量达到该预设数量时，进入步骤408；
当该指定缓存区间中可用缓存块的数量未达到该预设数量时，本次控制流程结束，直接进入步骤409。
步骤408、关闭该指定缓存区间的电源和时钟。
即此时，关闭该指定缓存区间；在后续存在待写入数据时可以再开启该指定缓存区间，即开启该指定缓存区间的电源和时钟。
步骤409、判断是否到达下一次获取各缓存区间的访问率、执行下一次控制流程的时刻。
具体实施时，可以设置访问率监控周期，周期性地获取访问率，进行电源电压和时钟周期的控制调整。即，此时该访问率监控周期即为电压调整周期和频率调整周期。此时，访问率监控周期应当根据实际情况选择一个适当的值，以防止电源电压和时钟频率的频繁调整。
由于时钟切换的延迟时间远小于电源切换的延迟时间，较佳的，也可以针对电源电压和时钟频率分别设置不同的访问率监控周期，针对电源电压设置的访问率监控周期应大于针对时钟频率设置的访问率监控周期，可以到达更优的控制效果。即，此时针对电源电压设置的访问率监控周期即为电压调整周期，针对时钟频率设置的访问率监控周期即为时钟频率调整周期。
进一步的，当仅设置了一个访问率监控周期时，也可以针对电源电压和时钟频率分别预设调整周期，预设电压调整周期和预设频率调整周期的大小关系本发明不作具体限定，较佳的，预设电压调整周期应大于预设频率调整周期，可以到达更优的控制效果。即在调整指定缓存区间的电源电压之前，确定当前时刻已到达采用预设电压调整周期调整该指定缓存区间的电源电压的时刻；在调整指定缓存区间的时钟频率之前，确定当前时刻已到达采用预设频率调整周期调整该指定缓存区间的时钟频率的时刻。
较佳的，由于预设频率调整周期小于预设电压调整周期，可以设置访问率监控周期等于预设频率调整周期，这样在每一次控制流程中，调整时钟频率之前，无需判断当前时刻是否已到达采用预设频率调整周期调整时钟频率的时刻，只需要在调整电源电压之前，判断当前时刻是否已到达采用预设电压调整周期调整电源电压的时刻即可。
上述根据缓存区间的访问率，控制缓存区间的功耗相关参数的具体方法仅为示例，并不用于限定本发明。在本发明的其它实施例中也可以采用其它方法，例如，可以预先设定访问率区间和功耗相关参数的对应关系，访问率越低的区间对应的功耗相关参数能够使缓存功耗越小，确定每个缓存区间的 访问率所处的访问率区间，即可以根据预设的对应关系确定出对应的功耗相关参数，进行控制。
综上，本发明实施例提供的多级缓存的功耗控制方法，对于多级缓存中待控制级缓存(二级或二级以上缓存)中的各缓存区间，分别进行功耗相关参数的动态控制，对于一些访问率较低的缓存区间，这部分缓存区间对计算机性能影响较小，可以通过调整这部分缓存区间的功耗相关参数减小这部分缓存区间的功耗，甚至关闭部分缓存区间，减少不必要的缓存刷新，从而减小了多级缓存的功耗。
显然，若在向待控制级缓存中写入数据时，将数据尽量集中写入该待控制级缓存中的一个或几个缓存区间中，便会使得该一个或几个缓存区间的访问率较高；而其它缓存区间写入的数据较少，甚至没有数据写入，访问率自然也较低；即这样可以大大增加访问率低的缓存区间的数量，进而可以通过调整功耗相关参数，减小更多缓存区间的功耗，进一步减小了多级缓存的功耗。
实际实施时，内存的内存地址中可以包含索引位，待控制级缓存的缓存地址中也包含索引位，其中，每个缓存地址对应一个缓存块，可以采用如下方式将内存中的指定数据写入该待控制级缓存：
获取该指定数据在内存中对应的内存地址包含的索引位，该索引位为指定索引位；按照预设的缓存区间顺序，依次确定各缓存区间中、包含该指定索引位的缓存地址对应的缓存块是否为可用缓存块，直至确定出可用缓存块；将内存中的该指定数据写入确定出的可用缓存块。
进一步的，当遍历所有缓存区间后，各缓存区间中包含该指定索引位的缓存地址对应的缓存块均不为可用缓存块时，按照上述预设的缓存区间顺序，将内存中的该指定数据写入第一个缓存区间中、包含该指定索引位的缓存地址对应的缓存块。
即将内存中的数据尽量集中写入预设的缓存区间顺序中，顺序靠前的缓存区间。
下面以多级缓存中的二级缓存为例，结合附图，对上述数据写入方法进行详细说明。如图5所示，具体可以包括如下步骤：
步骤501、获取待写入二级缓存的指定数据对应的内存地址中的索引位。
步骤502、判断预设的缓存区间顺序中第一个缓存区间中，步骤501获取的索引位对应的缓存块是否为可用缓存块。
当第一个缓存区间中，步骤501获取的索引位对应的缓存块不是可用缓存块时，进入步骤503，继续寻找可用缓存块；
当第一个缓存区间中，步骤501获取的索引位对应的缓存块是可用缓存块时，直接进入步骤506。
步骤503、按照预设的缓存区间顺序，判断下一个缓存区间中，步骤501获取的索引位对应的缓存块是否为可用缓存块。
若该下一个缓存区间处于关闭状态，则将该下一个缓存区间开启。
当该下一个缓存区间中，步骤501获取的索引位对应的缓存块是可用缓存块时，进入步骤504；
当该下一个缓存区间中，步骤501获取的索引位对应的缓存块不是可用缓存块时，进入步骤505。
步骤504、将指定数据写入步骤503确定出的可用缓存块，本次数据写入流程结束。
步骤505、判断步骤503中的下一个缓存区间是否为预设的缓存区间顺序中的最后一个缓存区间。
当步骤503中的下一个缓存区间不是最后一个缓存区间时，返回步骤503，继续寻找可用缓存快；
当步骤503中的下一个缓存区间已经是最后一个缓存区间时，进入步骤506。
步骤506、将指定数据写入第一个缓存区间中对应的缓存块。
为便于上述数据写入方法的实现，具体实施时，可以将多级缓存中待控制级缓存(二级或二级以上缓存)划分为大小相等的n个缓存区间，每个缓 存区间均包括m个缓存块，较佳的，m＝2、4、8、16……2L1，L1≥1，此时，索引位的位数为以2为底的m的对数。
进一步的，缓存地址中还可以包含区间位，用于标识每个缓存块所属的缓存区间。较佳的，n＝2、4、8、16……2L2，L2≥1，此时，区间位的位数为以2为底的n的对数。
具体的，可以将区间位作为缓存地址中的高位，索引位作为缓存地址中的低位。
例如，如下表所示：
Figure PCTCN2014092545-appb-000001
如上表所示，此时，多级缓存中待控制级缓存(二级或二级以上缓存)被分为2个缓存区间，区间位的位数为1位；每个缓存区间包括4个缓存块，索引位的位数为2位。
内存地址中包含的索引位的位数应该和缓存地址中包含的索引位的位数相同，进一步的，内存地址中还可以包含标识位。
具体的，可以将标识位作为内存地址中的高位，索引位作为内存地址中的低位。
对应于上述表格所示的缓存地址，内存地址可以如下表所示：
Figure PCTCN2014092545-appb-000002
假设当前待控制级缓存(二级或二级以上缓存)各缓存区间中的缓存块均为可用缓存块，将内存中内存地址为00011、01000、11001的数据采用上述数据写入方法写入该待控制级缓存时，写入结果如图6所示，上述数据分别写入了缓存地址为011、000、001的缓存块，可见内存中不同位置的数据集中写入了缓存区间0中。后续在访问缓存时，缓存区间0的访问率较高，可以调整功耗相关参数以满足性能需求，例如设置较高的电源电压和时钟频率；而缓存区间1则可以调整功耗相关参数以减少功耗损失，例如设置较低的电源电压和时钟频率，甚至可以关闭缓存区间1的电源和时钟。
具体在记录内存地址与缓存地址的映射关系时可以采用LUT(Look-Up Table，查找表)，较佳的，也可以采用如下的方式记录，其中可用位用于标识对应的缓存块是否为可用缓存块。
可用位 区间位 标识位 索引位
0 0 010 00
0 0 110 01
1 0 000 11
表中，区间位+索引位＝缓存地址，标识位+索引位＝内存地址。
综上所述，采用本发明实施例提供的控制方法，在对多级缓存中待控制 级缓存(二级或二级以上缓存)包括的各缓存区间分别进行管理控制时，综合考虑到了各缓存区间的访问率和使用率，能够在保证性能的同时避免功耗损失。
本发明上述实施例提供的多级缓存的功耗控制方法适用于多种系统架构，例如，单核处理器系统、多核处理器系统等。
对于多核处理器系统，既适用于多核同步处理器系统，也适用于多核异步处理器系统。例如图7所示的多核异步处理器系统，以二级缓存为例，采用本发明实施例提供的多级缓存的功耗控制方法，可以将二级缓存0、二级缓存1……二级缓存n作为一个整体进行缓存区间的划分、管理；也可以对二级缓存0、二级缓存1……二级缓存n单独进行缓存区间的划分、管理，较佳的，此时不同二级缓存上的缓存区间编号是连续的，例如二级缓存0包括的缓存区间编号为1、2、3，二级缓存1包括的缓存区间编号可以从4开始。
本发明上述实施例提供的多级缓存的功耗控制方法还可以应用于图8所示的大小核架构中，针对大核的多级缓存中的二级或二级以上缓存，和小核的多级缓存中的二级或二级以上缓存，可以分别进行分区管理。
基于同一发明构思，根据本发明上述实施例提供的多级缓存的功耗控制方法，相应地，本发明实施例还提供一种多级缓存的功耗控制装置，其结构示意图如图9所示，具体包括：
获取单元901，用于获取多级缓存中待控制级缓存包括的各缓存区间的访问率；其中，该待控制级缓存为多级缓存中的二级或二级以上缓存；该待控制级缓存包括至少两个缓存区间，每个缓存区间包括至少一个缓存块；
控制单元902，用于根据各缓存区间的访问率，控制各缓存区间的功耗相关参数。
其中，该功耗相关参数为和缓存功耗相关的参数，即能够对缓存功耗产生影响的参数。具体的，当功耗相关参数为和缓存功耗正相关的参数时，缓存区间的访问率越低，控制该缓存区间的该功耗相关参数越小，使得该缓存区间的功耗越小；当功耗相关参数为和缓存功耗负相关的参数时，缓存区间 的访问率越低，控制该缓存区间的该功耗相关参数越大，使得该缓存区间的功耗越小。
即针对多级缓存中的待控制级缓存(二级或二级以上缓存)的不同缓存区间，功耗相关参数的具体值可以不同。
进一步的，该功耗相关参数可以包括电源电压和/或时钟频率；电源电压和时钟频率均为和缓存功耗正相关的功耗相关的参数；
在本发明的一个具体实施例中，控制单元902，具体用于各缓存区间中的每个缓存区间为指定缓存区间，当该指定缓存区间的访问率高于第一预设阈值时，调整该指定缓存区间的电源电压和/或时钟频率升高，以满足性能需求；当该指定缓存区间的访问率低于第二预设阈值时，调整该指定缓存区间的电源电压和/或时钟频率降低，以减小功耗损失；其中，第一预设阈值大于第二预设阈值。
较佳的，控制单元902，还用于在调整该指定缓存区间的电源电压之前，确定当前时刻已到达采用预设电压调整周期调整指定缓存区间的电源电压的时刻；在调整该指定缓存区间的时钟频率之前，确定当前时刻已到达采用预设频率调整周期调整指定缓存区间的时钟频率的时刻。
其中，预设电压调整周期和预设频率调整周期的大小关系本发明不作具体限定，较佳的，由于时钟切换的延迟时间远小于电源切换的延迟时间，因此，预设电压调整周期可以大于预设频率调整周期，能够到达更优的控制效果。
进一步的，控制单元902，还用于记录该指定缓存区间的访问率低于第二预设阈值的次数，当该指定缓存区间的访问率低于第二预设阈值的次数达到预设次数、且该指定缓存区间中可用缓存块的数量达到预设数量时，关闭该指定缓存区间的电源和/或时钟。
其中，可用缓存块包括空闲缓存块，也可以进一步包括超过预设时长未被访问的缓存块。
具体的，预设数量可以为该指定缓存区间中缓存块的数量的一半。即此 时，该指定缓存区间的访问率较低，存储的数据较少，可以关闭该指定缓存区间以进一步减小功耗损失。
上述电源电压和时钟频率仅为示例，本发明的其它具体实施例中功耗相关参数也可以为其它能够对缓存功耗产生影响的参数，在此不再进行举例说明。
上述根据缓存区间的访问率，控制缓存区间的功耗相关参数的具体方式仅为示例，并不用于限定本发明。
若在向待控制级缓存中写入数据时，将数据尽量集中写入该待控制级缓存中的一个或几个缓存区间中，便会使得该一个或几个缓存区间的访问率较高；而其它缓存区间写入的数据较少，甚至没有数据写入，访问率自然也较低；即这样可以大大增加访问率低的缓存区间的数量，进而可以通过调整功耗相关参数，减小更多缓存区间的功耗，进一步减小了多级缓存的功耗。
因此，较佳的，该多级缓存的功耗控制装置还包括写入单元，用于具体采用如下方式将内存中的指定数据写入待控制级缓存：
获取该指定数据在内存中对应的内存地址包含的索引位，该索引位为指定索引位；其中，内存的内存地址和待控制级缓存的缓存地址均包含索引位，每个缓存地址对应一个缓存块；按照预设的缓存区间顺序，依次确定各缓存区间中、包含该指定索引位的缓存地址对应的缓存块是否为可用缓存块，直至确定出可用缓存块；将内存中的该指定数据写入确定出的可用缓存块。
进一步的，该写入单元，还用于在遍历所有缓存区间后，当各缓存区间中，包含该指定索引位的缓存地址对应的缓存块均不为可用缓存块时，按照预设的缓存区间顺序，将内存中的该指定数据写入第一个缓存区间中、包含该指定索引位的缓存地址对应的缓存块。
即将内存中的数据尽量集中写入预设的缓存区间顺序中，顺序靠前的缓存区间。
进一步的，待控制级缓存的缓存地址还包含区间位；该区间位为缓存地址中的高位，索引位为缓存地址中的低位。
内存的内存地址还包含标识位；该标识位为内存地址中的高位，索引位为内存地址中的低位。
上述各单元的功能可对应于图2、图4或图5所示流程中的相应处理步骤，在此不再赘述。
本发明实施例还提供了一种移动终端设备，包括上述多级缓存的功耗控制装置。
基于同一发明构思，根据本发明上述实施例提供的多级缓存的功耗控制方法，相应地，本发明实施例还提供一种移动终端设备，其结构示意图如图10所示，包括处理器1001和存储器1002，处理器1001运行存储器1002中存储的预设程序，用于：
获取多级缓存中待控制级缓存包括的各缓存区间的访问率；其中，该待控制级缓存为多级缓存中的二级或二级以上缓存；该待控制级缓存包括至少两个缓存区间，每个缓存区间包括至少一个缓存块；根据各缓存区间的访问率，控制各缓存区间的功耗相关参数。
进一步的，该功耗相关参数包括电源电压和/或时钟频率；
处理器1001，具体用于：
各缓存区间中的每个缓存区间为指定缓存区间，当该指定缓存区间的访问率高于第一预设阈值时，调整该指定缓存区间的电源电压和/或时钟频率升高；当该指定缓存区间的访问率低于第二预设阈值时，调整该指定缓存区间的电源电压和/或时钟频率降低；其中，第一预设阈值大于第二预设阈值。
较佳的，处理器1001，还用于：
在调整该指定缓存区间的电源电压之前，确定当前时刻已到达采用预设电压调整周期调整指定缓存区间的电源电压的时刻；在调整该指定缓存区间的时钟频率之前，确定当前时刻已到达采用预设频率调整周期调整指定缓存区间的时钟频率的时刻；其中，预设电压调整周期大于预设频率调整周期。
进一步的，处理器1001，还用于：
当该指定缓存区间的访问率低于第二预设阈值的次数达到预设次数、且 该指定缓存区间中可用缓存块的数量达到预设数量时，关闭该指定缓存区间的电源和/或时钟。
较佳的，处理器1001，还用于具体采用如下方式将内存中的指定数据写入待控制级缓存：
获取该指定数据在内存中对应的内存地址包含的索引位，该索引位为指定索引位；其中，内存的内存地址和待控制级缓存的缓存地址均包含索引位，每个缓存地址对应一个缓存块；按照预设的缓存区间顺序，依次确定各缓存区间中、包含该指定索引位的缓存地址对应的缓存块是否为可用缓存块，直至确定出可用缓存块；将内存中的该指定数据写入确定出的可用缓存块。
进一步的，处理器1001，还用于：
当各缓存区间中，包含该指定索引位的缓存地址对应的缓存块均不为可用缓存块时，按照预设的缓存区间顺序，将内存中的该指定数据写入第一个缓存区间中、包含该指定索引位的缓存地址对应的缓存块。
进一步的，待控制级缓存的缓存地址还包含区间位；
该区间位为缓存地址中的高位，索引位为缓存地址中的低位。
上述处理器的功能可对应于图2、图4或图5所示流程中的相应处理步骤，在此不再赘述。
采用本发明实施例提供的移动终端设备，可以减小设备功耗，延长设备的续航时间，进而提高了用户的使用体验。
基于同一发明构思，根据本发明上述实施例提供的多级缓存的功耗控制方法，相应地，本发明实施例还提供一种计算机程序产品，该计算机程序产品包括可读取存储介质用于存储计算机程序代码，该计算机程度代码运行在一个处理器上，该计算机程序代码包括：用于获取多级缓存中待控制级缓存包括的各缓存区间的访问率；其中，该待控制级缓存为多级缓存中的二级或二级以上缓存；该待控制级缓存包括至少两个缓存区间，每个缓存区间包括至少一个缓存块；用于根据各缓存区间的访问率，控制各缓存区间的功耗相关参数。
进一步的，该功耗相关参数包括电源电压和/或时钟频率；
该计算机程序代码包括：具体用于各缓存区间中的每个缓存区间为指定缓存区间，当该指定缓存区间的访问率高于第一预设阈值时，调整该指定缓存区间的电源电压和/或时钟频率升高；当该指定缓存区间的访问率低于第二预设阈值时，调整该指定缓存区间的电源电压和/或时钟频率降低；其中，第一预设阈值大于第二预设阈值。
较佳的，该计算机程序代码包括：还用于在调整该指定缓存区间的电源电压之前，确定当前时刻已到达采用预设电压调整周期调整指定缓存区间的电源电压的时刻；在调整该指定缓存区间的时钟频率之前，确定当前时刻已到达采用预设频率调整周期调整指定缓存区间的时钟频率的时刻；其中，预设电压调整周期大于预设频率调整周期。
进一步的，该计算机程序代码包括：还用于当该指定缓存区间的访问率低于第二预设阈值的次数达到预设次数、且该指定缓存区间中可用缓存块的数量达到预设数量时，关闭该指定缓存区间的电源和/或时钟。
较佳的，该计算机程序代码包括：还用于具体采用如下方式将内存中的指定数据写入待控制级缓存：
获取该指定数据在内存中对应的内存地址包含的索引位，该索引位为指定索引位；其中，内存的内存地址和待控制级缓存的缓存地址均包含索引位，每个缓存地址对应一个缓存块；按照预设的缓存区间顺序，依次确定各缓存区间中、包含该指定索引位的缓存地址对应的缓存块是否为可用缓存块，直至确定出可用缓存块；将内存中的该指定数据写入确定出的可用缓存块。
进一步的，该计算机程序代码包括：还用于当各缓存区间中，包含该指定索引位的缓存地址对应的缓存块均不为可用缓存块时，按照预设的缓存区间顺序，将内存中的该指定数据写入第一个缓存区间中、包含该指定索引位的缓存地址对应的缓存块。
进一步的，待控制级缓存的缓存地址还包含区间位；
该区间位为缓存地址中的高位，索引位为缓存地址中的低位。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中特定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中特定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中特定的功能的步骤。
尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
显然，本领域的技术人员可以对本发明实施例进行各种改动和变型而不脱离本发明实施例的精神和范围。这样，倘若本发明实施例的这些修改和变 型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (23)

  1. 一种多级缓存的功耗控制方法，其特征在于，包括：
    获取多级缓存中待控制级缓存包括的各缓存区间的访问率；其中，所述待控制级缓存为所述多级缓存中的二级或二级以上缓存；所述待控制级缓存包括至少两个缓存区间，每个缓存区间包括至少一个缓存块；
    根据所述各缓存区间的访问率，控制各缓存区间的功耗相关参数。
  2. 如权利要求1所述的方法，其特征在于，所述功耗相关参数包括电源电压和/或时钟频率；
    根据所述各缓存区间的访问率，控制各缓存区间的功耗相关参数，包括：
    所述各缓存区间中的每个缓存区间为指定缓存区间，当所述指定缓存区间的访问率高于第一预设阈值时，调整所述指定缓存区间的电源电压和/或时钟频率升高；
    当所述指定缓存区间的访问率低于第二预设阈值时，调整所述指定缓存区间的电源电压和/或时钟频率降低；
    其中，所述第一预设阈值大于所述第二预设阈值。
  3. 如权利要求2所述的方法，其特征在于，在调整所述指定缓存区间的电源电压之前，还包括：
    确定当前时刻已到达采用预设电压调整周期调整所述指定缓存区间的电源电压的时刻；
    在调整所述指定缓存区间的时钟频率之前，还包括：
    确定当前时刻已到达采用预设频率调整周期调整所述指定缓存区间的时钟频率的时刻；
    其中，所述预设电压调整周期大于所述预设频率调整周期。
  4. 如权利要求2或3所述的方法，其特征在于，根据所述各缓存区间的访问率，控制各缓存区间的功耗相关参数，还包括：
    当所述指定缓存区间的访问率低于第二预设阈值的次数达到预设次数、 且所述指定缓存区间中可用缓存块的数量达到预设数量时，关闭所述指定缓存区间的电源和/或时钟。
  5. 如权利要求1-4任一所述的方法，其特征在于，具体采用如下方式将内存中的指定数据写入所述待控制级缓存：
    获取所述指定数据在内存中对应的内存地址包含的索引位，所述索引位为指定索引位；其中，所述内存的内存地址和所述待控制级缓存的缓存地址均包含索引位，每个缓存地址对应一个缓存块；
    按照预设的缓存区间顺序，依次确定所述各缓存区间中、包含所述指定索引位的缓存地址对应的缓存块是否为可用缓存块，直至确定出可用缓存块；
    将内存中的所述指定数据写入确定出的可用缓存块。
  6. 如权利要求5所述的方法，其特征在于，还包括：
    当所述各缓存区间中，包含所述指定索引位的缓存地址对应的缓存块均不为可用缓存块时，按照所述预设的缓存区间顺序，将内存中的所述指定数据写入第一个缓存区间中、包含所述指定索引位的缓存地址对应的缓存块。
  7. 如权利要求5或6所述的方法，其特征在于，所述待控制级缓存的缓存地址还包含区间位；
    所述区间位为所述缓存地址中的高位，所述索引位为所述缓存地址中的低位。
  8. 一种多级缓存的功耗控制装置，其特征在于，包括：
    获取单元，用于获取多级缓存中待控制级缓存包括的各缓存区间的访问率；其中，所述待控制级缓存为所述多级缓存中的二级或二级以上缓存；所述待控制级缓存包括至少两个缓存区间，每个缓存区间包括至少一个缓存块；
    控制单元，用于根据所述各缓存区间的访问率，控制各缓存区间的功耗相关参数。
  9. 如权利要求8所述的装置，其特征在于，所述功耗相关参数包括电源电压和/或时钟频率；
    所述控制单元，具体用于所述各缓存区间中的每个缓存区间为指定缓存 区间，当所述指定缓存区间的访问率高于第一预设阈值时，调整所述指定缓存区间的电源电压和/或时钟频率升高；当所述指定缓存区间的访问率低于第二预设阈值时，调整所述指定缓存区间的电源电压和/或时钟频率降低；其中，所述第一预设阈值大于所述第二预设阈值。
  10. 如权利要求9所述的装置，其特征在于，所述控制单元，还用于在调整所述指定缓存区间的电源电压之前，确定当前时刻已到达采用预设电压调整周期调整所述指定缓存区间的电源电压的时刻；在调整所述指定缓存区间的时钟频率之前，确定当前时刻已到达采用预设频率调整周期调整所述指定缓存区间的时钟频率的时刻；其中，所述预设电压调整周期大于所述预设频率调整周期。
  11. 如权利要求9或10所述的装置，其特征在于，所述控制单元，还用于当所述指定缓存区间的访问率低于第二预设阈值的次数达到预设次数、且所述指定缓存区间中可用缓存块的数量达到预设数量时，关闭所述指定缓存区间的电源和/或时钟。
  12. 如权利要求8-11任一所述的装置，其特征在于，所述装置还包括写入单元，用于具体采用如下方式将内存中的指定数据写入所述待控制级缓存：
    获取所述指定数据在内存中对应的内存地址包含的索引位，所述索引位为指定索引位；其中，所述内存的内存地址和所述待控制级缓存的缓存地址均包含索引位，每个缓存地址对应一个缓存块；按照预设的缓存区间顺序，依次确定所述各缓存区间中、包含所述指定索引位的缓存地址对应的缓存块是否为可用缓存块，直至确定出可用缓存块；将内存中的所述指定数据写入确定出的可用缓存块。
  13. 如权利要求12所述的装置，其特征在于，所述写入单元，还用于当所述各缓存区间中，包含所述指定索引位的缓存地址对应的缓存块均不为可用缓存块时，按照所述预设的缓存区间顺序，将内存中的所述指定数据写入第一个缓存区间中、包含所述指定索引位的缓存地址对应的缓存块。
  14. 如权利要求12或13所述的装置，其特征在于，所述待控制级缓存 的缓存地址还包含区间位；
    所述区间位为所述缓存地址中的高位，所述索引位为所述缓存地址中的低位。
  15. 一种移动终端设备，其特征在于，包括如权利要求8-14任一所述的多级缓存的功耗控制装置。
  16. 一种移动终端设备，其特征在于，包括处理器和存储器，所述处理器运行所述存储器中存储的预设程序，用于：
    获取多级缓存中待控制级缓存包括的各缓存区间的访问率；其中，所述待控制级缓存为所述多级缓存中的二级或二级以上缓存；所述待控制级缓存包括至少两个缓存区间，每个缓存区间包括至少一个缓存块；根据所述各缓存区间的访问率，控制各缓存区间的功耗相关参数。
  17. 如权利要求16所述的设备，其特征在于，所述功耗相关参数包括电源电压和/或时钟频率；
    所述处理器，具体用于：
    所述各缓存区间中的每个缓存区间为指定缓存区间，当所述指定缓存区间的访问率高于第一预设阈值时，调整所述指定缓存区间的电源电压和/或时钟频率升高；当所述指定缓存区间的访问率低于第二预设阈值时，调整所述指定缓存区间的电源电压和/或时钟频率降低；其中，所述第一预设阈值大于所述第二预设阈值。
  18. 如权利要求17所述的设备，其特征在于，所述处理器，还用于：
    在调整所述指定缓存区间的电源电压之前，确定当前时刻已到达采用预设电压调整周期调整所述指定缓存区间的电源电压的时刻；在调整所述指定缓存区间的时钟频率之前，确定当前时刻已到达采用预设频率调整周期调整所述指定缓存区间的时钟频率的时刻；其中，所述预设电压调整周期大于所述预设频率调整周期。
  19. 如权利要求17或18所述的设备，其特征在于，所述处理器，还用于：
    当所述指定缓存区间的访问率低于第二预设阈值的次数达到预设次数、且所述指定缓存区间中可用缓存块的数量达到预设数量时，关闭所述指定缓存区间的电源和/或时钟。
  20. 如权利要求16-19任一所述的设备，其特征在于，所述处理器，还用于具体采用如下方式将内存中的指定数据写入所述待控制级缓存：
    获取所述指定数据在内存中对应的内存地址包含的索引位，所述索引位为指定索引位；其中，所述内存的内存地址和所述待控制级缓存的缓存地址均包含索引位，每个缓存地址对应一个缓存块；按照预设的缓存区间顺序，依次确定所述各缓存区间中、包含所述指定索引位的缓存地址对应的缓存块是否为可用缓存块，直至确定出可用缓存块；将内存中的所述指定数据写入确定出的可用缓存块。
  21. 如权利要求20所述的设备，其特征在于，所述处理器，还用于：
    当所述各缓存区间中，包含所述指定索引位的缓存地址对应的缓存块均不为可用缓存块时，按照所述预设的缓存区间顺序，将内存中的所述指定数据写入第一个缓存区间中、包含所述指定索引位的缓存地址对应的缓存块。
  22. 如权利要求20或21所述的设备，其特征在于，所述待控制级缓存的缓存地址还包含区间位；
    所述区间位为所述缓存地址中的高位，所述索引位为所述缓存地址中的低位。
  23. 一种计算机程序产品，其特征在于，所述计算机程序产品包括可读取存储介质用于存储计算机程序代码，所述计算机程度代码运行在一个处理器上，所述计算机程序代码包括：用于获取多级缓存中待控制级缓存包括的各缓存区间的访问率；其中，所述待控制级缓存为所述多级缓存中的二级或二级以上缓存；所述待控制级缓存包括至少两个缓存区间，每个缓存区间包括至少一个缓存块；用于根据所述各缓存区间的访问率，控制各缓存区间的功耗相关参数。
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