WO2016076850A1 - Réécriture de données - Google Patents

Réécriture de données Download PDF

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Publication number
WO2016076850A1
WO2016076850A1 PCT/US2014/065193 US2014065193W WO2016076850A1 WO 2016076850 A1 WO2016076850 A1 WO 2016076850A1 US 2014065193 W US2014065193 W US 2014065193W WO 2016076850 A1 WO2016076850 A1 WO 2016076850A1
Authority
WO
WIPO (PCT)
Prior art keywords
memory
data
power supply
controller
segregated
Prior art date
Application number
PCT/US2014/065193
Other languages
English (en)
Inventor
Patrick A. Raymond
Nathan S. DENEUI
Dennis W. FOTHERGILL
Original Assignee
Hewlett Packard Enterprise Development Lp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Enterprise Development Lp filed Critical Hewlett Packard Enterprise Development Lp
Priority to PCT/US2014/065193 priority Critical patent/WO2016076850A1/fr
Priority to TW104135602A priority patent/TW201633050A/zh
Publication of WO2016076850A1 publication Critical patent/WO2016076850A1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations

Definitions

  • Servers may provide architectures for backing up data to flash or persistent memory as well as back-up power sources for powering this back-up of data after the loss of power.
  • Figure 1 illustrates a block diagram of an example of a system for data write back according to the present disclosure
  • Figure 2 illustrates a block diagram of an example of a system for data write back according to the present disclosure
  • Figure 3 illustrates a block diagram of an example of a system for data write back, according to the present disclosure.
  • Figure 4 illustrates an example data write back flow method according to the present disclosure. Detailed Description
  • a computing data storage system can include a number of nodes that support a number of loads.
  • the nodes can be a number of servers, for example.
  • a number of loads can include storage controllers or devices associated with the servers.
  • a load can include cache memory, dual inline memory modules (DIMMs), Non-Volatile Dual In-Line Memory Modules (NVDIMMs), and/or array control logic, among other storage controllers and/or devices associated with the servers.
  • DIMMs dual inline memory modules
  • NVDIMMs Non-Volatile Dual In-Line Memory Modules
  • array control logic among other storage controllers and/or devices associated with the servers.
  • a removal of a primary power supply can be scheduled or un-scheduled.
  • a scheduled removal of the primary power supply can be the result of scheduled maintenance on the number of nodes and/or the number of loads.
  • An unscheduled primary power supply removal can be an interruption in the primary power supply.
  • An un-scheduled primary power supply removal can occur when, for example, the primary power supply fails momentarily and/or for an extended period of time.
  • Failure can include an unintentional loss of power to nodes and/or loads from the primary power supply.
  • a micro-uninterruptible power supply can be a secondary power supply that is used to provide emergency power to a load when a primary power supply (e.g., input power source) is interrupted. Interruption of a primary power supply can refer to a power failure, power surge, inadequate power, and/or transient faults.
  • AiUPS can provide near-instantaneous protection from power interruptions by supplying energy stored in batteries, supercapacitors, or flywheels, among others.
  • a ⁇ can be a secondary power supply that is used to provide power for moving data from cache memory to non-volatile memory when the primary power is removed (e.g., backup mode).
  • the ⁇ can reside in a power supply slot and/or be a shared ⁇ , in that the shared ⁇ associated with a particular node is shared among a plurality of loads associated with that node.
  • Examples of the present disclosure can include a system that includes a [iUPS to signal a primary power supply interruption to a controller.
  • the controller can segregate a portion of memory and/or restore data to a segregated portion of memory in response to the primary power supply interruption signal.
  • FIG. 1 illustrates a block diagram of an example of a system 100 for data write back according to the present disclosure.
  • the system 100 can include a ⁇ 102 to signal 122 a primary power supply interruption to a controller 104.
  • a ⁇ can refer to an electrical apparatus that provides a temporary source of power to a load 1 18 when a primary power supply is interrupted (e.g., fails) and can be integrated into a node 1 16 (e.g., an integrated component of the server node).
  • An integrated component of the node 1 16, as used herein, can include a separate component from the node 1 16 that is combined with the node 1 16 such that the node 1 16 and the integrated component function together as a single unit.
  • a ⁇ can reside in a power supply slot of the node 1 16 (e.g., be physically and/or directly plugged in to a power supply slot of the node 1 16).
  • the ⁇ 102 can be used to protect hardware and components of the system 100, such as a system central processing unit (CPU) 106 and system DIMMs 108, from data loss in response to the primary power supply interruption.
  • CPU system central processing unit
  • DIMMs 108 system DIMMs
  • the controller 104 can manage access to memory 1 10, 1 12, and the controller 104 can segregate a portion of memory 1 14. The segregated portion of memory can be performed by the controller 104 at power up. The controller can segregate a portion of memory 1 14, for data storage. In some examples, the
  • a hidden partition can refer to a segment of non-volatile memory that is not visible to the CPU, and is exclusively reserved for a data dump upon a primary power supply interruption.
  • a data dump can refer to an amount of data transferred from one system or location to another.
  • the controller can create a hidden partition in which the segregated portion of memory 1 14 can reside in preparation for a data dump.
  • the controller 104 can identify within the portion of segregated memory an associated number of drives within the system 100.
  • the controller 104 can identify a sequential bandwidth of the associated number of the drives.
  • the controller 104 can include a delay period to assign, for restoration, a portion of persistent data to the associated number of drives. For example, the controller can delay assigning the data to be restored. Further, the controller 104 can restore data to the segregated portion of memory 1 14 in response to the primary power supply interruption signal 122.
  • the ⁇ 102 can be an integrated component of a node 1 16 and/or provide the temporary source of power to a load 1 18 associated with a node 1 16 for a threshold of time.
  • the integrated power supply can include a iUPS that is used to provide power for moving data from cache memory to nonvolatile memory when the primary power is interrupted.
  • the ⁇ can reside in a power supply slot of the node and/or be a shared ⁇ , in that the shared ⁇ associated with a particular node is shared among a plurality of loads associated with that node.
  • the ⁇ can be integrated into the node.
  • the node 1 16 and the load 1 18 can be in communication via pathway 120 (e.g., link).
  • node 1 16 can host a number of devices, such as local memory or data storage (e.g., referred generally as memory).
  • the memory may contain volatile and non-volatile memory (e.g., cache, DIMM, NVDIMM).
  • Node 1 16 can include other devices such as cache memory, DIMMs, array control logic, and storage controllers, among other devices associated with the node 1 16.
  • the node 1 16 can also include a control logic unit (not shown).
  • the segregated portion of memory 1 14 can be available for data write back during a primary power supply interruption. That is, upon primary power supply interruption, data can be dumped into the segregated portion of memory 1 14 and data write back to non-volatile memory can be performed.
  • the controller 104 can linearly restore the data from the data dump. As used herein, a linear restoration of data can refer to a straight chain of data. That is, the data is saved and restored in a sequential order. Further, the controller 104 can, in some examples, restore system functions associated with the data. In other words, data saved with the segregated portion of memory 1 14 can be implemented and restored to the functionality of the system 100.
  • a primary power supply interruption signal can be a signal that
  • a primary power supply interruption signal can include a signal from the controller 104 communicated through a system complex programmable logic device (CPLD) wired into a power button logic of the node 1 16 to initiate a sequenced shutdown of the node 1 16 as if a power button on the node 1 16 had been pressed.
  • CPLD complex programmable logic device
  • a primary power supply interruption signal can be a signal from a primary power supply unit of the primary power supply propagated using a general purpose interface (GPI) pin on a southbridge (e.g., one of two chips in a core logic chipset on a motherboard, in a northbridge/southbridge chipset architecture, of a CPU) of a CPU of the node 1 16.
  • the pin can be programmed to signal a primary power supply interruption to the operating system and the node 1 16 can then execute a segregate engine, as further discussed in Figure 2.
  • FIG. 2 illustrates a block diagram of an example of a system 230 for data write back according to the present disclosure.
  • the system 230 can utilize hardware, software (e.g., program instructions), firmware, and/or logic to perform a number of functions described herein.
  • the system 230 can be any combination of hardware and program instructions configured to share information.
  • the hardware can, for example, include a processing resource 232 and a memory resource 236 (e.g., computer or machine readable medium (CRM/MRM), database, etc.).
  • a processing resource 232 can include one or more processors capable of executing instructions stored by the memory resource 236.
  • the processing resource 232 may be implemented in a single node (e.g., node 1 16 illustrated in Figure 1 ) or distributed across multiple nodes.
  • the program instructions e.g., computer or machine readable instructions (CRI/MRI)
  • CRM computer or machine readable instructions
  • the processing resource 232 can include instructions stored on the memory resource 236 and executable by the processing resource 232 to perform a particular function, task and/or action (e.g., segregate a portion of memory 238).
  • the memory resource 236 can be a non-transitory MRM, include one or more memory components capable of storing instructions that can be executed by a processing resource 232, and may be integrated in a single node or distributed across multiple nodes.
  • the memory resource 236 can be in communication with the processing resource 232 via a communication link (e.g., a path) 234.
  • communication link 234 can provide a wired and/or wireless connection between the processing resource 232 and the memory resource 236.
  • the memory resource 236 can include segregate 238 instructions, signal 240 instructions, and/or restore data to segregate instructions.
  • instructions include at least software that can be executed by a processing resource, for example, processing resource 232, to perform a particular task, function and/or action.
  • the plurality of instructions may be combined or may be subroutines of other instructions.
  • the segregate 238 instructions, signal 240 instructions, and/or restore 242 instructions can be individual instructions located on one memory resource 236. Examples are not so limited, however, and a plurality of instructions can be located at separate and distinct memory resource locations, for example, in a distributed computing environment, cloud computing environment, etc.
  • the system 230 can include instructions executable to identify, using a controller (e.g., controller 104 illustrated in Figure 1 ), the hidden partition, including the segregated portion of memory. That is, the controller can identify the hidden partition and locate the segregated portion of memory during a data dump. In other words, the controller can, in some instances, guide the data to the segregated portion of memory for cache write back. The data within the segregated portion of memory can be restored and implemented within the system.
  • a controller e.g., controller 104 illustrated in Figure 1
  • the controller can identify the hidden partition and locate the segregated portion of memory during a data dump.
  • the controller can, in some instances, guide the data to the segregated portion of memory for cache write back. The data within the segregated portion of memory can be restored and implemented within the system.
  • Each of the plurality of instructions can include instructions that when executed by the processing resource 232 can function as an engine.
  • segregate 238 instructions can include instructions that when executed by the processing resource 232 can function as a segregation engine (not shown).
  • the signal 240 instructions can include instructions that when executed by the processing resource 232 can function as a signal engine (not shown).
  • the restore 242 instructions can include instructions that when executed by the processing resource 232 can function as a restore engine (not shown).
  • the plurality of engines can include a combination of hardware and software (e.g., program instructions), but at least include hardware configured to perform particular functions, tasks, and/or actions.
  • the plurality of engines can be used to segregate, using a controller coupled to a node, a portion of memory, wherein the segregated portion of memory is a hidden partition, signal, using a ⁇ to the controller, a primary power supply interruption, wherein theiUPS is integrated to the node, and restore, in response to the signaled primary power supply interruption, data to the segregated portion of memory.
  • the system 230 can include a database (not shown) accessible to and in communication with the plurality of engines (e.g., segregation engine, signal engine, restore engine).
  • the system 230 can include additional or fewer engines than described to perform the various functions described herein and examples are not limited to the example shown in Figure 2.
  • the system 230 can include hardware, for example, in the form of transistor logic and/or application specific integrated circuitry (ASICs), firmware, and software, for example, in the form of machine readable and executable instructions (e.g., program instructions stored in a machine readable medium), which, in cooperation can form the computing device as discussed in connection with Figure 2.
  • ASICs application specific integrated circuitry
  • Examples are not limited to the example instructions shown in Figure 2 and in some cases a number of instructions can operate together to function as a particular engine.
  • one or more engines described, or one or more instructions described may be combined or may be a sub-engine of another engine.
  • the engines and/or instructions of Figure 2 can be located in a single system and/or computing system or reside in separate distinct locations in a distributed network, cloud computing, enterprise service environment (e.g., Software as a Service (SaaS) environment), etc.
  • SaaS Software as a Service
  • Figure 3 illustrates a block diagram of an example of a segregated portion of memory 314 for data write back, according to the present disclosure.
  • segregated portion of memory 314 can include within a segregated portion of memory (e.g., portion 1 14 illustrated in Figure 1 ) cache information 352, metadata 354, and data 356.
  • the segregation of a portion of memory can be initiated during system power up. That is, in some instances, the portion of memory (e.g., portion 1 14 as illustrated in Figure 1 ) can be segregated prior to a primary power supply interruption. The portion of memory can be segregated by a controller as a precaution in the event of a primary power supply interruption and forthcoming data dump.
  • a controller e.g., controller 104 illustrated in Figure 1
  • the data can be sequentially ordered such that the different types of data (e.g., cache data 352, metadata 354, and data 356) are categorized.
  • restoring data to the segregated portion of memory can restore functions associated with the data upon system power up. That is, the data dump into the segregated portion of memory can save the data and implement the data, thereby restoring the functions associated with the saved data.
  • cache data 352 stored within the segregated portion of memory can be used by the CPU upon system power up. For instance, the cache data can be written back such that the CPU can utilize the data.
  • FIG. 4 illustrates an example data write back flow method 460 according to the present disclosure.
  • the method 460 can include segregating, using a controller coupled to a node, a portion of memory, wherein the segregated portion of memory is a hidden partition.
  • the controller can segregate a portion of memory to be designated for memory in the event of a primary power interruption.
  • the segregated portion of memory can be a hidden partition.
  • the hidden partition can isolate the portion of memory such that the computing system does not use the portion of memory for memory storage during normal functioning of the system.
  • the method 460 can include signaling, using a ⁇ , to the controller a primary power supply interruption.
  • the iUPS can be integrated to the node and can include providing backup power supply as a temporary source of power to the node for a threshold of time. That is, the [iUPS can be associated with the node and provide a source of backup power supply upon primary power supply interruption.
  • the ⁇ can provide the backup power supply for a finite period of time. For example, upon primary power supply interruption, the ⁇ can provide power to the node for a threshold of time, such as sixty (60) seconds.
  • the method 460 can include identifying, using the controller and in response to the signal, the hidden partition including the segregated portion of memory.
  • the ⁇ can provide power for a threshold of time, during which time the controller can identify the hidden partition.
  • the controller can proceed to data dump. That is, the controller can transfer data to the hidden partition, including the segregated portion of memory. The data can be saved within the segregated portion of memory and written to nonvolatile memory.
  • the method 460 can include sequentially transferring data to the segregated portion of memory. For instance, the controller can transfer the data in a sequential manner.
  • the method 460 can include restoring, in response to the identified segregated portion of memory, data to the segregated portion of memory.
  • the data saved within the segregated portion of memory can be written to non-volatile memory.
  • the data can be implemented and restored upon system power up. That is, the data dump to the segregated portion of memory can be saved, implemented, and thereby restored to the system.
  • the method 460 can include a plurality of controllers, including the aforementioned controller and a plurality of drives associated with a plurality of portions of memory, performing a plurality of restorations of data to a plurality of segregated portions of memory. That is, multiple controllers running multiple sets of drives can perform data dumps and restore data to memory.
  • logic is an alternative or additional processing resource to perform a particular action and/or function, etc., described herein, which includes hardware, e.g., various forms of transistor logic, application specific integrated circuits (ASICs), etc., as opposed to computer executable instructions (e.g., software firmware, etc.) stored in memory and executable by a processor.
  • hardware e.g., various forms of transistor logic, application specific integrated circuits (ASICs), etc.
  • computer executable instructions e.g., software firmware, etc.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)
  • Power Sources (AREA)

Abstract

Des modes de réalisation donnés à titre d'exemple concernent la réécriture de données. L'invention concerne par exemple un système de réécriture de données, comprenant un module d'alimentation sans micro-coupure (µUPS) servant à signaler une interruption d'alimentation électrique primaire à un contrôleur, ce dernier pouvant séparer une partie de mémoire et restaurer des données dans la partie de mémoire séparée en réponse au signal d'interruption d'alimentation électrique primaire.
PCT/US2014/065193 2014-11-12 2014-11-12 Réécriture de données WO2016076850A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/US2014/065193 WO2016076850A1 (fr) 2014-11-12 2014-11-12 Réécriture de données
TW104135602A TW201633050A (zh) 2014-11-12 2015-10-29 資料寫回技術

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PCT/US2014/065193 WO2016076850A1 (fr) 2014-11-12 2014-11-12 Réécriture de données

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11397678B2 (en) 2020-10-20 2022-07-26 Red Hat, Inc. Pooling distributed storage nodes that have backup power supplies and write-back caching capabilities

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0718766A2 (fr) * 1994-12-21 1996-06-26 Symbios Logic Inc. Méthode d'opération d'un réseau de disques de stockage de données
US5889933A (en) * 1997-01-30 1999-03-30 Aiwa Co., Ltd. Adaptive power failure recovery
US20110066792A1 (en) * 2008-02-10 2011-03-17 Rambus Inc. Segmentation Of Flash Memory For Partial Volatile Storage
KR20110121579A (ko) * 2010-04-30 2011-11-07 주식회사 태진인포텍 반도체 저장장치 백업 및 복구 시스템 및 방법
JP2012226569A (ja) * 2011-04-20 2012-11-15 Fanuc Ltd 記憶装置のデータ保護装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0718766A2 (fr) * 1994-12-21 1996-06-26 Symbios Logic Inc. Méthode d'opération d'un réseau de disques de stockage de données
US5889933A (en) * 1997-01-30 1999-03-30 Aiwa Co., Ltd. Adaptive power failure recovery
US20110066792A1 (en) * 2008-02-10 2011-03-17 Rambus Inc. Segmentation Of Flash Memory For Partial Volatile Storage
KR20110121579A (ko) * 2010-04-30 2011-11-07 주식회사 태진인포텍 반도체 저장장치 백업 및 복구 시스템 및 방법
JP2012226569A (ja) * 2011-04-20 2012-11-15 Fanuc Ltd 記憶装置のデータ保護装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11397678B2 (en) 2020-10-20 2022-07-26 Red Hat, Inc. Pooling distributed storage nodes that have backup power supplies and write-back caching capabilities

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