WO2016074152A1 - Method and apparatus for processing differential clock recovery - Google Patents

Abstract

The present invention provides a method and apparatus for processing differential clock recovery. The method comprises: a receiving side device receives a first Ethernet packet sent by a sending side device, wherein the first Ethernet packet is an Ethernet packet acquired by the sending side device after converting a time division multiplexing (TDM) service data frame according to a packet delivery rate of the sending side device; the receiving side device acquires a frequency deviation value according to the packet delivery rate of the receiving side device, the working clock frequency of a counter on the sending side device and the value of the counter in the acquired first Ethernet packet; the receiving side device acquires the output frequency of a phase-locked loop by means of the frequency deviation value; and the receiving side device recovers the TDM service data frame from the first Ethernet packet according to the output frequency of the phase-locked loop. In the present invention, a frequency deviation value is acquired by means of software according to the value of a counter in a first Ethernet packet, and therefore different hardware solutions are mutually compatible.

Description

Method and device for processing differential clock recovery Technical field

The embodiments of the present invention relate to communication technologies, and in particular, to a method and an apparatus for processing differential clock recovery.

Background technique

The Circuit Emulation Service (CES) technology can implement the Internet Protocol IP encapsulation of traditional Time Division Multiplexing (TDM) format information. Specifically, the transmitting side encapsulates different numbers of TDM timeslots into IP packets for transmission, and then removes the TDM time slots in the IP packets from the packets to the TDM time slots on the receiving side, thereby implementing TDM. The service traverses the Internet Protocol (IP) network. The CES service uses the CES technology to encapsulate the TDM service data with a special circuit emulation header, and then transmits the packet to the receiving side through a packet switching network (PSN) to decapsulate and reconstruct the TDM based on the clock information. business. The clock information of the TDM service (that is, the clock frequency of the TDM service) is different. Therefore, in the CES service, the clock information of the TDM service must be transmitted along with the CES service, and then recovered together on the receiving side as the TDM service clock. .

In addition, in the CES service, the differential clock recovery (DCR) technology can implement the reliable transmission of the TDM service clock information in the radio bearer network. FIG. 1 is a schematic diagram of the application scenario of the DCR technology in the radio bearer network in the prior art. . As shown in FIG. 1 , the scenario mainly involves: a transmitting side device 1, a receiving side device 2, a TDM device 3, a TDM device 4, and a packet switching network 5. The TDM device 3 provides the TDM service to the transmitting device 1 , and the transmitting device 1 and the receiving device 2 have the same local reference clock, and the two transmit the CES service through the Packet Switching Network (PSN). The receiving device 2 provides the TDM service recovered from the CES service to the TDM device 4.

Specifically, in the application scenario shown in FIG. 1 , the main workflow of the DCR technology is: on the transmitting side, the transmitting device 1 extracts clock information of the TDM service from the TDM service provided by the TDM device 3, and then uses the local reference. Clock comparison, calculate the frequency offset value freq between the two, and then root The data frame of the TDM service is encapsulated into the Ethernet packet according to the Packet Per Second (PPS) of the transmitting device, and the frequency offset value freq is written to the specified location of the Ethernet packet, and then the PSN is used to The Ethernet message is sent out. On the receiving side, after receiving the Ethernet message sent by the transmitting device 1, the receiving device 2 extracts freq from the specified position of the Ethernet message, and then adds freq to the local reference clock, and the calculated frequency information is The clock information of the TDM service, where the local reference clock of the receiving device 2 is the same as the local reference clock of the transmitting device 1, and then the Ethernet packet is restored to the TDM service according to the clock information of the TDM service, and is provided to the TDM. Device 4.

However, since the frequency offset value is calculated by hardware on the transmitting side, the frequency offset value freq calculated in real time is not high, and is limited by hardware conditions. When the transmitting side device uses different hardware schemes to calculate the frequency offset value freq. The same device on the receiving side cannot implement interworking between different hardware solutions, which limits the application range of DCR technology.

Summary of the invention

The embodiment of the invention provides a method and a device for processing a differential clock recovery. The receiving device also obtains a frequency control word through software according to the value of the counter in the first Ethernet message, thereby implementing interworking between different hardware solutions.

A first aspect of the embodiments of the present invention provides a method for processing differential clock recovery, where the method includes:

Receiving, by the receiving device, the first Ethernet packet sent by the sending device, where the first Ethernet packet is obtained by converting, by the transmitting device, the time division multiplexing TDM service data frame according to the sending rate of the sending device. Ethernet message;

The receiving side device acquires a frequency offset value according to the packet sending rate of the receiving device, the working clock frequency of the counter on the transmitting device, and the obtained value in the counter in the first Ethernet packet; wherein the receiving side The sending rate of the device is the same as the sending rate of the transmitting device, and the value in the counter is time stamp information recorded by the counter at the working clock frequency of the counter;

The receiving side device acquires an output frequency of the phase locked loop by using the frequency offset value;

The receiving side device recovers the TDM service data frame from the first Ethernet packet according to an output frequency of the phase locked loop.

In a first possible implementation manner of the first aspect, if the first Ethernet packet includes a value in a counter, the receiving, for the first Ethernet packet sent by each of the sending side devices, the receiving The side device obtains the frequency offset value according to the packet sending rate of the receiving device, the operating clock frequency of the counter on the transmitting device, and the obtained value in the counter in the first Ethernet packet, which specifically includes:

Determining, according to the packet sending rate K of the receiving device, the working clock frequency f ₀ of the counter on the transmitting device and the value t ₁ in the counter in the first Ethernet packet,

Obtain the frequency control word freq_offset;

Wherein, T is a packet sending period, T=1/K, and t′ ₁ is a value in a counter in the second Ethernet packet, and the second Ethernet packet is received by the receiving device and the first ether. The Ethernet message adjacent to the packet.

In a second possible implementation manner of the first aspect, if the first Ethernet message includes a value in the at least two first counters, and a value in the at least two second counters, for each of the sending sides The first Ethernet packet sent by the device, the receiving side device acquires the frequency according to the packet sending rate of the receiving device, the working clock frequency of the counter on the transmitting device, and the obtained value in the counter in the first Ethernet message. The bias value includes:

According to the packet rate K of the receiving device, the operating clock frequency f ₁₀ of the first counter on the transmitting device, the operating clock frequency f ₁₁ of the second counter on the transmitting device, and the first counter in the first Ethernet packet. a value t ₁₀ and a value t ₁₁ in the second counter in the first Ethernet message, using a formula

Receiving an Ethernet message adjacent to the first Ethernet message;

The receiving side device acquires the frequency control word according to the relative frequency control word.

In a third possible implementation manner of the first aspect, if the first Ethernet packet includes a value in a counter, the first Ethernet message sent by each of the sending side devices, the receiving side The device obtains the frequency offset value according to the packet sending rate of the receiving device, the operating clock frequency of the counter on the transmitting device, and the obtained value in the counter in the first Ethernet packet, which specifically includes:

The receiving side device in the first packet sending period according to the packet sending rate K of the receiving device, the value t' _1n in the counter in the Ethernet packet received by the receiving device in the nth packet sending period, and the first packet sending period The value t ₁ in the counter in the received Ethernet message and the working clock frequency f ₀ of the counter on the transmitting device are calculated by using a formula

Obtaining the frequency control word freq_offset;

Where T is the delivery period, T=1/K.

With reference to the first possible implementation of the first aspect, to any possible implementation of the third possible implementation of the first aspect, in a fourth possible implementation manner of the first aspect, And the at least two the first Ethernet packets sent by the sending device, the method further includes:

Obtaining a final frequency control word from a frequency control word corresponding to the first Ethernet message sent by all the sending side devices;

And the receiving side device acquires an output frequency of the phase locked loop by using the frequency control word, specifically:

The receiving side device acquires an output frequency of the phase locked loop by using the final frequency control word.

With the fourth possible implementation of the first aspect, in a fifth possible implementation manner of the first aspect, after the acquiring the frequency control word, the method further includes:

The frequency control word is filtered.

A second aspect of the embodiments of the present invention provides a processing apparatus for differential clock recovery, where the apparatus includes:

The receiving module is configured to receive the first Ethernet packet sent by the sending device, where the first Ethernet packet is used by the sending device to convert the time division multiplexed TDM service data frame according to the sending rate of the sending device. Ether message obtained afterwards;

a frequency offset value obtaining module, configured to obtain a frequency offset value according to an output rate of the receiving device, a working clock frequency of the counter on the transmitting device, and a value in the obtained counter in the first Ethernet message; The sending rate of the receiving side device is the same as the sending rate of the sending side device, and the value in the counter is time stamp information recorded by the counter at the working clock frequency of the counter;

An output module, configured to obtain an output frequency of the phase locked loop by using the frequency offset value;

And a recovery module, configured to recover the TDM service data frame from the first Ethernet packet according to an output frequency of the phase locked loop.

In a first possible implementation manner of the second aspect, if the first Ethernet packet includes a value in a counter, the frequency offset value acquiring module is specifically configured to:

Determining, according to the packet sending rate K of the receiving device, the working clock frequency f ₀ of the counter on the transmitting device and the value t ₁ in the counter in the first Ethernet packet,

Obtain the frequency control word freq_offset;

Wherein, T is a packet sending period, T=1/K, and t′ ₁ is a value in a counter in the second Ethernet packet, and the second Ethernet packet is received by the receiving device and the first ether. The Ethernet message adjacent to the packet.

In a second possible implementation manner of the second aspect, if the first Ethernet message includes a value in the at least two first counters and a value in the at least two second counters, the frequency offset value acquiring module Specifically used for:

According to the packet rate K of the receiving device, the operating clock frequency f ₁₀ of the first counter on the transmitting device, the operating clock frequency f ₁₁ of the second counter on the transmitting device, and the first counter in the first Ethernet packet. a value t ₁₀ and a value t ₁₁ in the second counter in the first Ethernet message, using a formula

Obtaining a relative frequency control word freq_offset1, and acquiring a frequency control word according to the relative frequency control word; wherein T is a packet sending period, T=1/K, and t′ ₁₀ is the first counter in the second Ethernet message value, t _'11 is an Ethernet packet a second value of the second counter, the second Ethernet packet to the reception-side device receives the first Ethernet packets in Ethernet frames adjacent Text.

In a third possible implementation manner of the second aspect, if the first Ethernet packet includes a value in a counter, the frequency offset value acquiring module is specifically configured to:

The receiving side device in the first packet sending period according to the packet sending rate K of the receiving device, the value t' _1n in the counter in the Ethernet packet received by the receiving device in the nth sending period, and the first packet sending period The value t ₁ in the counter in the received Ethernet message and the working clock frequency f ₀ of the counter on the transmitting device are calculated by using a formula

Obtaining the frequency control word freq_offset;

Where T is the delivery period, T=1/K.

Combining the first possible implementation of the second aspect with the third possible implementation of the second aspect In a fourth possible implementation manner of the second aspect, if the receiving side device receives the first Ethernet packet sent by the at least two sending side devices, the frequency is The offset obtaining module is further configured to obtain a final frequency control word from the frequency control words corresponding to the first Ethernet message sent by all the sending side devices;

The output frequency acquisition module is further configured to acquire an output frequency of the phase locked loop by using the final frequency control word.

In conjunction with the fourth possible implementation of the second aspect, in a fifth possible implementation manner of the second aspect, the device further includes:

And a filtering module, configured to filter the frequency control word.

The method for processing the differential clock recovery provided by the embodiment, the first Ethernet message sent by the sending device is received by the receiving device, according to the sending rate of the receiving device, the working clock frequency of the counter on the transmitting device, and the obtained first Obtain a frequency offset value in the counter in the Ethernet packet, input the frequency offset value into the phase-locked loop, obtain the output frequency of the phase-locked loop, and use the output frequency as the clock frequency of the TDM service from the first Ethernet packet. Recover TDM service data frames. In the present embodiment, the frequency offset value is obtained by software according to the value of the counter in the first Ethernet message. Therefore, in the embodiment, the method for obtaining the frequency offset value by using hardware calculation in the transmitting device is used in this embodiment. Even if the transmitting device uses different hardware solutions, the receiving device can obtain the frequency offset value through software according to the value of the counter in the first Ethernet packet, and implement interworking between different hardware solutions.

DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief description of the drawings used in the embodiments or the prior art description will be briefly described below. Obviously, the drawings in the following description It is a certain embodiment of the present invention, and other drawings can be obtained from those skilled in the art without any inventive labor.

1 is a schematic diagram of an application scenario of a DCR technology in a radio bearer network in the prior art;

2 is a flowchart of a method for processing differential clock recovery according to Embodiment 1 of the present invention;

3 is a flowchart of a method for processing differential clock recovery according to Embodiment 2 of the present invention;

4 is a flowchart of a method for processing differential clock recovery according to Embodiment 3 of the present invention;

FIG. 5 is a flowchart of a method for processing differential clock recovery according to Embodiment 5 of the present invention; FIG.

FIG. 6 is a schematic structural diagram of a processing apparatus for differential clock recovery according to Embodiment 6 of the present invention; FIG.

FIG. 7 is a schematic structural diagram of a processing apparatus for differential clock recovery according to Embodiment 11 of the present invention.

detailed description

The technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. It is a partial embodiment of the invention, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

Embodiment 1

FIG. 2 is a flowchart of a method for processing differential clock recovery according to Embodiment 1 of the present invention. As shown in FIG. 2, the method in this embodiment includes:

The receiving device receives the first Ethernet packet sent by the sending device.

The first Ethernet packet is an Ethernet packet obtained by converting the TDM service data frame according to the packet sending rate of the transmitting device.

In this embodiment, a counter is set on the transmitting device, and the working clock of the counter is synchronized with the system clock. In addition, the transmitting device converts the TDM service into an Ethernet packet according to the packet sending rate information of the transmitting device, and takes the value in the counter and writes the value in the counter to the designated location of the Ethernet packet to generate the first Ethernet packet, and then The first Ethernet message is sent to the receiving device. The working clock frequency of the counter refers to the frequency at which the counter is counted. The value in the counter refers to the value recorded by the counter in the preset period, which is equivalent to a time stamp information.

It should be noted that, in this embodiment, the same receiving side device may receive only the first Ethernet packet sent by the sending device, and may also receive the first Ethernet packet sent by the multiple sending device. In addition, for each first Ethernet message, the first Ethernet message may include only one value in one counter, or may include a value in multiple counters, that is, multiple counters are set on the sending side device, for each The counters set an operating clock frequency, and the operating clock frequency of each counter is different, which is not limited in the present invention.

The receiving device obtains the frequency offset value according to the packet sending rate of the receiving device, the working clock frequency of the counter on the transmitting device, and the value in the counter in the obtained first Ethernet message.

The sending rate of the receiving device is the same as the sending rate of the transmitting device, and the value in the counter is The timestamp information recorded by the counter at the operating clock frequency of the counter.

In this embodiment, the working clock frequency of the counter on the transmitting device is written into the receiving device in advance. When a counter is set on the transmitting device, only the operating clock frequency of the counter is written into the receiving device. After receiving the first Ethernet packet, the receiving device obtains the frequency offset value according to the packet sending rate of the receiving device, the working clock frequency of the counter, and the value of the counter in the obtained first Ethernet packet; When multiple counters are set, the working clock frequency of each counter needs to be written into the receiving device. After receiving the first Ethernet packet, the receiving device receives the packet rate according to the receiving device and each counter. The working clock frequency and the value of each counter in the first Ethernet message obtain the relative frequency offset value, and then obtain the frequency offset value according to the relative frequency offset value.

It should be noted that, in this embodiment, in the receiving device, the frequency offset value can be obtained by using software, and there are various methods for obtaining the frequency offset value, and those skilled in the art can select a suitable method to obtain the frequency offset value. The invention is not limited thereto.

103. The receiving device acquires an output frequency of the phase locked loop by using a frequency offset value.

In this embodiment, the frequency offset value is used as an input of the phase locked loop to obtain the output frequency of the phase locked loop.

104. The receiving device recovers the TDM service data frame from the first Ethernet packet according to the output frequency of the phase locked loop.

In this embodiment, the output frequency of the phase-locked loop is used as the clock frequency of the TDM service, and the TDM service data frame is recovered from the first Ethernet packet according to the clock frequency.

The method for processing the differential clock recovery provided by the embodiment, the first Ethernet message sent by the sending device is received by the receiving device, according to the sending rate of the receiving device, the working clock frequency of the counter on the transmitting device, and the obtained first Obtain a frequency offset value in the counter in the Ethernet packet, input the frequency offset value into the phase-locked loop, obtain the output frequency of the phase-locked loop, and use the output frequency as the clock frequency of the TDM service from the first Ethernet packet. Recover TDM service data frames. In the present embodiment, the frequency offset value is obtained by software according to the value of the counter in the first Ethernet message. Therefore, in the embodiment, the method for obtaining the frequency offset value by using hardware calculation in the transmitting device is used in this embodiment. Even if the transmitting device uses different hardware solutions, the receiving device can obtain the frequency offset value through software according to the value of the counter in the first Ethernet packet, and implement interworking between different hardware solutions.

Embodiment 2

FIG. 3 is a flowchart of a method for processing differential clock recovery according to Embodiment 2 of the present invention. In this reality In the embodiment, the technical solution of the embodiment is described in detail by taking the value of a counter included in the first Ethernet packet as an example. As shown in FIG. 3, the method in this embodiment includes:

201. The receiving device receives the first Ethernet packet sent by the sending device.

The first Ethernet packet is an Ethernet packet obtained by converting the TDM service data frame according to the packet sending rate of the transmitting device.

In this embodiment, 201 is the same as the implementation principle of 101 in the first embodiment shown in FIG. 2, and details are not described herein again.

202. According to the packet sending rate K of the receiving device, the working clock frequency f ₀ of the counter on the transmitting device, and the value t ₁ in the counter in the first Ethernet message, the frequency control word freq_offset is obtained by using formula (1). ;

Where T is the packet-issuing period, T=1/K, t′ ₁ is the value in the counter in the second Ethernet message, and the second Ethernet packet is the Ethernet that is received by the receiving device and adjacent to the first Ethernet packet. Message.

It should be noted that, in this embodiment, the first Ethernet packet and the second Ethernet packet carry an identifier (ID), an ID in the first Ethernet packet, and an identifier in the second Ethernet packet. The ID is adjacent, and the ID in the second Ethernet packet is greater than the ID in the first Ethernet packet. For example, the ID in the first Ethernet packet is 3, and the ID in the second Ethernet packet is 4. The Ethernet message is adjacent to the second Ethernet message.

Optionally, in this embodiment, if the first Ethernet packet includes the count difference Δcnt of the line clock corresponding to the sending side device and the system clock at the same frequency f, the frequency control word may also be obtained by using formula (2).

203. The receiving device acquires an output frequency of the phase locked loop by using a frequency control word.

In this embodiment, the local reference clock frequency is used as the input of the phase locked loop, and the frequency control word is used as the input of the phase locked loop feedback circuit, and the output frequency is obtained at the output end of the phase locked loop. The frequency control word is equivalent to a proportional value, that is, the phase-locked loop outputs the local reference clock frequency according to a certain ratio according to the frequency control word.

204. The receiving device recovers the TDM from the first Ethernet packet according to the output frequency of the phase locked loop. Business data frame.

In this embodiment, 204 is the same as the implementation principle of 104 in the first embodiment shown in FIG. 2, and details are not described herein again.

The method for processing the differential clock recovery provided in this embodiment, when the value of the counter is included in the first Ethernet packet, the first Ethernet message sent by the sending device is received by the receiving device, according to the packet sending rate of the receiving device. And obtaining a frequency control word by inputting a working clock frequency of the counter on the transmitting device and a value in the obtained counter in the first Ethernet message, inputting the frequency control word into the phase locked loop, and acquiring an output frequency of the phase locked loop, The output frequency is used as the clock frequency of the TDM service to recover the TDM service data frame from the first Ethernet packet. Since the frequency control word is obtained by software according to the value of the counter in the first Ethernet message, the method for calculating the frequency offset value by using the hardware in the transmitting device is compared to the method in the prior art. The transmitting device uses different hardware schemes. The receiving device can obtain the frequency control word through software according to the value of the counter in the first Ethernet message, and obtain the output frequency of the phase locked loop through the frequency control word to implement different hardware. Interworking between the schemes, and only need to set a simple counter on the transmitting side, the value in the counter can be written into the Ethernet packet, and the calculation of the frequency offset value is not dependent on the complicated hardware, thereby reducing the hardware of the transmitting side. Implementation complexity and equipment costs.

Embodiment 3

FIG. 4 is a flowchart of a method for processing differential clock recovery according to Embodiment 3 of the present invention. In this embodiment, the first Ethernet message includes a value in the at least two first counters and a value in the at least two second counters, that is, an example in which the first Ethernet message includes a plurality of counters. The technical solution of this embodiment will be described in detail. As shown in FIG. 4, the method in this embodiment includes:

301. The receiving device receives the first Ethernet packet sent by the sending device.

The first Ethernet packet is an Ethernet packet obtained by converting the TDM service data frame according to the packet sending rate of the transmitting device.

In this embodiment, the implementation principle of 301 is the same as that of 101 in the first embodiment shown in FIG. 2, and details are not described herein again.

302. According to the packet sending rate K of the receiving device, the working clock frequency f ₁₀ of the first counter on the transmitting device, the working clock frequency f ₁₁ of the second counter on the transmitting device, and the first counter in the first Ethernet packet. The value t ₁₀ and the value t ₁₁ in the second counter in the first Ethernet message, using equation (3), obtain the relative frequency control word freq_offset1.

Where freq_offset1 is the relative frequency control word, T is the packet sending period, T=1/K, K is the packet sending rate of the receiving device, and t′ ₁₀ is the value in the first counter in the second Ethernet message, t′ ₁₁ is The value of the second counter in the second Ethernet packet, where the second Ethernet packet is an Ethernet packet received by the receiving device and adjacent to the first Ethernet packet.

It should be noted that, in this embodiment, the first Ethernet packet and the second Ethernet packet carry an identifier (ID), an ID in the first Ethernet packet, and an identifier in the second Ethernet packet. The ID is adjacent, and the ID in the second Ethernet packet is greater than the ID in the first Ethernet packet. For example, the ID in the first Ethernet packet is 3, and the ID in the second Ethernet packet is 4. The Ethernet message is adjacent to the second Ethernet message.

303. The receiving device acquires a frequency control word according to the relative frequency control word.

In this embodiment, after obtaining the relative frequency control word of the first Ethernet message, there are various methods for obtaining the final frequency control word according to the relative frequency control word. For example, the receiving side device receives two adjacent first ethers. After the messages A and B, according to the method of step 302, the relative frequency control words freq_offset_a and freq_offset_b of the first ethereal messages A and B are respectively obtained, and then freq_offset_a and freq_offset_b are added or subtracted to obtain the final frequency control word. It is also possible to select other corresponding methods to obtain the final frequency control word according to different TDM services, which is not limited in the present invention.

304. The receiving device acquires an output frequency of the phase locked loop by using a frequency control word.

In this embodiment, the local reference clock frequency is used as the input of the phase locked loop, and the frequency control word is used as the input of the phase locked loop feedback circuit, and the output frequency is obtained at the output end of the phase locked loop. The frequency control word is equivalent to a proportional value, that is, the phase-locked loop outputs the local reference clock frequency according to a certain ratio according to the frequency control word.

305. The receiving device recovers the TDM service data frame from the first Ethernet packet according to the output frequency of the phase locked loop.

In this embodiment, the implementation principle of 305 is the same as that of 104 in the first embodiment shown in FIG. 2, and details are not described herein again.

The method for processing the differential clock recovery provided in this embodiment includes multiple When the value in the counter is received by the receiving device, the first Ethernet packet sent by the transmitting device is received, according to the packet sending rate of the receiving device, the working clock frequency of the counter on the transmitting device, and the obtained first Ethernet packet. The value in the counter obtains the relative frequency control word between the two adjacent first Ethernet messages received by the receiving device, and obtains the corresponding frequency control word through the relative frequency control word, and inputs the frequency control word into the lock The phase loop acquires the output frequency of the phase-locked loop, and uses the output frequency as the clock frequency of the TDM service to recover the TDM service data frame from the first Ethernet packet. In the embodiment, the receiving side device can still use the value of multiple counters in the first Ethernet packet sent by the sending device, as compared with the method for obtaining the frequency offset value by using the hardware calculation in the sending device. According to the values of the plurality of counters in the first Ethernet message, the frequency control word is obtained by software, and the output frequency of the phase-locked loop is obtained through the frequency control word, thereby achieving interworking between different hardware solutions, and only on the transmitting side A simple counter needs to be set, and the value in the counter can be written into the Ethernet packet. The calculation of the frequency offset value is not dependent on the complicated hardware, which reduces the complexity and equipment cost of the hardware implementation on the transmitting side.

Embodiment 4

Further, on the basis of the first embodiment shown in FIG. 2, in the differential clock recovery processing method provided in the fourth embodiment of the present invention, the implementation is described in detail by taking the value of a counter included in the first packet as an example. The technical solution of the example. In the fourth embodiment, the frequency control word is calculated after a plurality of packet sending periods. Specifically, according to the packet sending rate K of the receiving device and the value of the counter in the Ethernet packet received by the receiving device in the nth sending period. t' _1n , the value t ₁ in the counter in the Ethernet message received by the receiving device and the working clock frequency f ₀ of the counter on the transmitting device in the first packet sending period, using the formula (4), the frequency control word is obtained.

Where T is the delivery period, T=1/K.

In this embodiment, the frequency control is calculated by using a plurality of packet sending periods. The method for calculating the frequency control word is the same as that of the second embodiment, and the other method steps are the same as those in the second embodiment, and details are not described herein again.

The differential clock recovery processing method provided in this embodiment reduces the minimum granularity of the frequency control word by calculating the frequency control word by a plurality of cycles, that is, reduces the inherent precision deviation, and improves the calculation precision of the frequency control word.

It should be noted that when the value of the counter is included in the first Ethernet packet, the frequency control word may be obtained by using the method in the second embodiment, or the frequency control word may be obtained by using the method in the fourth embodiment. There are no restrictions in the invention.

Embodiment 5

FIG. 5 is a flowchart of a method for processing differential clock recovery according to Embodiment 5 of the present invention. In this embodiment, the receiving side device receives the first Ethernet packet sent by the at least two sending side devices as an example, that is, the value of the plurality of counters in the first Ethernet packet is an example, and the technology in this embodiment is introduced in detail. Program. As shown in FIG. 5, the method includes:

401. The receiving device receives the first Ethernet packet sent by the sending device.

In this embodiment, the receiving side device simultaneously receives the first Ethernet message sent by the multiple sending side devices, where each first Ethernet message is a corresponding sending side device, and the TDM service data is sent according to the sending rate of the sending side device. The Ethernet message obtained after the frame is converted, each first Ethernet message may include only one value in a counter, or may include values in multiple counters, and each counter has a different working clock frequency.

402. Obtain a frequency control word corresponding to the first Ethernet packet sent by each sending device.

In this embodiment, the corresponding method is selected according to the actual situation, and the frequency control word corresponding to the first Ethernet packet sent by each sending device is obtained, for example, when the first Ethernet packet includes a value in a counter. The frequency control word may be obtained by using the method provided in the second embodiment or the fourth embodiment. When the first Ethernet message includes the values in the plurality of counters, the frequency control word may be obtained by using the method provided in the third embodiment.

403. Obtain a final frequency control word by using a frequency control word corresponding to the first Ethernet message sent by all the sending side devices.

In this embodiment, there are various methods for obtaining the final frequency control word from the frequency control words corresponding to all the first Ethernet messages, for example, performing an addition or subtraction operation between the frequency control words to obtain the final frequency control word. According to different TDM services, a frequency control word suitable for the TDM service is selected as the final frequency control word among all the frequency control words, or another method is selected to obtain the frequency control word, which is not used in the present invention. Limited.

404. Obtain an output frequency of the phase locked loop by using a final frequency control word.

In this embodiment, the local reference clock frequency is used as the input of the phase locked loop, and the final frequency control is performed. As the input of the phase-locked loop feedback circuit, the word gets the output frequency at the output of the phase-locked loop. The final frequency control word is equivalent to a proportional value, that is, the phase-locked loop outputs the local reference clock frequency according to a certain ratio according to the final frequency control word.

405. The receiving device recovers the TDM service data frame from the first Ethernet packet according to the output frequency of the phase locked loop.

Optionally, in this embodiment, after acquiring the frequency control word, the method further includes:

The frequency control word is filtered.

In this embodiment, the acquired frequency control word corresponding to the first Ethernet message sent by each sending side device may be filtered to filter out high frequency partial noise, thereby achieving stable frequency offset output and reducing randomness deviation. The specific filtering method may adopt a mean value, a mean square error, a finite unit impulse response (FIR), or other filtering methods, and is not limited thereto.

The method for processing the differential clock recovery provided in this embodiment, when the receiving side device simultaneously receives the first Ethernet packets sent by the multiple sending side devices, respectively, obtains the frequency control corresponding to the first Ethernet message sent by each transmitting device. The word obtains the final frequency control word from the frequency control word corresponding to the first Ethernet message sent by all the transmitting side devices, and obtains the output frequency of the phase locked loop through the final frequency control word, and uses the output frequency as the clock of the TDM service. Frequency, recovering TDM service data frames from the first Ethernet message. In this embodiment, the receiving side device simultaneously receives the first Ethernet message sent by the multiple sending side devices, and uses the software to calculate the frequency control word corresponding to each Ethernet message to obtain the final frequency control word, and implements the cross-message. The calculation of the frequency control word enables interoperability between different hardware solutions.

Embodiment 6

FIG. 6 is a schematic structural diagram of a processing apparatus for differential clock recovery according to Embodiment 6 of the present invention. As shown in FIG. 6, the apparatus includes a receiving module 11, a frequency offset value acquiring module 12, an output frequency acquiring module 13, and a recovery module 14. The receiving module 11 is configured to receive the first Ethernet packet sent by the sending device, where the first Ethernet packet is obtained by the transmitting device according to the sending rate of the transmitting device, and the time division multiplexed TDM service data frame is converted. Ether message. The frequency offset value obtaining module 12 is configured to obtain a frequency offset value according to the packet sending rate of the receiving device, the working clock frequency of the counter on the transmitting device, and the value in the counter in the acquired first Ethernet packet; wherein, the receiving device Contract rate The same as the sending rate of the transmitting side device, the value in the counter is the time stamp information recorded by the counter at the working clock frequency of the counter. The output frequency acquisition module 13 is configured to obtain the output frequency of the phase locked loop by using the frequency offset value. The recovery module 14 is configured to recover the TDM service data frame from the first Ethernet packet according to the output frequency of the phase locked loop.

The device in this embodiment may be used to implement the technical solution of the method embodiment shown in FIG. 2, and the implementation principle and technical effects are similar, and details are not described herein again.

Optionally, the processing device for the differential clock recovery may be disposed in a receiving side device that receives the first Ethernet message.

Example 7

Further, on the basis of the foregoing sixth embodiment, the processing device for the differential clock recovery provided by the seventh embodiment of the present invention, if the first Ethernet message includes a value in a counter, the frequency offset value obtaining module 12 is specifically The method is: according to the sending rate K of the receiving device, the working clock frequency f ₀ of the counter on the transmitting device, and the value t ₁ in the counter in the first Ethernet packet, using a formula

Obtaining the frequency control word freq_offset; wherein, T is a packet sending period, T=1/K, t′ ₁ is a value in a counter in the second Ethernet message, and the second Ethernet message is received by the receiving device An Ethernet message adjacent to the first Ethernet message.

The device in this embodiment may be used to implement the technical solution of the method embodiment shown in FIG. 3, and the implementation principle and technical effects are similar, and details are not described herein again.

Optionally, the processing device for the differential clock recovery may be disposed in a receiving side device that receives the first Ethernet message.

Example eight

Further, on the basis of the foregoing sixth embodiment, the processing apparatus for differential clock recovery provided by the eighth embodiment of the present invention, if the first Ethernet message includes a value of at least two first counters, at least two The value of the second counter is used by the frequency offset value obtaining module 12 according to the packet sending rate K of the receiving device, the working clock frequency f ₁₀ of the first counter on the transmitting device, and the working clock frequency of the second counter on the transmitting device. f ₁₁ , the value t ₁₀ in the first counter in the first Ethernet message and the value t ₁₁ in the second counter in the first Ethernet message, using a formula

Obtaining the relative frequency control word freq_offset1, control word acquisition frequency and the relative frequency control word; wherein, T is the contract period, T = 1 / K, t '10 is the value of the first counter in said second Ethernet packets, t _'11 is an Ethernet packet a second value of the second counter, the second Ethernet packet to the receiving-side device and the adjacent first Ethernet packets received Ethernet packets.

The device in this embodiment may be used to implement the technical solution of the method embodiment shown in FIG. 4, and the implementation principle and technical effects are similar, and details are not described herein again.

Optionally, the processing device for the differential clock recovery may be disposed in a receiving side device that receives the first Ethernet message.

Example nine

Further, on the basis of the foregoing embodiment 6, the processing device for the differential clock recovery provided by the ninth embodiment of the present invention, if the first Ethernet message includes a value in a counter, the frequency offset value obtaining module 12 is specifically used. According to the packet rate K of the receiving device, the value t' _1n in the counter in the Ethernet packet received by the receiving device in the nth packet sending period, and the Ethernet packet received by the receiving device in the first packet sending period. The value t ₁ in the middle counter and the working clock frequency f ₀ of the counter on the transmitting side device are calculated using the formula

Obtain the frequency control word freq_offset; where T is the packet sending period, T=1/K.

The device in this embodiment may be used to perform the technical solution of the method embodiment in the fourth embodiment, and the implementation principle and the technical effect are similar, and details are not described herein again.

Optionally, the processing device for the differential clock recovery may be disposed in a receiving side device that receives the first Ethernet message.

Example ten

Further, on the basis of any one of Embodiments 6 to 9 above, the processing apparatus for differential clock recovery provided by Embodiment 10 of the present invention, if the receiving side device receives the first Ethernet message sent by at least two transmitting side devices The frequency offset value obtaining module 12 is further configured to obtain a final frequency control word from the frequency control words corresponding to the first Ethernet message sent by all the transmitting side devices. The output frequency acquisition module 13 is further configured to obtain the output frequency of the phase locked loop through the final frequency control word.

The device in this embodiment may be used to implement the technical solution of the method embodiment shown in FIG. 5, and the implementation principle and technical effects are similar, and details are not described herein again.

Optionally, the processing device for the differential clock recovery may be disposed in a receiving side device that receives the first Ethernet message.

Embodiment 11

FIG. 7 is a schematic structural diagram of a processing apparatus for differential clock recovery according to Embodiment 11 of the present invention. Based on the sixth embodiment shown in FIG. 6, as shown in FIG. 7, the apparatus further includes a filtering module 15 for performing filtering processing on the frequency control word.

In this embodiment, the filtering module 15 is added, and the frequency control word acquired by the frequency offset value obtaining module 12 can be filtered to filter out high-frequency partial noise, thereby achieving stable frequency offset output and reducing randomness deviation.

Optionally, the processing device for the differential clock recovery may be disposed in a receiving side device that receives the first Ethernet message.

One of ordinary skill in the art will appreciate that all or part of the steps to implement the various method embodiments described above may be accomplished by hardware associated with the program instructions. The aforementioned program can be stored in a computer readable storage medium. When the program is executed, the steps of the foregoing method embodiments are performed; and the foregoing storage medium includes: a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk. A variety of media that can store program code.

Finally, it should be noted that the above embodiments are merely illustrative of the technical solutions of the present invention, and are not intended to be limiting; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art will understand that The technical solutions described in the foregoing embodiments may be modified, or some or all of the technical features may be equivalently replaced; and the modifications or substitutions do not deviate from the technical solutions of the embodiments of the present invention. range.

Claims (12)

1. A method for processing differential clock recovery, comprising:

   Receiving, by the receiving device, the first Ethernet packet sent by the sending device, where the first Ethernet packet is obtained by converting, by the transmitting device, the time division multiplexing TDM service data frame according to the sending rate of the sending device. Ethernet message;

   The receiving side device acquires a frequency offset value according to the packet sending rate of the receiving device, the working clock frequency of the counter on the transmitting device, and the obtained value in the counter in the first Ethernet packet; wherein the receiving side The sending rate of the device is the same as the sending rate of the transmitting device, and the value in the counter is time stamp information recorded by the counter at the working clock frequency of the counter;

   The receiving side device acquires an output frequency of the phase locked loop by using the frequency offset value;

   The receiving side device recovers the TDM service data frame from the first Ethernet packet according to an output frequency of the phase locked loop.
2. The method according to claim 1, wherein if the first Ethernet message includes a value in a counter, the first Ethernet message sent by each of the sending side devices, the receiving side The device obtains the frequency offset value according to the packet sending rate of the receiving device, the operating clock frequency of the counter on the transmitting device, and the obtained value in the counter in the first Ethernet packet, which specifically includes:

   Determining, according to the packet sending rate K of the receiving device, the working clock frequency f ₀ of the counter on the transmitting device and the value t ₁ in the counter in the first Ethernet packet,

   

   Obtaining a frequency control word freq_offset; wherein, T is a packet sending period, T=1/K, t′ ₁ is a value in a counter in the second Ethernet message, and the second Ethernet message is received by the receiving device An Ethernet message adjacent to the first Ethernet message.
3. The method according to claim 1, wherein if the first Ethernet message includes a value in at least two first counters and a value in at least two second counters, then for each of the transmitting sides The first Ethernet packet sent by the device, the receiving side device acquires the frequency according to the packet sending rate of the receiving device, the working clock frequency of the counter on the transmitting device, and the obtained value in the counter in the first Ethernet message. The bias value includes:

   According to the packet rate K of the receiving device, the operating clock frequency f ₁₀ of the first counter on the transmitting device, the operating clock frequency f ₁₁ of the second counter on the transmitting device, and the first counter in the first Ethernet packet. a value t ₁₀ in the middle and a value t ₁₁ in the second counter in the first Ethernet message, using a formula

   

   Obtaining the relative frequency control word freq_offset1;

   Wherein, T is a packet sending period, T=1/K, and the second Ethernet packet is an Ethernet message received by the receiving device and adjacent to the first Ethernet packet;

   The receiving side device acquires the frequency control word according to the relative frequency control word.
4. The method according to claim 1, wherein if the first Ethernet message includes a value in a counter, the first Ethernet message sent by each of the sending side devices, the receiving side The device obtains the frequency offset value according to the packet sending rate of the receiving device, the operating clock frequency of the counter on the transmitting device, and the obtained value in the counter in the first Ethernet packet, which specifically includes:

   The receiving side device in the first packet sending period according to the packet sending rate K of the receiving device, the value t' _1n in the counter in the Ethernet packet received by the receiving device in the nth packet sending period, and the first packet sending period The value t ₁ in the counter in the received Ethernet message and the working clock frequency f ₀ of the counter on the transmitting device are calculated by using a formula

   

   Obtaining the frequency control word freq_offset;

   Where T is the delivery period, T=1/K.
5. The method according to any one of claims 2-4, wherein, if the receiving side device receives the first Ethernet message sent by the at least two sending side devices, the method further includes:

   Obtaining a final frequency control word from a frequency control word corresponding to the first Ethernet message sent by all the sending side devices;

   And the receiving side device acquires an output frequency of the phase locked loop by using the frequency control word, specifically:

   The receiving side device acquires an output frequency of the phase locked loop by using the final frequency control word.
6. The method according to claim 5, wherein after the obtaining the frequency control word, the method further comprises:

   The frequency control word is filtered.
7. A processing device for differential clock recovery, comprising:

   The receiving module is configured to receive the first Ethernet packet sent by the sending device, where the first Ethernet packet is used by the sending device to convert the time division multiplexed TDM service data frame according to the sending rate of the sending device. Ether message obtained afterwards;

   a frequency offset value obtaining module, configured to obtain a frequency offset value according to an output rate of the receiving device, a working clock frequency of the counter on the transmitting device, and a value in the obtained counter in the first Ethernet message; The sending rate of the receiving side device is the same as the sending rate of the sending side device, and the value in the counter is time stamp information recorded by the counter at the working clock frequency of the counter;

   An output frequency acquisition module, configured to obtain an output frequency of the phase locked loop by using the frequency offset value;

   And a recovery module, configured to recover the TDM service data frame from the first Ethernet packet according to an output frequency of the phase locked loop.
8. The apparatus according to claim 7, wherein if the first Ethernet message includes a value in a counter, the frequency offset value obtaining module is specifically configured to:

   Determining, according to the packet sending rate K of the receiving device, the working clock frequency f ₀ of the counter on the transmitting device and the value t ₁ in the counter in the first Ethernet packet,

   

   Obtain the frequency control word freq_offset;

   Wherein, T is a packet sending period, T=1/K, and t′ ₁ is a value in a counter in the second Ethernet packet, and the second Ethernet packet is received by the receiving device and the first ether. The Ethernet message adjacent to the packet.
9. The apparatus according to claim 7, wherein if the first Ethernet message includes a value in at least two first counters and a value in at least two second counters, the frequency offset value acquiring module Specifically used for:

   According to the packet rate K of the receiving device, the operating clock frequency f ₁₀ of the first counter on the transmitting device, the operating clock frequency f ₁₁ of the second counter on the transmitting device, and the first counter in the first Ethernet packet. a value t ₁₀ in the middle and a value t ₁₁ in the second counter in the first Ethernet message, using a formula

   

   Obtaining a relative frequency control word freq_offset1, and acquiring a frequency control word according to the relative frequency control word; wherein T is a packet sending period, T=1/K, and t′ ₁₀ is the first counter in the second Ethernet message value, t _'11 is an Ethernet packet a second value of the second counter, the second Ethernet packet to the reception-side device receives the first Ethernet packets in Ethernet frames adjacent Text.
10. The apparatus according to claim 7, wherein if the first Ethernet message includes a value in a counter, the frequency offset value obtaining module is specifically configured to:

    The receiving side device in the first packet sending period according to the packet sending rate K of the receiving device, the value t' _1n in the counter in the Ethernet packet received by the receiving device in the nth sending period, and the first packet sending period The value t ₁ in the counter in the received Ethernet message and the working clock frequency f ₀ of the counter on the transmitting device are calculated by using a formula

    

    Obtain the frequency control word freq_offset;

    Where T is the delivery period, T=1/K.
11. The apparatus according to any one of claims 8 to 10, wherein if the receiving side device receives the first Ethernet message sent by at least two of the transmitting side devices, the frequency offset value is obtained. The module is further configured to obtain a final frequency control word by using a frequency control word corresponding to the first Ethernet message sent by all the sending side devices;

    The output frequency acquisition module is further configured to acquire an output frequency of the phase locked loop by using the final frequency control word.
12. The device according to claim 11, wherein the device further comprises:

    And a filtering module, configured to filter the frequency control word.

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