WO2016056140A1 - Dispositif d'interface et système informatique comprenant le dispositif d'interface - Google Patents

Dispositif d'interface et système informatique comprenant le dispositif d'interface Download PDF

Info

Publication number
WO2016056140A1
WO2016056140A1 PCT/JP2014/077260 JP2014077260W WO2016056140A1 WO 2016056140 A1 WO2016056140 A1 WO 2016056140A1 JP 2014077260 W JP2014077260 W JP 2014077260W WO 2016056140 A1 WO2016056140 A1 WO 2016056140A1
Authority
WO
WIPO (PCT)
Prior art keywords
command
host
communication processor
computer system
storage
Prior art date
Application number
PCT/JP2014/077260
Other languages
English (en)
Japanese (ja)
Inventor
雄策 清田
哲弘 後藤
吉宏 豊原
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to PCT/JP2014/077260 priority Critical patent/WO2016056140A1/fr
Priority to JP2016552796A priority patent/JP6262360B2/ja
Priority to US15/505,746 priority patent/US10409519B2/en
Publication of WO2016056140A1 publication Critical patent/WO2016056140A1/fr

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/0644—Management of space entities, e.g. partitions, extents, pools
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G06F3/0631—Configuration or reconfiguration of storage systems by allocating resources to storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0662—Virtualisation aspects
    • G06F3/0665—Virtualisation aspects at area level, e.g. provisioning of virtual or logical volumes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0689—Disk arrays, e.g. RAID, JBOD
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory

Definitions

  • the present invention relates to an interface device that processes an I / O command, and a computer system that includes the interface device and includes a logical partitioning function.
  • the protocol chip installed in the Host Bus Adapter is generally equipped with a communication processor for offloading the connection protocol.
  • a communication processor for offloading the connection protocol.
  • Such load is increasing.
  • the processing performance of the communication processor in the protocol chip becomes a performance bottleneck, there is a method of controlling one Fiber Channel port with a plurality of communication processors (see, for example, Patent Document 1 below).
  • the method of Patent Document 1 includes a plurality of communication processors on an HBA, and controls a frame received by a fiber channel port in parallel by a plurality of protocol control circuits.
  • the driver that operates on the host and controls the plurality of communication processors distributes the load of the I / O command among the plurality of communication processors provided on the HBA.
  • the load varies (first problem). Since the load varies, even if the number of communication processors increases, the improvement in transaction performance is hindered.
  • An algorithm for improving the efficiency of sequential access is generally implemented in a storage device when sequential read / write commands are continued. If the sequentiality is lost, the response performance of the storage device is degraded.
  • the storage controls data transfer in units called blocks, but the tape device controls data transfer with a block size larger than the disk device (for example, 8 to 64 times). Therefore, when I / O command processing for the tape device and I / O command processing for the disk device are requested from the same communication processor, the processing time of the I / O command of the tape device having a large block size increases, and the fiber channel port A waiting time occurs in I / O command processing to a disk device having a small block size sharing the same, resulting in performance degradation.
  • the system design that separates the HBA connected to the disk device and the tape device has secured a communication band dedicated to the tape device so that it does not become a performance bottleneck of the entire system. It was. However, since it is necessary to introduce a tape-dedicated HBA, the introduction cost increases.
  • the third problem is not limited to the case where a tape device and a disk device coexist as connection destination devices, but also occurs depending on the characteristics of the database stored in the storage device.
  • a case where a business system (OLTP) and an information system (DWH) are mixed in a storage apparatus connected to the same port will be described as an example.
  • OLTP is online transaction processing, and is a mechanism for performing a series of processing between a host and a user terminal connected via a network, and generally handles data input and search transactions.
  • the block size processed by one I / O command is small (several kilobytes), and high-speed response performance is required.
  • DWH data warehouse
  • I / O command is large (several tens of kilobytes or more), and throughput performance is required rather than response performance.
  • OLTP is an I / O command with a small block size
  • DWH is controlled with an I / O command with a large block size, so a disk device and a tape device are connected to the same port of the HBA.
  • I / O command processing for OLTP and DWH is requested from the same communication processor, the processing time for DWH having a large block size of the I / O command is increased, so that the OLTP processing having a small block size of the I / O command is performed. Waiting time occurs. For this reason, the response performance required for OLTP decreases.
  • Patent Document 1 does not disclose how to assign a communication processor to a logical partition (hereinafter referred to as LPAR) created on a host.
  • LPAR logical partition
  • An object of the present invention is to improve the processing performance for a storage apparatus in order to solve the above-described problems.
  • a computer system includes a host computer including a host memory and a plurality of host processors, a storage apparatus, and an interface including a plurality of communication processors connected to the host computer and the storage apparatus.
  • a host system wherein the host computer includes a first host memory area that is a partial area of the host memory, at least one of the plurality of host processors, and at least one of the plurality of communication processors. The first logical partition that is the target of occupying and allocating one is created.
  • FIG. 6 is an explanatory diagram of an input / output control example 1 by the host according to the first embodiment.
  • FIG. 6 is an explanatory diagram of an input / output control example 2 by the host according to the first embodiment.
  • FIG. 10 is an explanatory diagram of an input / output control example 3 by the host according to the first embodiment.
  • It is a block diagram which shows the hardware structural example of a communication system. It is explanatory drawing which shows the example of a memory content of block size information (block_size_info). It is explanatory drawing which shows the detailed structure in HBA. It is a block diagram which shows the functional structural example of a host. It is explanatory drawing which shows the sequence of a communication system.
  • FIG. 10 It is a flowchart which shows the example of a detailed process sequence of the communication processor selection process (step S803) shown in FIG. 10 is a flowchart illustrating a detailed processing procedure example of an access determination process (step S904) illustrated in FIG. 9. It is a figure which shows the structure of the computer system of Example 2. FIG. It is a figure which shows resource allocation of Example 2.
  • a fiber channel HBA will be described, but the connection between the host and the storage device may be other than the fiber channel. These include, for example, InfiniBand, Ethernet, and PCI-Express. HBA is also an example, and the technology disclosed in the embodiments can be applied to any interface device for connecting a host to a storage apparatus.
  • the communication processors appearing in the following description do not share hardware circuits, it is not essential.
  • each of a plurality of cores provided by a technology such as Intel Hyper-Threading Technology may be regarded as a communication processor. Needless to say, the core may correspond to the communication processor. The same applies to the host CPU 401 and the storage processor.
  • the host determines the I / O characteristics based on the I / O load for each communication processor, the requested I / O command type to the storage device, and the access address by a driver that controls a plurality of communication processors in the HBA.
  • the server causes an arbitrary communication processor to exclusively control an I / O command to the connected LU or an I / O command having a specific block size, and selects a communication processor that processes the I / O command.
  • FIG. 1 is an explanatory diagram of an input / output control example 1 by the host according to the first embodiment.
  • the input / output control example 1 improves the transaction performance by a load balance method in which the load of the I / O command is evenly distributed among a plurality of communication processors provided on the HBA.
  • a communication system 100 includes a host 101, an HBA 102, and a disk device 103 that is an example of a storage device.
  • the host 101 has an HBA driver 110 that controls the HBA 102.
  • the HBA 102 has a plurality of cores # 0 to # 3 and a port 120, and transfers an I / O command to the disk device 103.
  • the number of cores is four as an example, but the number is not limited to four and may be two or more. It is assumed that I / O commands A to E are input to the host 101 in alphabetical order.
  • the disk device 103 has a plurality of logical units LU # 0 to LU # 3.
  • the number of logical units is four as an example, but is not limited to four and may be two or more. Further, the number may not be the same as the number of cores.
  • the host 101 selects the cores to which the I / O commands A to E are assigned by looking at the load states of the plurality of cores # 0 to # 3.
  • the black rectangles in the cores # 1 to # 3 are I / O commands input before the I / O commands A to E.
  • the HBA driver 110 assigns the assignment destination of the I / O command A to the core # 0 having the smallest number of preceding I / O commands.
  • the HBA driver 110 assigns an assignment destination of the I / O command B to any of the cores # 0 to # 2 having the smallest number of preceding I / O commands.
  • a core with a smaller number is selected.
  • the HBA driver 110 assigns the assignment destination of the I / O command C to the core # 1 having the smallest number of preceding I / O commands, and assigns the assignment destination of the next I / O command D to the preceding address.
  • FIG. 2 is an explanatory diagram of an input / output control example 2 by the host according to the first embodiment.
  • the input / output control example 2 improves the transaction performance when the I / O characteristic of the I / O command to the storage apparatus is sequential.
  • I / O commands A to E are input to the host 101 in alphabetical order.
  • Data in the command also uses the same sign as the command.
  • data in command A is data A.
  • the data is accompanied by an LU number and R / W.
  • a combination of data, LU number and R / W constitutes one I / O command.
  • the LU number is identification information that uniquely identifies the logical unit in the disk device 103 that is the access destination of the data. For example, an I / O command with the LU number “0” is output to the logical unit LU # 0 of the disk device 103.
  • R / W is an access type indicating whether the I / O command is a read command or a write command.
  • the HBA driver 110 fetches I / O commands A, B, C, D, E in order.
  • the HBA driver 110 determines the continuity of consecutive I / O commands and the identity of access types. For consecutive I / O commands (A, B), both access types are “R” (read). If it is determined that the addresses to be accessed are continuous, consecutive I / O commands (A, B) are processed by the same core.
  • the HBA driver 110 passes a continuous I / O command (A, B) to the core # 0, and the core # 0 sends a continuous I / O command (A, B) via the port 120.
  • the I / O commands A and B are transferred to the logical unit LU # 0 in this order.
  • the HBA driver 110 determines the same for consecutive I / O commands (B, C), (C, D), and (D, E).
  • the HBA driver 110 sets the I / O command C to the core # 1, the I / O command D to the core # 2, and the I / O command E to the core # 3 according to the load balance method as shown in FIG. assign.
  • the core # 1 transfers the I / O command C to the logical unit LU # 1
  • the core # 2 transfers the I / O command D to the logical unit LU # 2
  • the core # 3 receives the I / O command.
  • Command E is transferred to logical unit LU # 3.
  • FIG. 3 is an explanatory diagram of an input / output control example 3 by the host 101 according to the first embodiment.
  • Input / output control example 3 improves transaction performance by an I / O command having a small block size when an I / O command having a small block size and a large I / O command are mixed in accessing a storage apparatus.
  • the input / output control example 3 as an example of the storage device, a case where the tape device 303 and the disk device 103 are connected via a fiber channel switch (not shown) connected to the port 120 of the HBA 102 will be described as an example.
  • the tape device 303 may be replaced with an information system (DWH), and the disk device 103 may be replaced with a business system (OLTP).
  • DWH information system
  • OLTP business system
  • the core # 0 is a communication processor dedicated to the tape device 303
  • the cores # 1 to # 3 are communication processors dedicated to the disk device 103.
  • I / O command sequence 300 I / O commands a to c and e are I / O commands having a small block size, and I / O commands d and f are I / O commands having a large block size.
  • the HBA driver 110 in the host 101 selects a transfer destination core from the block sizes of the I / O commands a to f that are sequentially input. Since the tape device 203 controls data transfer with a block size larger than the disk device 103 (for example, 8 times to 64 times), the HBA driver 110 sends the I / O commands d and f to the core # 0 in the input order. Forward to.
  • the I / O command having a small block size that has been affected by the processing of the I / O command having a large block size has been reduced.
  • the processing performance can be improved.
  • the HBAs 102 that have so far been required to be divided into a plurality according to the type of connected storage and the database can be consolidated into a single sheet, so that the system introduction cost can be reduced.
  • the HBA driver 110 distributes the I / O commands a to c and e to the core # 1 to the core # 3.
  • the allocation destination core is selected according to the LU number specified in the I / O commands a to c and e.
  • the HBA driver 110 selects the same core as a distribution destination based on the continuity of consecutive I / O commands and the identity of the access type.
  • the core # corresponding to the logical unit LU # 1 1 is transferred.
  • the I / O command load among the plurality of cores can be operated in parallel without being biased, and the transaction performance of the port 120 can be improved.
  • FIG. 4 is a block diagram illustrating a hardware configuration example of the communication system 100.
  • the communication system 100 includes a host 101, an HBA 102, and a storage device 440.
  • the host 101 and the HBA 102 are connected via a PCI bus, and a storage apparatus 440 is connected to the tip of the HBA 102 via an I / O interface control unit 433 (corresponding to the port 120).
  • the storage device 440 has one or more storage areas.
  • the storage area is an area where data is read or written by an I / O command.
  • the storage device 440 when the storage device 440 is the disk device 103, it has one or more logical disks as shown in FIG. Further, the storage device 440 may be one or more tape devices 303. Further, the storage device 340 may include a disk device 103 and a tape device 303 as shown in FIG. The storage device 340 may be a storage device 340 in an information system (DWH) or a business system (OLTP). Note that the host 101 treats the storage device 340 as an access destination as a logical unit regardless of whether it is a physical disk device 103 or a tape device 303.
  • DWH information system
  • OLTP business system
  • the host 101 has a host CPU (Central Processing Unit) 401 and a host memory 402.
  • the host CPU 401 controls the host 101.
  • the host memory 402 serves as a work area for the host CPU 401.
  • the host memory 402 is a non-transitory recording medium that stores various programs and data. Examples of the host memory 402 include a ROM (Read Only Memory), a RAM (Random Access Memory), a HDD (Hard Disk Drive), and a flash memory.
  • the host memory 402 has a program area 410, an HBA driver data area 420, and an MMIO space 430.
  • An application 411, an OS (Operating System) 412, and an HBA driver 110 are stored in the program area 410 and executed by the host CPU 301.
  • the HBA driver 110 includes a communication processor selection program 313.
  • the communication processor information group 421 is communication processor information 421-0 to 321-N for each communication processor.
  • the communication processor information is information for managing a corresponding communication processor in the communication processor group in the HBA 102.
  • the communication processor information 421-0 to 421-N includes the number of commands being executed (exec_cmd_num).
  • the number of commands being executed (exec_cmd_num) is the number of I / O commands currently being processed. A larger value of the number of commands being executed (exec_cmd_num) indicates that a load is applied to the communication processor.
  • the connected LU information group 423 is connected LU information 423-0 to 423-N for each logical unit.
  • the connected LU information 423-0 to 423-N is information for managing logical units.
  • the connection LU information 423-0 to 423-N includes final command information (last_cmd_info), continuation determination information (next_LBA_adr_info), occupation allocation information (dev_info), and final core information (last_core_info). Have.
  • the final command information (last_cmd_info) is information indicating whether the access type of the I / O command executed for the logical unit is write (W) or read (R).
  • the continuation determination information is information for determining whether or not the access pattern to the logical unit is sequential. Specifically, for example, the continuation determination information (next_LBA_adr_info) is the sum of the access address to the logical unit and the block size of the I / O command to be accessed.
  • Occupied allocation information is management information for causing a specific communication processor to occupy and control the I / O command to the transfer destination logical unit. Specifically, for example, identification information that uniquely identifies a specific communication processor to be exclusively allocated.
  • Occupancy allocation information (dev_info) is a parameter that the operator sets in the HBA driver data area 320 via the application 411 when the communication system 100 is introduced.
  • the final core information is information for managing the communication processor that lastly activated the I / O command for the logical unit. Specifically, for example, the identification information uniquely identifies the communication processor that last activated the I / O command for the LU.
  • Block size information (block_size_info) 422 is information that occupies the communication processor that controls the I / O command according to the block size. Specifically, for example, the block size information (block_size_info) 422 is a block size of an I / O command associated with the communication processor.
  • the MMIO space 430 is an abbreviation for a Memory Mapped Input Output space, and is an address space used for the HBA driver 110 to access an I / O device register such as the HBA 102.
  • the HBA 102 includes a plurality of communication processor control units 430-0 to 430-N.
  • the communication processor control units 430-0 to 430-N access the corresponding logical unit via the I / O interface control unit 433.
  • the communication processor control units 430-0 to 430-N include I / O command activation registers 431-0 to 431-N and communication processors 432-0 to 432-N.
  • the I / O command activation registers 431-0 to 431-N hold I / O commands from the HBA driver 110.
  • the internal configuration of the HBA 102 will be described later.
  • FIG. 5 is an explanatory diagram showing an example of the contents stored in the block size information (block_size_info) 422.
  • the block size information (block_size_info) 422 is information in which the block size is associated with the occupation control processor number.
  • the block size is the block size of the I / O command.
  • the exclusive control processor number is the number of the communication processor that performs exclusive control.
  • the communication processor that performs exclusive control is a communication processor that is selected when an I / O command having a corresponding block size is received. For example, when the block size of the I / O command is 16 [KB], the communication processor # 3 is a communication processor whose occupation is controlled. Therefore, the destination of the I / O command is the communication processor # 3. “Not set” indicates that a communication processor for exclusive control is not determined.
  • FIG. 6 is an explanatory diagram showing a detailed configuration within the HBA 102.
  • the I / O command activation registers 431-0 to 431-N are mapped to the MMIO space 430.
  • the HBA driver 110 can access the I / O command activation registers 431-0 to 431-N, and the I / O command activation registers 431-0 to 431-N are HBAs operating on the host 101.
  • the driver 110 can issue an I / O command execution instruction to the communication processor.
  • the HBA 102 stacks the I / O command instructed from the HBA driver 110 in the I / O command activation queue 600 for each communication processor, and notifies the communication processor group 432 of the activation of the I / O command. Thereafter, the communication processor group 432 sends an I / O command to the storage apparatus 440 via the I / O interface control unit 433.
  • the connection 400 between the host 101 and the HBA 102 may be a connection based on, for example, PCI-Express, but may be another connection. Further, the host 101 may have a form in which the HBA 102 is incorporated.
  • FIG. 7 is a block diagram illustrating a functional configuration example of the host 101.
  • the control device 700 that is the host 101 is a control device that controls a plurality of processors corresponding to each of a plurality of storage areas provided in an interface that accesses the plurality of storage areas.
  • the plurality of storage areas are storage areas in the storage device 440, and correspond to, for example, logical units of the disk device 103 and the tape device 303.
  • the plurality of processors is, for example, the communication processor group 432, and the interface for accessing the plurality of storage areas is, for example, the HBA 102 having the communication processor group 432.
  • the control device 700 includes an update unit 701, a selection unit 702, an output unit 703, a determination unit 704, and a storage unit 705.
  • the update unit 701 to the determination unit 704 realize their functions by causing the host CPU 401 to execute the HBA driver 110 shown in FIG. 4, for example.
  • the storage unit 705 realizes its function by the host memory 402.
  • the update unit 701 uses a command being executed by each processor of the plurality of processors for the storage area corresponding to the processor. Update the load. Specifically, for example, the updating unit 701 updates the number of commands being executed (exec_cmd_num) stored in the communication processor information 321-0 to 321-N of the communication processor information group 421. That is, the update unit 701 increments the number of commands being executed (exec_cmd_num) by 1 when an I / O command is issued to the communication processor, and decrements by 1 when an end notification is received from the communication processor.
  • the selection unit 702 selects a processor to which any command is assigned as a plurality of processors based on the load due to the command being executed for each processor updated by the update unit 701 for any command in the command string. Choose from. Specifically, for example, the selection unit 702 selects a communication processor having the smallest number of commands being executed (exec_cmd_num) as an allocation destination.
  • the output unit 703 outputs any command to the processor selected by the selection unit 702. Specifically, for example, the output unit 703 transmits an I / O command to the logical unit corresponding to the communication processor of the allocation destination by the I / O interface control unit.
  • the determination unit 704 has continuity in the addresses accessed in any of the plurality of storage areas for the first command and the second command immediately after the first command in the command string, and the access type is It is determined whether or not they are the same. Specifically, for example, the determination unit 704 determines address continuity and access type identity for consecutive I / O commands.
  • the determination unit 704 includes the continuous determination information (next_LBA_adr_info) of the preceding first command among consecutive I / O commands and the second command following among the consecutive I / O commands. Compare the access address of.
  • the continuation determination information (next_LBA_adr_info) is the sum of the access address to the logical unit and the block size of the I / O command to be accessed. If they match, the determination unit 704 determines that the first command and the second command have continuity.
  • the determination unit 704 refers to the last command information (last_cmd_info), specifies whether the access type of the first command is write (W) or read (R), and matches the access type of the second command It is determined whether or not to do. If they match, the determination unit 704 determines that the access types of the first command and the second command are the same.
  • the selection unit 702 does not select the second command allocation destination based on the number of commands being executed (exec_cmd_num).
  • the selection unit 702 determines that the addresses accessed by the determination unit 704 are continuous and the access types are the same, the selection unit 702 stores the storage area accessed by the first command among the plurality of processors. Select the corresponding processor. For example, when the access destination of the first command is the logical unit # 0, the access destination of the second command is also the logical unit # 0. However, the selection unit 702 selects an assignment destination of the second command according to the number of commands being executed (exec_cmd_num) when the addresses are not continuous or when the access types are not identical.
  • the storage unit 705 has a first correspondence in which identification information of a specific processor among a plurality of processors is associated with identification information of a specific storage area in a plurality of storage areas to be accessed by the specific processor Store information.
  • the first correspondence information is exclusive allocation information (dev_info) in the connected LU information 423-0 to 423-N. That is, the specific processor identification information is the number of the logical unit specified by the connected LU information 423-0 to 423-N, and the specific storage area identification information is stored in the dedicated allocation information (dev_info). Is the number of the selected communication processor.
  • the determination unit 704 refers to the first correspondence information, identifies the storage area identification information of the access destination of the second command held by the second command, and the specific storage area It is determined whether the identification information matches.
  • the selection unit 702 selects a specific processor.
  • the selection unit 702 selects the second command As the allocation destination, the communication processor specified by the communication processor number stored in the exclusive allocation information (dev_info) of the connected LU information 423-0 of the logical unit # 0 is selected.
  • the storage unit 705 stores second correspondence information in which identification information of a specific processor among a plurality of processors is associated with the size of a command output from the specific processor to an access destination.
  • the second correspondence information is block size information (block_size_info) 422.
  • the determination unit 704 refers to the second correspondence information, and determines whether or not the size of the second command matches the size of the command output from the specific processor to the access destination. Determine.
  • the selection unit 702 selects the specific processor.
  • the block size of the second command which is the succeeding I / O command, is 16.0 [KB]
  • the block size corresponds to 16.0 [KB] in the block size information (block_size_info) 422.
  • the selection unit 702 selects the communication processor # 3 as an assignment destination of the second command.
  • FIG. 8 is an explanatory diagram showing a sequence of the communication system 100.
  • a program such as the application 411, the OS 412, and the HBA driver 110 may be described as the subject.
  • the host CPU 401 uses the host memory 402 to perform processing determined by the program being executed by the host CPU 401. It is synonymous with the explanation with the subject.
  • the application 411 sends a transmission / reception request to the storage apparatus 440 to the OS 412 (step S801).
  • the OS 412 that has received the request issues an I / O command to the HBA driver 110 (step S802).
  • the communication processor selection program 413 of the HBA driver 110 executes a communication processor selection process for starting an I / O command (step S803).
  • the communication processor selected in step S803 is referred to as “selected communication processor”. Details of the communication processor selection process (step S803) will be described later with reference to FIG.
  • the HBA driver 110 issues an I / O command to the selected communication processor through the output unit 703 (step S804). After issuing the I / O command, the HBA driver 110 causes the update unit 701 to use the continuation determination information (next_LBA_adr_info), which is connection LU information in the transfer destination logical unit of the I / O command, the final command information (last_cmd_info), and the final core. Information (last_core_info) is updated (step S805).
  • the continuation determination information (next_LBA_adr_info) is updated to the sum of the access address to the logical unit and the access block size.
  • the final command information (last_cmd_info) is updated to control information indicating writing (W) when the I / O command issued in step S804 is writing, and reading (R) when reading.
  • the final core information (last_core_info) is updated to the number of the selected communication processor selected in the communication processor selection process (step S803).
  • the HBA driver 110 updates the number of I / O commands currently being executed in the selected communication processor (step S806). Specifically, the number (1) of I / O commands issued in step S804 is added to the number of commands being executed (exec_cmd_num) indicating the number of I / O commands currently being executed by the selected communication processor. . When an I / O command completion notification is received from the selected communication processor, the number of commands being executed (exec_cmd_num) is subtracted.
  • FIG. 9 is a flowchart showing a detailed processing procedure example of the communication processor selection processing (step S803) shown in FIG.
  • the HBA driver 110 determines whether or not the block size of the I / O command (hereinafter referred to as a start command) issued from the OS 412 in step S802 is set to be exclusively controlled by a specific communication processor by the determination unit 704. Is determined (step S901). Specifically, for example, the HBA driver 110 determines with reference to the block size information (block_size_info) 322 shown in FIG.
  • block_size_info block size information
  • step S901 if the exclusive control processor number corresponding to the block size is “not set”, step S901 is No, and if there is an exclusive control processor number, step S901 is Yes. In the case of step S901: Yes, the process proceeds to step S903, and the HBA driver 110 selects the communication processor having the occupation control processor number by the selection unit 702 (step S903).
  • step S901: No the HBA driver 110 determines whether or not the activation command transfer destination logical unit is set to be exclusively controlled by a specific communication processor by the determination unit 704 (step S902). Specifically, for example, the HBA driver 110 makes a determination with reference to the dedicated allocation information (dev_info) of the transfer destination logical unit. That is, if the exclusive control processor number is “not set” in the exclusive allocation information (dev_info) of the transfer destination logical unit, step S902: No, and if the exclusive control processor number is present, step S902: Yes. In the case of step S902: Yes, the process proceeds to step S903, and the HBA driver 110 uses the selection unit 702 to select the communication processor having the occupation control processor number (step S903).
  • the tape device 203 When the LU connected to the HBA 102 is the disk device 103 and the tape device 203, the tape device 203 is placed ahead of one HBA 102 by allocating I / O command control for the LU of the tape device 203 to a specific communication processor. Can be prevented from being degraded when the disk device 103 is connected.
  • step S901 No, the HBA driver 110 performs an access determination process by the determination unit 704 (step S904). Details of the access determination process (step S904) will be described later with reference to FIG. 8. In the access determination process (step S904), it is determined whether or not the access to the transfer destination logical unit is a sequential access.
  • step S905: Yes When access to the transfer destination logical unit is sequential access (step S905: Yes), the process proceeds to step S906, and when access is not sequential (step S905: No), the process proceeds to step S907.
  • step S905 the HBA driver 110 refers to the last core information (last_core_info) by the selection unit 702, and finally issued the I / O command to the transfer destination logical unit.
  • a processor is specified and the communication processor is selected (step S906).
  • the HBA driver 110 uses the selection unit 702 to select a communication processor having the least loaded I / O command load among the plurality of communication processors (step S907). ). For example, the HBA driver 110 selects a communication processor having the smallest number of commands being executed (exec_cmd_num).
  • FIG. 10 is a flowchart showing a detailed processing procedure example of the access determination processing (step S904) shown in FIG.
  • the HBA driver 110 uses the determination unit 704 to determine whether or not the activation command is the same type as the access type last executed for the transfer destination logical unit (step S1001). Specifically, the HBA driver 110 determines whether or not the access type of the start command matches the access type specified by the last command information (last_cmd_info). If they are not the same type (step S1001: No), the HBA driver 110 determines that the activation command is random access (step S1004). Since it is random access, the process proceeds to step S1004.
  • the HBA driver 110 causes the determination unit 704 to determine whether the activation command is continuous with the address last executed in the transfer destination logical unit. Is determined (step S1002). Specifically, the HBA driver 110 refers to continuation determination information (next_LBA_adr_info) calculated from the address of the last I / O command executed for the transfer destination logical unit and its block size (next_LBA_adr_info). next_LBA_adr_info) and the address of the start command are determined to match.
  • step S1002: Yes the HBA driver 110 determines that the activation command is sequential access (step S1003) by the determination unit 704, and when they do not match (step S1002: No), the activation command is random access. (Step S1004). After steps S1003 and S1004, the process proceeds to step S905, and the access determination process (step S904) ends.
  • step S1002 the case where the continuation determination information (next_LBA_adr_info) matches the address of the start command has been described as an example.
  • the sequential access determination algorithm in the storage device 440 operates even when the access addresses are not continuous. There is a case.
  • the storage apparatus 440 may operate as a sequential access. Therefore, the address determination method by the HBA driver 110 may be determined to be regarded as a sequential access if the address is shifted within this several hundred bytes. Further, a method may be used in which the deviation of the address range is parameterized and can be changed according to the sequential access algorithm of the connected storage apparatus 440.
  • the HBA driver 110 that controls the HBA 102 determines the I / O characteristics based on the I / O load for each communication processor, the access type to the storage device 440, the access address, and the block size. Select the communication processor that activates the O command. Thereby, the transaction performance of the HBA 102 can be improved. In addition, data transfer without a performance bottleneck can be realized by allowing a specific communication processor to exclusively control I / O command processing to the connected LU.
  • FIG. 11 shows the structure of the computer system of Example 2.
  • FIG. 11 This embodiment is different in that an LPAR is created in the host 101 and the inside of the storage apparatus 440 is disclosed.
  • Other points, in particular, the internal configuration of the HBA 102 have been described in the first embodiment, and will be omitted. It should be noted that the entity that does not exist in FIG. 11 but exists in the first embodiment is simply omitted, and there is no intention of positively excluding that entity.
  • “Proc” 432 included in the HBA 102 represents the communication processor 432
  • “Proc” 44011 included in the storage device 440 represents the storage processor.
  • the HBA 102 includes a data transfer engine 1021 (abbreviated as “E” in FIG. 11).
  • the communication processor 432 that can be used for each port of the HBA 102 is shown for ease of implementation, but this is not essential.
  • Examples of the data transfer engine 1021 include a DMA engine and an engine that controls frame transmission / reception of the HBA 102, but the data transfer engine 1021 is not limited to this as long as it is an entity that performs data transfer between the storage device 440 and the host memory 402.
  • the LPAR 10110 is a logical host generated in the host 101, and is assigned with a host CPU 401 and a part of the host memory 402 or a predetermined memory amount.
  • the LPAR 10110 executes the application 411, the OS 412, or the HBA driver 110 according to these allocated host resources.
  • the HBA driver 110 and the OS 412 may be different software modules, but they may not be so.
  • the HBA driver 110 and the application 411 need not be different software modules.
  • LPAR 10110 is typically generated by: * Hypervisor system: A hypervisor program is executed by the host CPU 401. * Container method: Instead of executing the OS 412 and the HBA driver 110 for each LPAR 10110, the OS 412 and the HBA driver 110 common to the LPARs 10110 are executed.
  • the LPAR 10110 can be regarded as an entity in which areas or amounts of the host CPU 401 and the host memory 402 used for the application 411 executed therein are separated.
  • the generation method of the LPAR 10110 may be other than this.
  • the hypervisor method is assumed.
  • the management computer occupies and allocates a specific communication processor 432 to the LPAR 10110 for which I / O performance (especially IOPS) is required.
  • I / O performance especially IOPS
  • the specific communication processor 432 is not used from another LPAR 10110.
  • performance conflicts with other LPARs 10110 can be resolved.
  • more efficient I / O processing can be performed.
  • One example is OLTP and DWH.
  • the management computer allocates a predetermined shared communication processor 432 (shared allocation). This is a countermeasure against a situation where the communication processor 432 used by the LPAR 10110 for I / O command transmission disappears when all the communication processors 432 are occupied.
  • Storage processor 44011 Receives and interprets an I / O command from the HBA 102, and performs data transfer in cooperation with a data transfer engine (not shown) in the storage device 440.
  • Pool A plurality of storage devices are included in the pool, and typically, the target data of the I / O command is transferred while operating the plurality of storage devices in parallel. Therefore, the number of storage devices included in the pool affects the IOPS limit that can be processed. Furthermore, since the storage device includes an HDD that accompanies the movement of the head and a nonvolatile memory (for example, a flash memory) that does not require the movement of the head, the type of the storage device also affects the IOPS limit of the pool.
  • the limit bandwidth is determined by the connection standard. * Pool: Since the bandwidth limit of the connection between the storage device and the storage controller 44010 is related in addition to the limit of the transfer capability of the storage device itself, typically the larger the number of storage devices, the better. Also, the type of storage device is related to the bandwidth.
  • the response time viewpoint relates to these IOPS viewpoints and bandwidth viewpoints, and further relates to the hit rate of the cache memory 44012. If the access characteristics of the application 411 are the same, the hit rate tends to improve as the amount of the cache memory 44010 increases. For this reason, when the amount of use of the cache memory 44010 increases in another LPAR 10110 and the amount of cache memory that can be used in the LPAR 10110 in which an important application is being executed decreases, the cache hit rate may decrease and the response time may deteriorate.
  • the integrated resource group 11000 is a logical entity including host resources and storage resources that are exclusively allocated to the LPAR 10110.
  • one host CPU 401, a part of the entire area provided by the host memory 402 (area 1011P), the communication processor # 7 of HBA # 2 (102), storage, and LPAR # 4 integrated resource group This indicates that the storage processor #D of the device 440, a partial area 44012P of the cache memory 44012, and the pool #C are included.
  • the storage resources of the integrated resource group 11000 may be shared by a plurality of LPARs 10110. This is for example:
  • the storage resource and the communication processor 432 may be shared. This example is a relatively realistic option when the number of communication processors 432 in the HBA 102 is less than or equal to the number of LPARs 10110.
  • the storage resource becomes a sharing target.
  • This example is suitable when HA clustering or performance clustering is performed between the LPARs 10110.
  • the load to be processed should be handled not as individual LPAR 10110 but as the entire cluster, and therefore the storage resource of the storage device 440 that is the shared access destination can be flexibly adjusted within the cluster rather than allocating storage resources to individual LPAR 10110 This is because the performance of the entire cluster should be improved.
  • occupied and allocated to (one or more) LPARs 10110 means that the allocation target is not used from the LPARs 10110 that are excluded from the allocation targets.
  • the throttling setting may be an internal LU or parity group, which will be described later, in addition to the port, LU, pool, cache memory, or the NIC (not shown) of the host 101. Also good. Further, the throttling setting may target other host resources and storage resources.
  • connection device or connection medium between HBA102 and storage controller This includes the HBA 102 port and the storage device 440 port.
  • the internal LU is a relationship that becomes an LU by being assigned with one or more LUNs to each of one or more ports of the storage apparatus 440.
  • MMIO mapping method >> In the MMIO mapping method, the MMIO space 430 of the HBA 102 is mapped to the LPAR physical address space 11111 of each LPAR 10110 (shaded area in the LA 11111 in FIG. 11).
  • the HBA driver 110 in the LPAR 10110 can transmit an I / O command to the HBA 102 by accessing the MMIO space mapped in the LPAR physical address space.
  • Virtual interface device method In the virtual interface device method, the hypervisor generates a virtual interface device and provides it to the OS 412 on the LPAR 10110. The hypervisor detects that the OS 412 issues an I / O command to the virtual interface device, and issues an I / O command to the HBA driver 110 executed on the hypervisor.
  • MMIO mapping method >> The I / O command processing when the communication processor 432 is exclusively assigned to the LPAR 10110 will be described as an example of read processing as follows.
  • Step 11-01 The application 411 issues a file read request designating the address of the read data storage destination in the virtual address space to the OS 412.
  • Step 11-02 The OS 412 receives the file read request, generates a read command based on the file read request, and issues the read command to the HBA driver 110 together with the read data storage destination address.
  • Step 11-03 The HBA driver 110 stores the received read command and read data storage destination address in the host memory 402.
  • the HBA driver 110 selects the communication processor 432 that is the destination of the read command received from the available communication processors 432.
  • the usable communication processor 432 grasps in advance before the file read request. For example, when the HBA driver 110 is activated, it is conceivable that the driver 110 receives and holds the identifier list of the communication processor 432 that can be used from the hypervisor, but may be grasped by other methods.
  • Step 11-05 The HBA driver 110 notifies the selected communication processor 432 that there is a read command to be transmitted by accessing a register in the MMIO space corresponding to the selected communication processor 432.
  • Step 11-06 The selected communication processor 432 detects the access of the register, and reads the read command and the read data storage destination address stored in the host memory 402 in Step 11-03.
  • Step 11-07 The selected communication processor 432 transmits a read command to the port of the storage apparatus 440 via the port of the HBA 102.
  • Step 11-08 The selected communication processor 432 transmits an instruction to write the data received from the storage device 440 to the read data storage destination address of the host memory 402 to the data transfer engine 1021.
  • the read or write data storage destination address received by the HBA 102 is indicated by an address in the LPAR physical address space, it may be converted to an address in the physical address space for the data transfer engine.
  • the conversion process may be performed by the hypervisor, the HBA 102, the hardware function of the host CPU 401, or the hardware function provided by the chip set on the host 101.
  • the request issued by the application may be a block access request other than a file.
  • Second method Virtual interface device method >> Similar to the description of the first method, I / O command processing when the communication processor 432 is exclusively allocated to the LPAR 10110 will be described as an example of read processing.
  • Step 12-01 The application 411 issues a file read request designating the address of the read data storage destination in the virtual address space to the OS 412 (same as method 1).
  • Step 12-02 The OS 412 receives the file read request, generates a read command based on the file read request, and issues the read command to the virtual interface device together with the read data storage destination address.
  • Step 12-02B The hypervisor detects that the OS 412 issues a read command to the virtual interface device, and issues a read command together with the read data storage destination address to the HBA driver 110.
  • the HBA driver 110 stores the received read command and read data storage destination address in the host memory 402.
  • Step 12-04 The HBA driver 110 selects the communication processor 432 that is the destination of the read command received from the available communication processors 432 (the selection method will be described later).
  • Step 12-05 to Step 12-08 Same as Step 11-05 to Step 11-08.
  • Step 12-04 when the allocation correspondence between LU and LPAR 10110 is 1: N, the following method may be adopted.
  • the HBA driver 110 receives a correspondence list between the LU and the communication processor 432 from the management computer and grasps it.
  • the correspondence list is a list generated by the management computer based on the “list of LUs accessed by each LPAR 10110” and the “list of communication processors 432 assigned to each LPAR 10110” stored in the management computer.
  • Step 12-04B The HBA driver 110 refers to the correspondence list and selects the communication processor 432 corresponding to the LU included in the received read command. That's it. Since other explanations are the same as those in method 1, they are omitted.
  • Virtual interface device method When a more general virtual interface device such as SATA (Serial ATA) can be provided, communication processor allocation can be applied to more types of OS 412. Then, communication processor assignment can be applied without enhancing (or slightly enhancing) a program operating on the LPAR 10110 such as the OS 412.
  • SATA Serial ATA
  • the HBA 102 provides the virtual HBA of the first method.
  • the hypervisor maps the virtual HBA's MMIO space only to a specific LPAR physical address space. Although it is not necessary to perform selection processing by the hypervisor, the HBA 102 needs to be enhanced.
  • the I / O low priority LPAR does not cause a performance conflict with the LPAR 10110 other than the other I / O low priority LPAR. Further, by performing the sharing setting in advance, it is possible to prevent the shared resource from being exhausted due to the exclusive use and prevent the I / O low priority LPAR from transmitting the I / O command.
  • the computer system may include a management computer.
  • the management computer includes a user interface that receives user input, a CPU that executes a management program, and a storage resource that stores configuration information regarding components of a computer system represented by the host 101, the storage device 440, and the like. Including.
  • the management computer may perform the following processing:
  • the management computer may execute the following processing by executing the management program:
  • the management computer receives user input including the LPAR 10110 identifier and which (or how many) communication processors 432 to allocate from the user through the user interface. Based on the reception, the management computer transmits a communication processor allocation instruction for the LPAR 10110 designated by the user to the host 101 (more precisely, the hypervisor of the host 101, the HBA driver 110, or the HBA 102). .
  • the management computer acquires information from the host 101 (more precisely, the hypervisor of the host 101, the HBA driver 110, or the HBA 102), and displays the allocation relationship between the LPAR 10110 and the communication processor 432 on the user interface. In this display, information such as whether the relationship is exclusive allocation or shared allocation may be displayed.
  • the communication processor 432 is exclusively allocated to the LPAR 10110 by transmitting different identifiers of the communication processors 432 to the respective HBA drivers 110 being executed in the LPAR 10110.
  • Virtual interface device method A list corresponding to a predetermined communication processor 432 is created and transmitted only to an LU accessed by the LPAR 10110 to occupy the predetermined communication processor 432.
  • the management computer stores a predetermined communication processor 432 and a predetermined storage resource for shared use based on user input. Then, when performing the dedicated allocation to the LPAR 10110 thereafter, the management computer performs a process for allocation so as to exclude the predetermined communication processor 432 and the predetermined storage resource managed as the shared use from the exclusive use target.
  • FIG. 12 is a diagram illustrating resource allocation according to the second embodiment.
  • An area 1201 in FIG. 12 shows the relationship between the IOPS requirement and the limit capacity of each communication processor 432 and storage resource.
  • An area 1202 in FIG. 12 is a diagram showing the relationship between the bandwidth requirement and the limit capacity of each communication processor 432 and storage resource.
  • each area indicates the size of the requirement or the limit performance of each communication processor 432 or storage resource.
  • the minimum value of the limit performance of the communication processor 432 and the storage resource that affects each requirement is the limit performance of the LPAR 10110.
  • the cache memory 44012 before the pool it is necessary to consider this point.
  • the area 1201 shows an example in which two communication processors 432, one storage processor 44011, and an exclusive allocation of the pool #A are calculated based on the 10 KIOPS IOPS requirement of LPAR # 1.
  • the limit performance of the communication processor 432, the storage processor 44011, and the pool that affect the IOPS is equal to or higher than the IOPS requirement.
  • the management computer calculates the number of communication processors 432 and the number or amount of storage resources to satisfy the IOPS requirement specified by the user input. The same applies to the area 1202.
  • the management computer may regard the LPAR 10110 corresponding to the requirements as an I / O low priority LPAR. Then, whether or not the I / O low priority LPAR may be determined for each requirement. For example, when the I / O low priority is determined only for the IOPS requirement, the management computer may sharely allocate the shared use communication processor 432 to the LPAR.
  • FIG. 12 shows an OLTP (On-Line Transaction Processing) Gold template and a DWH (Data WearHouse) Silver template as an example.
  • This template is information created in advance by a user who is familiar with the above-mentioned I / O characteristics.
  • the OLTP Gold template requires an IOPS requirement of 10 KIOPS and a bandwidth requirement of 1 GByte / s. It is an example described as being.
  • the template may describe the number and amount of host resources, communication processors 432, and storage resources instead of numerical values of such I / O performance requirements.
  • the template may include information indicating whether the assignment is required to be occupied or shared. The example 2 has been described above.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Software Systems (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)

Abstract

La présente invention concerne un système informatique qui comprend : un ordinateur hôte qui comporte une mémoire hôte et une pluralité de processeurs hôtes; un dispositif de mémoire; et un dispositif d'interface qui est connecté à l'ordinateur hôte et au dispositif de mémoire et qui comprend une pluralité de processeurs de communication. Selon la présente invention, une première partition logique créée est le sujet de l'allocation et occupe les éléments suivants : une première région de mémoire hôte qui est une région de la mémoire hôte; au moins un processeur de la pluralité de processeurs hôtes; et au moins un processeur de la pluralité de processeurs de communication.
PCT/JP2014/077260 2014-10-10 2014-10-10 Dispositif d'interface et système informatique comprenant le dispositif d'interface WO2016056140A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/JP2014/077260 WO2016056140A1 (fr) 2014-10-10 2014-10-10 Dispositif d'interface et système informatique comprenant le dispositif d'interface
JP2016552796A JP6262360B2 (ja) 2014-10-10 2014-10-10 計算機システム
US15/505,746 US10409519B2 (en) 2014-10-10 2014-10-10 Interface device, and computer system including interface device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2014/077260 WO2016056140A1 (fr) 2014-10-10 2014-10-10 Dispositif d'interface et système informatique comprenant le dispositif d'interface

Publications (1)

Publication Number Publication Date
WO2016056140A1 true WO2016056140A1 (fr) 2016-04-14

Family

ID=55652792

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2014/077260 WO2016056140A1 (fr) 2014-10-10 2014-10-10 Dispositif d'interface et système informatique comprenant le dispositif d'interface

Country Status (3)

Country Link
US (1) US10409519B2 (fr)
JP (1) JP6262360B2 (fr)
WO (1) WO2016056140A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017187582A1 (fr) * 2016-04-27 2017-11-02 株式会社日立製作所 Système informatique et serveur
WO2018008103A1 (fr) * 2016-07-06 2018-01-11 株式会社日立製作所 Procédé de commande d'interruption et dispositif d'interface
WO2018064247A1 (fr) * 2016-09-28 2018-04-05 Amazon Technologies, Inc. Virtualisation de stockage non volatil au niveau d'un dispositif périphérique
JP2020524840A (ja) * 2017-06-16 2020-08-20 アリババ グループ ホウルディング リミテッド ハードウェア仮想化のための方法及び装置

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10372692B2 (en) * 2015-01-25 2019-08-06 Iguazio Systems Ltd. Virtual data objects
US20180150331A1 (en) * 2016-11-30 2018-05-31 International Business Machines Corporation Computing resource estimation in response to restarting a set of logical partitions
US11093140B2 (en) * 2018-01-19 2021-08-17 Micron Technology, Inc. Performance allocation among users for accessing non-volatile memory devices
US10705747B2 (en) * 2018-03-21 2020-07-07 Micron Technology, Inc. Latency-based storage in a hybrid memory system
JP2022144675A (ja) * 2021-03-19 2022-10-03 キオクシア株式会社 情報処理装置、制御方法、および情報処理システム

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050240924A1 (en) * 2004-04-02 2005-10-27 Emulex Design & Manufacturing Corporation Prerequisite-based scheduler
JP2007316724A (ja) * 2006-05-23 2007-12-06 Hitachi Ltd 計算機システム、管理計算機及びプログラム配布方法
JP2008152594A (ja) * 2006-12-19 2008-07-03 Hitachi Ltd マルチコアプロセッサ計算機の高信頼化方法
JP2009230381A (ja) * 2008-03-21 2009-10-08 Hitachi Ltd ストレージシステム及びボリューム割当方法並びに管理装置
JP2012185660A (ja) * 2011-03-04 2012-09-27 Nec Corp コンピュータシステム及びコンピュータシステム起動方法
WO2013001578A1 (fr) * 2011-06-29 2013-01-03 株式会社日立製作所 Dispositif de commande d'entrée/sortie et procédé de traitement d'image pour dispositif de commande d'entrée/sortie

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7937616B2 (en) * 2005-06-28 2011-05-03 International Business Machines Corporation Cluster availability management

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050240924A1 (en) * 2004-04-02 2005-10-27 Emulex Design & Manufacturing Corporation Prerequisite-based scheduler
JP2007316724A (ja) * 2006-05-23 2007-12-06 Hitachi Ltd 計算機システム、管理計算機及びプログラム配布方法
JP2008152594A (ja) * 2006-12-19 2008-07-03 Hitachi Ltd マルチコアプロセッサ計算機の高信頼化方法
JP2009230381A (ja) * 2008-03-21 2009-10-08 Hitachi Ltd ストレージシステム及びボリューム割当方法並びに管理装置
JP2012185660A (ja) * 2011-03-04 2012-09-27 Nec Corp コンピュータシステム及びコンピュータシステム起動方法
WO2013001578A1 (fr) * 2011-06-29 2013-01-03 株式会社日立製作所 Dispositif de commande d'entrée/sortie et procédé de traitement d'image pour dispositif de commande d'entrée/sortie

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017187582A1 (fr) * 2016-04-27 2017-11-02 株式会社日立製作所 Système informatique et serveur
JPWO2017187582A1 (ja) * 2016-04-27 2018-11-22 株式会社日立製作所 計算機システム及びサーバ
WO2018008103A1 (fr) * 2016-07-06 2018-01-11 株式会社日立製作所 Procédé de commande d'interruption et dispositif d'interface
WO2018064247A1 (fr) * 2016-09-28 2018-04-05 Amazon Technologies, Inc. Virtualisation de stockage non volatil au niveau d'un dispositif périphérique
CN109791471A (zh) * 2016-09-28 2019-05-21 亚马逊科技公司 虚拟化外围装置处的非易失性存储装置
US10318162B2 (en) 2016-09-28 2019-06-11 Amazon Technologies, Inc. Peripheral device providing virtualized non-volatile storage
US11249647B2 (en) 2016-09-28 2022-02-15 Amazon Technologies, Inc. Suspend, restart and resume to update storage virtualization at a peripheral device
US11868617B2 (en) 2016-09-28 2024-01-09 Amazon Technologies, Inc. Virtualizing non-volatile storage at a peripheral device
JP2020524840A (ja) * 2017-06-16 2020-08-20 アリババ グループ ホウルディング リミテッド ハードウェア仮想化のための方法及び装置
US11467978B2 (en) 2017-06-16 2022-10-11 Alibaba Group Holding Limited Method and apparatus for hardware virtualization
JP7220163B2 (ja) 2017-06-16 2023-02-09 アリババ グループ ホウルディング リミテッド ハードウェア仮想化のための方法及び装置

Also Published As

Publication number Publication date
US20170277470A1 (en) 2017-09-28
JP6262360B2 (ja) 2018-01-17
US10409519B2 (en) 2019-09-10
JPWO2016056140A1 (ja) 2017-07-06

Similar Documents

Publication Publication Date Title
JP6262360B2 (ja) 計算機システム
CN107690622B (zh) 实现硬件加速处理的方法、设备和系统
US11093177B2 (en) Virtualized OCSSDs spanning physical OCSSD channels
JP7280508B2 (ja) 情報処理装置、情報処理方法および仮想マシン接続管理プログラム
US9697024B2 (en) Interrupt management method, and computer implementing the interrupt management method
KR20200017363A (ko) 호스트 스토리지 서비스들을 제공하기 위한 NVMe 프로토콜에 근거하는 하나 이상의 호스트들과 솔리드 스테이트 드라이브(SSD)들 간의 관리되는 스위칭
US10248460B2 (en) Storage management computer
US9092366B2 (en) Splitting direct memory access windows
JP5969122B2 (ja) ホストバスアダプタおよびシステム
JP2013531283A (ja) ストレージの仮想化機能と容量の仮想化機能との両方を有する複数のストレージ装置を含んだストレージシステム
JP2003256150A (ja) 記憶制御装置および記憶制御装置の制御方法
US9582214B2 (en) Data access method and data access apparatus for managing initialization of storage areas
US20220066928A1 (en) Pooled memory controller for thin-provisioning disaggregated memory
US9104601B2 (en) Merging direct memory access windows
CN111367472A (zh) 虚拟化方法和装置
US9239681B2 (en) Storage subsystem and method for controlling the storage subsystem
US11080192B2 (en) Storage system and storage control method
WO2021120843A1 (fr) Procédé d'attribution de mémoire d'hôte en nuage, hôte en nuage, dispositif et support de stockage
WO2018173300A1 (fr) Procédé de commande d'e/s et système de commande d'e/s
KR20230111055A (ko) 분할운용 컴퓨팅 시스템 및 방법
CN114296639A (zh) 命令处理方法及闪存设备
WO2017113329A1 (fr) Procédé de gestion d'antémémoire pour grappe d'hôtes et hôte

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14903575

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 15505746

Country of ref document: US

ENP Entry into the national phase

Ref document number: 2016552796

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 14903575

Country of ref document: EP

Kind code of ref document: A1