WO2016048131A1 - Power-on-reset circuit - Google Patents

Power-on-reset circuit Download PDF

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Publication number
WO2016048131A1
WO2016048131A1 PCT/MY2015/050100 MY2015050100W WO2016048131A1 WO 2016048131 A1 WO2016048131 A1 WO 2016048131A1 MY 2015050100 W MY2015050100 W MY 2015050100W WO 2016048131 A1 WO2016048131 A1 WO 2016048131A1
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WIPO (PCT)
Prior art keywords
por
trip point
module
voltage
power supply
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PCT/MY2015/050100
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French (fr)
Inventor
Hasmayadi Abdul Majid
Chieu Yin Chia
Original Assignee
Mimos Berhad
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Mimos Berhad filed Critical Mimos Berhad
Publication of WO2016048131A1 publication Critical patent/WO2016048131A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/14—Modifications for compensating variations of physical values, e.g. of temperature
    • H03K17/145—Modifications for compensating variations of physical values, e.g. of temperature in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/30—Modifications for providing a predetermined threshold before switching
    • H03K17/302—Modifications for providing a predetermined threshold before switching in field-effect transistor switches

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Abstract

The present invention relates to a power-on-reset (POR) circuit (100) that generates an absolute power-on-reset trip point voltage. The POR circuit (100) comprises of a power supply independent module (10), a power supply dependent module (20), a first tuning module (30), a second tuning module (40), an inverter module (50), a voltage comparison module (60) and a feedback module (70).

Description

POWER-ON-RESET CIRCUIT
FIELD OF INVENTION
The present invention relates to a power-on-reset circuit. More particularly, the present invention relates to a power-on-reset circuit that generates an absolute power-on-reset trip point voltage.
BACKGROUND OF THE INVENTION
A power-on-reset (POR) in digital circuits provides a regulated voltage to a microprocessor or microcontroller to ensure that the microprocessor or microcontroller will start in the same condition each time they are powered up. A basic POR circuit usually comprises of a capacitor in series with a resistor, wherein the POR circuit measures a time period during which the rest of the circuit is held in a reset state. During operation, a digital circuit may lose the power supply signal. When a power supply signal approaches a stable operating potential, a POR signal is used to reset the digital circuits.
An example of a POR circuit is disclosed in a United States Patent number 8547147 B2. The POR circuit comprises of a self-bias module to provide a reference voltage, a feedback module to provide a feedback voltage, a comparison module to compare the feedback voltage to the reference voltage, an inverter to couple the output the comparison module to enable input of the self-bias module and a switch module to disable the self-bias module when the feedback voltage exceeds the reference voltage.
In another United States Patent number 8508264 B1 , it also discloses a power on reset (POR) circuit. The POR circuit comprises of a PMOS transistor coupled to a first voltage rail at its source, a drive circuit coupled to the drain of the PMOS transistor to output a POR signal, a voltage divider coupled between the drain of the PMOS transistor and the second voltage rail, a switch network having first and second switches, and a controller coupled to the first and the second switches.
However, it has been a major challenge to inventors in producing a POR circuit that has an absolute trip point voltage due to process variation. Besides a false reset of internal latches because of process variation, the reset period of the POR circuits also sometimes takes too long. Therefore, there is still a need to provide a POR circuit that produces an absolute voltage without having to design a complex circuit. SUMMARY OF INVENTION
The present invention relates to a power-on-reset circuit (POR) that generates an absolute power-on-reset (POR) trip point voltage. The power-on-reset (POR) circuit (100) comprises of a power supply independent module (10) to provide a first reference current within a predetermined range, a power supply dependent module (20) to provide a second current which increases according to a divided power supply voltage, an inverter module (50) to couple a POR trip point (15) to the output of the POR circuit (100), a voltage comparison module (60) to compare a power supply voltage with an expected POR trip point voltage, and a feedback module (70) to decide the adjustment of the POR trip point voltage based on the output of the comparison module (60). Additionally, the POR circuit (100) is characterised in that a first tuning module (30) to adjust the first reference current and a second tuning module (40) to adjust the second current.
The first tuning module (30) includes at least one P-channel Metal-Oxide- Semiconductor field effect (PMOS) transistor, wherein the source of the at least one PMOS transistor is connected to a power supply voltage and the drain of the at least one PMOS transistor is connected to the POR trip point (15), and at least two switches connected to the at least one PMOS transistor, wherein the at least two switches are used either to connect the gate of the at least one PMOS transistor to the independent power supply module (10) or directly to the power supply voltage. On the other hand, the second tuning module (40) includes at least one N-channel Metal-Oxide-Semiconductor field effect (NMOS) transistor, wherein the drain of the at least one NMOS transistor is connected to the POR trip point (15), and at least two switches connected to the at least one NMOS transistor, wherein the at least two switches are used either to connect the gate of the at least one NMOS transistor to the power supply dependent module (20) or to ground.
Preferably, the first tuning module (30) includes at least one PMOS transistor, wherein the first tuning module (30) may include at least two switches connected to each PMOS transistor. Preferably, the second tuning module (40) includes at least one NMOS transistor, wherein the second tuning module (40) at least two switches connected to each NMOS transistor.
A method to generate an absolute power-on-reset (POR) trip point voltage is characterised by the steps of generating a first reference current; conducting a second current once the power supply voltage hits a specific voltage based on a ratio of the power supply voltage; pulling a POR decision trip point to ground to trigger a POR trip point voltage; comparing an expected POR trip point voltage to the POR trip point voltage by a voltage comparison module (60); adjusting the first reference current by increasing the number of P-channel Metal-Oxide-Semiconductor field effect (PMOS) transistors at a first tuning module (30) or adjusting the second current by reducing the number of N-channel Metal-Oxide-Semiconductor field effect (NMOS) transistors at a second tuning module (40) to adjust the POR trip point voltage to the expected POR trip point voltage if the POR trip point voltage is lower than the expected POR trip point voltage; adjusting the first reference current by reducing the number of PMOS transistors at the first tuning module (30) or adjusting the second current by increasing the number of NMOS transistors at the second tuning module (40) to adjust the POR trip point voltage to the expected POR trip point voltage if the POR trip point voltage is higher than the expected POR trip point voltage; comparing the trip point voltage to the expected POR trip point voltage by the voltage comparison module (60) once the power supply voltage is ramped up; and generating a signal by a feedback module (70) to stop the adjustment of the first reference current and second current once the POR trip point voltage has a similar value to the expected POR trip point voltage.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
FIG. 1 illustrates a block diagram of a power-on-reset (POR) circuit (100) according to an embodiment of the present invention. FIG. 2 illustrates a schematic diagram of a power supply independent module (10) of the POR circuit (100) of FIG. 1.
FIG. 3 illustrates a schematic diagram of a power supply dependent module (20) of the POR circuit (100) of FIG. 1.
FIG. 4 illustrates a schematic diagram of a fist tuning module (30) of the POR circuit of FIG. 1. FIG. 5 illustrates a schematic diagram of a second tuning module (40) of the POR circuit of FIG. 1.
FIG. 6 illustrates a schematic diagram of a feedback module (70) of the POR circuit of FIG. 1.
FIG. 7 illustrates a flowchart of a method to generate an absolute POR trip point voltage according to an embodiment of the present invention.
FIG. 8 illustrates timing waveforms of relevant signals in generating a POR trip point voltage.
DESCRIPTION OF THE PREFERRED EMBODIMENT
A preferred embodiment of the present invention will be described herein below with reference to the accompanying drawings. In the following description, well known functions or constructions are not described in detail since they would obscure the description with unnecessary detail.
Reference is made initially to FIG. 1 , which illustrates a block diagram of a power-on-reset (POR) circuit (100) according to an embodiment of the present invention. The POR circuit (100), which produces an absolute trip point voltage by adjusting a trip point voltage, comprises of a power supply independent module (10), a power supply dependent module (20), a first tuning module (30), a second tuning module (40), an inverter module (50), a voltage comparison module (60) and a feedback module (70). The power supply independent module (10), which is connected to the power supply dependent module (20) in series, receives a power supply voltage, Vdd, to provide a first reference current within a predetermined range. Referring to FIG. 2, it shows that the power supply independent module (10) comprises of four P-channel Metal-Oxide-Semiconductor field effect (PMOS) transistors (11 , 12, 13, 14), four N- channel Metal-Oxide-Semiconductor field effect (NMOS) transistors (16, 17, 18, 19) and a resistor. A first PMOS transistor (11) has its source connected to the power supply voltage, Vdd. The first PMOS transistor (11) has its gate connected to the gate of a first NMOS transistor (16), whereas the drain of the first PMOS transistor (11) is connected to the gate of a first NMOS transistor (16) and the drain of the second NMOS transistor (17).
A second PMOS transistor (12) has its source connected to the power supply voltage, Vdd. The gate of the second PMOS transistor (12) is connected to the gate of a third PMOS transistor (13), the gate of a fourth PMOS transistor (14), the drain of the third PMOS transistor (13) and the drain of a fourth NMOS transistor (19). The second PMOS transistor (12) has its drain connected to the drain of the first NMOS transistor (16) and the drain of a third NMOS transistor (18).
The third PMOS transistor (13) has its source connected to the power supply voltage, Vdd. The gate of the third PMOS transistor (13) is connected to the gate of the second PMOS transistor (12), the gate of the fourth PMOS transistor (14), the drain of the third PMOS transistor (13) and the drain of the fourth NMOS transistor (19). Besides connected to the gate of the third PMOS transistor (13), the drain of the third PMOS transistor (13) is also connected to the gate of the fourth PMOS transistor (14) and the drain of the fourth NMOS transistor (19).
The fourth PMOS transistor (14) has its source connected to the power supply voltage, Vdd. The gate of the fourth PMOS transistor (14) is connected the gate of the second PMOS transistor (12), the gate of the third PMOS transistor (13), the drain of the third PMOS transistor (13) and the drain of the fourth NMOS transistor (19). The fourth PMOS transistor (14) has its drain connected to the drain of an NMOS transistor (21) in the power supply dependent module (20) to create a power-on-reset (POR) trip point (15).
The first NMOS transistor (16) has its drain connected to the drain of the second PMOS transistor (12). The gate of the first NMOS transistor (16) is connected to gate of the first PMOS transistor (11), the drain of the first PMOS transistor (11) and the drain of the second NMOS transistor (17). The first NMOS transistor (16) has its source connected to the drain of the second PMOS transistor (12), the gate of the second NMOS transistor (17) and the drain of the third NMOS transistor (18).
The second NMOS transistor (17) has its drain connected to the drain of the first PMOS transistor (11) and the gate of the first NMOS transistor (16). The gate of the second NMOS transistor (17) is connected to the source of the first NMOS transistor (16), whereas the source of the second NMOS transistor (17) is connected to ground.
The third NMOS transistor (18) has its drain connected to the drain of the second PMOS transistor (12), the source of the first NMOS transistor (16), the gate of the third NMOS transistor (18) and the gate of the fourth NMOS transistor (19). The gate of the third NMOS transistor (18) is connected to the drain of the third NMOS transistor (18) and the gate of the fourth NMOS transistor (19), whereas the source of the third NMOS transistor (18) is connected to ground.
The fourth NMOS transistor (19) has its drain connected to the drain of the third PMOS transistor (13). The gate of the fourth NMOS transistor (19) is connected to the third NMOS transistor (18), whereas the source of the fourth NMOS transistor (19) is connected serially to the resistor that is connected to ground.
Gates of the third and fourth PMOS transistors (13, 14) have the same gate to source voltage and this is known as current mirroring for a multiplier effect of the first reference current. The dimension which may include the width and length of the second and third PMOS transistors (12, 13), the third and fourth NMOS transistors (18, 19) and the resistor determines the magnitude of the first reference current. The first PMOS transistor (11) and the first and second NMOS transistors (16, 17) are used as a startup for the first reference current. Similar to the power supply independent module (10), the power supply dependent module (20) also receives the power supply voltage, Vdd, to provide a second current which increases according to a divided power supply voltage within a predetermined range. Referring to FIG. 3, it shows that the power supply dependent module (20) comprises of an NMOS transistor (21) and a voltage divider (25) which includes two resistors in series. The gate of the NMOS transistor (21) is connected to the voltage divider (25), whereas the source of the NMOS transistor (21) is connected to ground. The dimension which may include the width and length of the NMOS transistor (21) and the resistors determines the magnitude of the second current.
The drain of the NMOS transistor (21) of the power supply dependent module (20) is connected to the drain of the fourth PMOS transistor (14) of the power supply independent module (10) to create the POR trip point (15). The POR trip point (15) is also connected to the first tuning module (30), the second tuning module (40) and the inverter module (50).
The first tuning module (30) is used to adjust the first reference current. Referring now to FIG. 4, it shows that the first tuning module (30) comprises of two PMOS transistors (31 , 32) with their sources connected to the power supply voltage, Vdd. On the other hand, the drains of the two PMOS transistors (31 , 32) are connected to the POR trip point (15). The first tuning module (30) further comprises of two switches connected to each PMOS transistor. These switches are used either to connect the gates of the two PMOS transistors (31 , 32) to the gate of the fourth PMOS transistor (14) in the independent power supply module (10), or directly to the power supply voltage, Vdd. If the gates of the two PMOS transistors (31 , 32) in the first tuning module (30) are connected to the gate of the fourth PMOS transistor (14) in the independent power supply module (10), more current is generated in the first reference current. However, if the gates of the two PMOS transistors (31 , 32) in the first tuning module (30) are connected to the power supply, less current is generated in the first reference current.
On the other hand, the second tuning module (40), which is connected to the power supply dependent module (20), is used to adjust the second current. Referring to FIG. 5, the second tuning module (40) comprises of two NMOS transistors (41 , 42) with the drains connected to the POR trip point (15); two switches to connect the gates of the two NMOS transistors (41 , 42) of the second tuning module (40) to the voltage divider (25) of the power supply dependent module (20); and two other switches to connect the gates of the two NMOS transistors (41 , 42) of the second tuning module (40) to ground. The second current can be adjusted depending on whether the switches connect the gate of the NMOS transistors (41 , 42) to the voltage divider (25) or to ground. If the switches connect the gates of the two NMOS transistors (41 , 42) of the second tuning module (40) to the voltage divider (25), then more current is added to the second current. On the other hand, if the switches connect the gates of the two NMOS transistors (41 , 42) of the second tuning module (40) to the ground, then current is reduced from the second current.
The inverter module (50) is used to couple the POR trip point (15) to the output of the POR circuit (100). It comprises of one PMOS transistor and one NMOS transistor with the gates connected to each other. The drain of PMOS transistor is also connected to the drain of the NMOS transistor. On the other hand, the source of the PMOS transistor is connected to the voltage power supply, Vdd. The source of the NMOS transistor is also connected to ground. The input of the inverter module (50) is connected to the POR trip point (15), whereas the output of the inverter module (50) is connected to a compare signal in the voltage comparison module (60) as shown in FIG. 1.
The voltage comparison module (60) is used to compare the power supply voltage, Vdd to an expected POR trip point voltage. The voltage comparison module (60) has one input connected to the power supply voltage, Vdd, and another input connected to the expected POR trip point voltage as shown in FIG. 1. On the other hand, the output of the voltage comparison module (60) is connected to the feedback module (70). The comparison of the voltage is triggered from the output of the inverter module (50). The trigger point for comparison in the voltage comparison module (60) is the rising edge of the output from the inverter module (50).
The feedback module (70) decides the adjustment of the POR trip point voltage based on the output of the voltage comparison module (60). Referring to FIG. 6, the feedback module (70) has an input connected to the voltage comparison module (60). On the other hand, to adjust the POR trip point voltage, a first output of the feedback module (70) is connected to the first tuning module (30) whereas a second output is connected to the second tuning module (40). Referring now to FIG. 7, it illustrates a flowchart of a method to generate an absolute POR trip point voltage according to an embodiment of the present invention. To generate a POR trip point voltage, two currents have to be compared. The power supply independent module (10) is turned on first to generate the first reference current, wherein as the power supply voltage, Vdd increases and a saw tooth ramp is provided as in step 210, the first reference current is generated. Once Vdd hits a specific voltage based on a ratio of the Vdd which is determined by the voltage divider (25), only then the power supply dependent module (20) starts conducting the second current and pulls the POR decision trip point to ground to trigger a POR trip point voltage. Timing waveforms of the relevant signals in generating the POR trip point voltage are shown in FIG. 8.
Due to process variation, the first reference current and the second current generated by the power supply independent module (10) and the power supply dependent module (20) respectively will vary. Eventually, this will also change the absolute value of the POR trip point voltage. However, the adjustment of the POR trip point voltage can be made by adjusting the first reference current through the additional branches of PMOS transistors (31 , 32) in the first tuning module (30) or by adjusting the second current through the additional branches of NMOS transistors (41 , 42) in the second tuning module (40).
Hence, in adjusting the POR trip point voltage to get an absolute POR trip point voltage, a multiplying effect of the first tuning module (30) and the second tuning module (40) can be enabled or disabled during the ramping up of the of Vdd. To enable the multiplying effect of the first tuning module (30), the number of PMOS transistors (31 , 32) is increased by connecting the gates of the PMOS transistors to the gate of the fourth PMOS transistor (14) of the power supply independent module (10) by using switches. To disable the multiplying effect of the first tuning module (30), the number of PMOS transistors (31 , 32) is reduced by connecting the gates of the PMOS transistors (31 , 32) to Vdd by switches. On the other hand, to enable the multiplying effect of the second tuning module (40), the number of NMOS transistors (41 , 42) is increased by connecting the gates of the NMOS transistors to the voltage divider (25) of the power supply dependent module (20) by switches. To disable the multiplying effect of the second tuning module (40), the number of NMOS transistors (41 , 42) is reduced by connecting the gates of the NMOS transistors to ground by switches.
To get an absolute POR trip point voltage, an expected POR trip point voltage is applied to the voltage comparison module (60) to be compared to the POR trip point voltage of the POR circuit (100). The output of the inverter module (50) is used as the trigger point for the voltage comparison module (60) to compare the expected POR trip point voltage with the applied power supply voltage, Vdd as in step 220.
If the POR trip point voltage is lower than the expected POR trip point voltage as in decision 230, the output from the voltage comparison module (60) shows a value of "1". To adjust the POR trip point voltage to the expected POR trip point voltage, the first tuning module (30) can be enabled to increase the number of PMOS transistors (31 , 32). Besides increasing the number of PMOS transistors (31 , 32) at the first tuning module (30), the POR trip point voltage can also be adjusted by reducing the number of NMOS transistors (41 , 42) at the second tuning module (40) as in step 240.
Once the Vdd is ramped up again due to the adjustment of the multiplied first reference current or the second current, the POR trip point voltage is compared once again to the expected POR trip point voltage as in step 241 and step 242. The output of the voltage comparison module (60) is then monitored as in decision 243. If the output has a value of "1", the process repeats from step 241. However, if the output of the voltage comparison module (60) has a value of "0", the POR trip point voltage is said to have a similar value to the expected POR trip point, and hence, the absolute POR trip point voltage is achieved. The switch settings of the PMOS transistors (31 , 32) and the NMOS transistors (41 , 42) are then stored after detecting the correct value from the voltage comparison module (60) as in step 260. Finally, a DONE signal is generated by the feedback module (70) as in step 270 to stop the adjustment of the first reference current and second current. On the other hand, if the POR trip point voltage is higher than the expected POR trip point voltage as in decision 230, the output from the voltage comparison module (60) shows a value of "0." To adjust the POR trip point voltage to the expected POR trip point voltage, the first tuning module (30) can be disabled to reduce the number of PMOS transistors (31 , 32). Besides reducing the number of PMOS transistors (31 , 32) in the first tuning module (30), the POR trip point voltage can also be adjusted by increasing the number of NMOS transistors (41 , 42) in the second tuning module (40). Once the Vdd is ramped up again due to the adjustment of the multiplied first reference current or the second current, the POR trip point voltage is compared once again to the expected POR trip point voltage as in step 251 and step 252. The output of the voltage comparison module (60) is then monitored as in decision 253. If the output has a value of "0", the process repeats from step 251. However, if the output of the voltage comparison module (60) has a value of "1", the POR trip point voltage is said to have a similar value to the expected POR trip point, and hence, the absolute POR trip point voltage is achieved. The switch settings of the PMOS transistors (31 , 32) and the NMOS transistors (41 , 42) are then stored after detecting the correct value from the voltage comparison module (60) as in step 260. Finally, a DONE signal is generated by the feedback module (70) as in step 270 to stop the adjustment of the first reference current and second current.
While embodiments of the invention have been illustrated and described, it is not intended that these embodiments illustrate and describe all possible forms of the invention. Rather, the words used in the specifications are words of description rather than limitation and various changes may be made without departing from the scope of the invention.

Claims

1. A power-on-reset (POR) circuit (100) comprises of:
a) a power supply independent module (10) to provide a first reference current within a predetermined range,
b) a power supply dependent module (20) to provide a second current which increases according to a divided power supply voltage,
c) an inverter module (50) to couple a POR trip point (15) to the output of the POR circuit (100),
d) a voltage comparison module (60) to compare a power supply voltage with an expected POR trip point voltage, and
e) a feedback module (70) to decide the adjustment of the POR trip point voltage based on the output of the voltage comparison module (60), characterised in that the POR circuit (100) further comprises of:
f) a first tuning module (30) to adjust the first reference current, wherein the first tuning module (30) includes:
i. at least one P-channel Metal-Oxide-Semiconductor field effect (PMOS) transistor, wherein the source of the at least one PMOS transistor is connected to a power supply voltage and the drain of the at least one PMOS transistor is connected to the POR trip point (15), and
ii. at least two switches connected to the at least one PMOS transistor, wherein the at least two switches are used either to connect the gate of the at least one PMOS transistor to the independent power supply module (10) or directly to the power supply voltage; and g) a second tuning module (40) to adjust the second current, wherein the second tuning module (40) includes:
i. at least one N-channel Metal-Oxide-Semiconductor field effect (NMOS) transistor, wherein the drain of the at least one NMOS transistor is connected to the POR trip point (15), and
ii. at least two switches connected to the at least one NMOS transistor, wherein the at least two switches are used either to connect the gate of the at least one NMOS transistor to the power supply dependent module (20) or to ground. The POR circuit (100) as claimed in claim 1 , wherein the first tuning module (30) includes at least one PMOS transistor.
The POR circuit (100) as claimed in claim 1 , wherein the first tuning module (30) includes at least two switches connected to each PMOS transistor.
The POR circuit (100) as claimed in claim 1 , wherein the second tuning module (40) includes at least one NMOS transistor.
The POR circuit (100) as claimed in claim 1 , wherein the second tuning module (40) includes at least two switches connected to each NMOS transistor.
A method to generate an absolute power-on-reset (POR) trip point voltage is characterised by the steps of:
a) generating a first reference current;
b) conducting a second current once power supply voltage hits a specific voltage based on a ratio of the power supply voltage;
c) pulling a POR decision trip point to ground to trigger a POR trip point voltage;
d) comparing an expected POR trip point voltage to the POR trip point voltage by a voltage comparison module (60);
e) adjusting the first reference current by increasing the number of P- channel Metal-Oxide-Semiconductor field effect (PMOS) transistors at a first tuning module (30) or adjusting the second current by reducing the number of N-channel Metal-Oxide-Semiconductor field effect (NMOS) transistors at a second tuning module (40) to adjust the POR trip point voltage to the expected POR trip point voltage if the POR trip point voltage is lower than the expected POR trip point voltage;
f) adjusting the first reference current by reducing the number of PMOS transistors at the first tuning module (30) or adjusting the second current by increasing the number of NMOS transistors at the second tuning module (40) to adjust the POR trip point voltage to the expected POR trip point voltage if the POR trip point voltage is higher than the expected POR trip point voltage; g) comparing the trip point voltage to the expected POR trip point voltage by the voltage comparison module (60) once the power supply voltage is ramped up; and
h) generating a signal by a feedback module (70) to stop the adjustment of the first reference current and second current once the POR trip point voltage has a similar value to the expected POR trip point voltage.
PCT/MY2015/050100 2014-09-26 2015-09-04 Power-on-reset circuit WO2016048131A1 (en)

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MYPI2014702828 2014-09-26

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI615854B (en) * 2016-12-09 2018-02-21 Powerchip Technology Corporation Memory apparatus

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5523710A (en) * 1994-05-17 1996-06-04 Matsushita Electric Industrial Co., Ltd. Initial value setting circuit
US20130176065A1 (en) * 2012-01-06 2013-07-11 Pio Balmelli Externally configurable power-on-reset systems and methods for integrated circuits
US8508264B1 (en) * 2012-01-30 2013-08-13 Texas Instruments Incorporated Power on reset apparatus

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5523710A (en) * 1994-05-17 1996-06-04 Matsushita Electric Industrial Co., Ltd. Initial value setting circuit
US20130176065A1 (en) * 2012-01-06 2013-07-11 Pio Balmelli Externally configurable power-on-reset systems and methods for integrated circuits
US8508264B1 (en) * 2012-01-30 2013-08-13 Texas Instruments Incorporated Power on reset apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI615854B (en) * 2016-12-09 2018-02-21 Powerchip Technology Corporation Memory apparatus

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