WO2016046970A1 - Dispositif de mémorisation - Google Patents

Dispositif de mémorisation Download PDF

Info

Publication number
WO2016046970A1
WO2016046970A1 PCT/JP2014/075680 JP2014075680W WO2016046970A1 WO 2016046970 A1 WO2016046970 A1 WO 2016046970A1 JP 2014075680 W JP2014075680 W JP 2014075680W WO 2016046970 A1 WO2016046970 A1 WO 2016046970A1
Authority
WO
WIPO (PCT)
Prior art keywords
command
read
data
memory
controller
Prior art date
Application number
PCT/JP2014/075680
Other languages
English (en)
Japanese (ja)
Inventor
英通 小関
昌弘 鶴谷
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to PCT/JP2014/075680 priority Critical patent/WO2016046970A1/fr
Publication of WO2016046970A1 publication Critical patent/WO2016046970A1/fr

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/16—Protection against loss of memory contents

Definitions

  • the present invention relates to storage device control.
  • An SSD is a semiconductor storage device that uses a flash memory (hereinafter, FM) as a storage medium.
  • FM flash memory
  • many SSDs are equipped with a NAND type FM.
  • FM reads and writes data in units called pages. Since FM cannot directly overwrite a page, in order to store new data in a page where data has already been stored, it is necessary to erase the data once. Data erasure is performed on a collection of pages called a block. Further, a block aggregate called a die is built in the FM. When the FM receives a command such as read, write, or erase, it performs a certain processing time called chip busy time and performs an internal operation of the FM. In the meantime, reading, writing, erasing, etc. to other pages and other blocks in the same die cannot be executed. Therefore, when a data read request for a page of another block of the same die is generated while a block is being erased, the read request is waited until the block erase is completed.
  • a command such as read, write, or erase
  • FM chip busy time is about 0.1 ms for page read and about several ms for page write, whereas block erasing requires a very long time of about several tens of ms. Therefore, the response time to the FM read request is originally about 0.1 ms if there is no conflict with block erasure, but if it collides with the block erase processing, it will be delayed significantly to about a dozen ms. Therefore, an SSD equipped with an FM having such response characteristics also has a risk of causing a significant response delay in principle.
  • system response delay for example, system response delay to bid instructions
  • system response delay to bid instructions can lead to huge losses, so it is a number of response requirements for storage devices Some have severe restrictions such as ms or less.
  • ms or less In order to use the SSD in such an environment, it is necessary to avoid a read response delay due to collision with erasure and realize a stable low response of the SSD.
  • the collection read refers to a process of generating data of a certain SSD in a RAID group using data and parity held in another SSD.
  • an SSD controller that controls the SSD (hereinafter referred to as an SSD controller) must determine whether or not the collection read is necessary. For this purpose, it is necessary for the SSD controller to know whether or not the FM (strictly speaking, the die) to which the read request will be issued is currently executing the block erase process.
  • a general SSD adopts a mechanism for simultaneously queuing a plurality of commands to the FM. Therefore, it is difficult for the SSD controller to grasp which command being queued is currently being executed by the FM.
  • one of the representative storage devices and semiconductor storage devices of the present invention provides command execution information such as the type of command being executed (read, write, erase, etc.) and the expected end time of the command.
  • An interface for notifying the SSD controller is provided, the FM controller updates the command execution information when executing the queued command, and the SSD controller executes the access destination execution information in advance when reading data from the FM. , It is confirmed whether the read destination FM is currently being erased. If the read destination FM is not being erased, normal read is performed. If the read destination FM is being erased, correction read is performed.
  • FIG. 1 is a diagram showing an outline of the present invention.
  • FIG. 2 is a diagram illustrating a configuration example of the storage system 10000 including the storage apparatus 10 according to the first embodiment.
  • FIG. 3 is a diagram illustrating a configuration example of the SSD 700.
  • FIG. 4 is a diagram illustrating a configuration example of the FM controller 717 and the FM chip 780.
  • FIG. 5 is a diagram illustrating a configuration example of a parity group.
  • FIG. 6 is a diagram illustrating a configuration example of the FM command management table 71630.
  • FIG. 7 is a diagram illustrating a configuration example of the parity group management table 71640.
  • FIG. 8 is a sequence diagram showing an outline of tasks of the SSD controller 710.
  • FIG. 8 is a sequence diagram showing an outline of tasks of the SSD controller 710.
  • FIG. 9 is a sequence diagram showing an overview of S102 which is data write processing of the SSD controller.
  • FIG. 10 is a sequence diagram showing an overview of S103 which is a data read process of the SSD controller.
  • FIG. 11 is a sequence diagram showing an overview of S303, which is the collection read process of the SSD controller.
  • FIG. 12 is a sequence diagram showing an overview of S105, which is the garbage collection process of the SSD controller.
  • FIG. 13 is a sequence diagram showing an outline of tasks of the FM controller 717.
  • FIG. 14 is a sequence diagram showing the exchange between the SSD controller 710 and the FM controller 717 in the data read process of the SSD controller according to the second embodiment.
  • FIG. 15 is a diagram illustrating a configuration example of the FM controller 717 according to the third embodiment.
  • FIG. 16 is a diagram illustrating a configuration example of the erasing execution flag 900.
  • FIG. 17 is a sequence diagram illustrating an outline of tasks of the FM controller 717 according to the third embodiment.
  • the nonvolatile semiconductor storage medium included in the SSD is assumed to be a flash memory (FM).
  • the flash memory is assumed to be a type of flash memory that is read / written in units of pages, typically a NAND flash memory.
  • the flash memory may be another type of flash memory instead of the NAND type.
  • other types of non-volatile semiconductor storage media such as a phase change memory may be employed.
  • SSD controller when the processing is described with “SSD controller” as a subject, the operation is realized by a processor (for example, CPU (Central Processing Unit)) in the SSD controller executing various control programs. Therefore, “SSD controller” may be read as “processor or control program”.
  • management table or the like, but the various information may be expressed in a data structure other than a table. Further, the “management table” can be referred to as “management information” to indicate that it does not depend on the data structure. Further, the process may be described with “program” as the subject.
  • the program is executed by a processor, such as an MP (Micro Processor) or CPU, and performs a predetermined process. Since the processor performs processing while appropriately using storage resources (for example, a memory) and a communication interface device (for example, a communication port), the subject of the processing may be a processor.
  • the processor may have dedicated hardware in addition to the CPU.
  • the computer program may be installed on each computer from a program source.
  • the program source may be provided by, for example, a program distribution server or a storage medium.
  • each element for example, the controller can be identified by a number or the like, but other types of identification information such as a name may be used as long as the information can identify each element.
  • identification information such as a name may be used as long as the information can identify each element.
  • the same reference numerals are given to the same parts.
  • the present invention is not limited to the present embodiment, and any application examples that meet the idea of the present invention can be applied. Included in the scope. Further, unless specifically limited, each component may be plural or singular.
  • FIG. 1 is a diagram showing an outline of the present invention.
  • the SSD 700 is connected to a host device such as the host computer 30 and the storage controller 100 which is a controller of the storage device.
  • the SSD 700 includes an SSD controller 710 for controlling the entire SSD 700 and a plurality of flash memory (FM) chips 780a, 780b, 780c, and 780d.
  • the SSD controller 710 further includes a processor 713, a cache memory 716 for temporarily storing data, a parity operation circuit 718 for executing various parity operations such as XOR (Exclusive OR) and Galois, and an FM for controlling the FM. Controllers 717a, 717b, 717c, and 717d are included.
  • the SSD controller 710 controls the entire SSD 700 by the processor 713 executing various control programs.
  • the FM controllers 717a to 717d include FM command queues 719a to 719d for the processor 713 to queue commands for the FM, and execution information 720a to 720d for storing the command execution status of the FM controllers 717a to 717d. It has been.
  • the execution information 720a to 720d stores the type of command currently being executed for the FM (read / write / erase, etc.), its expected end time, and the like.
  • an erasing command (“EZ” in the figure) is queued in the FM controller 717a, and the command is executed on the FM chip 780a.
  • the execution information 720a stores, by the FM controller 717a, the FM chip 780a currently performing the erasing process when the FM controller 717a executes the erasing process and the expected end time.
  • the FM chips 780a to 780d are used in a RAID 5 configuration.
  • the FM chip 780a stores data 300
  • the FM chip 780b stores data 301
  • the FM chip 780c stores data 302.
  • the FM chip 780d stores a parity 303 generated by performing an XOR operation on the data 300 to 302. Therefore, one piece of data can be regenerated from the remaining data and parity.
  • the data 300 can be regenerated by performing an XOR operation on the data 301, the data 302, and the parity 303.
  • the RAID level may take various levels such as RAID 6 and RAID 1 in addition to RAID 5.
  • the internal operation when the SSD 700 receives a read request for data 300 from the host computer 30 or the storage controller 100 as a host device will be described.
  • the FM chip 780a is executing the erasing process
  • the processor 713 requests the FM controller 717a to read the data 300
  • the read command is waited until the erasing process being executed is completed.
  • the read process by the read command collides with the erase process (access or process conflict), and the read process is awaited, so that the response to the read command is greatly delayed.
  • the processor 713 in order to avoid the above influence (occurrence of response delay), the processor 713 first refers to the execution information 720a to determine whether or not the read command for the data 300 can be immediately executed. (S1). As a result of the reference, it can be seen that the FM chip 780a is currently being erased in the execution information 720a and that immediate access is impossible. Therefore, the processor 713 uses a normal read (hereinafter referred to as normal read) method for acquiring the data 300. Is changed to collection read (S2). The collection read refers to a process for generating data using parity.
  • the processor 713 reads the data 301, the data 302, and the parity 303 from the FM to the cache memory 716, and then inputs them to the parity calculation circuit 718 to generate the data 300.
  • the data 300 obtained in this way is returned to the host device.
  • the processor 713 to the SSD controller 710 performs control so that two or more erase commands are not issued simultaneously to a plurality of FMs constituting a parity group. That is, the processor 713 or the SSD controller 710 issues an erase command to only one FM among a plurality of FMs constituting the parity group, and after the erase command is completed, the erase command is issued to another FM of the parity group. Issue.
  • the SSD controller 710 can select the collection read and avoid the collision in the case where the read command collides with the erasure in the normal read, and can suppress the occurrence of the SSD response delay.
  • FIG. 2 is a diagram illustrating a configuration example of the storage system 10000 including the storage apparatus 10 according to the first embodiment.
  • the storage system 10000 includes a storage device 10 and a host computer 30.
  • the host computer 30 is an example of a host device that uses the storage device 10.
  • the host computer 30 is, for example, an application server.
  • the host computer 30 and the storage apparatus 10 communicate via a SAN (Storage Area Network) 20.
  • SAN Storage Area Network
  • another type of communication network for example, a LAN (Local Area Network)
  • one host computer 30 and one storage device 10 are provided, but at least one of them may be plural.
  • the host computer 30 executes control software (not shown) that issues a control command or the like to the storage apparatus 10, thereby issuing a control command or the like to the storage apparatus 10 for maintenance management.
  • the storage apparatus 10 includes a storage controller 100 and a disk box 110 connected to the storage controller 100.
  • the storage controller 100 controls the operation of the storage device 10.
  • the storage controller 100 includes a communication interface device, a memory, and a control device connected to them.
  • As the communication interface devices there are a host I / F 101 which is a front-end communication interface device and a disk I / F 107 which is a back-end communication interface device.
  • As a control device there is a processor (for example, CPU) 104.
  • the host I / F 101, the cache memory 103, the processor 104, and the disk I / F 107 are connected to the internal network 102 by a dedicated connection bus such as PCI (Peripheral Component Interconnect) (registered trademark), for example. Communication is possible via the internal network 102.
  • the cache memory 103 is connected to the internal network 102 by a dedicated connection bus such as DDR3 (Double Data Rate3).
  • the host I / F 101 is an interface for connecting the storage apparatus 10 to the SAN 20.
  • the internal network 102 is a network for connecting devices existing inside the storage apparatus 10.
  • the internal network 102 includes a switch. Instead of the internal network 102, ASICs (Application Specific Integrated Circuits) having an assist function such as a switch function, DMA (Direct Memory Access) transfer, and RAID calculation may be used.
  • ASICs Application Specific Integrated Circuits
  • DMA Direct Memory Access
  • the processor 104 controls the entire storage apparatus 10. There are a plurality of processors 104. In this case, the plurality of processors 104 can control the storage apparatus 10 in cooperation or sharing.
  • the cache memory 103 is an area for storing computer programs and data necessary for the processor 104 to control the storage apparatus 10.
  • the disk I / F 107 is an interface for connecting the storage controller 100 and the disk box 110.
  • the disk box 110 includes a plurality of different types of drives (for example, non-volatile physical storage media such as the HDD 111 and the SSD 700).
  • a RAID group is composed of the same type of drives. Each RAID group provides a logical volume as a user data storage space.
  • the HDD 111 and the SSD 700 are shown as the disks constituting the disk box 110, they may be configured only by the SSD 700.
  • the SSD 700 may be mounted as a storage medium in the host computer 30 or may be mounted as a cache device. Similarly, the SSD 700 may be connected to the internal network 102 as a part of the cache device of the storage apparatus 10.
  • FIG. 3 is a diagram illustrating a configuration example of the SSD 700.
  • the SSD 700 includes a plurality of flash memory chips 780 and an SSD controller 710 connected thereto.
  • the SSD controller 710 controls the operation of the SSD 700.
  • the SSD controller 710 includes a communication interface device, a memory, a control device connected thereto, and a hardware circuit that executes a parity operation.
  • the parity calculation function may be realized by software by the CPU.
  • a communication interface device there are a disk I / F 711 which is a front-end communication interface device and a flash memory (FM) controller 717 which is a back-end communication interface device.
  • the memory there is a cache memory 716.
  • There is a parity operation circuit as a hardware device that executes the parity operation. Note that the parity calculation function may be realized in software by the processor 713 executing a dedicated program.
  • the disk I / F 711, the processor 713, the cache memory 716, the FM controller 717, and the parity calculation circuit 718 are connected via an internal network 712.
  • the disk I / F 711 is connected to the disk I / F 107 of the storage controller 100 through a dedicated connection bus.
  • the internal network 712 is a network for connecting devices.
  • the internal network 712 may include a switch.
  • the internal network 712 may be replaced by ASICs having a switch function.
  • the processor 713 controls the entire SSD 700.
  • the cache memory 716 is an area for storing computer programs and data necessary for the processor 713 to control the SSD 700.
  • the cache memory 716 manages the logical-physical conversion table 71600 for managing the correspondence between logical addresses and physical addresses, the data cache area 71620 for caching user data, and the number of commands for the die in the flash memory chip 780.
  • the FM controller 717 is an interface for connecting the SSD controller 710 and the flash memory 780.
  • the SSD is a storage medium that includes a plurality of flash memories and a controller that controls them, and the external shape and the like are not limited to form factors.
  • a nonvolatile semiconductor memory such as a NOR type or a NAND type may be used.
  • MRAM Magneticoresistive random access memory
  • ReRAM resistance random access memory
  • FeRAM Feroelectric random access memory
  • Various semiconductor memories may be used.
  • FIG. 4 is a diagram illustrating a configuration example of the FM controller 717 and the FM chip 780.
  • FM chip 780 is constructed from a plurality of dies 781. Further, the die 781 is constructed by a plurality of blocks 782, and the block 782 is constructed by a plurality of pages 783.
  • the minimum unit of read / write in the flash memory is a page
  • the minimum unit of data erasure is a block.
  • a flash memory that has received a command such as read / write / erase transitions to a chip busy state. The time required for the internal processing of the flash memory is called chip busy time. The flash memory cannot process the next command until the chip busy state is completed.
  • the range of influence is die units. For this reason, while a certain die performs reading or writing on a certain page, it is impossible to execute access to other pages in the same die in parallel. Similarly, while erasing one block of a die, erasing another block in the same die cannot be performed.
  • the FM controller 717 has a die control unit 721 for controlling the die 781.
  • the die control unit 721 has a one-to-one correspondence with the die 781, but one die control unit 721 may control a plurality of dies 781.
  • the die control unit 721 includes a command queue 719 for the processor 713 to queue a command for the FM chip 780, and execution information 720 for notifying the processor 713 of information on the command being executed.
  • the command queue 719 includes a normal queue 7191 and a priority queue 7192, and the processor 713 can select a queuing destination according to the priority of the command.
  • the commands queued in the priority queue 7192 are executed before the commands queued in the normal queue 7191.
  • a collection read process can be executed in a short time by providing a policy such as queuing a read command for collection read in the priority queue and queuing other commands in the normal queue.
  • the execution information 720 has a command type 7201 and an expected end time 7202.
  • the command type 7201 the type of command currently being executed (read, write, erase, etc.) is input by the FM controller 717.
  • the FM controller 717 inputs an estimated time at which the command being executed ends. Since the standard value of the chip busy time is determined for each chip, the FM controller 717 can predict the end time by adding the chip busy time to the current time.
  • FIG. 5 is a diagram illustrating a configuration example of a parity group.
  • a parity group is a group of flash memories that form a RAID configuration.
  • the dies 781a, 781c, and 781e belong to the same parity group 800, and further include only the die # 0 controlled by each FM controller (717e, 717f, and 717g).
  • the dies 781b, 781d, and 781f belong to the same parity group 801, and further include only the die of the die # 1 controlled by each FM controller.
  • the dies 781g, 781h, and 781j belong to the same parity group 802, and further include only the die #N controlled by each FM controller.
  • the parity group is configured so that the same die is not shared among a plurality of parity groups.
  • the SSD controller 710 controls so that the total number of erase commands issued to the die within a certain parity group is 1 or less. This means that, for example, in the parity group 800, the total number of erase commands queued in the dies 781a, 781c, and 781e at a certain time becomes 1 or less. This is to ensure that when the normal read collides with the erase command and switches to the collection read, the collection read does not collide with the erase command.
  • FIG. 6 is a diagram illustrating a configuration example of the FM command management table 71630.
  • the FM command management table 71630 includes a parity group # 71631, a die # 71632, a command type 71633, FM controller (FMC) # 0 71634 to FMC # N 71737, and a total value 71638.
  • FMC FM controller
  • Parity group # 71631 is an identifier of a parity group and is a unique number.
  • the die # 71632 is an identifier of a die that forms the parity group.
  • the command type 71633 represents the type of a read / write / erase command queued in the die, and each command has attributes of “normal” and “priority”. “Normal” means the number of commands queued in the normal queue, and “priority” means the number of commands queued in the priority queue.
  • FMC # 0 71634 to FMC # N 71637 indicate the number of command queuing per FM controller.
  • the total value 71638 indicates the total value of the queued commands.
  • parity group # 800 is composed of dies of die # 0 belonging to FMC # 0 to FMC #N.
  • One read command for the normal queue is assigned to FMC # 0 and to FMC # 1. It shows that a total of five, two and two in FMC # N, are queued. Since there is one command queued in the other FMC 71636, the total value 71638 is six.
  • FIG. 7 is a diagram showing a configuration example of the parity group management table 71640.
  • the parity group management table 71640 includes a parity group # 71641, a stripe column # 71642, a type 71642, an FM controller (FMC) # 71644, a die # 71465, a block # 71646, and a page # 71647.
  • FMC FM controller
  • Parity group # 71641 is an identifier of the parity group and is a unique number.
  • a stripe column 71642 indicates a parity protection unit.
  • the type 71643 indicates the type of data and parity belonging to the stripe column.
  • FMC # 71644 to page # 71647 indicate which page of which FMC, which die, which block belongs to which data or page.
  • FIG. 8 is a sequence diagram showing an outline of tasks of the SSD controller 710.
  • the SSD controller 710 checks whether there is a read or write request from the host device (S100). If there is a request (S100: Yes), the SSD controller 710 determines the type (S101). If the type is a write request (S101: write), the SSD controller 710 executes a write process (S101: Yes). S102) (detailed in FIG. 12). Thereafter, the process proceeds to S104. On the other hand, when the determination result in S101 is a read request (S101: Read), the SSD controller 710 executes a read process (S103) (detailed in FIG. 10). Thereafter, the process proceeds to S104. On the other hand, if the determination result in S100 is no request (S100: No), the process proceeds to S104 as it is.
  • the SSD controller 710 determines whether garbage collection is necessary (S104). Since the flash memory is a write-once storage medium, it is necessary to retain a certain amount of erased blocks for writing write data in the SSD. Garbage collection is a process for generating erased blocks. Specifically, the SSD controller 710 generates a block that holds only invalid pages by moving and consolidating the valid pages scattered in the block to another block, and erases the block. Then, a new erased block is generated. When the determination result in S104 indicates that garbage collection is required (S104: Yes), the SSD controller 710 executes garbage collection (S105) (detailed in FIG. 12). Thereafter, the process proceeds to S106. On the other hand, if the determination result in S104 indicates that garbage collection is not required (S104: No), the process proceeds directly to S106.
  • the SSD controller 710 determines whether there is a request to stop the device (SSD700) (S106). When there is an apparatus stop request (S106: Yes), the SSD controller 710 ends a series of processes. On the other hand, when the determination result in S106 is that there is no stop request (S106: No), the SSD controller 710 returns the process to S100 and continues the series of processes.
  • FIG. 9 is a sequence diagram showing an outline of S102 which is the data write process of the SSD controller.
  • the SSD controller 710 stores the write data received from the host device in the cache memory 716 (S200), and notifies the host device of the end of the write process (S201). Next, the SSD controller 710 determines the storage destination parity group when the write data has accumulated to some extent in the cache memory 716 or when a certain time has elapsed since the write data is stored in the cache memory 716, and performs parity operation on the data. Input to the circuit 718 to generate parity data. At this time, the SSD controller 710 updates the parity group management table 71640 (S202).
  • the SSD controller 710 stores data and parity in each page.
  • the SSD controller 710 instructs the FM controller 717 to write data and parity, and after incrementing the number of queuing commands in the FM command management table 71630 (S203), The process ends.
  • FIG. 10 is a sequence diagram showing an overview of S103, which is a data read process of the SSD controller.
  • the SSD controller 710 identifies the access destination page and die from the read command received from the host device (S300), and determines whether the access destination die is executing the erase command or not in the command type 7201 in the execution information 720. (S301). As a result of the determination in S301, when the access destination die is executing the erase command (S301: Yes), the SSD controller 710 refers to the estimated end time 7202 in the execution information 720 until the command being executed ends. It is determined whether it takes a long time (S302). The case requiring a long time is, for example, a case where a time of several ms or more is expected to be completed. Note that the threshold for determination may be set by the user in the SSD according to the intended use. As a result of the determination in S302, when it takes time until the end (S302: Yes), the SSD controller 710 executes the collection read (S303) (detailed in FIG. 11), and ends the series of processes.
  • the SSD The controller 710 performs normal read processing as it is (S304) and ends a series of processing. In S304, the SSD controller 710 instructs the FM controller 717 to read data, and increments the number of queuing commands in the FM command management table 71630.
  • FIG. 11 is a sequence diagram showing an overview of S303, which is the collection read process of the SSD controller.
  • the SSD controller 710 refers to the parity group management table 71640, and instructs the FM controller 717 to read data other than the read target data and parity from the stripe column to which the read target data belongs to the cache memory 716. It is issued to (S400). Note that a read request may be queued in the priority queue 7192 in order to execute this process quickly.
  • the SSD controller 710 increments the number of queuing commands in the FM command management table 71630.
  • the SSD controller 710 inputs the data and parity read to the cache memory 716 to the parity calculation circuit 718, and generates read target data (S401). After the generated read target data is sent to the host device (S402), the SSD controller 710 ends a series of processes.
  • FIG. 12 is a sequence diagram showing an overview of S105, which is the garbage collection process of the SSD controller.
  • the SSD controller 710 confirms whether there is an erasable block (S500). As a result of the determination in S500, if there is no erasable block (S500: No), the process proceeds to S501, and the SSD controller 710 performs a data movement process for generating an erasable block (S501). Thereafter, the process proceeds to S502. On the other hand, if it is determined in S500 that there is an erasable block (S500: Yes), the process proceeds directly to S502.
  • the SSD controller 710 checks whether the total queuing number of erase commands in the parity group to which the erase target block belongs is less than 1 by referring to the FM command management table 71630 (S502). As a result of the determination in S502, if it is determined that the total queuing number of erase commands is less than 1 (S502: Yes), the process proceeds to S503, and the SSD controller 710 sets the block erase command of the parity group to 1 (S503), and a series of processing ends.
  • FIG. 13 is a sequence diagram showing an outline of the task of the FM controller 717.
  • the FM controller 717 selects a die to be processed and checks whether a command is queued in the priority queue of the die (S600). As a result of the determination in S600, if the command is not queued in the priority queue (S600: No), the FM controller 717 checks whether the command is queued in the normal queue (S601). If the command is queued in the priority queue as a result of the determination in S600 (S600: Yes), or if the command is queued in the normal queue as a result of the determination in S601 (S601: Yes), The process proceeds to S602. In step S602, the FM controller 717 executes the queued command and updates the execution information 720.
  • the FM controller 717 registers the execution command type in the command type 7201 and registers the expected end time in the expected end time 7202 (S602). Thereafter, the process proceeds to S603. On the other hand, as a result of the determination in S601, if the command is not queued in the normal queue, the process proceeds to S603 as it is.
  • the FM controller 717 checks the presence / absence of a completed command (S603). If there is an end command as a result of the determination in S603 (S603: Yes), the FM controller 717 performs a command end notification to the SSD controller 710 and clears the execution information 720 (S604). The process proceeds to S605. On the other hand, if the result of determination in S603 is that there is no end command (S603: No), the process proceeds directly to S605. In S605, the FM controller 717 confirms the presence / absence of its own stop request (S605), and if there is a stop request (S605: Yes), the series of processing ends. On the other hand, if there is no request to stop the FM controller 717 in S605, the FM controller 717 selects the next processing target die (S606), returns to S600 as it is, and continues a series of processes.
  • Example 2 In the first embodiment, a case has been described in which the execution information of the FM controller 717 is referred to determine execution of normal reading or correction reading before the SSD controller 710 performs reading.
  • the SSD controller 710 queues a read request to the FM controller 717, a collision occurs if the FM controller 717 is already executing an erasing process on the read target die.
  • the SSD controller 710 switches to the collection read.
  • FIG. 14 is a sequence diagram showing an exchange between the SSD controller 710 and the FM controller 717 in the data read process of the SSD controller according to the second embodiment.
  • the SSD controller 710 identifies the access destination page and die (S700), and performs normal read processing as shown in S304 (S701). Thereafter, the process proceeds to S706.
  • the FM controller 717 receives the read request (S702)
  • the FM controller 717 determines whether the access destination die is executing the erase command and requires time to finish (S703). If the result of the determination in S703 is affirmative (S703: Yes), the FM controller 717 notifies the SSD controller 710 that a collision with the erase command has occurred (S704).
  • the FM controller 717 notifies the SSD controller 710 of queuing OK (S705).
  • the SSD controller 710 checks an answer to the command queuing to the FM controller 717 (S706).
  • the SSD controller 710 executes a collection read process (S707), and ends a series of processes.
  • the SSD controller 710 ends the series of processes as it is.
  • the SSD controller 710 performs control so that the number of erase commands queued in each parity group is 1 or less.
  • the control is realized by the function of the FM controller 717 will be described.
  • the FM controllers 717 work together to control the number of erase commands executed for each parity group to be 1 or less.
  • the SSD controller 710 has an effect that commands can be freely queued to the FM controller 717.
  • FIG. 15 is a diagram illustrating a configuration example of the FM controller 717 according to the third embodiment. The difference from the first and second embodiments is that an erasing execution flag 900 is provided (details will be described with reference to FIG. 16).
  • the erasure in progress flag 900 is used to share information as to which FM controller is executing an erasure command between FM controllers.
  • the FM controller 717 that intends to execute the erasing process refers to this flag to first determine whether another FM controller 717 is already executing the erasing process. If no other FM controller 717 is in the erasing process, the FM controller 717 starts the erasing process (at this time, the FM controller 717 sets the erasing execution flag 900), and the other FM controller 717 performs the erasing process. In the case of the medium, the FM controller 717 postpones the execution of the erasing process. Therefore, the erasing execution flag 900 is shared by all FM controllers 717.
  • FIG. 16 is a diagram showing a configuration example of the erasing execution flag 900.
  • the erasing execution flag 900 includes a parity group # 9001, a die # 9002, and FMC # 0 9003 to FMC # N 9006.
  • Parity group # 9001 is an identifier of a parity group.
  • the die # 9002 is an identifier of a die that constitutes the parity group.
  • FMC # 0 9003 to FMC # N 9006 indicate which FMC is currently executing an erase command. Specifically, an FMC having a value “0” indicates that an erase command is not being executed, and an FMC having a value “1” indicates that an erase command is being executed.
  • parity group # 800 indicates that FMC # 1 is currently executing an erase command
  • parity group # 801 indicates that no FMC is currently executing an erase command
  • parity group # 802 is FMC # 1. 0 indicates that an erase command is currently being executed.
  • FIG. 17 is a sequence diagram showing an outline of tasks of the FM controller 717 according to the third embodiment.
  • the FM controller 717 selects a die to be processed and checks whether a command is queued in the priority queue of the die (S800). If the command is not queued in the priority queue as a result of the determination in S800 (S800: No), the FM controller 717 checks whether the command is queued in the normal queue (S801). If the command is queued in the priority queue as a result of the determination in S600 (S800: Yes), or if the command is queued in the normal queue as a result of the determination in S801 (S801: Yes), The process proceeds to S802. In S802, the FM controller 717 determines whether the command is an erase command (S802).
  • the process proceeds to S803, and the FM controller 717 refers to the erase execution flag 900 to determine whether the erase command can be executed (S803). . If the FM controller 717 determines in S803 that the erase command can be executed, the execution flag of the erase execution flag 900 is set (the value is changed from “0” to “1”) (S804). , The process proceeds to S805. On the other hand, if the FM controller 717 determines in S803 that the erase command cannot be executed, the process proceeds to S806.
  • the FM controller 717 checks whether there is a completed command (S806). If the end command is present as a result of the determination in S806 (S806: Yes), the FM controller 717 determines whether the command is an erase command (S807). If the result of determination in S807 is that the command is an erase command (S807: Yes), the FM controller 717 drops the execution flag of the erase execution flag 900 (changes the value from “1” to “0”). ) (S808), the process proceeds to S810. If the result of the determination in S807 is that the command is not an erase command (S807: No), the FM controller 717 proceeds to S810, performs command completion notification to the SSD controller 710, and clears the execution information 720.
  • S810 the process proceeds to S809.
  • S806 the result of determination in S806 is that there is no end command
  • processing proceeds directly to S809.
  • S809 the presence or absence of a stop request from the FM controller 717 is confirmed (S809). If there is a stop request (S809: Yes), the FM controller 717 ends a series of processes. On the other hand, when there is no stop request of the FM controller 717 in S809 (S809: No), the FM controller 717 selects the next processing target die (S811), the process returns to S800 as it is, and a series of Continue processing.
  • the SSD controller 710 does not need to control the number of erase commands to be queued to the FM controller 717, so that commands can be queued freely regardless of the command type.
  • the third embodiment has an effect that the determination process of S502 can be skipped (the determination is uniformly Yes) in the sequence of FIG.
  • the target of collision avoidance is not limited to the erase command, but may be applied to a write command or the like.
  • the present invention may be applied to avoid collision between an I / O request from a higher-level device and an SSD internal process such as garbage collection.
  • garbage collection is an operation of reading mirrored data from the FM.
  • this invention is not limited to the above-mentioned Example, Various modifications are included.
  • the above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described. Further, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. Further, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.
  • Each of the above-described configurations, functions, processing units, processing means, and the like may be realized by hardware by designing a part or all of them with, for example, an integrated circuit.
  • Each of the above-described configurations, functions, and the like may be realized by software by interpreting and executing a program that realizes each function by the processor.
  • Information such as programs, tables, and files for realizing each function may be stored in a memory, a recording device such as a hard disk or SSD, or a recording medium such as an IC card, SD card, or DVD.
  • a recording device such as a hard disk or SSD
  • a recording medium such as an IC card, SD card, or DVD.
  • control lines and information lines indicate what is considered necessary for the explanation, and not all the control lines and information lines on the product are necessarily shown. Actually, it may be considered that almost all the components are connected to each other.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

Selon l'invention, un contrôleur SSD utilise une pluralité de mémoires flash dans une configuration RAID et peut générer, par collecte utilisant la parité, des données à lire si une mémoire flash spécifique ne peut pas lire des données de manière instantanée. Un contrôleur de mémoire flash a une interface pour notifier le contrôleur SSD d'informations d'exécution des informations concernant, par exemple, qui commande est en cours d'exécution par rapport à une mémoire flash. Le contrôleur SSD, lors de la réception d'une demande de lecture provenant d'un dispositif de niveau supérieur, se réfère aux informations d'exécution du contrôleur de mémoire flash qui commande une mémoire flash à lire, et, si la mémoire flash de la destination d'accès est en train d'exécuter une instruction individuelle nécessitant une période longue, par exemple, un processus d'effacement, exécute une lecture de collecte et envoie des données à lire au dispositif de niveau supérieur.
PCT/JP2014/075680 2014-09-26 2014-09-26 Dispositif de mémorisation WO2016046970A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2014/075680 WO2016046970A1 (fr) 2014-09-26 2014-09-26 Dispositif de mémorisation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2014/075680 WO2016046970A1 (fr) 2014-09-26 2014-09-26 Dispositif de mémorisation

Publications (1)

Publication Number Publication Date
WO2016046970A1 true WO2016046970A1 (fr) 2016-03-31

Family

ID=55580529

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2014/075680 WO2016046970A1 (fr) 2014-09-26 2014-09-26 Dispositif de mémorisation

Country Status (1)

Country Link
WO (1) WO2016046970A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107145311A (zh) * 2017-06-12 2017-09-08 郑州云海信息技术有限公司 一种io数据处理方法及系统
US10528464B2 (en) 2016-11-04 2020-01-07 Toshiba Memory Corporation Memory system and control method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11191037A (ja) * 1997-12-26 1999-07-13 Hitachi Ltd データ記憶装置
US7945752B1 (en) * 2008-03-27 2011-05-17 Netapp, Inc. Method and apparatus for achieving consistent read latency from an array of solid-state storage devices
US20130019057A1 (en) * 2011-07-15 2013-01-17 Violin Memory, Inc. Flash disk array and controller
JP2013200692A (ja) * 2012-03-23 2013-10-03 Toshiba Corp メモリシステム

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11191037A (ja) * 1997-12-26 1999-07-13 Hitachi Ltd データ記憶装置
US7945752B1 (en) * 2008-03-27 2011-05-17 Netapp, Inc. Method and apparatus for achieving consistent read latency from an array of solid-state storage devices
US20130019057A1 (en) * 2011-07-15 2013-01-17 Violin Memory, Inc. Flash disk array and controller
JP2013200692A (ja) * 2012-03-23 2013-10-03 Toshiba Corp メモリシステム

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10528464B2 (en) 2016-11-04 2020-01-07 Toshiba Memory Corporation Memory system and control method
CN107145311A (zh) * 2017-06-12 2017-09-08 郑州云海信息技术有限公司 一种io数据处理方法及系统
CN107145311B (zh) * 2017-06-12 2020-06-19 苏州浪潮智能科技有限公司 一种io数据处理方法及系统

Similar Documents

Publication Publication Date Title
US9652156B2 (en) Host read command return reordering based on time estimation of flash read command completion
CN108292196B (zh) 数据写入方法、装置和计算机可读存储介质
US10725865B2 (en) Storage unit and storage device
US8254172B1 (en) Wear leveling non-volatile semiconductor memory based on erase times and program times
US9021178B2 (en) High performance path for command processing
US8380922B1 (en) Data storage device comprising host interface state machine blocking on target logical block address
US11720283B2 (en) Coherent access to persistent memory region range
US20150081967A1 (en) Management of storage read requests
KR20140013098A (ko) 메모리 시스템 컨트롤러들을 포함하는 장치 및 관련 방법들
CN110895448B (zh) 用于管理存储器系统中的有效数据的设备和方法
KR20140012175A (ko) 메모리 시스템 제어기를 구비하는 장치 및 관련 방법
US10901626B1 (en) Storage device
US20120221771A1 (en) Data storage system and data mapping method of the same
JP2009163647A (ja) ディスクアレイ装置
JP5987498B2 (ja) ストレージ仮想化装置、ストレージ仮想化方法及びストレージ仮想化プログラム
US11269559B2 (en) Data processing device
US11163501B2 (en) Raid storage multi-step command system
US11023322B2 (en) Raid storage-device-assisted parity update data storage system
TWI786288B (zh) 儲存裝置、儲存裝置的控制方法及記錄媒體
US10592113B2 (en) Method for transferring command from host to device controller and system using the same
KR102366512B1 (ko) 논리 블록 어드레싱 범위 충돌 크롤러
WO2016046970A1 (fr) Dispositif de mémorisation
EP3166019B1 (fr) Dispositifs de mémoire et procédé
WO2015170702A1 (fr) Dispositif de stockage, système de traitement d'informations, procédé de commande de stockage et programme
US20110173372A1 (en) Method and apparatus for increasing file copy performance on solid state mass storage devices

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14902452

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 14902452

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP