WO2016042287A1 - Puf and address dependent data encryption - Google Patents

Puf and address dependent data encryption Download PDF

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Publication number
WO2016042287A1
WO2016042287A1 PCT/GB2015/052388 GB2015052388W WO2016042287A1 WO 2016042287 A1 WO2016042287 A1 WO 2016042287A1 GB 2015052388 W GB2015052388 W GB 2015052388W WO 2016042287 A1 WO2016042287 A1 WO 2016042287A1
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WIPO (PCT)
Prior art keywords
data
key
memory
circuitry
function
Prior art date
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Ceased
Application number
PCT/GB2015/052388
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French (fr)
Inventor
Vikas Chandra
Robert Campbell Aitken
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ARM Ltd
Original Assignee
ARM Ltd
Advanced Risc Machines Ltd
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Publication date
Application filed by ARM Ltd, Advanced Risc Machines Ltd filed Critical ARM Ltd
Priority to GB1701458.0A priority Critical patent/GB2544672B/en
Priority to CN201580048288.2A priority patent/CN106688027A/en
Publication of WO2016042287A1 publication Critical patent/WO2016042287A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1408—Protection against unauthorised use of memory or access to memory by using cryptography
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
    • G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09C—CIPHERING OR DECIPHERING APPARATUS FOR CRYPTOGRAPHIC OR OTHER PURPOSES INVOLVING THE NEED FOR SECRECY
    • G09C1/00—Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
    • H04L9/0861—Generation of secret information including derivation or calculation of cryptographic keys or passwords
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
    • H04L9/0861—Generation of secret information including derivation or calculation of cryptographic keys or passwords
    • H04L9/0866—Generation of secret information including derivation or calculation of cryptographic keys or passwords involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1052—Security improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/40—Specific encoding of data in memory or cache
    • G06F2212/402—Encrypted data
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12—Details relating to cryptographic hardware or logic circuitry
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/12—Transmitting and receiving encryption devices synchronised or initially set up in a particular manner

Definitions

  • This disclosure relates to the field of data processing systems. More particularly, this disclosure relates to the encryption of data within data processing systems.
  • apparatus comprising:
  • key generation circuitry to generate a key as a function of said address
  • encryption circuitry to encrypt said unencrypted data to form said encrypted data as a function of said key.
  • apparatus comprising:
  • memory means for storing encrypted data representing unencrypted data at a storage location specified by an address
  • key generation means for generating a key as a function of said address
  • encryption means for encrypting said unencrypted data to form said encrypted data as a function of said key.
  • the present disclosure provides a method comprising the steps of: storing encrypted data representing unencrypted data at a storage location specified by an address;
  • apparatus comprising:
  • key generation circuitry to generate a key as a function of said address
  • decryption circuitry to decrypt said encrypted data to form said unencrypted data as a function of said key.
  • apparatus comprising:
  • memory means for storing encrypted data representing unencrypted data at a storage location specified by an address
  • key generation means for generating a key as a function of said address
  • decryption means for decrypting said encrypted data to form said unencrypted data as a function of said key.
  • the present disclosure provides a method comprising the steps of:
  • Figure 1 schematically illustrates a data processing system
  • Figure 2 schematically illustrates a mechanism for encrypting unencrypted data upon data write
  • Figure 3 schematically illustrates a mechanism for decrypting encrypted data upon data read
  • Figure 4 schematically illustrates a mechanism for both encrypting and decrypting data
  • Figure 5 is a flow diagram schematically illustrating an encrypting write process
  • Figure 6 is a flow diagram schematically illustrating a decrypting read process.
  • At least example embodiments of the disclosure provide a low energy and secure mechanism for protecting data whereby the same data written to different addresses within a memory will be encrypted with different keys and accordingly highly likely have a different form. This provides resistance against attacks based upon data remnance as it renders it difficult to identify any particular data within the memory as the same data will highly likely be represented in different forms at different storage locations within the memory.
  • the key generation circuitry comprises physically unclonable function circuitry (PUF circuitry).
  • PAF circuitry physically unclonable function circuitry
  • the address may be used as a challenge input to the physically unclonable function circuitry and the key may be a response output from the physically unclonable function circuitry.
  • the variation from instance to instance of the physically unclonable function circuitry has the result that even if multiple different apparatuses are using the same secret data, the variation in the physically unclonable function circuitry between those different apparatuses will mean that the keys used for the same addresses in the different apparatuses will highly likely be different. Accordingly, such embodiments provide for different keys to be used for different addresses within the same device and for different keys to be used for the same addresses within different devices. This helps resist another form of attack whereby the attacker might seek to analyse multiple devices in order to identify common data at the same addresses within different devices.
  • the encryption circuitry may use the key in a variety of different ways, one particularly secure way in which the encryption circuitry may be configured is so as to perform one-time-pad encryption of the encrypted data using the key.
  • Such one-time- pad encryption in which any form of unencrypted data may be formed from any form of encrypted data by using a suitable key has the advantage that knowledge of the encrypted data will not assist in yielding any information regarding either the key or the unencrypted data.
  • Security may be improved within at least some embodiments in which the key has a character width greater than or equal to the character width of the unencrypted data.
  • the use of keys which are at least as wide as the unencrypted data they protect permits a higher degree of security.
  • the secret data in some circumstances is likely to be relatively short, it may generally be possible to provide a key which is at least as great in character width.
  • the above techniques are generally applicable in providing data security, they can be used with particular advantage to protect systems within which the memory has data remnance behaviour whereby data values stored within the memory induce physical changes within the memory which permit reconstruction of data erased from the memory. Examples of such memories include SRAM memory and DRAM memory.
  • a non-volatile memory is an extreme example of a memory which has data remnance as its nature is that it is intended to provide perfect data remnance.
  • aspects of the present disclosure comprise a mechanism for writing data to a memory in accordance with the present technique and mechanisms for reading data from a memory in accordance with the present techniques. These mechanisms may also be used in combination. Such embodiments may share the key generation circuitry in a manner which ensures that the same key is generated for encryption as for decryption when the same storage location within the memory is being addressed. Such encryption is turned symmetric encryption.
  • Figure 1 schematically illustrates a data processing system 2 in the form of a system-on- chip integrated circuit for use in an internet-of-things device.
  • Such data processing systems 2 typically have a limited energy supply and accordingly encryption and decryption mechanisms they use are required to meet strict energy requirements.
  • the data processing system 2 includes a processor core 4 for executing program instructions and performing data accesses to a memory 6 via encryption and decryption circuitry 8.
  • the data processing system 2 communicates with other data processing systems via input/output circuitry 10 and an antenna 12.
  • the memory 6 is a memory exhibiting data remnance behaviour, such as, for example, an SRAM memory, a DRAM memory or a non- volatile memory.
  • the processor core 4 executes program instructions and manipulates data which are stored within the memory 6.
  • the program instructions and the data stored within the memory 6 are transformed between an unencrypted form used by the processor core 4 and an encrypted form stored within the memory 6 via the encryption and decryption circuitry 8.
  • Figure 2 schematically illustrates a mechanism for transforming unencrypted data [u 3 i : u 0 ] in the form of 32-bit data words into encrypted data [e 31 :e 0 ].
  • An address comprising a 32-bit address [a 3 i:ao] is supplied as an address to an address input of the memory 6 as well as the input to key generation circuitry 12, which had the form of physically unclonable function circuitry.
  • the key generation circuitry 12 receives the address as a challenge input to the PUF circuitry and generates the key as a response output from the PUF circuitry.
  • the key is a 32-bit key [k 31 :ko].
  • the nature of the physically unclonable function circuitry 12 is such that different instances of this circuit 12 will have different forms such that the same address when applied as a challenge input to these different instances will highly likely generate a different response output. Such device-to-device variation is part of the security afforded by the use of the physically unclonable function circuitry.
  • An individual instance of the physical unclonable function circuitry will repeatedly generate the same response output from the same challenge input such that the key generated for a given address may be the same on both writing the data into the memory 6 and reading the data out of the memory 6. The key can thus be used to support symmetric encryption.
  • the key generated by the key generation circuitry 12 is supplied as one input to encryption circuitry 14 which performs a bitwise XOR operation upon the key and the unencrypted data so as to generate the encrypted data.
  • the encryption circuitry may comprise, for example, 32 parallel XOR gates.
  • the encrypted data which is output from the input circuitry 14 is written into the memory 6 at the address specified.
  • Figure 3 schematically illustrates a mechanism for reading encrypted data from the memory 6.
  • the address is applied to the same key generation circuitry 12 which was used when writing data into the memory 6, or at least key generation circuitry which will generate the same key value for the same address as the key generation circuitry which was used during the write operation.
  • the address is applied to the memory 6 and serves to read encrypted data from the storage location specified by the address.
  • the encrypted data is supplied as one input together with the key to decryption circuitry 16.
  • the decryption circuitry 16 performs a bitwise XOR operation, which may be implemented by 32 parallel XOR gates.
  • the output from the decryption circuitry is the unencrypted data.
  • Figure 4 schematically illustrates an embodiment employing both mechanisms for encrypting data and decrypting data which share the same encryption circuitry 12.
  • the encrypted data is applied upon writing to a write port of the memory 6.
  • the encrypted data is read from a read port of the memory 6 upon a read operation.
  • a signal r/w specifying whether a read or a write operation is being performed is supplied to the memory 6.
  • FIG. 5 is a flow diagram schematically illustrating an encrypting write process.
  • processing waits until there is data to write.
  • Step 20 serves to form a key using the physically unclonable function circuitry 12 and the address to which the write data is to be made as the challenge input to the physically unclonable function circuitry 12.
  • the key is the response output from the physically unclonable function circuitry 12.
  • the key and the unencrypted data forming the write are subject to a bitwise XOR operation to form the encrypted data.
  • the encrypted data is written into the storage location specified by the address which was used to form the key at step 20.
  • Figure 6 schematically illustrates a decrypting read process.
  • processing waits until there is a data read to perform.
  • the key for decrypting the read data is formed from the address specified for the read using the physically unclonable function circuitry 12.
  • the encrypted data is read from the storage location in the memory 6 specified by the address for the read.
  • the key formed at step 28 and the encrypted data read at step 30 are subject to a bitwise XOR operation to form the unencrypted data, which is then returned to service the data read.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Storage Device Security (AREA)

Abstract

Encryption of data within a memory (6) is provided by key generation circuitry (12) which serves to generate a key as a function of the address within the memory (6) being accessed and then encryption circuitry (14) or decryption circuitry (16) which serve respectively to encrypt or decrypt the data as a function of the key that has been generated based upon the address. The encryption and the decryption may be performed using a bitwise XOR operation. The key generation circuitry may have the form of physically unclonable function circuitry, which varies from instance to instance of implementation and that operates to generate the same key for the same address upon both write and read operations within the same instance.

Description

PUF AND ADDRESS DEPENDENT DATA ENCRYPTION
This disclosure relates to the field of data processing systems. More particularly, this disclosure relates to the encryption of data within data processing systems.
It is known to protect sensitive data, such as encryption key data, financial data and the like, using encryption mechanisms within data processing systems. An assumption often made within data processing systems in relation to the protection of data is that when that data is erased from a memory, then it will not be recoverable. For example, when power to a volatile memory is removed, the data within that memory is assumed to be erased. However, in practice there may be physical characteristics of the memory that allow erased data to be reconstructed. Data remnance poses a threat to systems that make this assumption, i.e. that data erased from a memory will not be recoverable.
Another potential problem with data encryption mechanisms is that these may consume a disadvantageous amount of energy when encrypting and decrypting data. For example, complex algorithms, such as RSA, can consume many hundreds of thousands of processing cycles to perform their encryption and decryption operations. Within systems with energy budget constraints, such as battery-operated internet-of things devices, the energy consumed by such encryption and decryption mechanisms is a disadvantage.
Viewed from one aspect the present disclosure provides apparatus comprising:
memory to store encrypted data representing unencrypted data at a storage location specified by an address;
key generation circuitry to generate a key as a function of said address;
encryption circuitry to encrypt said unencrypted data to form said encrypted data as a function of said key.
Viewed from another aspect the present disclosure provides apparatus comprising:
memory means for storing encrypted data representing unencrypted data at a storage location specified by an address;
key generation means for generating a key as a function of said address;
encryption means for encrypting said unencrypted data to form said encrypted data as a function of said key.
Viewed from another aspect the present disclosure provides a method comprising the steps of: storing encrypted data representing unencrypted data at a storage location specified by an address;
generating a key as a function of said address;
encrypting said unencrypted data to form said encrypted data as a function of said key.
Viewed from another aspect the present disclosure provides apparatus comprising:
memory to store encrypted data representing unencrypted data at a storage location specified by an address;
key generation circuitry to generate a key as a function of said address;
decryption circuitry to decrypt said encrypted data to form said unencrypted data as a function of said key.
Viewed from another aspect the present disclosure provides apparatus comprising:
memory means for storing encrypted data representing unencrypted data at a storage location specified by an address;
key generation means for generating a key as a function of said address;
decryption means for decrypting said encrypted data to form said unencrypted data as a function of said key.
Viewed from another aspect the present disclosure provides a method comprising the steps of:
storing encrypted data representing unencrypted data at a storage location specified by an address;
generating a key as a function of said address;
decrypting said encrypted data to form said unencrypted data as a function of said key.
Example embodiments will now be described, by way of example only, with reference to the accompanying drawings in which:
Figure 1 schematically illustrates a data processing system;
Figure 2 schematically illustrates a mechanism for encrypting unencrypted data upon data write;
Figure 3 schematically illustrates a mechanism for decrypting encrypted data upon data read;
Figure 4 schematically illustrates a mechanism for both encrypting and decrypting data; Figure 5 is a flow diagram schematically illustrating an encrypting write process; and
Figure 6 is a flow diagram schematically illustrating a decrypting read process.
At least example embodiments of the disclosure provide a low energy and secure mechanism for protecting data whereby the same data written to different addresses within a memory will be encrypted with different keys and accordingly highly likely have a different form. This provides resistance against attacks based upon data remnance as it renders it difficult to identify any particular data within the memory as the same data will highly likely be represented in different forms at different storage locations within the memory.
Security is further enhanced when the key generation circuitry comprises physically unclonable function circuitry (PUF circuitry). There are a variety of different possible forms for such physically unclonable function circuitry, as will be known to those in this technical field.
The address may be used as a challenge input to the physically unclonable function circuitry and the key may be a response output from the physically unclonable function circuitry. The variation from instance to instance of the physically unclonable function circuitry has the result that even if multiple different apparatuses are using the same secret data, the variation in the physically unclonable function circuitry between those different apparatuses will mean that the keys used for the same addresses in the different apparatuses will highly likely be different. Accordingly, such embodiments provide for different keys to be used for different addresses within the same device and for different keys to be used for the same addresses within different devices. This helps resist another form of attack whereby the attacker might seek to analyse multiple devices in order to identify common data at the same addresses within different devices.
While it will be appreciated that the encryption circuitry may use the key in a variety of different ways, one particularly secure way in which the encryption circuitry may be configured is so as to perform one-time-pad encryption of the encrypted data using the key. Such one-time- pad encryption in which any form of unencrypted data may be formed from any form of encrypted data by using a suitable key has the advantage that knowledge of the encrypted data will not assist in yielding any information regarding either the key or the unencrypted data.
Security may be improved within at least some embodiments in which the key has a character width greater than or equal to the character width of the unencrypted data. The use of keys which are at least as wide as the unencrypted data they protect permits a higher degree of security. In practice, as the secret data in some circumstances is likely to be relatively short, it may generally be possible to provide a key which is at least as great in character width. While the above techniques are generally applicable in providing data security, they can be used with particular advantage to protect systems within which the memory has data remnance behaviour whereby data values stored within the memory induce physical changes within the memory which permit reconstruction of data erased from the memory. Examples of such memories include SRAM memory and DRAM memory. A non-volatile memory is an extreme example of a memory which has data remnance as its nature is that it is intended to provide perfect data remnance.
It will be appreciated that different aspects of the present disclosure comprise a mechanism for writing data to a memory in accordance with the present technique and mechanisms for reading data from a memory in accordance with the present techniques. These mechanisms may also be used in combination. Such embodiments may share the key generation circuitry in a manner which ensures that the same key is generated for encryption as for decryption when the same storage location within the memory is being addressed. Such encryption is turned symmetric encryption.
Figure 1 schematically illustrates a data processing system 2 in the form of a system-on- chip integrated circuit for use in an internet-of-things device. Such data processing systems 2 typically have a limited energy supply and accordingly encryption and decryption mechanisms they use are required to meet strict energy requirements. The data processing system 2 includes a processor core 4 for executing program instructions and performing data accesses to a memory 6 via encryption and decryption circuitry 8. The data processing system 2 communicates with other data processing systems via input/output circuitry 10 and an antenna 12. The memory 6 is a memory exhibiting data remnance behaviour, such as, for example, an SRAM memory, a DRAM memory or a non- volatile memory.
In operation the processor core 4 executes program instructions and manipulates data which are stored within the memory 6. The program instructions and the data stored within the memory 6 are transformed between an unencrypted form used by the processor core 4 and an encrypted form stored within the memory 6 via the encryption and decryption circuitry 8.
Figure 2 schematically illustrates a mechanism for transforming unencrypted data [u3i:u0] in the form of 32-bit data words into encrypted data [e31:e0]. An address comprising a 32-bit address [a3i:ao] is supplied as an address to an address input of the memory 6 as well as the input to key generation circuitry 12, which had the form of physically unclonable function circuitry. There are a variety of different ways in which such physically unclonable function circuitry may be formed, e.g. a memory which boots to contain data dependent upon minor physical variations within the individual memory cells, data derived based upon the outcome of race conditions which vary with minor physical variations within the paths, and other examples. The key generation circuitry 12 receives the address as a challenge input to the PUF circuitry and generates the key as a response output from the PUF circuitry. The key is a 32-bit key [k31:ko].
The nature of the physically unclonable function circuitry 12 is such that different instances of this circuit 12 will have different forms such that the same address when applied as a challenge input to these different instances will highly likely generate a different response output. Such device-to-device variation is part of the security afforded by the use of the physically unclonable function circuitry. An individual instance of the physical unclonable function circuitry will repeatedly generate the same response output from the same challenge input such that the key generated for a given address may be the same on both writing the data into the memory 6 and reading the data out of the memory 6. The key can thus be used to support symmetric encryption.
As illustrated in Figure 2, the key generated by the key generation circuitry 12 is supplied as one input to encryption circuitry 14 which performs a bitwise XOR operation upon the key and the unencrypted data so as to generate the encrypted data. The encryption circuitry may comprise, for example, 32 parallel XOR gates. The encrypted data which is output from the input circuitry 14 is written into the memory 6 at the address specified.
Figure 3 schematically illustrates a mechanism for reading encrypted data from the memory 6. The address is applied to the same key generation circuitry 12 which was used when writing data into the memory 6, or at least key generation circuitry which will generate the same key value for the same address as the key generation circuitry which was used during the write operation. The address is applied to the memory 6 and serves to read encrypted data from the storage location specified by the address. The encrypted data is supplied as one input together with the key to decryption circuitry 16. The decryption circuitry 16 performs a bitwise XOR operation, which may be implemented by 32 parallel XOR gates. The output from the decryption circuitry is the unencrypted data.
Figure 4 schematically illustrates an embodiment employing both mechanisms for encrypting data and decrypting data which share the same encryption circuitry 12. The encrypted data is applied upon writing to a write port of the memory 6. The encrypted data is read from a read port of the memory 6 upon a read operation. A signal r/w specifying whether a read or a write operation is being performed is supplied to the memory 6.
As illustrated in Figure 4, the XOR operation performed in a bitwise fashion by the encryption circuitry 14 is reversed by the XOR operation performed by the decryption circuitry 16.
Figure 5 is a flow diagram schematically illustrating an encrypting write process. At step 18 processing waits until there is data to write. Step 20 serves to form a key using the physically unclonable function circuitry 12 and the address to which the write data is to be made as the challenge input to the physically unclonable function circuitry 12. The key is the response output from the physically unclonable function circuitry 12. At step 22, the key and the unencrypted data forming the write are subject to a bitwise XOR operation to form the encrypted data. At step 24 the encrypted data is written into the storage location specified by the address which was used to form the key at step 20.
Figure 6 schematically illustrates a decrypting read process. At step 26 processing waits until there is a data read to perform. At step 28 the key for decrypting the read data is formed from the address specified for the read using the physically unclonable function circuitry 12. At step 30 the encrypted data is read from the storage location in the memory 6 specified by the address for the read. At step 32 the key formed at step 28 and the encrypted data read at step 30 are subject to a bitwise XOR operation to form the unencrypted data, which is then returned to service the data read.
Although illustrative embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments, and that various changes, additions and modifications can be effected therein by one skilled in the art without departing from the scope and spirit of the invention as defined by the appended claims. For example, various combinations of the features of the dependent claims could be made with the features of the independent claims without departing from the scope of the present invention.

Claims

CLAIMS:
1. Apparatus comprising:
memory to store encrypted data representing unencrypted data at a storage location specified by an address;
key generation circuitry to generate a key as a function of said address;
encryption circuitry to encrypt said unencrypted data to form said encrypted data as a function of said key.
2. Apparatus as claimed in claim 1, wherein a given data value stored at different storage locations is encrypted using keys generated as a function of different respective addresses.
3. Apparatus as claimed in any one of claim 1 and 2, wherein key generation circuitry comprises physically unclonable function circuitry, wherein said address is a challenge input to said physically unclonable function circuitry and said key is a response output from said physically unclonable function circuitry.
4. Apparatus as claimed in any preceding claim, wherein said encryption circuitry has a configuration to perform one-time -pad encryption of said unencrypted data using said key.
5. Apparatus as claimed in any preceding claim, wherein said key has a character width greater than or equal to a character width of said unencrypted data.
6. Apparatus as claimed in any preceding claim, wherein said encryption circuitry has a configuration to perform a bitwise XOR of said unencrypted data with said key to form said encrypted data.
7. Apparatus as claimed in any preceding claim, wherein said memory has data remanence behaviour whereby data values stored within said memory induce physical changes within said memory to permit reconstruction of data erased from said memory.
8. Apparatus as claimed in claim 7, wherein said memory is one of: an SRAM memory;
a DRAM memory; and
a non- volatile memory.
9. A method comprising the steps of:
storing encrypted data representing unencrypted data at a storage location specified by an address;
generating a key as a function of said address;
encrypting said unencrypted data to form said encrypted data as a function of said key.
10. Apparatus comprising:
memory to store encrypted data representing unencrypted data at a storage location specified by an address;
key generation circuitry to generate a key as a function of said address;
decryption circuitry to decrypt said encrypted data to form said unencrypted data as a function of said key.
11. Apparatus as claimed in claim 10, wherein a given data value stored at different storage locations is encrypted using keys generated as a function of different respective addresses.
12. Apparatus as claimed in any one of claims 10 and 11, wherein key generation circuitry comprises physically unclonable function circuitry, wherein said address is a challenge input to said physically unclonable function circuitry and said key is a response output from said physically unclonable function circuitry.
13. Apparatus as claimed in any one of claims 10 to 12, wherein said decryption circuitry has a configuration to perform one-time-pad decryption of said encrypted data using said key.
14. Apparatus as claimed in any one of claims 10 to 13, wherein said key has a character width greater than or equal to a character width of said encrypted data.
15. Apparatus as claimed in any one of claims 10 to 14, wherein said decryption circuitry has a configuration to perform a bitwise XOR of said encrypted data with said key to form said unencrypted data.
16. Apparatus as claimed in any one of claims 10 to 15, wherein said memory has data remanence behaviour whereby data values stored within said memory induce physical changes within said memory to permit reconstruction of data erased from said memory.
17. Apparatus as claimed in claim 16, wherein said memory is one of:
an SRAM memory;
a DRAM memory; and
a non- volatile memory.
18. Apparatus as claimed in any one of claims 10 to 17, comprising encryption circuitry to encrypt said unencrypted data to form said encrypted data as a function of said key.
19. A method comprising the steps of:
storing encrypted data representing unencrypted data at a storage location specified by an address;
generating a key as a function of said address;
decrypting said encrypted data to form said unencrypted data as a function of said key.
PCT/GB2015/052388 2014-09-15 2015-08-17 Puf and address dependent data encryption Ceased WO2016042287A1 (en)

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