CN110611565B - Data processing system, method and electronic equipment - Google Patents
Data processing system, method and electronic equipment Download PDFInfo
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- CN110611565B CN110611565B CN201910724642.9A CN201910724642A CN110611565B CN 110611565 B CN110611565 B CN 110611565B CN 201910724642 A CN201910724642 A CN 201910724642A CN 110611565 B CN110611565 B CN 110611565B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
- H04L9/0861—Generation of secret information including derivation or calculation of cryptographic keys or passwords
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
- H04L9/3271—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response
- H04L9/3278—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response using physically unclonable functions [PUF]
Abstract
The application provides a data processing system, a data processing method and electronic equipment. The data processing system includes: data input end, data output end, key generating circuit, memory, encrypting circuit and decrypting circuit. The encryption circuit and the decryption circuit simultaneously reconstruct the logic mapping relation of the encryption circuit and the decryption circuit according to the same secret key generated by the secret key generation circuit, the encryption circuit encrypts data to be stored received by the data input end and stores the encrypted data in the memory, and the decryption circuit decrypts the encrypted data and outputs the decrypted data to the data output end. Because the encryption circuit can be reconstructed, different encryption circuits are generated according to different keys, so that different encryption modes are generated, data storage is safer, and compared with the prior art, the data storage safety of the chip of the Internet of things can be ensured.
Description
Technical Field
The present application relates to the field of chip data storage, and in particular, to a data processing system, method and electronic device.
Background
The internet of things will be the next "important productivity" for the rapid development of the world, and is another trillion-level market behind the relay communication network.
With the development of the internet of things technology, after popularization, the number of chips (sensors, electronic tags and matched interface devices) for animals, plants, machines and articles greatly exceeds the number of mobile phones, more and more devices are connected to the internet of things cloud platform, and data information reported to the internet of things cloud platform shows explosive growth, so that how to ensure the data storage safety of the internet of things chips is a technical problem to be solved urgently in the field.
Disclosure of Invention
The application aims to provide a data processing system, a data processing method and electronic equipment so as to ensure the data storage security of an Internet of things chip.
A first aspect of the present application provides a data processing system comprising:
a data input for receiving data to be stored;
a data output terminal for outputting the stored data;
a key generation circuit for generating a key;
a memory for storing data;
the input end of the encryption circuit is connected to the output end of the secret key generation circuit and the data input end, the output end of the encryption circuit is connected to the input end of the memory, and the encryption circuit is a reconfigurable circuit and is used for encrypting data to be stored;
the input end of the decryption circuit is connected to the output end of the secret key generation circuit and the output end of the memory, the output end of the decryption circuit is connected to the data output end, and the decryption circuit is a reconfigurable circuit and is used for decrypting encrypted data;
the encryption circuit and the decryption circuit simultaneously reconstruct the logic mapping relation of the encryption circuit and the decryption circuit according to the same secret key generated by the secret key generating circuit, the encryption circuit encrypts the data to be stored received by the data input end and stores the data in the memory, and the decryption circuit decrypts the encrypted data and outputs the decrypted data to the data output end.
In some embodiments of the present application, the key generation circuit employs a Physically Unclonable Function (PUF) circuit, and the key is PUF data.
In some embodiments of the present application, the means for simultaneously reconstructing the logical mapping relationship for the encryption circuit and the decryption circuit comprises at least one of:
performing XOR operation on the key and the current logical mapping relation data;
performing addition/subtraction operation by using the key and the current logical mapping relation data;
and mapping the current logical mapping relation data by using the key as a lookup table.
A second aspect of the present application provides a data processing method based on the data processing system in the first aspect, including:
according to the same key generated by the key generation circuit, simultaneously reconstructing the logical mapping relation of the encryption circuit and the decryption circuit to obtain a reconstructed encryption circuit and a reconstructed decryption circuit;
the data input end receives data to be stored;
the reconstruction encryption circuit encrypts the data to be stored and stores the data in a memory;
when the data is read, the reconstruction decryption circuit decrypts the encrypted data and outputs the decrypted data to the data output end.
In some embodiments of the present application, the key generation circuit employs a Physically Unclonable Function (PUF) circuit, and the key is PUF data.
In some embodiments of the application, the reconstructing the logical mapping relationship between the encryption circuit and the decryption circuit according to the same key generated by the key generation circuit to obtain a reconstructed encryption circuit and a reconstructed decryption circuit includes:
and performing exclusive-OR operation on the same key generated by the key generation circuit and the current logical mapping relation data of the encryption circuit and the decryption circuit respectively to obtain a reconstructed encryption circuit and a reconstructed decryption circuit.
In some embodiments of the present application, the reconstructing the logical mapping relationship between the encryption circuit and the decryption circuit according to the same key generated by the key generation circuit to obtain a reconstructed encryption circuit and a reconstructed decryption circuit includes:
and respectively carrying out addition/subtraction operation on the same secret key generated by the secret key generating circuit and the current logical mapping relation data of the encryption circuit and the decryption circuit to obtain a reconstructed encryption circuit and a reconstructed decryption circuit.
In some embodiments of the present application, the reconstructing the logical mapping relationship between the encryption circuit and the decryption circuit according to the same key generated by the key generation circuit to obtain a reconstructed encryption circuit and a reconstructed decryption circuit includes:
and respectively realizing the mapping of the current logic mapping relation data of the encryption circuit and the decryption circuit by taking the same key generated by the key generation circuit as a lookup table to obtain a reconstructed encryption circuit and a reconstructed decryption circuit.
A third aspect of the present application provides an electronic device comprising the data processing system of the first aspect described above.
Compared with the prior art, in the data processing system provided by the first aspect of the present application, the encryption circuit and the decryption circuit reconstruct the logical mapping relationship of the encryption circuit and the decryption circuit according to the same key generated by the key generation circuit, the encryption circuit encrypts the data to be stored received by the data input end and stores the encrypted data in the memory, and the decryption circuit decrypts the encrypted data and outputs the decrypted data to the data output end. Because the encryption circuit can be reconstructed, different encryption circuits are generated according to different keys, so that different encryption modes are generated, data storage is safer, and compared with the prior art, the data storage safety of the chip of the Internet of things can be ensured.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 illustrates a schematic diagram of a data processing system provided by some embodiments of the present application;
FIG. 2 illustrates a flow chart of a method of data processing provided by some embodiments of the present application;
fig. 3 illustrates a schematic diagram of an electronic device provided by some embodiments of the present application.
Description of the main elements
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50 |
| Data |
60 |
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10 |
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20 |
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30 |
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40 |
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
It is to be noted that, unless otherwise specified, technical or scientific terms used herein shall have the ordinary meaning as understood by those skilled in the art to which this application belongs.
In addition, the terms "first" and "second", etc. are used to distinguish different objects, rather than to describe a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
The embodiment of the application provides a data processing system, a data processing method based on the data processing system, and an electronic device using the data processing system, which are described below with reference to the accompanying drawings.
Referring to FIG. 1, a schematic diagram of a data processing system is shown, according to some embodiments of the present application.
As shown, the data processing system 100 includes: data input 50, data output 60, key generation circuit 10, memory 20, encryption circuit 30, decryption circuit 40.
The data input 50 is for receiving data to be stored. The data output 60 is used to output the stored data. The key generation circuit 10 is configured to generate a key, where the key is used for encrypting and decrypting data, and the key generation circuit 10 may be, for example, a PUF circuit, or may be another type of key generation circuit, which is not limited in this embodiment. The memory 20 is used to store encrypted data. The input end of the encryption circuit 30 is connected to the output end of the key generation circuit 10 and the data input end 50, the output end of the encryption circuit 30 is connected to the input end of the memory 20, the encryption circuit 30 is a reconfigurable circuit, the reconfigurable circuit is a circuit with a variable logic mapping relation, and the encryption circuit 30 is used for encrypting data to be stored. An input of the decryption circuit 40 is connected to an output of the key generation circuit 10 and an output of the memory 20, an output of the decryption circuit 40 is connected to the data output 60, the decryption circuit 40 is also a reconfigurable circuit, the decryption circuit 40 is for decrypting encrypted data.
It should be noted that the logic mapping relationship of the reconfigurable circuit is not fixed, and the logic mapping relationship of each chip using the reconfigurable circuit may not be the same.
The logic mapping relation between the 2-bit data a and the data b is used for explaining that the logic mapping relation of the reconfigurable circuit is not fixed, and the data a and the data b can have the following logic mapping relation through the reconfigurable circuit:
a＝00→b＝10
a＝01→b＝00
a＝10→b＝11
a＝11→b＝01
or:
a＝00→b＝11
a＝01→b＝10
a＝10→b＝01
a＝11→b＝00
or
a＝00→b＝01
a＝01→b＝00
a＝10→b＝11
a＝11→b＝10
Even more complex logical mappings.
Therefore, in this embodiment, the encryption circuit 30 and the decryption circuit 40 reconstruct their logical mapping relationships at the same time according to the same key generated by the key generation circuit 10, the encryption circuit 30 encrypts the data to be stored received by the data input end DataIn and stores the encrypted data in the memory 20, and the decryption circuit 40 decrypts the encrypted data and outputs the decrypted data to the data output end 60.
Compared with the prior art, in the data processing system provided in the embodiment of the present application, the encryption circuit and the decryption circuit reconstruct the logical mapping relationship of the encryption circuit and the decryption circuit according to the same key generated by the key generation circuit, the encryption circuit encrypts the data to be stored received by the data input terminal and stores the encrypted data in the memory, and the decryption circuit decrypts the encrypted data and outputs the decrypted data to the data output terminal. Because the encryption circuit can be reconstructed, different encryption circuits are generated according to different keys, so that different encryption modes are generated, data storage is safer, and compared with the prior art, the data storage safety of the chip of the Internet of things can be ensured.
A PUF (Physical Unclonable Function) circuit, which may be used to realize functions such as generation of a chip ID (Identification number), encryption/decryption, and protection of an IP (intellectual property) core.
Therefore, on the basis of the above embodiments, in other embodiments of the present application, the key generation circuit 10 may employ a physically unclonable function PUF circuit, and the key is PUF data.
In this embodiment, the PUF circuit generates PUF data, and configures the reconfigurable encryption circuit according to the PUF data to change the logic of the circuit, so as to encrypt and convert data input to the data input terminal 50, and the PUF data configures the reconfigurable decryption circuit at the same time to obtain recoverable data. Because the PUF secret key has extremely high security, the reconfigurable encryption circuit is reconfigured based on PUF data, and the security of the data processing system is further improved.
On the basis of the foregoing embodiments, in other embodiments of the present application, the manner of reconstructing the logical mapping relationship between the encryption circuit 30 and the decryption circuit 40 at the same time may include at least one of the following:
the first method is as follows: and performing XOR operation on the key and the current logical mapping relation data to obtain a reconstructed logical mapping relation in the conversion mode.
The second method comprises the following steps: and performing addition/subtraction operation on the key and the current logical mapping relation data to obtain a reconstructed logical mapping relation under the conversion mode.
The third method comprises the following steps: and mapping the current logical mapping relation data by taking the key as a lookup table to obtain a reconstructed logical mapping relation in the conversion mode.
In this embodiment, the logic mapping relationship of the reconfigurable circuit is configured, different operation modes can be selected, different conversion modes can be generated, and any one of the above operation modes or a combination of the above operation modes can be adopted.
In the above embodiment, a data processing system is provided, and based on the data processing system, the application also provides a data processing method. Referring to fig. 2, a flow chart of a data processing method provided in some embodiments of the present application is shown, the method including the following steps:
step S101: and simultaneously reconstructing the logic mapping relation of the encryption circuit and the decryption circuit according to the same key generated by the key generation circuit to obtain a reconstructed encryption circuit and a reconstructed decryption circuit.
Step S102: the data input end receives data to be stored.
Step S103: and the reconstruction encryption circuit encrypts the data to be stored and stores the data in a memory.
Step S104: when reading data, the reconstruction decryption circuit decrypts the encrypted data and outputs the decrypted data to the data output end.
In some embodiments of the present application, the key generation circuit employs a Physically Unclonable Function (PUF) circuit, and the key is PUF data.
In some embodiments of the present application, the step S101 may be implemented as: and performing exclusive-OR operation on the same key generated by the key generation circuit and the current logical mapping relation data of the encryption circuit and the decryption circuit respectively to obtain a reconstructed encryption circuit and a reconstructed decryption circuit.
In other embodiments of the present application, the step S101 may be implemented as: and respectively carrying out addition/subtraction operation on the same secret key generated by the secret key generating circuit and the current logical mapping relation data of the encryption circuit and the decryption circuit to obtain a reconstructed encryption circuit and a reconstructed decryption circuit.
In still other embodiments of the present application, the step S101 may be further implemented as: and respectively realizing the mapping of the current logic mapping relation data of the encryption circuit and the decryption circuit by taking the same key generated by the key generation circuit as a lookup table to obtain a reconstructed encryption circuit and a reconstructed decryption circuit.
The data processing method provided by the above embodiment of the present application and the data processing system provided by the embodiment of the present application have the same inventive concept and the same beneficial effects.
In the above embodiment, a data processing system is provided, and correspondingly, the present application also provides an electronic device, which may be a sensor, an electronic tag, or an electronic device for a client, and the data processing system 100 is used in the electronic device. Please refer to fig. 3, which illustrates a schematic diagram of an electronic device according to some embodiments of the present application.
The electronic device provided by the above embodiment of the present application and the data processing system provided by the embodiment of the present application have the same beneficial effects from the same inventive concept.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present disclosure, and the present disclosure should be construed as being covered by the claims and the specification.
Claims (7)
1. A data processing system, comprising:
a data input for receiving data to be stored;
a data output terminal for outputting the stored data;
a key generation circuit for generating a key;
a memory for storing data;
the input end of the encryption circuit is connected to the output end of the secret key generation circuit and the data input end, the output end of the encryption circuit is connected to the input end of the memory, and the encryption circuit is a reconfigurable circuit and is used for encrypting data to be stored;
the input end of the decryption circuit is connected to the output end of the secret key generation circuit and the output end of the memory, the output end of the decryption circuit is connected to the data output end, and the decryption circuit is a reconfigurable circuit and is used for decrypting encrypted data;
the encryption circuit and the decryption circuit simultaneously reconstruct the logic mapping relation of the encryption circuit and the decryption circuit according to the same key generated by the key generation circuit and the current logic mapping relation of the encryption circuit and the decryption circuit;
the encryption circuit encrypts data to be stored received by the data input end and stores the encrypted data in the memory, and the decryption circuit decrypts the encrypted data and outputs the decrypted data to the data output end;
the key generation circuit adopts a Physical Unclonable Function (PUF) circuit, and the key is PUF data.
2. The data processing system of claim 1, wherein the means for simultaneously reconstructing the logical mapping for the encryption circuit and the decryption circuit comprises at least one of:
performing XOR operation on the key and the current logical mapping relation data;
performing addition/subtraction operation by using the key and the current logical mapping relation data;
and mapping the current logical mapping relation data by using the key as a lookup table.
3. A data processing method based on the data processing system of any one of claims 1 to 2, comprising:
reconstructing the logic mapping relation of the encryption circuit according to the key generated by the key generation circuit and the current logic mapping relation of the encryption circuit to obtain a reconstructed encryption circuit;
reconstructing the logical mapping relation of the decryption circuit according to the same key and the current logical mapping relation of the decryption circuit to obtain a reconstructed decryption circuit;
the data input end receives data to be stored;
the reconstruction encryption circuit encrypts the data to be stored and stores the data in a memory;
when the data is read, the reconstruction decryption circuit decrypts the encrypted data and outputs the decrypted data to the data output end;
the key generation circuit adopts a Physical Unclonable Function (PUF) circuit, and the key is PUF data.
4. The data processing method of claim 3, wherein reconstructing the logical mapping relationship between the encryption circuit and the decryption circuit according to the same key generated by the key generation circuit to obtain the reconstructed encryption circuit and the reconstructed decryption circuit comprises:
and performing exclusive-OR operation on the same key generated by the key generation circuit and the current logical mapping relation data of the encryption circuit and the decryption circuit respectively to obtain a reconstructed encryption circuit and a reconstructed decryption circuit.
5. The data processing method of claim 3, wherein reconstructing the logical mapping relationship between the encryption circuit and the decryption circuit according to the same key generated by the key generation circuit to obtain the reconstructed encryption circuit and the reconstructed decryption circuit comprises:
and respectively carrying out addition/subtraction operation on the same secret key generated by the secret key generating circuit and the current logical mapping relation data of the encryption circuit and the decryption circuit to obtain a reconstructed encryption circuit and a reconstructed decryption circuit.
6. The data processing method of claim 3, wherein reconstructing the logical mapping relationship between the encryption circuit and the decryption circuit according to the same key generated by the key generation circuit to obtain the reconstructed encryption circuit and the reconstructed decryption circuit comprises:
and respectively realizing the mapping of the current logic mapping relation data of the encryption circuit and the decryption circuit by taking the same key generated by the key generation circuit as a lookup table to obtain a reconstructed encryption circuit and a reconstructed decryption circuit.
7. An electronic device, characterized in that it comprises a data processing system according to any one of claims 1 to 2.
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| CN201910724642.9A CN110611565B (en) | 2019-08-07 | 2019-08-07 | Data processing system, method and electronic equipment |
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| CN201910724642.9A CN110611565B (en) | 2019-08-07 | 2019-08-07 | Data processing system, method and electronic equipment |
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| WO2005029765A1 (en) * | 2003-09-19 | 2005-03-31 | Sony Corporation | Transmitting apparatus, receiving apparatus, and data transmitting system |
| CN1635731A (en) * | 2003-12-27 | 2005-07-06 | 海信集团有限公司 | Reconfigurable password coprocessor circuit |
| CN1710955A (en) * | 2004-06-18 | 2005-12-21 | 罗姆股份有限公司 | Apparatus key protection method, enciphering and deciphering apparatus and video transmitting receiving apparatus |
| CN101116081A (en) * | 2005-02-11 | 2008-01-30 | 通用数据保护公司 | Method and system for microprocessor data security |
| CN101646167A (en) * | 2009-09-04 | 2010-02-10 | 西安电子科技大学 | Wireless network-accessing intelligent terminal and data processing method thereof |
| US9483664B2 (en) * | 2014-09-15 | 2016-11-01 | Arm Limited | Address dependent data encryption |
| KR102201642B1 (en) * | 2014-11-28 | 2021-01-13 | 삼성전자주식회사 | Physically unclonable function circuit and key enrolling method thereof |
| CN106707139B (en) * | 2017-01-03 | 2019-06-04 | 大唐微电子技术有限公司 | A kind of testing scanning chain device and implementation method |
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