WO2016036892A1 - Métallisation de cellule solaire à double niveau possédant des barres omnibus métalliques de premier niveau - Google Patents

Métallisation de cellule solaire à double niveau possédant des barres omnibus métalliques de premier niveau Download PDF

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Publication number
WO2016036892A1
WO2016036892A1 PCT/US2015/048211 US2015048211W WO2016036892A1 WO 2016036892 A1 WO2016036892 A1 WO 2016036892A1 US 2015048211 W US2015048211 W US 2015048211W WO 2016036892 A1 WO2016036892 A1 WO 2016036892A1
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Prior art keywords
level metal
emitter
base
level
fingers
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PCT/US2015/048211
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English (en)
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Pawan Kapur
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Solexel, Inc.
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Publication of WO2016036892A1 publication Critical patent/WO2016036892A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H01L31/0682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells

Definitions

  • the present disclosure relates in general to the fields of solar photovoltaic (PV) cells, and more particularly solar cell metallization.
  • PV solar photovoltaic
  • Efficient solar cell metallization requires base metallization contacting base regions of the solar cell and base busbar(s) collecting current from the base metallization as well as emitter metallization contacting emitter regions of the solar cell and emitter busbar(s) collecting current from the emitter metallization.
  • These basic metallization structures are applicable to various types of front and back contact solar cells including front and back junction back contact solar cells.
  • multi-level solar cell metallization structures often rely on conductive vias/posts/paths for electrical connection between metallization layers.
  • the required conductive current paths from the cell base and emitter metallization to the second level metallization may impose current collection restrictions and constraints in the cell.
  • numerous conductive paths between metallization layers may result in solar cell fabrication throughput reduction as well as solar cell metallization structure constraints.
  • an interdigitated back contact solar cell is provided which substantially eliminates or reduces disadvantages and deficiencies associated with previously developed interdigitated back contact solar cells and metallization structures.
  • An interdigitated back contact solar cell comprises a solar cell substrate having a light receiving frontside and a backside comprising base and emitter regions.
  • a first level metal (Ml) is positioned on the substrate backside contacting the base and emitter regions.
  • the first level metal (Ml) has an interdigitated pattern of base and emitter busbars.
  • Each first level metal (Ml) base busbar has a plurality of base fingers and each first level metal (Ml) emitter busbar has a plurality of emitter fingers.
  • a second level metal (M2) layer is connected to the first level metal (Ml) layer.
  • the second level metal (M2) has an interdigitated pattern of second level metal (M2) base fingers parallel and connected to the first level metal (Ml) base busbars and second level metal (M2) emitter fingers parallel and connected to the first level metal (Ml) emitter busbars. At least one second level metal (M2) base busbar is connected to the second level metal (M2) base fingers and at least one second level metal (M2) emitter busbar is connected to the second level metal (M2) emitter fingers.
  • Fig. 1 is a top view diagram the backside of a back contact solar cell showing a first level metal Ml;
  • Fig. 2 is a top view diagram the backside of a back contact solar cell showing a second level metal M2 corresponding to the first level metal Ml of Fig. 1;
  • Figs. 3A through 3C are top view diagrams of the backside of a back contact solar cell showing the first level metal Ml of Fig. 1 with alternative Ml to M2 connection embodiments for the second level metal of Fig. 2;
  • Fig. 4 is a selected cross-sectional diagrams along axis A' of Fig. 2, showing a back contact back junction dual-level metallization and backplane solar cell architecture;
  • Fig. 5 is a representative backplane-attached solar cell manufacturing process flow based on epitaxial silicon and porous silicon lift-off processing
  • Fig. 6 is a representative solar cell and module fabrication process flow using starting crystalline (mono-crystalline or multi-crystalline) silicon wafers.
  • the present application provides an efficient and comprehensive solar cell current collection solution having substantially improved fabrication advantages.
  • the novel solar cell and metallization structures described herein utilize a multi-layer metallization structure, such as a two-level metallization structure, comprising an on-cell base and emitter metallization first level metal (Ml) and a second level metal (M2) collecting power from the first level metal.
  • the second level metal (M2) may comprise an interdigitated pattern of base and emitter current collection fingers, base and emitter busbars, and also provide cell to cell (or sub-cell to sub-cell) interconnection.
  • the first level metal (Ml) comprises an interdigitated back contact metallization structure having an interdigitated pattern of first level metal (Ml) base and emitter busbars with each first level metal (Ml) base busbars having a plurality of orthogonal (perpendicular) first level metal (Ml) base fingers and each of first level metal (Ml) emitter busbars having a plurality of orthogonal (perpendicular) first level metal (Ml) emitter fingers such that the first level metal (Ml) base fingers interdigitate with the first level metal (Ml) emitter fingers.
  • the first level metal (Ml) base busbars are positioned underneath second level metal (M2) base fingers and the first level metal (Ml) emitter busbars are positioned underneath second level metal (M2) emitter fingers - or in other words the M2 base and emitter fingers cover the Ml base and emitter busbars, respectively.
  • This solution reduces and/or relaxes first level metal (Ml) to second level metal (M2) connection (i.e., electrical contact) requirements.
  • Ml may comprise parallel interdigitated base and emitter lines collecting solar cell absorber power and M2 may provide solar cell electrical connection and provide connection between Ml base and emitter lines.
  • the metal layers in the disclosed multi-level metal designs may be separated by a dielectric such as a resin/fiber based prepreg material.
  • interconnection structures include conductive epoxy posts or in the case of an insulating layer (e.g., an insulating dielectric layer such as prepreg) positioned between Ml and M2 conductive material filled vias through the insulating layer.
  • an insulating layer e.g., an insulating dielectric layer such as prepreg
  • a dual level solar cell metallization structure for a back contact back junction solar cell may provide several advantages, such as: allowing for a thinner metal in contact with the silicon (e.g., first level metal M2) as the dual-level metallization eliminates or reduces stresses of the otherwise thick metallization needed for a back contacted back junction solar cell.
  • Thinner metallization in contact with semiconductors absorbers e.g., silicon
  • semiconductors absorbers e.g., silicon
  • reduced metal to silicon stress effects e.g., mechanical stress effects of thicker metallization, thermal stress effects of coefficient of thermal expansion mismatch between metals and semiconductors
  • Metal stress effects reduction, and particularly metal on silicon stress effects reduction improve the manufacturability of solar cells by improving fabrication yield through reducing breaking and cracking of semiconductor absorbers due to metal stress - an advantage emphasized with respect to thinner absorbers.
  • a dual-level back contact back junction metallization structure may avoid busbar induced electrical shading. Additionally, a dual-level back contact back junction metallization structure may provide a path for dry metallization fabrication by allowing for higher resistance first level metal level Ml formation methods, such as screen paste aluminum Al metal, because the current needs to be carried by first level metal Ml only for a relatively short distance before it is pulled up to wider second level metal M2.
  • first level metal level Ml formation methods such as screen paste aluminum Al metal
  • the dual level back contact back junction solar cell metallization structure may be particularly advantageous having a dielectric between the first and second level metals as a mechanical support, in the case of manufacturing thin crystalline silicon solar cells (e.g., having a semiconductor absorber thickness in the range of approximately 5m to 100 ⁇ ).
  • a significant cost of a dual level metallization and backplane scheme is already absorbed in the mechanical support carrier attribute of the interlayer dielectric.
  • Structures and methods relating to backplane supported back contact back junction solar cells having dual-level metallization may be found in U.S. Pat. Pub.
  • a requirement for dual level metallization is a first level metallization to second level metallization connection, such as conductive vias through an electrically insulating backplane connecting a first level metal Ml to a second level metal M2.
  • First level metal Ml to second level metal M2 connection described herein in the context of vias through an electrically insulating backplane, is dictated by, in combination with conductivity requirements, first level metal interdigitated finger pitch and second level metal interdigitated finger pitch.
  • Additional dual level metallization structure considerations relate to cell edge current collection. Dual level metallization structures having first level metal Ml lines running in a perpendicular direction (on the same level) to the primary direction of first level metal Ml lines at the edge of the cell are described in U.S.
  • an orthogonal dual level metallization structure may require a via on every first level metal Ml line for each orthogonal (perpendicular) second level metal M2 line.
  • each via hole landing may have a landing pad on first level metal Ml larger than the size of the via itself and made up of metal paste which stops the via drill.
  • the landing pad may be slightly larger than the size than the size of the via itself which results in tight alignment tolerances and a risk of shunting due to
  • each base and emitter line may have several M1/M2 connections (e.g., conductive vias through an electrically insulating backplane) to transport the current upwards towards the second level metal M2.
  • M1/M2 connections e.g., conductive vias through an electrically insulating backplane
  • the spacing of the M1/M2 connections (e.g., conductive vias through an electrically insulating backplane) in the direction along the line is limited by the metal resistance, while the M1/M2 connection (e.g., conductive vias through an electrically insulating backplane) spacing perpendicular the first level metal Ml is limited by the design (e.g., the base and emitter line pitch).
  • lasers may be used in creating solar cell diffusions which correspond to the first level metal Ml pattern (e.g., an interdigitated pattern of base and emitter diffusion regions corresponding to an interdigitated pattern of first level metal Ml base and emitter fingers).
  • first level metal Ml pattern e.g., an interdigitated pattern of base and emitter diffusion regions corresponding to an interdigitated pattern of first level metal Ml base and emitter fingers.
  • the laser e.g., pico-second laser
  • second level metal M2 thickness may be required to substantial to ensure there are no or minimal resistive losses.
  • the present application provides an efficient and comprehensive solar cell current collection solution addressing the previously described first level metal Ml inefficiencies including increasing fabrication throughput by reducing/relaxing constraints on the number of M1/M2 connections (e.g., conductive vias through a backplane) required - in other words, less M1/M2 connections (e.g., conductive vias through a backplane) may increase fabrication throughput.
  • M1/M2 connections e.g., conductive vias through a backplane
  • the number of required M1/M2 connections e.g., conductive vias through a backplane
  • the number of required M1/M2 connections is independent of the pitch of first level metal Ml base and emitter fingers.
  • Fig. 1 is a top view diagram the backside of a back contact solar cell showing a first level metal Ml referred to herein as a fishbone metallization.
  • Fig. 1 is a drawing of the backside of a back contact back junction solar cell 10 showing a first level metal Ml base and emitter metallization pattern. The first level metal base and emitter
  • Fishbone first level metal Ml pattern comprises an interdigitated pattern of base busbars 12 with corresponding orthogonal base fingers 14 and emitter busbars 16 with corresponding orthogonal emitter fingers 18 patterned over the backside of the back contact solar cell for majority and minority carrier collection (metallization patterns not shown to scale, for example pattern pitch and metallization busbar and finger width).
  • the first level metal Ml structure provided herein may be referred to as a fishbone as descriptive reference (i.e., a first level metal Ml busbar is the fish backbone and the first level metal Ml busbars corresponding first level metal Ml fingers are the protruding fishbones).
  • First level metal Ml orthogonal base fingers 14 and orthogonal emitter fingers 18 may have the pitch and dimensions as a first level metal Ml without first level metal busbars (i.e., a non-fishbone first level metal Ml).
  • First level metal Ml interdigitated busbars e.g., base busbars 12 and emitter busbars 16
  • M1/M2 connection e.g., conductive vias
  • first level metal Ml busbar width should be sufficient to act as a landing for conductive vias as described herein.
  • first level metal Ml may have many busbars (e.g., ten first level metal Ml busbars per 156 by 156 mm solar cell or master cell).
  • Fig. 2 is a top view diagram the backside of a back contact solar cell showing a second level metal M2 corresponding to the first level metal Ml of Fig. 1.
  • Fig. 2 is a drawing of the backside of a back contact back junction solar cell 10 showing a second level metal M2 base and emitter metallization pattern.
  • Second level metal M2 pattern comprises an interdigitated pattern of base busbar 22 with corresponding orthogonal base fingers 24 and emitter busbar 26 with corresponding orthogonal emitter fingers 28 patterned over (i.e., overlying) the first level metal Ml of Fig. 1.
  • Second level metal base fingers 24 are positioned on an electrically insulating backplane (not shown) and over and parallel to first level metal base busbars 12.
  • Second level metal emitter fingers 28 are positioned on an electrically insulating backplane (not shown) and over and parallel to first level metal emitter busbars 16.
  • Conductive vias conductive vias are under second level metal M2 fingers and not shown in Fig. 2) through the electrically insulating backplane (backplane not shown in Fig.
  • second level metal Ml of Fig. 1 has four fingers (two base fingers 24 and two emitter fingers 28), importantly and in fabrication more realistically, and dependent on considerations such as solar cell absorber resistivity and metal conductivity, second level metal M2 may have many fingers corresponding to the first level metal busbars (e.g., ten second level metal M2 fingers corresponding to ten first level metal Ml busbars per 156 by 156 mm solar cell or master cell).
  • Figs. 3A through 3C are top view diagrams of the backside of a back contact solar cell showing the first level metal Ml of Fig. 1 with alternative Ml to M2 connection (e.g., conductive vias through an electrically insulating backplane) embodiments for the second level metal of Fig. 2.
  • Ml to M2 connection e.g., conductive vias through an electrically insulating backplane
  • conductive vias 30 connect a first level metal Ml to a second level metal M2 (overlying second level metal M2 not shown in Figs. 3A through 3C).
  • conductive vias 30 connect second level metal base fingers 24 to corresponding first level metal base busbars 12 and connect second level metal emitter fingers 28 to corresponding first level metal emitter busbars 16.
  • Fig. 3 A shows an M1/M2 connection embodiment having two conductive vias per first level metal Ml busbar (note vias are positioned at the ends of corresponding second level metal M2 fingers).
  • Fig. 3B shows an M1/M2 connection embodiment having three conductive vias per first level metal Ml busbar.
  • Fig. 3C shows an M1/M2 connection embodiment having six conductive vias per first level metal Ml busbar (note vias are positioned between first level metal fingers).
  • a conductive via may correspond to each first level metal Ml finger or first level metal finger pair on each side of the corresponding first level metal Ml busbar). Note that there is at least one conductive via per first level metal Ml busbar to transfer current to the corresponding second level metal M2 finger. It may be advantageous to position one M1/M2 connection (e.g., conductive vias through a backplane) per first level metal Ml finger or first level metal Ml finger set (e.g., per first level metal Ml finger set shown in Fig. 3A).
  • M1/M2 connection e.g., conductive vias through a backplane
  • the vias may have a diameter of approximately 200 ⁇ and the number of vias may be larger and correspond to the number of first level metal Ml fingers (e.g., twenty to thirty vias per first level metal Ml busbar per 156 by 156 mm solar cell or master cell, in other words vias positioned corresponding to the first level metal Ml base and emitter fingers and approximately 1 to 4 mm apart).
  • first level metal Ml has base and emitter busbars perpendicular to the interdigitated base and emitter fingers.
  • the corresponding solar cell absorber base and emitter diffusions e.g., base and emitter diffusion regions formed by laser patterning of field oxide and corresponding dopant deposition and diffusion in the absorber may
  • first level metal Ml fingers correspond (i.e., run underneath) the first level metal Ml fingers (e.g., shown as base fingers 14 and emitter fingers 18 in Fig. 1) and may not necessarily have to correspond (i.e. run underneath) the first level metal Ml busbar (e.g., shown as base busbar 12 and emitter busbar 16 in Fig. 1).
  • first level metal Ml busbars may run on the field oxide without any contact to underlying semiconductor absorber (e.g., silicon).
  • the novel solar cell and metallization structures described herein utilize a multilayer metallization structure, such as a two-level metallization structure, comprising a base and emitter metallization first level metal (Ml) and a second level metal (M2) collecting power from the first level metal.
  • Second level metal M2 fingers (not shown in Fig. 1) run parallel to first level metal Ml busbars at a different level above (i.e., on) an interlevel M1/M2 dielectric (e.g., a backplane and carrier structure for thin silicon, for example prepreg).
  • First level metal Ml connects to second level metal M2 through via holes in the interlevel dielectric/electrical insulator, referred to herein as a backplane.
  • the solar cell current is pulled up to second level metal M2 using conductive vias through a backplane to the first level metal Ml busbars.
  • the dual level metallization solution creates first level metal Ml busbars and lands (positions) the vias only on the first level metal Ml busbars.
  • the first level metal Ml has alternate busbars of emitter and base and fingers of the opposite polarity interrupted for and attached to the busbars depending on polarity.
  • the width of the busbars, which dictates the interdigitated first level metal Ml finger interruption extent, may be carefully design to balance the tradeoff between series resistance of the carriers in the semiconductor absorber (e.g., silicon) because of the interruption and the series resistance of the first level metal Ml busbar, which dictates the extent of via spacing on the busbar.
  • the metallization patterns not shown to scale for example the pitch between metallization fingers, pitch between metallization busbars, pitch between metallization fingers and busbars, as well as the size in terms of width, length, and height, of the busbars and fingers may be adjusted dependent on, for example, semiconductor material and solar cell efficiency qualities as well as metallization material and conductivity properties.
  • Design considerations for the dual level metallization structure include, for example, the length of the first level metal Ml finger or the spacing between the first level metal Ml busbars may be dictated by the resistance of the first level metal Ml metal (e.g., aluminum, copper, silver) and should be such that the resistive losses in the fingers does not compromise the fill factor of the solar cell. Thus, in consideration with design factors, the better the conductivity of the metal material the larger the spacing between the metal busbars may be. Additionally, the width of the first level metal Ml busbar may balance between the resistance of the semiconductor material (e.g., silicon) and the first level metal Ml busbar.
  • the semiconductor material e.g., silicon
  • a larger width may provide less resistance of the first level metal Ml busbar which may allow the vias to be spaced further apart on the first level metal Ml busbar - but may also increase the interruption in the fingers of the opposite polarity, hence the series resistance of the carriers in the semiconductor absorber (e.g., silicon) becomes larger.
  • the semiconductor absorber e.g., silicon
  • an optimal busbar width which has minimal to no impact on the fill factor may be utilized.
  • the two-level metallization back contact back junction solar cell structures provided have a first level metal Ml with several busbars which minimizes the length of the fingers and thus also allows for a thinner first level metal Ml .
  • Solar cell current is pulled up to second level metal M2 at every first level metal Ml busbar.
  • first level metal Ml busbars runs parallel to and under the second level metal M2 fingers (fingers sometimes referred to as metal lines herein).
  • This two-level metallization solution may eliminate known inefficiencies of alternative dual level metallization.
  • the two-level metallization solutions provided may substantially dramatically reduce the number of Ml to M2 connections (e.g., via holes) and increase the throughput processing (e.g., increase via drill processing throughput).
  • the M1/M2 connection spacing (e.g., conductive vias through a backplane) is dictated by the resistance of the first level metal Ml (i.e., a higher conductivity of metal affords larger spacing of connections, for example vias) and the perpendicular direction M1/M2 connection (e.g., conductive vias through a backplane) pitch was entirely dictated by the finger pitch of first level metal Ml .
  • the M1/M2 connection e.g., conductive vias through a backplane spacing in the direction perpendicular to the first level metal Ml fingers is not constrained by the pitch of the first level metal Ml fingers, but by the conductivity of metal 1.
  • first level metal Ml pitch substantially increases or relaxes the pitch requirements of the first level metal Ml fingers.
  • a first level metal Ml pitch limited by semiconductor absorber (e.g., silicon) resistance considerations, may be approximately lmm.
  • the two-level metallization solutions provided having first level metal Ml busbars provide a substantially larger first level metal Ml fingers pitch, for example in the range of approximately 3 to 4 mm or more depending upon the conductivity, which may substantially reduce the required number of M1/M2 connections (e.g., conductive vias through a backplane). Additionally, the two-level metallization solutions provided may relax the alignment tightness of the M1/M2 connections (e.g., conductive vias through a backplane and corresponding via landing pads).
  • the vias may now land on the relatively wide first level metal M2 busbars - thus making the process dramatically more manufacturable.
  • first level metal Ml busbars running in the perpendicular direction to the first level metal Ml fingers the motivation for solar cell absorber edge collection is relaxed.
  • the perpendicular first level metal Ml busbars do not need diffusions and connections to the semiconductor (e.g., silicon) underneath and may be run over an insulator (e.g., oxide layer).
  • base and emitter diffusion lines may run in one direction (i.e., in the direction corresponding to first level metal Ml interdigitated fingers) and may substantially increase the throughput of the contact open processes (e.g., contact open processes utilizing laser ablation, for example a pico-second laser).
  • first level metal Ml busbars runs parallel to the second level metal M2 fingers with a series of connections (e.g., conductive vias through a backplane) connecting first level metal Ml and first level metal M2, the current in this direction is shared between the two metals (i.e., the first level metal Ml busbar and the
  • Fig. 4 is a selected cross-sectional diagrams along axis A' of Fig. 2, showing a back contact back junction dual-level metallization and backplane solar cell architecture in accordance with the disclosed subject matter.
  • Fig. 4 is a cross-sectional diagram along A' axis and showing second level metal M2 emitter finger 28 connection to first level metal Ml emitter busbar 16 (shown as the patterned Ml contacting the doped emitter contact in Fig. 4) and second level metal M2 base finger 24 connection to first level metal Ml base busbar 12 (shown as the patterned Ml contacting the doped base contact in Fig. 4) by conductive vias through backplane.
  • trench-partitioned isled solar cells are provided. Structures and methods for forming isled solar cells having integrated backplane supported dual level metallization structure referred to as an iCell may be found in related U.S. Patent Pub. 2014/0370650 published Dec. 18, 2014, which is hereby incorporated by reference in its entirety.
  • Fig. 5 is a representative backplane-attached icell manufacturing process flow based on epitaxial silicon and porous silicon lift-off processing. This process flow is for fabrication of backplane-attached, back-contact / back-junction solar cells (icells) using two patterned layers of solar cell metallization (Ml and M2).
  • This example is shown for a solar cell with selective emitter, i.e., a main patterned field emitter with lighter emitter doping formed using a lighter boron-doped silicate glass (first BSG layer with smaller boron doping deposited by Tool 3), and more heavily-boron-doped emitter contact regions using a more heavily boron-doped silicate glass (second BSG layer with larger boron doping deposited by Tool 5).
  • first BSG layer with smaller boron doping deposited by Tool 3 lighter boron-doped silicate glass
  • second BSG layer with larger boron doping deposited by Tool 5 more heavily-boron-doped silicate glass
  • the icell designs are applicable to a wide range of other solar cell structures and process flows, including but not limited to the IBC solar cells without selective emitter (i.e., same emitter boron doping in the field emitter and emitter contact regions).
  • This example is shown for an IBC icell with an n-type base and p-type emitter. However, the polarities can be changed so that the solar cell has p- type base and n-type emitter instead.
  • Fig. 5 is a representative manufacturing process flow embodiment for the fabrication of back-contact back-junction crystalline monolithic isled silicon solar cells (icells). Specifically, Fig. 5 provides for the formation of an epitaxial (epi) solar cell, optionally with a monolithically integrated bypass switch (MIBS) pn junction diode, and having a double borosilicate glass (BSG) selective emitter. As shown in this flow, mini- cell trench isolation regions are formed at Tool 13, after cell release border scribe and cell lift-off release and before texturization of the exposed released side (also known as frontside or sunnyside of the resulting icell).
  • MIBS monolithically integrated bypass switch
  • BSG double borosilicate glass
  • the mini-cell trench isolation regions may be formed after texture and post texture clean in Tool 14, and before frontside passivation (shown as PECVD).
  • PECVD frontside passivation
  • Performing the pulsed laser scribing before wet etch texture may have an added advantage of removing any laser-induced scribed silicon edge damage through wet etching and removal of damaged silicon.
  • a representative process flow for forming a monolithic isled (tiled) back- contact/back-junction (IBC) solar cell using epitaxial silicon lift-off processing may comprise the following fabrication steps: 1) start with reusable crystalline (mono- crystalline or multi-crystalline) silicon template; 2) form porous silicon on template (for example, bilayer porous silicon with a lower porosity surface layer and a higher porosity buried layer using anodic etch in HF/IPA or HF/acetic acid); 3) deposit epitaxial silicon with in-situ doping (for instance, n-type phosphorus doped epitaxial silicon); 4) perform back-contact/back-junction cell processing while the epitaxial silicon substrate resides on its template, including formation of patterned field emitter junction, backside passivation, doped base and emitter contact regions for subsequent metallized solar cell ohmic contacts, and formation of a first metallization layer (also known as Ml) - alternatively an example of a back-contact/back-
  • ALD Atomic Layer Deposition
  • passivation layer deposition such as a thin sub-30 nm layer of aluminum oxide, amorphous silicon, or amorphous silicon oxide directly on the cleaned, textured silicon surface and underneath the silicon nitride ARC layer - if using a multi-layer frontside passivation / ARC structure, such as a two-layer structure of one of the above- mentioned passivation layers covered by the silicon nitride ARC layer, the entire stack may also be deposited using PECVD using a vacuum-integrated process).
  • ALD Atomic Layer Deposition
  • the frontside passivation and ARC layer deposition will not only cover the frontside surfaces of the mini-cells or isles, it will also cover the sidewalls of the trench-partitioned isles or mini- cells, hence, substantially improving the passivation and ARC properties of the icell by improving the passivation and light capturing properties of the trench sidewalls as well as the top surfaces of the isles.
  • the remaining solar cell fabrication process step involves completion of the second metallization layer (M2) on the backplane- attached solar cell backside.
  • a plurality of via holes are drilled according to a pre-designed via hole pattern, for instance using laser drilling, into the thin (e.g., 25 microns up to 250 microns backplane thickness), electrically insulating, continuous backplane layer (e.g., a 25 micron to 100 micron thick laminated prepreg sheet).
  • the number of via holes on a solar cell (e.g., 156 mm x 156 mm icell) backplane may be on the order of 100' s to 1000's.
  • the via holes may have average diagonal hole dimension (e.g., average diameter of each via hole) in the range of 10's of microns to 100's of microns (for instance, about 100 microns to 300 microns).
  • the laser-drilled via holes through the electrically insulating backplane layer are positioned to land on the interdigitated base and emitter metallization fingers (formed by the first level of patterned metallization by screen printing of a metallic paste or by physical-vapor deposition and patterning of a metal layer such as a metal comprising aluminum or aluminum-silicon alloy).
  • via holes will serve as the interconnection channels or plugs between the first layer of patterned metallization or Ml formed directly on the solar cell backside prior to the backplane attachment / lamination and the second layer of patterned metal or M2 to be formed immediately after formation of the laser-drilled via holes.
  • the second level of patterned metallization M2 may be formed by one of several methods, including but not limited to one or a combination of: (1) Physical-Vapor Deposition or PVD (thermal evaporation and/or electron-beam evaporation and/or plasma sputtering) of an inexpensive high-conductivity metal comprising, for instance, aluminum and/or copper (other metals may also be used) followed by pulsed laser ablation patterning, (2) Physical-Vapor Deposition or PVD (thermal evaporation and/or electron-beam evaporation and/or plasma sputtering) of an inexpensive high-conductivity metal comprising, for instance, aluminum and/or copper (other metals may also be used) followed by metal etch patterning (e.g.
  • etch paste screen printing of an etch paste or screen printing of a resist followed by a metal wet etch process and subsequent removal of the resist
  • Screen printing or stencil printing of a suitable metal paste such as a paste comprising copper and/or aluminum
  • Inkjet printing or aerosol printing of a suitable metal paste such as a paste comprising copper and/or aluminum
  • Patterned plating of a suitable metal for instance, copper plating.
  • the patterned second layer of metallization may also comprise a thin capping layer (for instance, a thin ⁇ 1 micron capping layer of NiV or Ni formed by plasma sputtering or screen printing or plating) to protect the main patterned M2 (e.g., aluminum and/or copper containing high conductivity metal) and to provide a suitable surface for soldering or conductive adhesive as needed.
  • a thin capping layer for instance, a thin ⁇ 1 micron capping layer of NiV or Ni formed by plasma sputtering or screen printing or plating
  • the back-contact / back-junction (IBC) solar cells described herein may utilize two layers of patterned metallization (Ml and M2), with the first patterned metallization layer Ml forming the interdigitated base and emitter metallization fingers on each mini-cell or isle according to a fine-pitch pattern (for instance, base-emitter Ml finger pitch in the range of about 200 microns to 2 mm, and in some cases in the range of about 500 microns to about 1 mm), and the second patterned layer of metallization M2 forming the final icell metallization and interconnecting the isles/sub-cells/ or mini-cells according to a pre-specified current and voltage scaling factor.
  • Ml and M2 patterned metallization
  • Patterned M2 may be have a much larger finger-to-finger pitch than patterned Ml fingers. This will substantially facilitate fabrication of patterned M2 according to a low- cost, high-yield manufacturing process. Patterned M2 not only formed the final icell patterned metallization, it also forms the electrically conductive via plugs through the laser-drilled via holes in order to complete the M2-to-Ml interconnections based on desired icell metallization structure.
  • the second layer of patterned metallization M2 can be used to not only complete the individual master cell (or icell) through sub-cell electrical interconnections, but also monolithically interconnect a plurality of icells sharing the same continuous backplane layer, hence, resulting in a Monolithic Module structure facilitated and enabled by the icells embodiments and with numerous additional benefits.
  • the above epitaxial silicon lift off icell process flows shows the process flow for fabricating monolithic icells with each icell being attached to its own separate pre-cut continuous backplane layer, and each individual backplane attached icell being processed through the entire backend process flow after its backplane lamination.
  • the icells processed using this approach will then be tested and sorted at the end of the process and can be assembled into the PV modules by interconnections of the icells to one another, for instance in electrical series, using tabbing and/or stringing of the cells (also involving soldering and/or conductive adhesives to interconnect the plurality of solar cells to one another as part of PV module assembly), and then completion of the module lamination and final module assembly and testing.
  • An alternative embodiment of an icell implementation resulting in a novel monolithic module structure involves attachment or lamination of a plurality of relatively closely-spaced icells (for instance, with the adjacent icell to icell spacing in the range of 50 microns up to about 2 mm, and often in the range of about 100 microns to 1 mm) on their backsides to a larger continuous backplane sheet at the Backplane Lamination (or attachment step) performed by Tool 12 in Fig. 5. The remaining process steps after Tool 12 are performed
  • the monolithic patterned M2 After completion of the final metallization (patterned second layer of metal M2), the monolithic patterned M2 not only completes the metallization pattern for each icell among the plurality of the icells sharing the larger continuous backplane layer, it also completes electrical interconnections of the plurality of icells to one another according to any desired arrangement, for instance,
  • a properly sized continuous backplane sheet e.g., a sheet of prepreg
  • the continuous backplane layer or sheet e.g., an aramid fiber / resin prepreg sheet with a thickness in the range of about 50 to 100 microns
  • a properly sized continuous backplane sheet e.g., a sheet of prepreg
  • the continuous backplane layer or sheet e.g., an aramid fiber / resin prepreg sheet with a thickness in the range of about 50 to 100 microns
  • the monolithic interconnections of the plurality of icells on a shared continuous backplane layer using the second layer of patterned metal M2 results in further reduction of the overall solar cell and PV module manufacturing cost as well as improved projected reliability of the PV modules during field operation (due to the elimination of soldered tabs, strings).
  • solar cell fabrication process flows including but not limited to the solar cells fabricated from starting monocrystalline wafers (e.g., Czochralski or CZ, Float Zone or FZ) or multi-crystalline wafers (from cast crystalline bricks or formed by a ribbon pulling process) or epitaxial growth or other substrate fabrication methods.
  • monocrystalline wafers e.g., Czochralski or CZ, Float Zone or FZ
  • multi-crystalline wafers from cast crystalline bricks or formed by a ribbon pulling process
  • epitaxial growth or other substrate fabrication methods e.g., icell embodiments may be applied to other semiconductor materials besides silicon as described before, including but not limited to gallium arsenide, germanium, gallium nitride, other compound semiconductors, or a combination thereof.
  • Fig. 6 is a high level solar cell and module fabrication process flow embodiment using starting crystalline (mono-crystalline or multi-crystalline) silicon wafers.
  • Fig. 6 shows a high-level icell process flow for fabrication of backplane-attached back- contact/back-junction (IBC) icells using two layers of metallization: Ml and M2.
  • the first layer or level of patterned cell metallization Ml is formed as essentially the last process step among a plurality of front-end cell fab processes prior to the backplane lamination to the partially processed icell (or a larger continuous backplane attached to a plurality of partially processed icells when fabricating monolithic modules as described earlier).
  • the front-end cell fab processes outlined in the top 4 boxes of Fig. 6 essentially complete the back-contact/back-junction solar cell backside structure through the patterned Ml layer.
  • Patterned Ml is designed to conform to the icell isles (mini-cells) and comprises a fine-pitch interdigitated metallization pattern as described for the epitaxial silicon icell process flow outlined in Fig. 5.
  • the fifth box from the top involves attachment or lamination of the backplane layer or sheet to the partially processed icell backside (or to the backsides of a plurality of partially processed icells when making a monolithic module) - this process step is essentially equivalent to the one performed by Tool 12 in Fig.
  • the sixth and seventh boxes from the top outline the back-end or post-backplane-attachment (also called post-lamination) cell fab processes to complete the remaining frontside (optional silicon wafer thinning etch to form thinner silicon absorber layer if desired, partitioning trenches, texturization, post-texturization cleaning, passivation and ARC) as well as the via holes and second level or layer of patterned metallization M2.
  • the "post- lamination" processes (or the back-end cell fab processes performed after the backplane attachment) outlined in the sixth and seventh boxes of Fig. 6 essentially correspond to the processes performed by Tools 13 through 18 for the epitaxial silicon lift off process flow shown in Fig. 5.
  • the bottom box in Fig. 6 describes the final assembly of the resulting icells into either flexible, lightweight PV modules or into rigid glass-covered PV modules. If the process flow results in a monolithic module comprising a plurality of icells monolithically interconnected together by the patterned M2 (as described earlier for the epitaxial silicon lift off process flow), the remaining PV module fabrication process outlined in the bottom box of Fig. 6 would be simplified since the plurality of the interconnected icells sharing a larger continuous backplane and the patterned M2 metallization for cell-to-cell interconnections are already electrically interconnected and there is no need for tabbing and/or stringing and/or soldering of the solar cells to one another.
  • the resulting monolithic module can be laminated into either a flexible, lightweight PV module (for instance, using a thin flexible fluoropolymer cover sheet such as ETFE or PFE on the frontside instead of rigid / heavy glass cover sheet) or a rigid, glass-covered PV module.
  • a flexible, lightweight PV module for instance, using a thin flexible fluoropolymer cover sheet such as ETFE or PFE on the frontside instead of rigid / heavy glass cover sheet
  • a rigid, glass-covered PV module for instance, using a thin flexible fluoropolymer cover sheet such as ETFE or PFE on the frontside instead of rigid / heavy glass cover sheet
  • Tables 1 and 2 below show two cell fabrication process flows beginning after first level metallization (Ml) formation and resulting in the solar cell structure of Fig. 4.
  • the backend fabrication process requires that the wafer is laminated to a specially designed backplane material (e.g., prepreg). Subsequent to this lamination, the backplane material (e.g., prepreg), which is stable under different chemistries, is used to support the silicon substrate during silicon etch back and thin down silicon (this renders a lower lifetime wafer to become higher efficiency).
  • a specially designed backplane material e.g., prepreg
  • An advantage of silicon etch back after the icell cut is that any laser damage during the cut is removed during the etch back process.
  • a second advantage is that because the laser icell cut now is partial (rest of the opening is done by the wet chemistry), the laser does not need to have selectivity to the backplane (e.g., prepreg) and thus wavelengths other than infra-red may be used (infrared laser has selectivity to the prepreg).
  • An additional advantage of the sequence of Table 2 is that since laser does not touch the backplane (e.g., prepreg) any splattering of the backplane (e.g., prepreg) and the ensuing particles are eliminated.
  • the patterned metal may followed by pads of screen printed paste on top of the patterned metal in specific locations.
  • the purpose of these pads is to serve as via drill stop for laser which is used to drill holes through the backplane (e.g., prepreg) to connect metal 1 and metal 2 later.
  • These pads may be made of materials such as aluminum paste or silver paste. If the metallization and contact schemed is based on screen printing, the pads would not constitute as an extra tool as the pads may be formed as the second step in the metallization screen print. However, for PVD based
  • a screen print step will be required if the pads are needed. If drill stop pads are not utilized, then the underlying PVD or the paste must be capable of serving as the via drill stop.
  • the solar cell structures described herein may utilize a multi-layer metallization structure, such as a two-level metallization structure, comprising an on-cell base and emitter metallization first level metal (Ml) and a second level metal (M2) collecting power (voltage and current) from the first level metal (hence, completing the solar cell metallization) and which may also form cell to cell interconnections.
  • the second level metal (M2) may comprise an interdigitated pattern of base and emitter current collection fingers and optionally solar cell base and emitter busbars (for example, M2 base and emitter fingers extending from base and emitter busbars, respectively).
  • the first level metal may comprise an interdigitated back contact metallization structure with relatively fine pitch interdigitated fingers (much finer pitch than the second level metal pitch) arranged parallel to the interdigitated fingers of M2.
  • a relatively thin electrically insulating backplane formed between Ml and M2 and attached to the solar cell provides solar cell structural support, Ml electrical insulation, and allows for solar cell fabrication (particularly M2 fabrication and solar cell frontside processing) processing improvement.
  • the backplane sheet may be a continuous flexible material closely CTE-matched with the solar cell semiconductor substrate material (e.g., crystalline silicon for silicon solar cells), laminated or otherwise attached to, for example, the back-contact / back-junction solar cell prior to completion of the remaining solar cell manufacturing process steps.
  • Ml may comprise interdigitated base and emitter lines (for instance, with base-emitter finger pitch of less than 2mm and in some instances less than 1mm) and M2 (in some instances with a much coarser base-emitter pitch compared to Ml) serves as the electrical connector among Ml base and emitter lines (i.e., a Ml pattern while the optional cell busbars may be placed on the M2 pattern).
  • the metal layers in the disclosed multi-level metal designs are separated by a dielectric or an electrically insulating layer, such as a resin/fiber based prepreg material or alternatively a suitable plastic or polymer based material, forming a continuous backplane for each of the plurality of solar cells in the solar cell array placed on the continuous backplane.
  • a dielectric or an electrically insulating layer such as a resin/fiber based prepreg material or alternatively a suitable plastic or polymer based material, forming a continuous backplane for each of the plurality of solar cells in the solar cell array placed on the continuous backplane.
  • the backplane should preferably be relatively closely CTE (Coefficient of Thermal Expansion) matched to the CTE of the
  • M1/M2 interconnection structures include conductive material filled vias through the insulating layer (e.g., an insulating dielectric layer such as prepreg backplane) positioned between Ml and M2 - laminated or attached to the backsides of the solar cells after formation of the patterned M2 layer.
  • insulating layer e.g., an insulating dielectric layer such as prepreg backplane
  • the solar cells provided may utilize a two-level metallization scheme comprising a first-level contact metallization (Ml) using a relatively thin patterned metal (e.g., thin aluminum formed by screen printing of an aluminum paste or inkjet printing of an aluminum ink, or alternatively plasma sputtering from an aluminum target followed by laser ablation or wet etch patterning) formed directly on the solar cell backside prior to backplane lamination, and a second level thin patterned metal M2 (e.g., comprising approximately 3 to 5 microns thick Al or alternatively, about one to several microns of copper, which may in either case be optionally capped with a solderable coating such as tin) formed after backplane lamination.
  • Ml first-level contact metallization
  • M2 e.g., thin aluminum formed by screen printing of an aluminum paste or inkjet printing of an aluminum ink, or alternatively plasma sputtering from an aluminum target followed by laser ablation or wet etch patterning
  • the patterned M2 layer may also be formed by using plating or lamination and patterning of a high-conductivity metal foil (comprising copper or aluminum).
  • the Ml and M2 layers are separated by the backplane and interconnected at designated regions through conductive via plugs (conductive via plugs may be formed during M2 formation).
  • Patterned M2 completes the cell-level electrical metallization and may also provide cell to cell electrical interconnections for a plurality of solar cells laminated to a continuous backplane - thus in some instances eliminating the need for separate cell to cell tabbing/bussing/soldering.
  • M2 may form array/module level bussing or interconnections when desired for array/module electrical interconnection design.
  • voltage and current scaling may relax and reduce M2 conductivity requirements and constraints. For example, in consideration with other factors, utilizing a thinner M2 metal (e.g., about 2 to 5 microns thick evaporated aluminum by PVD or about 1 to few microns of copper formed by plasma sputtering or evaporation) as compared to thicker M2 metallization (e.g., about 50 to 80 microns thick electroplated copper).
  • M2 metal e.g., about 2 to 5 microns thick evaporated aluminum by PVD or about 1 to few microns of copper formed by plasma sputtering or evaporation
  • thicker M2 metallization e.g., about 50 to 80 microns thick electroplated copper.
  • the thickness of Ml and M2 metallization layers may also be adjusted based on the number, dimensions, and shape of the interdigitated fingers on the Ml layer and M2 layer.
  • Ml is patterned with finer interdigitated fingers as compared to the interdigitated fingers of M2.
  • Structures and methods for forming isled solar cells having integrated backplane supported dual level metallization structure referred to as an iCell may be found in related U.S. Patent Pub. 2014/0370650 published Dec. 18, 2014, referenced previously.
  • Physically or regionally isolated isles i.e., the initial semiconductor substrate partitioned into a plurality of substrate isles supported on a shared continuous backplane
  • the resulting isles for instance, trench isolated from one another using trench isolation regions or cuts through the semiconductor substrate, for example using laser or mechanical scribing
  • a continuous backplane for example a flexible backplane such as an electrically insulating prepreg layer
  • the completed solar cell (referred to as a master cell or iCell) comprises a plurality of monolithically integrated isles/sub-cells/mini-cells, in some instances attached to a flexible backplane (e.g., one made of a prepreg materials, for example having a relatively good Coefficient of Thermal Expansion or CTE match to that of the semiconductor substrate material such as crystalline silicon), providing increased solar cell flexibility and pliability while suppressing or even eliminating micro-crack generation and crack propagation or breakage in the semiconductor substrate layer.
  • a flexible backplane e.g., one made of a prepreg materials, for example having a relatively good Coefficient of Thermal Expansion or CTE match to that of the semiconductor substrate material such as crystalline silicon
  • a flexible monolithically isled (or monolithically integrated group of isles) cell also called an iCell
  • a flexible monolithically isled (or monolithically integrated group of isles) cell provides improved cell planarity and relatively small or negligible cell bow throughout solar cell processing steps such as any optional semiconductor layer thinning etch, texture etch, post-texture clean, PECVD passivation and anti-reflection coating (ARC) processes (and in some processing embodiments also allows for sunny- side -up PECVD processing of the substrates due to mitigation or elimination of thermally-induced cell warpage), and final solar cell metallization.
  • ARC anti-reflection coating
  • the cell structures and fabrication embodiments provided are applicable to various dual level metallization schemes utilizing a backplane and M2 metallization layer.
  • the solar cell base and emitter contact metallization pattern is formed directly on the cell backside, for instance using a thin layer of screen printed or inkjet printed or plasma sputtered (PVD) or evaporated aluminum (or aluminum silicon alloy or Al/NiV/Sn stack) material layer.
  • PVD screen printed or inkjet printed or plasma sputtered
  • evaporated aluminum or aluminum silicon alloy or Al/NiV/Sn stack
  • Ml defines the solar cell contact metallization pattern, for example fine-pitch interdigitated back-contact (IBC) conductor fingers defining the base and emitter regions of the IBC cell.
  • the Ml layer extracts the solar cell current and voltage (hence the solar cell power) and transfers the solar cell electrical power through the conductive via plugs formed in the backplane to the second level/layer of high-conductivity solar cell metallization (herein referred to as M2) formed after Ml .
  • M2 second level/layer of high-conductivity solar cell metallization
  • the conductive via plugs can be formed concurrently during the formation of the patterned M2 layer, for example after laser drilling of via holes in the backplane layer.
  • the backplane material attached to the backside of the solar cell(s) and placed between patterned Ml and M2 layers may be a thin (e.g., between approximately 25 microns and 1 mm and in some instances between approximately 25 microns and 250 microns) sheet of a polymeric material with sufficiently low coefficient of thermal expansion (CTE) which is closely matched to that of the semiconductor absorber layer in order to avoid causing excessive thermally induced stresses and warpage on the solar cell array.
  • CTE coefficient of thermal expansion
  • the backplane material should meet process integration requirements for the backend cell fabrication processes, in particular chemical resistance during wet texturing of the cell frontside and thermal stability during the PECVD deposition of the frontside passivation and anti-reflection coating (ARC) layer.
  • the electrically insulating backplane material should also meet the module-level lamination process and long-term reliability requirements. While various suitable polymeric (such as plastics, fluoropolymers, prepregs, etc.) and suitable non-polymeric materials (such as glass, ceramics, etc.) may be used as the backplane material, backplane material choice depends on many considerations including, but not limited to, material cost, ease of process integration, reliability, pliability, mass density, etc. [051] An advantageous material choice for the backplane material is prepreg and more particularly an aramid fiber resin based prepreg. In some instances, a non-woven aramid fiber is particularly advantageous.
  • prepregs are reinforcing materials pre- impregnated with resin and ready to use to produce composite parts (prepregs may be used to produce composites faster and easier than wet lay-up systems). Prepregs may be manufactured by combining reinforcement fibers or fabrics with specially formulated pre-catalyzed resins using equipment designed to ensure consistency. Inexpensive prepreg material is commonly used in printed circuit boards.
  • the backplane (e.g., prepreg sheet) may be attached to the solar cell backside using a vacuum laminator. Upon applying a combination of heat and pressure, the thin backplane (e.g., prepreg sheet) is permanently laminated or attached to the backside of the partially-processed (or even fully-processed) solar cell.
  • subsequent post-lamination fabrication process steps may include: (i) completion of the texture and passivation processes on the sunnysides (frontsides) of the solar cell, (ii) completion of the high conductivity metallization (M2) on the backside of the solar cell (which may comprise part of the solar cell backplane).
  • the high- conductivity metallization M2 layer (for example comprising aluminum, copper, or silver, with aluminum and/or copper being preferred compared to silver because of much lower material cost) comprising both the emitter and base polarities is formed on the laminated backplane attached to the backside of the solar cell.
  • a higher conductivity M2 layer is formed on the backplane.
  • Via holes in some instances up to hundreds or thousands of via holes per solar cell
  • may have diameters in some instances tapered) in the range of approximately 50 up to 500 microns (particularly in the diameter range of about 100 to 300 microns).
  • These via holes land on pre-specified landing pad regions of Ml for electrical connection between the patterned M2 and Ml layers through conductive plugs formed in these via holes.
  • the vias may be covered or at least partially filled with conductive metallization and M2 may be deposited in separate steps and in other instances M2 deposition at least partially covers or partially fills the vias in the same M2 deposition or formation step.
  • the patterned high-conductivity metallization layer M2 is formed (for example by plasma sputtering, plating, evaporation, or a combination thereof - using an M2 material comprising, for instance, aluminum, Al/NIV, Al/NiV/Sn, or copper or solder-coated copper).
  • the patterned M2 layer may be designed parallel to Ml - in other words rectangular or tapered M2 fingers parallel and over corresponding Ml fingers.
  • Optional solar cell busbars may be positioned on the M2 layer, to eliminate electrical shading losses associated with on-cell busbars.
  • both the base and emitter interconnections and busbars may be positioned on the M2 layer on the solar cell backside backplane, electrical access is provided to both the base and emitter terminals of the solar cell on the backplane from the backside of the solar cell.

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Abstract

Une cellule solaire à contact arrière interdigitée comprend un substrat de cellule solaire présentant une face avant de réception de lumière et une face arrière comprenant des régions de base et d'émetteur. Un métal de premier niveau (Ml) est positionné sur le côté arrière du substrat en contact avec les régions de base et d'émetteur. Le métal de premier niveau (Ml) a un motif interdigité de barres omnibus de base et d'émetteur. Chaque barre omnibus de base de métal de premier niveau (Ml) a une pluralité de doigts de base et chaque barre omnibus d'émetteur de métal de premier niveau (Ml) a une pluralité de doigts d'émetteur. Une couche de métal de second niveau (M2) est connectée à la couche de métal de premier niveau (Ml). Le métal de second niveau (M2) a un motif interdigité de doigts de base de métal de second niveau (M2) parallèles et connectés aux barres omnibus de base de métal de premier niveau (Ml) et de doigts d'émetteur de métal de second niveau (M2) parallèles et connectés aux barres omnibus d'émetteur de métal de premier niveau (Ml). Au moins une barre omnibus de base de métal de second niveau (M2) est connectée aux doigts de base de métal de second niveau (M2) et au moins une barre omnibus d'émetteur de métal de second niveau (M2) est connectée aux doigts d'émetteur de métal de second niveau (M2).
PCT/US2015/048211 2014-09-02 2015-09-02 Métallisation de cellule solaire à double niveau possédant des barres omnibus métalliques de premier niveau WO2016036892A1 (fr)

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US11888077B2 (en) 2016-09-26 2024-01-30 Nederlandse Organisatie Voor Toegepast-Natuurwetenschappelijk Onderzoek Tno Photovoltaic module with back contact foil
CN109888044A (zh) * 2019-01-23 2019-06-14 茂迪太阳能科技（东莞）有限公司 Ibc全背电极电池片的焊接方法、装置及电池片
CN109888044B (zh) * 2019-01-23 2021-11-26 茂迪太阳能科技（东莞）有限公司 Ibc全背电极电池片的焊接方法、装置及电池片

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