WO2016029517A1 - Thin film transistor array substrate and pixel darkening processing method thereof - Google Patents

Thin film transistor array substrate and pixel darkening processing method thereof Download PDF

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Publication number
WO2016029517A1
WO2016029517A1 PCT/CN2014/086626 CN2014086626W WO2016029517A1 WO 2016029517 A1 WO2016029517 A1 WO 2016029517A1 CN 2014086626 W CN2014086626 W CN 2014086626W WO 2016029517 A1 WO2016029517 A1 WO 2016029517A1
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Prior art keywords
thin film
film transistor
pixel electrode
pixel
array substrate
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PCT/CN2014/086626
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French (fr)
Chinese (zh)
Inventor
高鹏
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深圳市华星光电技术有限公司
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Publication of WO2016029517A1 publication Critical patent/WO2016029517A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a thin film transistor array substrate and a pixel darkening processing method thereof.
  • a conventional thin film transistor array substrate includes a plurality of pixels including a pixel electrode, a thin film transistor switch, and the like.
  • a thin film transistor switch of a part of a pixel may not be normally switched according to a scan signal. At this time, the pixel becomes a defective pixel, and the defective pixel tends to receive the data line all the time. The data signal is thus always in a bright state.
  • the presence of the defective pixel affects the display quality of the display panel.
  • An object of the present invention is to provide a thin film transistor array substrate and a pixel darkening processing method thereof, which can perform darkening processing on a part of pixels, so that a region corresponding to a dark-dotted pixel is displayed as a normally dark state. .
  • a thin film transistor array substrate comprising: at least one data line; at least one scan line; at least one common line; at least one first pixel, the first pixel comprising a first thin film transistor and a first pixel An electrode, the first thin film transistor being connected to the data line, the scan line and the first pixel electrode, the first pixel electrode being insulated from the common line; and at least one dark-dotted pixel
  • the dark-dotted pixel is formed by darkening a second pixel of the thin film transistor array substrate, and the dark-spotted pixel includes a second thin film transistor and a second pixel electrode
  • the second thin film transistor is connected to the scan line and the second pixel electrode, the second thin film transistor is disconnected from the data line, and the second pixel electrode is in common with the An insulating layer is disposed between the lines, the second pixel electrode is electrically connected to the common line; and the second thin film transistor includes a second gate and a second a second drain, an area of the first overlapping portion of the second source and the second gate is zero
  • the disconnected state is by cutting a connection line between the second thin film transistor and the data line to insulate the second thin film transistor and the data line To form.
  • connection line between the second thin film transistor and the data line is cut using a first laser.
  • a connection line between the second thin film transistor and the data line is cut by dropping a first etching liquid.
  • the electrical connection state is formed by forming a recess at a predetermined position on the surface of the second pixel electrode and providing an electrical connection member in the recess;
  • the second pixel electrode and the common line are electrically connected by the electrical connection.
  • the recess is formed by irradiating the predetermined position with a second laser.
  • the recess penetrates the second pixel electrode and the insulating layer in a first direction, and the first direction is a direction perpendicular to a plane in which the second pixel electrode is located.
  • the recess is formed by dropping a second etching liquid at the predetermined position.
  • a thin film transistor array substrate comprising: at least one data line; at least one scan line; at least one common line; at least one first pixel, the first pixel comprising a first thin film transistor and a first pixel An electrode, the first thin film transistor being connected to the data line, the scan line and the first pixel electrode, the first pixel electrode being insulated from the common line; and at least one dark-dotted pixel
  • the dark-dotted pixel is formed by darkening a second pixel of the thin film transistor array substrate, and the dark-spotted pixel includes a second thin film transistor and a second pixel electrode
  • the second thin film transistor is connected to the scan line and the second pixel electrode, the second thin film transistor is disconnected from the data line, and the second pixel electrode is in common with the An insulating layer is disposed between the lines, and the second pixel electrode is electrically connected to the common line.
  • the disconnected state is by cutting a connection line between the second thin film transistor and the data line to insulate the second thin film transistor and the data line To form.
  • connection line between the second thin film transistor and the data line is cut using a first laser.
  • a connection line between the second thin film transistor and the data line is cut by dropping a first etching liquid.
  • the electrical connection state is formed by forming a recess at a predetermined position on the surface of the second pixel electrode and providing an electrical connection member in the recess;
  • the second pixel electrode and the common line are electrically connected by the electrical connection.
  • the recess is formed by irradiating the predetermined position with a second laser.
  • the recess penetrates the second pixel electrode and the insulating layer in a first direction, and the first direction is a direction perpendicular to a plane in which the second pixel electrode is located.
  • the recess is formed by dropping a second etching liquid at the predetermined position.
  • a pixel dark spot processing method for the above thin film transistor array substrate comprising: cutting a connection line between the second thin film transistor and the data line, so that the second thin film transistor and the a data line is insulated; a recess is formed at a predetermined position on a surface of the second pixel electrode; and an electrical connection is disposed in the recess to pass the second pixel electrode and the common line
  • the electrical connectors are electrically connected.
  • the step of cutting a connection line between the second thin film transistor and the data line includes: using the first laser to the second thin film transistor and the data The connecting line between the lines is cut.
  • the step of forming a recess at a predetermined position of a surface of the second pixel electrode includes: illuminating the predetermined position with a second laser to be at the predetermined position The cavity is formed.
  • the recess penetrates the second pixel electrode and the insulating layer in a first direction, and the first direction is perpendicular to a plane where the second pixel electrode is located direction.
  • the present invention can make the relative potential of the second pixel electrode in the dark-spotted pixel be 0, and the liquid crystal molecules corresponding to the dark-spotted pixel cannot pass the second The voltage difference conversion of the pixel electrode is deflected, and therefore, the area corresponding to the darkened pixel is displayed as a normally dark state.
  • FIG. 1 is a schematic view of a thin film transistor array substrate of the present invention
  • FIG. 2 is a schematic cross-sectional view of the A-A' of the second pixel of FIG. 1 before forming a recess;
  • FIG. 3 is a schematic cross-sectional view of the A-A' of the second pixel of FIG. 1 after forming a recess;
  • Figure 4 is a cross-sectional view showing the A-A' of the first embodiment in which the electrical connecting member is disposed in the recess of Figure 1;
  • Figure 5 is a cross-sectional view of the A-A' of the second embodiment in which the electrical connector is disposed in the recess of Figure 1;
  • FIG. 6 is an equivalent circuit diagram of a pixel subjected to dark dot processing in FIG. 1;
  • FIG. 7 is a flowchart of a method for processing a pixel dark spot of the thin film transistor array substrate of the present invention.
  • FIG. 1 is a schematic diagram of a thin film transistor array substrate of the present invention.
  • the thin film transistor array substrate of this embodiment includes at least one data line 102, at least one scan line 101, at least one common line 103, at least one first pixel, and at least one dark-dotted pixel.
  • the first pixel includes a first thin film transistor 104 and a first pixel electrode 106, and the first thin film transistor 104 is connected to the data line 102, the scan line 101, and the first pixel electrode 106.
  • the first pixel electrode 106 is insulated from the common line 103. Specifically, a first gate of the first thin film transistor 104 is connected to the scan line 101, and a first source of the first thin film transistor 104 is connected to the data line 102.
  • the first thin film transistor 104 is connected.
  • the drain is connected to the first pixel electrode 106.
  • An insulating layer 201 is disposed between the first pixel electrode 106 and the common line 103.
  • the dark-dotted pixel is formed by darkening a second pixel of the thin film transistor array substrate, and the dark-dotted pixel includes a second thin film transistor 105 and a second pixel electrode 107.
  • the second thin film transistor 105 is connected to the scan line 101 and the second pixel electrode 107. Specifically, the second gate electrode 1051 of the second thin film transistor 105 is connected to the scan line 101. The second drain electrode 1053 of the second thin film transistor 105 is connected to the second pixel electrode 107.
  • the second thin film transistor 105 is disconnected from the data line 102, and the insulating layer 201 is disposed between the second pixel electrode 107 and the common line 103, and the second pixel electrode 107 is The common line 103 is in an electrically connected state.
  • the disconnected state is performed by cutting a connection line between the second thin film transistor 105 and the data line 102 to make the second thin film transistor 105 and the data line 102 insulation is formed.
  • connection line between the second thin film transistor 105 and the data line 102 is cut by using a first laser.
  • the disconnected state may be formed by cutting the connecting wire by etching, for example, by dropping a first corrosive liquid (for example, an acidic liquid).
  • a first corrosive liquid for example, an acidic liquid.
  • FIG. 2 is a schematic cross-sectional view of the second pixel of FIG. 1 before forming the recess 110
  • FIG. 3 is the second pixel of FIG. 1 after the recess 110 is formed.
  • A-A' is a schematic cross-sectional view
  • FIG. 4 is a cross-sectional view taken along line AA' of the first embodiment in which the electrical connector 401 is disposed in the cavity 110 of FIG.
  • the electrical connection state is formed by forming the cavity 110 at a predetermined position 109 on the surface of the second pixel electrode 107, and the electrical connection is disposed in the cavity 110.
  • Piece 401 is formed.
  • the recess 110 is formed by irradiating the predetermined position 109 with a second laser.
  • the excitation of the second laser may cause a portion of the metal material/metal oxide material in the second pixel electrode 107 to be cleaved, thereby forming a An opening portion 1071; or the excitation of the second laser light may cause a portion of the metal material/metal oxide material of the common line 103 to be cleaved to form a second split portion.
  • the first split portion 1071 tends to adhere to the edge of the hole of the recess 110, and the second split portion tends to adhere to the bottom edge of the recess 110, and the first split portion
  • the second opening portion 1071 or the second opening portion may be in contact with the second pixel electrode 107 and the common line 103 at the same time, so that the second pixel electrode 107 and the common line 103 are electrically connected.
  • the event that some of the first split portion 1071 or the second split portion simultaneously contacts the second pixel electrode 107 and the common line 103 is a probability event (ie, an event that rarely occurs)
  • the present invention provides the electrical connector 401 at the recess 110 based on the above-described phenomenon. Therefore, the technical solution of the present invention is advantageous for ensuring the number of pixels in the dark-dot processing.
  • the two-pixel electrode 107 is electrically connected to the common line 103.
  • the recess 110 may be formed by etching the predetermined position 109.
  • the recess 110 may be by dropping a second corrosive liquid at the predetermined position 109 ( For example, an acidic liquid is formed.
  • the second pixel electrode 107 and the common line 103 are electrically connected through the electrical connector 401.
  • the predetermined position 109 is one of overlapping portions of the second pixel electrode 107 and the common line 103.
  • the recess 110 penetrates the second pixel electrode 107 and the insulating layer 201 in a first direction, and the first direction is a direction perpendicular to a plane in which the second pixel electrode 107 is located. Further, the recess 110 extends inside the common line 103 in the first direction.
  • the electrical connector 401 fills the cavity 110.
  • the electrical connector 401 is a metal (eg, iron, copper, etc.), an alloy, a conductive paste, or the like.
  • the electrical connector 401 may be formed by laser gas phase film formation (Laser Chemical Vapor)
  • the manner of Deposition is formed by depositing a conductive material (for example, iron, copper, alloy, conductive paste, etc.) at the cavity 110.
  • FIG. 5 there is shown a cross-sectional view of the second embodiment of the electrical connector 401 in the recess 110 of Figure 1 taken along line A-A'.
  • the electrical connector 401 is attached to the bottom surface and the sidewall of the recess 110, that is, the conductive material is coated on the bottom surface and the sidewall of the recess 110. on.
  • the conductive material may be coated on the bottom surface and the sidewall of the recess 110 by sputtering or spraying.
  • FIG. 6 is an equivalent circuit diagram of a pixel subjected to dark dot processing in FIG.
  • the dark-dotted pixel includes a second thin film transistor 105, a liquid crystal capacitor (by the second pixel electrode 107 and a color filter disposed opposite to the thin film transistor array substrate)
  • the common electrode on the light sheet substrate constitutes 601 and the storage capacitor 602.
  • the connection line between the second source 1052 of the second thin film transistor 105 and the data line 102 is cut off at the disconnection 108, that is, the second source 1052 and the data line
  • the disconnection 108 is disconnected at the disconnection 108; the second pixel electrode 107 and the common line 103 are electrically connected through a connection line.
  • the second source 1052 and the second gate 1051 have a first overlapping portion in the first direction, and the second drain 1053 and the The second gate electrode 1051 also has a second overlapping portion in the first direction; therefore, the second source electrode 1052 and the second gate electrode 1051 constitute a gate-source capacitance Cgs (not shown), The second drain 1053 and the second gate 1051 constitute a gate drain capacitance Cgd (not shown).
  • the second thin film transistor 105 opens a current path between the second source 1052 and the second drain 1053, in order to prevent the charge on the gate source capacitor from passing through the The current channel flows to the second drain electrode 1053 and is transmitted to the second pixel electrode 107.
  • the second source electrode 1052 and the second gate electrode 1051 are disposed.
  • the area of the first overlapping portion is zero, that is, the gate source capacitance disappears (does not exist).
  • the state in which the area of the first overlapping portion is zero is formed by removing the first overlapping portion of the source by laser cutting, etching, or the like.
  • the second drain 1053 and the second gate 1051 are The area of the second overlapping portion is also zero, that is, the gate-drain capacitance disappears (does not exist). Also, the state in which the area of the second overlapping portion is zero is also formed by removing the second overlapping portion of the drain by laser cutting or etching or the like.
  • the relative potential of the second pixel electrode 107 in the dark-dotted pixel is zero.
  • Liquid crystal cell corresponding to the thin film transistor array substrate of the present invention Liquid Crystal After the cell is energized, the pixel voltage corresponding to the dark-spotted pixel is 0, and the liquid crystal molecules corresponding to the dark-spotted pixel cannot be converted by the voltage difference of the second pixel electrode 107. Deflection, therefore, the area of the liquid crystal cell corresponding to the darkened pixel is displayed as a normally dark state.
  • FIG. 7 is a flowchart of a method for processing a pixel dark spot of the thin film transistor array substrate of the present invention.
  • Step 701 cutting a connection line between the second thin film transistor 105 and the data line 102 to insulate the second thin film transistor 105 from the data line 102;
  • Step 702 forming a recess 110 at a predetermined position 109 of the surface of the second pixel electrode 107;
  • Step 703 the electrical connector 401 is disposed in the recess 110 to electrically connect the second pixel electrode 107 and the common line 103 through the electrical connector 401.
  • the step of cutting the connection line between the second thin film transistor 105 and the data line 102 includes:
  • connection line between the second thin film transistor 105 and the data line 102 is cut by a first laser.
  • the connecting line is cut by etching, for example, by dropping a first etching liquid (for example, an acidic liquid).
  • a first etching liquid for example, an acidic liquid
  • the step of forming the recess 110 on the predetermined position 109 of the surface of the second pixel electrode 107 includes:
  • the predetermined position 109 is illuminated with a second laser to form the recess 110 at the predetermined position 109.
  • the predetermined location 109 is etched to form the recess 110 at the predetermined location 109, for example, a second etching liquid is dropped at the predetermined location 109 (eg, The acidic liquid) is used to form the recess 110.
  • a second etching liquid is dropped at the predetermined location 109 (eg, The acidic liquid) is used to form the recess 110.
  • the predetermined position 109 is one of the overlapping portions of the second pixel electrode 107 and the common line 103.
  • the recess 110 penetrates the second pixel electrode 107 and the insulating layer 201 in a first direction, and the first direction is perpendicular to a plane where the second pixel electrode 107 is located. direction.
  • the recess 110 extends inside the common line 103 in the first direction.
  • the step of disposing the electrical connector 401 in the cavity 110 includes:
  • a conductive material for example, iron, copper, alloy, conductive paste, or the like is deposited at the recess 110 by laser vapor phase film formation to form the electrical connector 401.
  • the electrical connector 401 can fill the cavity 110.
  • the step of disposing the electrical connector 401 in the cavity 110 includes:
  • the conductive material is coated on the bottom surface and the sidewall of the recess 110 by sputtering or spraying to form the electrical connector 401.
  • the electrical connector 401 is attached to the bottom surface and the sidewall of the recess 110, that is, the conductive material is coated on the bottom surface and the sidewall of the recess 110.
  • the pixel dark spot processing method of the thin film transistor array substrate of the present invention further includes the following steps:
  • the above technical solution is advantageous for avoiding that the charge on the gate source capacitor flows through the current path to the second drain 1053, and is transmitted to the second pixel electrode 107, and is beneficial to avoid the gate leakage capacitance.
  • the charge is transferred to the second pixel electrode 107.
  • the above technical solution of the present invention is advantageous for ensuring that the second pixel electrode 107 in the dark-spotted pixel is electrically connected to the common line 103, thereby ensuring darkening of the second pixel. Success rate.

Abstract

A thin film transistor array substrate and a pixel darkening processing method thereof. The thin film transistor array substrate comprises a data line (102), a scanning line (101), a common line (103), a first pixel, and a pixel on which darkening processing has been performed. The pixel on which darkening processing has been performed comprises a second thin film transistor (105) and a second pixel electrode (107). The second thin film transistor (105) is disconnected from the data line (102). An insulation layer (201) is disposed between the second pixel electrode (107) and the common line (103). The second pixel electrode (107) is electrically connected to the common line (103).

Description

薄膜晶体管阵列基板及其像素暗点化处理方法 Thin film transistor array substrate and pixel dark point processing method thereof 技术领域Technical field
本发明涉及显示技术领域，特别涉及一种薄膜晶体管阵列基板及其像素暗点化处理方法。The present invention relates to the field of display technologies, and in particular, to a thin film transistor array substrate and a pixel darkening processing method thereof.
背景技术Background technique
传统的薄膜晶体管阵列基板包含若干个像素，该像素包括像素电极、薄膜晶体管开关等器件。A conventional thin film transistor array substrate includes a plurality of pixels including a pixel electrode, a thin film transistor switch, and the like.
传统的薄膜晶体管阵列基板在制作过程中，往往会发生部分像素的薄膜晶体管开关无法根据扫描信号进行正常的开关操作，此时，该像素则会成为缺陷像素，该缺陷像素往往会一直接收数据线的数据信号，从而一直处于亮态。In the fabrication process of a conventional thin film transistor array substrate, a thin film transistor switch of a part of a pixel may not be normally switched according to a scan signal. At this time, the pixel becomes a defective pixel, and the defective pixel tends to receive the data line all the time. The data signal is thus always in a bright state.
该缺陷像素的存在会影响显示面板的显示质量。The presence of the defective pixel affects the display quality of the display panel.
故，有必要提出一种新的技术方案，以解决上述技术问题。Therefore, it is necessary to propose a new technical solution to solve the above technical problems.
技术问题technical problem
本发明的目的在于提供一种薄膜晶体管阵列基板及其像素暗点化处理方法，其能对部分像素进行暗点化处理，从而使得经过暗点化处理的像素所对应的区域显示为常暗态。An object of the present invention is to provide a thin film transistor array substrate and a pixel darkening processing method thereof, which can perform darkening processing on a part of pixels, so that a region corresponding to a dark-dotted pixel is displayed as a normally dark state. .
技术解决方案Technical solution
一种薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括：至少一数据线；至少一扫描线；至少一公共线；至少一第一像素，所述第一像素包括第一薄膜晶体管和第一像素电极，所述第一薄膜晶体管与所述数据线、所述扫描线和所述第一像素电极连接，所述第一像素电极与所述公共线绝缘；以及至少一经过暗点化处理的像素，所述经过暗点化处理的像素是对所述薄膜晶体管阵列基板的第二像素进行暗点化处理来形成的，所述经过暗点化处理的像素包括第二薄膜晶体管和第二像素电极，其中，所述第二薄膜晶体管与所述扫描线和所述第二像素电极连接，所述第二薄膜晶体管与所述数据线处于断开连接状态，所述第二像素电极与所述公共线之间设置有绝缘层，所述第二像素电极与所述公共线处于电性连接状态；所述第二薄膜晶体管包括第二栅极、第二源极和第二漏极，所述第二源极与所述第二栅极的所述第一重叠部分的面积为零，所述第二漏极与所述第二栅极的所述第二重叠部分的面积也为零。A thin film transistor array substrate, comprising: at least one data line; at least one scan line; at least one common line; at least one first pixel, the first pixel comprising a first thin film transistor and a first pixel An electrode, the first thin film transistor being connected to the data line, the scan line and the first pixel electrode, the first pixel electrode being insulated from the common line; and at least one dark-dotted pixel The dark-dotted pixel is formed by darkening a second pixel of the thin film transistor array substrate, and the dark-spotted pixel includes a second thin film transistor and a second pixel electrode The second thin film transistor is connected to the scan line and the second pixel electrode, the second thin film transistor is disconnected from the data line, and the second pixel electrode is in common with the An insulating layer is disposed between the lines, the second pixel electrode is electrically connected to the common line; and the second thin film transistor includes a second gate and a second a second drain, an area of the first overlapping portion of the second source and the second gate is zero, and the second drain and the second of the second gate The area of the overlap is also zero.
在上述薄膜晶体管阵列基板中，所述断开连接状态是通过对所述第二薄膜晶体管和所述数据线之间的连接线进行切割，以使所述第二薄膜晶体管和所述数据线绝缘来形成的。In the above thin film transistor array substrate, the disconnected state is by cutting a connection line between the second thin film transistor and the data line to insulate the second thin film transistor and the data line To form.
在上述薄膜晶体管阵列基板中，所述第二薄膜晶体管和所述数据线之间的连接线是利用第一激光来进行切割的。In the above thin film transistor array substrate, a connection line between the second thin film transistor and the data line is cut using a first laser.
在上述薄膜晶体管阵列基板中，所述第二薄膜晶体管和所述数据线之间的连接线是通过滴入第一腐蚀液体来进行切割的。In the above thin film transistor array substrate, a connection line between the second thin film transistor and the data line is cut by dropping a first etching liquid.
在上述薄膜晶体管阵列基板中，所述电性连接状态是通过在所述第二像素电极的表面的预定位置上形成一凹洞，并在所述凹洞内设置电性连接件来形成的；其中，所述第二像素电极和所述公共线通过所述电性连接件电性连接。In the above-mentioned thin film transistor array substrate, the electrical connection state is formed by forming a recess at a predetermined position on the surface of the second pixel electrode and providing an electrical connection member in the recess; The second pixel electrode and the common line are electrically connected by the electrical connection.
在上述薄膜晶体管阵列基板中，所述凹洞是通过利用第二激光照射所述预定位置来形成的。In the above thin film transistor array substrate, the recess is formed by irradiating the predetermined position with a second laser.
在上述薄膜晶体管阵列基板中，所述凹洞在第一方向上贯穿所述第二像素电极和所述绝缘层，所述第一方向为垂直于所述第二像素电极所在的平面的方向。In the above thin film transistor array substrate, the recess penetrates the second pixel electrode and the insulating layer in a first direction, and the first direction is a direction perpendicular to a plane in which the second pixel electrode is located.
在上述薄膜晶体管阵列基板中，所述凹洞是通过在所述预定位置滴入第二腐蚀液体来形成的。In the above thin film transistor array substrate, the recess is formed by dropping a second etching liquid at the predetermined position.
一种薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括：至少一数据线；至少一扫描线；至少一公共线；至少一第一像素，所述第一像素包括第一薄膜晶体管和第一像素电极，所述第一薄膜晶体管与所述数据线、所述扫描线和所述第一像素电极连接，所述第一像素电极与所述公共线绝缘；以及至少一经过暗点化处理的像素，所述经过暗点化处理的像素是对所述薄膜晶体管阵列基板的第二像素进行暗点化处理来形成的，所述经过暗点化处理的像素包括第二薄膜晶体管和第二像素电极，其中，所述第二薄膜晶体管与所述扫描线和所述第二像素电极连接，所述第二薄膜晶体管与所述数据线处于断开连接状态，所述第二像素电极与所述公共线之间设置有绝缘层，所述第二像素电极与所述公共线处于电性连接状态。A thin film transistor array substrate, comprising: at least one data line; at least one scan line; at least one common line; at least one first pixel, the first pixel comprising a first thin film transistor and a first pixel An electrode, the first thin film transistor being connected to the data line, the scan line and the first pixel electrode, the first pixel electrode being insulated from the common line; and at least one dark-dotted pixel The dark-dotted pixel is formed by darkening a second pixel of the thin film transistor array substrate, and the dark-spotted pixel includes a second thin film transistor and a second pixel electrode The second thin film transistor is connected to the scan line and the second pixel electrode, the second thin film transistor is disconnected from the data line, and the second pixel electrode is in common with the An insulating layer is disposed between the lines, and the second pixel electrode is electrically connected to the common line.
在上述薄膜晶体管阵列基板中，所述断开连接状态是通过对所述第二薄膜晶体管和所述数据线之间的连接线进行切割，以使所述第二薄膜晶体管和所述数据线绝缘来形成的。In the above thin film transistor array substrate, the disconnected state is by cutting a connection line between the second thin film transistor and the data line to insulate the second thin film transistor and the data line To form.
在上述薄膜晶体管阵列基板中，所述第二薄膜晶体管和所述数据线之间的连接线是利用第一激光来进行切割的。In the above thin film transistor array substrate, a connection line between the second thin film transistor and the data line is cut using a first laser.
在上述薄膜晶体管阵列基板中，所述第二薄膜晶体管和所述数据线之间的连接线是通过滴入第一腐蚀液体来进行切割的。In the above thin film transistor array substrate, a connection line between the second thin film transistor and the data line is cut by dropping a first etching liquid.
在上述薄膜晶体管阵列基板中，所述电性连接状态是通过在所述第二像素电极的表面的预定位置上形成一凹洞，并在所述凹洞内设置电性连接件来形成的；其中，所述第二像素电极和所述公共线通过所述电性连接件电性连接。In the above-mentioned thin film transistor array substrate, the electrical connection state is formed by forming a recess at a predetermined position on the surface of the second pixel electrode and providing an electrical connection member in the recess; The second pixel electrode and the common line are electrically connected by the electrical connection.
在上述薄膜晶体管阵列基板中，所述凹洞是通过利用第二激光照射所述预定位置来形成的。In the above thin film transistor array substrate, the recess is formed by irradiating the predetermined position with a second laser.
在上述薄膜晶体管阵列基板中，所述凹洞在第一方向上贯穿所述第二像素电极和所述绝缘层，所述第一方向为垂直于所述第二像素电极所在的平面的方向。In the above thin film transistor array substrate, the recess penetrates the second pixel electrode and the insulating layer in a first direction, and the first direction is a direction perpendicular to a plane in which the second pixel electrode is located.
在上述薄膜晶体管阵列基板中，所述凹洞是通过在所述预定位置滴入第二腐蚀液体来形成的。In the above thin film transistor array substrate, the recess is formed by dropping a second etching liquid at the predetermined position.
一种上述薄膜晶体管阵列基板的像素暗点化处理方法，所述方法包括：对所述第二薄膜晶体管和所述数据线之间的连接线进行切割，以使所述第二薄膜晶体管和所述数据线绝缘；在所述第二像素电极的表面的预定位置上形成一凹洞；以及在所述凹洞内设置电性连接件，以使所述第二像素电极和所述公共线通过所述电性连接件电性连接。A pixel dark spot processing method for the above thin film transistor array substrate, the method comprising: cutting a connection line between the second thin film transistor and the data line, so that the second thin film transistor and the a data line is insulated; a recess is formed at a predetermined position on a surface of the second pixel electrode; and an electrical connection is disposed in the recess to pass the second pixel electrode and the common line The electrical connectors are electrically connected.
在上述像素暗点化处理方法中，所述对所述第二薄膜晶体管和所述数据线之间的连接线进行切割的步骤包括：利用第一激光对所述第二薄膜晶体管和所述数据线之间的连接线进行切割。In the above pixel darkening processing method, the step of cutting a connection line between the second thin film transistor and the data line includes: using the first laser to the second thin film transistor and the data The connecting line between the lines is cut.
在上述像素暗点化处理方法中，所述在所述第二像素电极的表面的预定位置上形成一凹洞的步骤包括：利用第二激光照射所述预定位置，以在所述预定位置上形成所述凹洞。In the above pixel dark spot processing method, the step of forming a recess at a predetermined position of a surface of the second pixel electrode includes: illuminating the predetermined position with a second laser to be at the predetermined position The cavity is formed.
在上述像素暗点化处理方法中，所述凹洞在第一方向上贯穿所述第二像素电极和所述绝缘层，所述第一方向为垂直于所述第二像素电极所在的平面的方向。In the pixel darkening processing method, the recess penetrates the second pixel electrode and the insulating layer in a first direction, and the first direction is perpendicular to a plane where the second pixel electrode is located direction.
有益效果 Beneficial effect
相对现有技术，本发明能使得所述经过暗点化处理的像素中的第二像素电极的相对电势为0，所述经过暗点化处理的像素所对应的液晶分子无法通过所述第二像素电极的电压差变换进行偏转，因此，与所述经过暗点化处理的像素对应的区域显示为常暗态。Compared with the prior art, the present invention can make the relative potential of the second pixel electrode in the dark-spotted pixel be 0, and the liquid crystal molecules corresponding to the dark-spotted pixel cannot pass the second The voltage difference conversion of the pixel electrode is deflected, and therefore, the area corresponding to the darkened pixel is displayed as a normally dark state.
附图说明DRAWINGS
图1为本发明的薄膜晶体管阵列基板的示意图；1 is a schematic view of a thin film transistor array substrate of the present invention;
图2为图1中的第二像素在形成凹洞前的A-A’截面示意图；2 is a schematic cross-sectional view of the A-A' of the second pixel of FIG. 1 before forming a recess;
图3为图1中的第二像素在形成凹洞后的A-A’截面示意图；3 is a schematic cross-sectional view of the A-A' of the second pixel of FIG. 1 after forming a recess;
图4为在图1中的凹洞内设置电性连接件的第一实施例的A-A’截面示意图；Figure 4 is a cross-sectional view showing the A-A' of the first embodiment in which the electrical connecting member is disposed in the recess of Figure 1;
图5为在图1中的凹洞内设置电性连接件的第二实施例的A-A’截面示意图；Figure 5 is a cross-sectional view of the A-A' of the second embodiment in which the electrical connector is disposed in the recess of Figure 1;
图6为图1中经过暗点化处理的像素的等效电路图；6 is an equivalent circuit diagram of a pixel subjected to dark dot processing in FIG. 1;
图7为本发明的薄膜晶体管阵列基板的像素暗点化处理方法的流程图。FIG. 7 is a flowchart of a method for processing a pixel dark spot of the thin film transistor array substrate of the present invention.
本发明的最佳实施方式BEST MODE FOR CARRYING OUT THE INVENTION
本说明书所使用的词语“实施例”意指用作实例、示例或例证。此外，本说明书和所附权利要求中所使用的冠词“一”一般地可以被解释为意指“一个或多个”，除非另外指定或从上下文清楚导向单数形式。The word "embodiment" as used in this specification is intended to serve as an example, instance, or illustration. In addition, the articles "a" or "an" or "an"
参考图1，图1为本发明的薄膜晶体管阵列基板的示意图。Referring to FIG. 1, FIG. 1 is a schematic diagram of a thin film transistor array substrate of the present invention.
本实施例的薄膜晶体管阵列基板包括至少一数据线102、至少一扫描线101、至少一公共线103、至少一第一像素以及至少一经过暗点化处理的像素。The thin film transistor array substrate of this embodiment includes at least one data line 102, at least one scan line 101, at least one common line 103, at least one first pixel, and at least one dark-dotted pixel.
其中，所述第一像素包括第一薄膜晶体管104和第一像素电极106，所述第一薄膜晶体管104与所述数据线102、所述扫描线101和所述第一像素电极106连接，所述第一像素电极106与所述公共线103绝缘。具体地，所述第一薄膜晶体管104的第一栅极与所述扫描线101连接，所述第一薄膜晶体管104的第一源极与所述数据线102连接，所述第一薄膜晶体管104的漏极与所述第一像素电极106连接。所述第一像素电极106和所述公共线103之间设置有绝缘层201。The first pixel includes a first thin film transistor 104 and a first pixel electrode 106, and the first thin film transistor 104 is connected to the data line 102, the scan line 101, and the first pixel electrode 106. The first pixel electrode 106 is insulated from the common line 103. Specifically, a first gate of the first thin film transistor 104 is connected to the scan line 101, and a first source of the first thin film transistor 104 is connected to the data line 102. The first thin film transistor 104 is connected. The drain is connected to the first pixel electrode 106. An insulating layer 201 is disposed between the first pixel electrode 106 and the common line 103.
所述经过暗点化处理的像素是对所述薄膜晶体管阵列基板的第二像素进行暗点化处理来形成的，所述经过暗点化处理的像素包括第二薄膜晶体管105和第二像素电极107。The dark-dotted pixel is formed by darkening a second pixel of the thin film transistor array substrate, and the dark-dotted pixel includes a second thin film transistor 105 and a second pixel electrode 107.
所述第二薄膜晶体管105与所述扫描线101和所述第二像素电极107连接，具体地，所述第二薄膜晶体管105的第二栅极1051与所述扫描线101连接，所述第二薄膜晶体管105的第二漏极1053与所述第二像素电极107连接。The second thin film transistor 105 is connected to the scan line 101 and the second pixel electrode 107. Specifically, the second gate electrode 1051 of the second thin film transistor 105 is connected to the scan line 101. The second drain electrode 1053 of the second thin film transistor 105 is connected to the second pixel electrode 107.
所述第二薄膜晶体管105与所述数据线102处于断开连接状态，所述第二像素电极107与所述公共线103之间设置有所述绝缘层201，所述第二像素电极107与所述公共线103处于电性连接状态。The second thin film transistor 105 is disconnected from the data line 102, and the insulating layer 201 is disposed between the second pixel electrode 107 and the common line 103, and the second pixel electrode 107 is The common line 103 is in an electrically connected state.
在本实施例中，所述断开连接状态是通过对所述第二薄膜晶体管105和所述数据线102之间的连接线进行切割，以使所述第二薄膜晶体管105和所述数据线102绝缘来形成的。In this embodiment, the disconnected state is performed by cutting a connection line between the second thin film transistor 105 and the data line 102 to make the second thin film transistor 105 and the data line 102 insulation is formed.
其中，所述第二薄膜晶体管105和所述数据线102之间的连接线是利用第一激光来进行切割的。The connection line between the second thin film transistor 105 and the data line 102 is cut by using a first laser.
作为一种可替代方案，所述断开连接状态可以是通过刻蚀的方式对所述连接线进行切割来形成的，例如，可以是通过滴入第一腐蚀液体（例如，酸性液体）的方式对所述连接线进行切割来形成的。As an alternative, the disconnected state may be formed by cutting the connecting wire by etching, for example, by dropping a first corrosive liquid (for example, an acidic liquid). The connecting line is cut to form.
参考图2至图4，图2为图1中的第二像素在形成凹洞110前的A-A’截面示意图，图3为图1中的第二像素在形成所述凹洞110后的A-A’截面示意图，图4为在图1中的所述凹洞110内设置电性连接件401的第一实施例的A-A’截面示意图。Referring to FIG. 2 to FIG. 4 , FIG. 2 is a schematic cross-sectional view of the second pixel of FIG. 1 before forming the recess 110 , and FIG. 3 is the second pixel of FIG. 1 after the recess 110 is formed. A-A' is a schematic cross-sectional view, and FIG. 4 is a cross-sectional view taken along line AA' of the first embodiment in which the electrical connector 401 is disposed in the cavity 110 of FIG.
在本实施例中，所述电性连接状态是通过在所述第二像素电极107的表面的预定位置109上形成所述凹洞110，并在所述凹洞110内设置所述电性连接件401来形成的。In the embodiment, the electrical connection state is formed by forming the cavity 110 at a predetermined position 109 on the surface of the second pixel electrode 107, and the electrical connection is disposed in the cavity 110. Piece 401 is formed.
在本实施例中，所述凹洞110是通过利用第二激光照射所述预定位置109来形成的。在利用第二激光照射所述预定位置109的过程中，所述第二激光的激发作用可能会使得所述第二像素电极107中部分的金属材料/金属氧化物材料被掀开，从而形成第一掀开部1071；或者，所述第二激光的激发作用可能会使得所述公共线103的部分金属材料/金属氧化物材料被掀开，从而形成第二掀开部。In the present embodiment, the recess 110 is formed by irradiating the predetermined position 109 with a second laser. In the process of illuminating the predetermined position 109 with the second laser, the excitation of the second laser may cause a portion of the metal material/metal oxide material in the second pixel electrode 107 to be cleaved, thereby forming a An opening portion 1071; or the excitation of the second laser light may cause a portion of the metal material/metal oxide material of the common line 103 to be cleaved to form a second split portion.
所述第一掀开部1071往往会附着于所述凹洞110的洞口边缘，所述第二掀开部往往会附着于所述凹洞110的洞底边缘，部分所述第一掀开部1071或所述第二掀开部甚至会同时与所述第二像素电极107和所述公共线103接触，从而使得所述第二像素电极107和所述公共线103电性连接。The first split portion 1071 tends to adhere to the edge of the hole of the recess 110, and the second split portion tends to adhere to the bottom edge of the recess 110, and the first split portion The second opening portion 1071 or the second opening portion may be in contact with the second pixel electrode 107 and the common line 103 at the same time, so that the second pixel electrode 107 and the common line 103 are electrically connected.
但是，部分所述第一掀开部1071或所述第二掀开部同时与所述第二像素电极107和所述公共线103接触这一事件是概率事件（即，很少会发生的事件），本发明在所述凹洞110处设置所述电性连接件401是基于上述现象而作出的改进，因此，本发明的技术方案有利于确保所述经过暗点化处理的像素中的第二像素电极107与所述公共线103电性连接。However, the event that some of the first split portion 1071 or the second split portion simultaneously contacts the second pixel electrode 107 and the common line 103 is a probability event (ie, an event that rarely occurs) The present invention provides the electrical connector 401 at the recess 110 based on the above-described phenomenon. Therefore, the technical solution of the present invention is advantageous for ensuring the number of pixels in the dark-dot processing. The two-pixel electrode 107 is electrically connected to the common line 103.
作为一种可替代方案，所述凹洞110可以是对所述预定位置109进行刻蚀来形成的，例如，所述凹洞110可以是通过在所述预定位置109滴入第二腐蚀液体（例如，酸性液体）来形成的。As an alternative, the recess 110 may be formed by etching the predetermined position 109. For example, the recess 110 may be by dropping a second corrosive liquid at the predetermined position 109 ( For example, an acidic liquid is formed.
其中，所述第二像素电极107和所述公共线103通过所述电性连接件401电性连接。所述预定位置109为所述第二像素电极107与所述公共线103的重叠部分中的一个区域。The second pixel electrode 107 and the common line 103 are electrically connected through the electrical connector 401. The predetermined position 109 is one of overlapping portions of the second pixel electrode 107 and the common line 103.
所述凹洞110在第一方向上贯穿所述第二像素电极107和所述绝缘层201，所述第一方向为垂直于所述第二像素电极107所在的平面的方向。进一步地，所述凹洞110在所述第一方向上延伸至所述公共线103内部。The recess 110 penetrates the second pixel electrode 107 and the insulating layer 201 in a first direction, and the first direction is a direction perpendicular to a plane in which the second pixel electrode 107 is located. Further, the recess 110 extends inside the common line 103 in the first direction.
在本实施例中，所述电性连接件401填充所述凹洞110。所述电性连接件401为金属（例如，铁、铜等）、合金、导电胶等材料。In the embodiment, the electrical connector 401 fills the cavity 110. The electrical connector 401 is a metal (eg, iron, copper, etc.), an alloy, a conductive paste, or the like.
所述电性连接件401可以是通过激光气相成膜（Laser Chemical Vapor Deposition）的方式在所述凹洞110处沉积导电材料（例如，铁、铜、合金、导电胶等）来形成的。The electrical connector 401 may be formed by laser gas phase film formation (Laser Chemical Vapor) The manner of Deposition) is formed by depositing a conductive material (for example, iron, copper, alloy, conductive paste, etc.) at the cavity 110.
参考图5，图5为在图1中的所述凹洞110内设置所述电性连接件401的第二实施例的A-A’截面示意图。Referring to Figure 5, there is shown a cross-sectional view of the second embodiment of the electrical connector 401 in the recess 110 of Figure 1 taken along line A-A'.
在本实施例中，所述电性连接件401附着在所述凹洞110的底面和侧壁上，即，所述导电材料涂布在所述凹洞110的所述底面和所述侧壁上。所述导电材料可以通过溅射或喷涂的方式涂布在所述凹洞110的所述底面和所述侧壁上。In this embodiment, the electrical connector 401 is attached to the bottom surface and the sidewall of the recess 110, that is, the conductive material is coated on the bottom surface and the sidewall of the recess 110. on. The conductive material may be coated on the bottom surface and the sidewall of the recess 110 by sputtering or spraying.
如图6所示，图6为图1中经过暗点化处理的像素的等效电路图。在本发明的薄膜晶体管阵列基板中，所述经过暗点化处理的像素包括第二薄膜晶体管105、液晶电容（由所述第二像素电极107和与所述薄膜晶体管阵列基板相对设置的彩色滤光片基板上的公共电极构成）601和存储电容602。所述第二薄膜晶体管105的所述第二源极1052与所述数据线102之间的所述连接线在断开处108被切断，即，所述第二源极1052与所述数据线102在所述断开处108断开连接；所述第二像素电极107与所述公共线103通过连接线建立电性连接。As shown in FIG. 6, FIG. 6 is an equivalent circuit diagram of a pixel subjected to dark dot processing in FIG. In the thin film transistor array substrate of the present invention, the dark-dotted pixel includes a second thin film transistor 105, a liquid crystal capacitor (by the second pixel electrode 107 and a color filter disposed opposite to the thin film transistor array substrate) The common electrode on the light sheet substrate constitutes 601 and the storage capacitor 602. The connection line between the second source 1052 of the second thin film transistor 105 and the data line 102 is cut off at the disconnection 108, that is, the second source 1052 and the data line The disconnection 108 is disconnected at the disconnection 108; the second pixel electrode 107 and the common line 103 are electrically connected through a connection line.
实际上，在所述第二薄膜晶体管105中，所述第二源极1052和所述第二栅极1051在所述第一方向上具有第一重叠部分，所述第二漏极1053和所述第二栅极1051在所述第一方向上也具有第二重叠部分；因此，所述第二源极1052和所述第二栅极1051构成栅源电容Cgs（图中未示出），所述第二漏极1053和所述第二栅极1051构成栅漏电容Cgd（图中未示出）。In fact, in the second thin film transistor 105, the second source 1052 and the second gate 1051 have a first overlapping portion in the first direction, and the second drain 1053 and the The second gate electrode 1051 also has a second overlapping portion in the first direction; therefore, the second source electrode 1052 and the second gate electrode 1051 constitute a gate-source capacitance Cgs (not shown), The second drain 1053 and the second gate 1051 constitute a gate drain capacitance Cgd (not shown).
在接收到扫描信号后，所述第二薄膜晶体管105会打开所述第二源极1052和所述第二漏极1053之间的电流通道，为了避免所述栅源电容上的电荷通过所述电流通道流通到所述第二漏极1053，并传输给所述第二像素电极107，在本发明的薄膜晶体管阵列基板中，所述第二源极1052与所述第二栅极1051的所述第一重叠部分的面积为零，即，所述栅源电容消失（不存在）。所述第一重叠部分的面积为零这一状态是通过激光切割、蚀刻等方式将所述源极的所述第一重叠部分移除来形成的。After receiving the scan signal, the second thin film transistor 105 opens a current path between the second source 1052 and the second drain 1053, in order to prevent the charge on the gate source capacitor from passing through the The current channel flows to the second drain electrode 1053 and is transmitted to the second pixel electrode 107. In the thin film transistor array substrate of the present invention, the second source electrode 1052 and the second gate electrode 1051 are disposed. The area of the first overlapping portion is zero, that is, the gate source capacitance disappears (does not exist). The state in which the area of the first overlapping portion is zero is formed by removing the first overlapping portion of the source by laser cutting, etching, or the like.
同样，为了避免所述栅漏电容上的电荷传输给所述第二像素电极107，在本发明的薄膜晶体管阵列基板中，所述第二漏极1053与所述第二栅极1051的所述第二重叠部分的面积也为零，即，所述栅漏电容消失（不存在）。同样，所述第二重叠部分的面积为零这一状态也是通过激光切割或蚀刻等方式将所述漏极的所述第二重叠部分移除来形成的。Also, in order to prevent the charge on the gate-drain capacitance from being transmitted to the second pixel electrode 107, in the thin film transistor array substrate of the present invention, the second drain 1053 and the second gate 1051 are The area of the second overlapping portion is also zero, that is, the gate-drain capacitance disappears (does not exist). Also, the state in which the area of the second overlapping portion is zero is also formed by removing the second overlapping portion of the drain by laser cutting or etching or the like.
在本发明的薄膜晶体管阵列基板中，所述经过暗点化处理的像素中的第二像素电极107的相对电势为0。在本发明的薄膜晶体管阵列基板所对应的液晶盒（Liquid Crystal Cell）通电后，所述经过暗点化处理的像素所对应的像素电压为0，所述经过暗点化处理的像素所对应的液晶分子无法通过所述第二像素电极107的电压差变换进行偏转，因此，所述液晶盒中与所述经过暗点化处理的像素对应的区域显示为常暗态。In the thin film transistor array substrate of the present invention, the relative potential of the second pixel electrode 107 in the dark-dotted pixel is zero. Liquid crystal cell corresponding to the thin film transistor array substrate of the present invention (Liquid Crystal After the cell is energized, the pixel voltage corresponding to the dark-spotted pixel is 0, and the liquid crystal molecules corresponding to the dark-spotted pixel cannot be converted by the voltage difference of the second pixel electrode 107. Deflection, therefore, the area of the liquid crystal cell corresponding to the darkened pixel is displayed as a normally dark state.
图7为本发明的薄膜晶体管阵列基板的像素暗点化处理方法的流程图。FIG. 7 is a flowchart of a method for processing a pixel dark spot of the thin film transistor array substrate of the present invention.
本实施例的薄膜晶体管阵列基板的像素暗点化处理方法包括以下步骤：The pixel dark spot processing method of the thin film transistor array substrate of this embodiment includes the following steps:
步骤701，对所述第二薄膜晶体管105和所述数据线102之间的连接线进行切割，以使所述第二薄膜晶体管105和所述数据线102绝缘；Step 701, cutting a connection line between the second thin film transistor 105 and the data line 102 to insulate the second thin film transistor 105 from the data line 102;
步骤702，在所述第二像素电极107的表面的预定位置109上形成一凹洞110；Step 702, forming a recess 110 at a predetermined position 109 of the surface of the second pixel electrode 107;
步骤703，在所述凹洞110内设置所述电性连接件401，以使所述第二像素电极107和所述公共线103通过所述电性连接件401电性连接。Step 703, the electrical connector 401 is disposed in the recess 110 to electrically connect the second pixel electrode 107 and the common line 103 through the electrical connector 401.
在本实施例中，所述对所述第二薄膜晶体管105和所述数据线102之间的连接线进行切割的步骤包括：In this embodiment, the step of cutting the connection line between the second thin film transistor 105 and the data line 102 includes:
利用第一激光对所述第二薄膜晶体管105和所述数据线102之间的连接线进行切割。The connection line between the second thin film transistor 105 and the data line 102 is cut by a first laser.
或者，作为一种可替代方案，通过刻蚀的方式对所述连接线进行切割，例如，通过滴入第一腐蚀液体（例如，酸性液体）的方式对所述连接线进行切割。Alternatively, as an alternative, the connecting line is cut by etching, for example, by dropping a first etching liquid (for example, an acidic liquid).
在本实施例中，所述在所述第二像素电极107的表面的预定位置109上形成所述凹洞110的步骤包括：In this embodiment, the step of forming the recess 110 on the predetermined position 109 of the surface of the second pixel electrode 107 includes:
利用第二激光照射所述预定位置109，以在所述预定位置109上形成所述凹洞110。The predetermined position 109 is illuminated with a second laser to form the recess 110 at the predetermined position 109.
或者，作为一种可替代方案，对所述预定位置109进行刻蚀，以在所述预定位置109上形成所述凹洞110，例如，在所述预定位置109滴入第二腐蚀液体（例如，酸性液体）来形成所述凹洞110。Alternatively, as an alternative, the predetermined location 109 is etched to form the recess 110 at the predetermined location 109, for example, a second etching liquid is dropped at the predetermined location 109 (eg, The acidic liquid) is used to form the recess 110.
其中，所述预定位置109为所述第二像素电极107与所述公共线103的重叠部分中的一个区域。The predetermined position 109 is one of the overlapping portions of the second pixel electrode 107 and the common line 103.
在本实施例中，所述凹洞110在第一方向上贯穿所述第二像素电极107和所述绝缘层201，所述第一方向为垂直于所述第二像素电极107所在的平面的方向。In the embodiment, the recess 110 penetrates the second pixel electrode 107 and the insulating layer 201 in a first direction, and the first direction is perpendicular to a plane where the second pixel electrode 107 is located. direction.
进一步地，所述凹洞110在所述第一方向上延伸至所述公共线103内部。Further, the recess 110 extends inside the common line 103 in the first direction.
在本实施例中，所述在所述凹洞110内设置所述电性连接件401的步骤包括：In this embodiment, the step of disposing the electrical connector 401 in the cavity 110 includes:
通过激光气相成膜的方式在所述凹洞110处沉积导电材料（例如，铁、铜、合金、导电胶等）来形成所述电性连接件401。A conductive material (for example, iron, copper, alloy, conductive paste, or the like) is deposited at the recess 110 by laser vapor phase film formation to form the electrical connector 401.
其中，所述电性连接件401可以填充所述凹洞110。The electrical connector 401 can fill the cavity 110.
此外，作为一种可替代方案，所述在所述凹洞110内设置所述电性连接件401的步骤包括：In addition, as an alternative, the step of disposing the electrical connector 401 in the cavity 110 includes:
通过溅射或喷涂的方式将所述导电材料涂布在所述凹洞110的所述底面和所述侧壁上，以形成所述电性连接件401。The conductive material is coated on the bottom surface and the sidewall of the recess 110 by sputtering or spraying to form the electrical connector 401.
其中，所述电性连接件401附着在所述凹洞110的底面和侧壁上，即，所述导电材料涂布在所述凹洞110的所述底面和所述侧壁上。The electrical connector 401 is attached to the bottom surface and the sidewall of the recess 110, that is, the conductive material is coated on the bottom surface and the sidewall of the recess 110.
本发明的薄膜晶体管阵列基板的像素暗点化处理方法还包括以下步骤：The pixel dark spot processing method of the thin film transistor array substrate of the present invention further includes the following steps:
通过激光切割、蚀刻等方式将所述源极的所述第一重叠部分移除，以使所述第一重叠部分的面积为零，其中，所述第一重叠部分为所述第二源极1052和所述第二栅极1051在所述第一方向上重叠的部分；和/或Removing the first overlapping portion of the source by laser cutting, etching, or the like such that an area of the first overlapping portion is zero, wherein the first overlapping portion is the second source a portion of the first gate 1051 and the second gate 1051 overlapping in the first direction; and/or
通过激光切割或蚀刻等方式将所述漏极的所述第二重叠部分移除，以使所述第二重叠部分的面积为零，其中，所述第二重叠部分为所述第二漏极1053和所述第二栅极1051在所述第一方向上重叠的部分。Removing the second overlapping portion of the drain by laser cutting or etching or the like such that the area of the second overlapping portion is zero, wherein the second overlapping portion is the second drain And a portion of the second gate 1051 that overlaps in the first direction.
上述技术方案有利于避免所述栅源电容上的电荷通过所述电流通道流通到所述第二漏极1053，并传输给所述第二像素电极107，以及有利于避免所述栅漏电容上的电荷传输给所述第二像素电极107。The above technical solution is advantageous for avoiding that the charge on the gate source capacitor flows through the current path to the second drain 1053, and is transmitted to the second pixel electrode 107, and is beneficial to avoid the gate leakage capacitance. The charge is transferred to the second pixel electrode 107.
本发明的上述技术方案有利于确保所述经过暗点化处理的像素中的所述第二像素电极107与所述公共线103电性连接，从而确保对所述第二像素进行暗点化处理的成功率。The above technical solution of the present invention is advantageous for ensuring that the second pixel electrode 107 in the dark-spotted pixel is electrically connected to the common line 103, thereby ensuring darkening of the second pixel. Success rate.
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。In the above, the present invention has been disclosed in the above preferred embodiments, but the preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various modifications without departing from the spirit and scope of the invention. The invention is modified and retouched, and the scope of the invention is defined by the scope defined by the claims.

Claims (20)

  1. 一种薄膜晶体管阵列基板，其中A thin film transistor array substrate, wherein
    所述薄膜晶体管阵列基板包括：The thin film transistor array substrate includes:
    至少一数据线；At least one data line;
    至少一扫描线；At least one scan line;
    至少一公共线；At least one public line;
    至少一第一像素，所述第一像素包括第一薄膜晶体管和第一像素电极，所述第一薄膜晶体管与所述数据线、所述扫描线和所述第一像素电极连接，所述第一像素电极与所述公共线绝缘；以及At least one first pixel, the first pixel includes a first thin film transistor and a first pixel electrode, and the first thin film transistor is connected to the data line, the scan line, and the first pixel electrode, a pixel electrode is insulated from the common line;
    至少一经过暗点化处理的像素，所述经过暗点化处理的像素是对所述薄膜晶体管阵列基板的第二像素进行暗点化处理来形成的，所述经过暗点化处理的像素包括第二薄膜晶体管和第二像素电极，其中，所述第二薄膜晶体管与所述扫描线和所述第二像素电极连接，所述第二薄膜晶体管与所述数据线处于断开连接状态，所述第二像素电极与所述公共线之间设置有绝缘层，所述第二像素电极与所述公共线处于电性连接状态；The dark-dotted pixel is formed by darkening the second pixel of the thin film transistor array substrate, and the dark-dotted pixel includes a second thin film transistor and a second pixel electrode, wherein the second thin film transistor is connected to the scan line and the second pixel electrode, and the second thin film transistor is disconnected from the data line, An insulating layer is disposed between the second pixel electrode and the common line, and the second pixel electrode is electrically connected to the common line;
    所述第二薄膜晶体管包括第二栅极、第二源极和第二漏极，所述第二源极与所述第二栅极的所述第一重叠部分的面积为零，所述第二漏极与所述第二栅极的所述第二重叠部分的面积也为零。The second thin film transistor includes a second gate, a second source, and a second drain, and an area of the first overlapping portion of the second source and the second gate is zero, The area of the second overlap portion of the second drain and the second gate is also zero.
  2. 根据权利要求1所述的薄膜晶体管阵列基板，其中The thin film transistor array substrate of claim 1, wherein
    所述断开连接状态是通过对所述第二薄膜晶体管和所述数据线之间的连接线进行切割，以使所述第二薄膜晶体管和所述数据线绝缘来形成的。The disconnected state is formed by cutting a connection line between the second thin film transistor and the data line to insulate the second thin film transistor from the data line.
  3. 根据权利要求2所述的薄膜晶体管阵列基板，其中The thin film transistor array substrate according to claim 2, wherein
    所述第二薄膜晶体管和所述数据线之间的连接线是利用第一激光来进行切割的。A connection line between the second thin film transistor and the data line is cut using a first laser.
  4. 根据权利要求2所述的薄膜晶体管阵列基板，其中The thin film transistor array substrate according to claim 2, wherein
    所述第二薄膜晶体管和所述数据线之间的连接线是通过滴入第一腐蚀液体来进行切割的。A connecting line between the second thin film transistor and the data line is cut by dropping a first etching liquid.
  5. 根据权利要求1所述的薄膜晶体管阵列基板，其中The thin film transistor array substrate of claim 1, wherein
    所述电性连接状态是通过在所述第二像素电极的表面的预定位置上形成一凹洞，并在所述凹洞内设置电性连接件来形成的；The electrical connection state is formed by forming a recess at a predetermined position on a surface of the second pixel electrode and providing an electrical connection member in the recess;
    其中，所述第二像素电极和所述公共线通过所述电性连接件电性连接。The second pixel electrode and the common line are electrically connected by the electrical connection.
  6. 根据权利要求5所述的薄膜晶体管阵列基板，其中The thin film transistor array substrate according to claim 5, wherein
    所述凹洞是通过利用第二激光照射所述预定位置来形成的。The cavity is formed by irradiating the predetermined position with a second laser.
  7. 根据权利要求5所述的薄膜晶体管阵列基板，其中The thin film transistor array substrate according to claim 5, wherein
    所述凹洞在第一方向上贯穿所述第二像素电极和所述绝缘层，所述第一方向为垂直于所述第二像素电极所在的平面的方向。The recess penetrates the second pixel electrode and the insulating layer in a first direction, and the first direction is a direction perpendicular to a plane in which the second pixel electrode is located.
  8. 根据权利要求5所述的薄膜晶体管阵列基板，其中The thin film transistor array substrate according to claim 5, wherein
    所述凹洞是通过在所述预定位置滴入第二腐蚀液体来形成的。The cavity is formed by dropping a second etching liquid at the predetermined position.
  9. 一种薄膜晶体管阵列基板，其中A thin film transistor array substrate, wherein
    所述薄膜晶体管阵列基板包括：The thin film transistor array substrate includes:
    至少一数据线；At least one data line;
    至少一扫描线；At least one scan line;
    至少一公共线；At least one public line;
    至少一第一像素，所述第一像素包括第一薄膜晶体管和第一像素电极，所述第一薄膜晶体管与所述数据线、所述扫描线和所述第一像素电极连接，所述第一像素电极与所述公共线绝缘；以及At least one first pixel, the first pixel includes a first thin film transistor and a first pixel electrode, and the first thin film transistor is connected to the data line, the scan line, and the first pixel electrode, a pixel electrode is insulated from the common line;
    至少一经过暗点化处理的像素，所述经过暗点化处理的像素是对所述薄膜晶体管阵列基板的第二像素进行暗点化处理来形成的，所述经过暗点化处理的像素包括第二薄膜晶体管和第二像素电极，其中，所述第二薄膜晶体管与所述扫描线和所述第二像素电极连接，所述第二薄膜晶体管与所述数据线处于断开连接状态，所述第二像素电极与所述公共线之间设置有绝缘层，所述第二像素电极与所述公共线处于电性连接状态。The dark-dotted pixel is formed by darkening the second pixel of the thin film transistor array substrate, and the dark-dotted pixel includes a second thin film transistor and a second pixel electrode, wherein the second thin film transistor is connected to the scan line and the second pixel electrode, and the second thin film transistor is disconnected from the data line, An insulating layer is disposed between the second pixel electrode and the common line, and the second pixel electrode is electrically connected to the common line.
  10. 根据权利要求9所述的薄膜晶体管阵列基板，其中The thin film transistor array substrate according to claim 9, wherein
    所述断开连接状态是通过对所述第二薄膜晶体管和所述数据线之间的连接线进行切割，以使所述第二薄膜晶体管和所述数据线绝缘来形成的。The disconnected state is formed by cutting a connection line between the second thin film transistor and the data line to insulate the second thin film transistor from the data line.
  11. 根据权利要求10所述的薄膜晶体管阵列基板，其中The thin film transistor array substrate according to claim 10, wherein
    所述第二薄膜晶体管和所述数据线之间的连接线是利用第一激光来进行切割的。A connection line between the second thin film transistor and the data line is cut using a first laser.
  12. 根据权利要求10所述的薄膜晶体管阵列基板，其中The thin film transistor array substrate according to claim 10, wherein
    所述第二薄膜晶体管和所述数据线之间的连接线是通过滴入第一腐蚀液体来进行切割的。A connecting line between the second thin film transistor and the data line is cut by dropping a first etching liquid.
  13. 根据权利要求9所述的薄膜晶体管阵列基板，其中The thin film transistor array substrate according to claim 9, wherein
    所述电性连接状态是通过在所述第二像素电极的表面的预定位置上形成一凹洞，并在所述凹洞内设置电性连接件来形成的；The electrical connection state is formed by forming a recess at a predetermined position on a surface of the second pixel electrode and providing an electrical connection member in the recess;
    其中，所述第二像素电极和所述公共线通过所述电性连接件电性连接。The second pixel electrode and the common line are electrically connected by the electrical connection.
  14. 根据权利要求13所述的薄膜晶体管阵列基板，其中The thin film transistor array substrate according to claim 13, wherein
    所述凹洞是通过利用第二激光照射所述预定位置来形成的。The cavity is formed by irradiating the predetermined position with a second laser.
  15. 根据权利要求13所述的薄膜晶体管阵列基板，其中The thin film transistor array substrate according to claim 13, wherein
    所述凹洞在第一方向上贯穿所述第二像素电极和所述绝缘层，所述第一方向为垂直于所述第二像素电极所在的平面的方向。The recess penetrates the second pixel electrode and the insulating layer in a first direction, and the first direction is a direction perpendicular to a plane in which the second pixel electrode is located.
  16. 根据权利要求13所述的薄膜晶体管阵列基板，其中The thin film transistor array substrate according to claim 13, wherein
    所述凹洞是通过在所述预定位置滴入第二腐蚀液体来形成的。The cavity is formed by dropping a second etching liquid at the predetermined position.
  17. 一种如权利要求9所述的薄膜晶体管阵列基板的像素暗点化处理方法，其中A pixel dark spot processing method for a thin film transistor array substrate according to claim 9, wherein
    所述方法包括：The method includes:
    对所述第二薄膜晶体管和所述数据线之间的连接线进行切割，以使所述第二薄膜晶体管和所述数据线绝缘；Cutting a connection line between the second thin film transistor and the data line to insulate the second thin film transistor from the data line;
    在所述第二像素电极的表面的预定位置上形成一凹洞；以及Forming a recess at a predetermined position of a surface of the second pixel electrode;
    在所述凹洞内设置电性连接件，以使所述第二像素电极和所述公共线通过所述电性连接件电性连接。An electrical connector is disposed in the recess to electrically connect the second pixel electrode and the common line through the electrical connector.
  18. 根据权利要求17所述的像素暗点化处理方法，其中The pixel darkening processing method according to claim 17, wherein
    所述对所述第二薄膜晶体管和所述数据线之间的连接线进行切割的步骤包括：The step of cutting the connection line between the second thin film transistor and the data line includes:
    利用第一激光对所述第二薄膜晶体管和所述数据线之间的连接线进行切割。The connecting line between the second thin film transistor and the data line is cut by a first laser.
  19. 根据权利要求17所述的像素暗点化处理方法，其中The pixel darkening processing method according to claim 17, wherein
    所述在所述第二像素电极的表面的预定位置上形成一凹洞的步骤包括：The step of forming a cavity at a predetermined position on a surface of the second pixel electrode includes:
    利用第二激光照射所述预定位置，以在所述预定位置上形成所述凹洞。The predetermined position is illuminated with a second laser to form the recess at the predetermined position.
  20. 根据权利要求17所述的像素暗点化处理方法，其中The pixel darkening processing method according to claim 17, wherein
    所述凹洞在第一方向上贯穿所述第二像素电极和所述绝缘层，所述第一方向为垂直于所述第二像素电极所在的平面的方向。The recess penetrates the second pixel electrode and the insulating layer in a first direction, and the first direction is a direction perpendicular to a plane in which the second pixel electrode is located.
PCT/CN2014/086626 2014-08-26 2014-09-16 Thin film transistor array substrate and pixel darkening processing method thereof WO2016029517A1 (en)

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