WO2016006297A1 - Electronic device, manufacturing method therefor, solid-state imaging device, and insulating material - Google Patents

Electronic device, manufacturing method therefor, solid-state imaging device, and insulating material Download PDF

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WO2016006297A1
WO2016006297A1 PCT/JP2015/061809 JP2015061809W WO2016006297A1 WO 2016006297 A1 WO2016006297 A1 WO 2016006297A1 JP 2015061809 W JP2015061809 W JP 2015061809W WO 2016006297 A1 WO2016006297 A1 WO 2016006297A1
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layer
electrode
electronic device
compound semiconductor
light emitting
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PCT/JP2015/061809
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French (fr)
Japanese (ja)
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俊貴 森脇
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ソニー株式会社
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K30/00Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/04Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
    • H01S5/042Electrical excitation ; Circuits therefor
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/549Organic PV cells
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present disclosure relates to an electronic device and a manufacturing method thereof, a solid-state imaging apparatus incorporating the electronic device, and an insulating material.
  • an electronic device including a photoelectric conversion element such as an image sensor is configured, for example, by sequentially stacking a first electrode, a light emitting / receiving layer constituting a photoelectric conversion site, and a second electrode.
  • the second electrode is a transparent electrode, which collects electrons with one electrode and collects holes with the other electrode to read out photocurrent.
  • the light emitting / receiving layer is made of, for example, an organic material, it is known that the light emitting / receiving layer is deteriorated by moisture or oxygen. Therefore, for example, the deterioration of the light emitting / receiving layer is suppressed by covering the second electrode with an insulating layer functioning as a protective layer (see, for example, JP-A-2013-118363).
  • the insulating layer is composed of a single layer of a silicon oxynitride layer, or alternatively, a two-layer structure of a silicon oxynitride layer (upper layer) / aluminum oxide layer or the like (lower layer).
  • the film is formed based on the vapor phase growth method.
  • the second electrode (counter electrode) is composed of a metal, a metal oxide, a metal nitride, a metal boride, an organic conductive compound, a mixture thereof, or the like. That is, the second electrode and the insulating layer are made of completely different materials. Therefore, it is necessary to form the second electrode and the insulating layer based on different processes.
  • the insulating layer is formed based on, for example, an atomic layer volume method such as a plasma CVD method or an ALCVD method.
  • the film formation temperature at this time is 150 ° C. to 250 ° C. or 100 ° C. to 200 ° C. is there.
  • an object of the present disclosure to provide an electronic device manufacturing method capable of being manufactured in a more rational method or in a lower temperature process, an electronic device obtainable by such a method, and such an electronic device It is an object of the present invention to provide a solid-state imaging device incorporating an insulating material and an insulating material.
  • an electronic device of the present disclosure is provided.
  • the second electrode is composed of at least a quaternary compound of indium (In), gallium (Ga) and / or aluminum (Al), zinc (Zn), and oxygen (O).
  • the light emitting / receiving layer is covered with an insulating layer composed of at least a quaternary compound of indium (In), gallium (Ga) and / or aluminum (Al), zinc (Zn), and oxygen (O).
  • the composition ratio of oxygen (O) in the insulating layer is higher than the composition ratio of oxygen (O) in the second electrode.
  • the solid-state imaging device of the present disclosure for achieving the above object includes the electronic device of the present disclosure.
  • a method of manufacturing an electronic device includes: A second electrode composed of at least a quaternary compound of indium (In), gallium (Ga) and / or aluminum (Al), zinc (Zn), and oxygen (O) on the light emitting / receiving layer. Is formed based on the sputtering method, and then The light emitting / receiving layer is composed of at least a quaternary compound of indium (In), gallium (Ga) and / or aluminum (Al), zinc (Zn), and oxygen (O) based on a sputtering method.
  • the composition ratio of oxygen (O) in the insulating layer is changed to oxygen (O) in the second electrode. Higher than the composition ratio.
  • an insulating material of the present disclosure includes at least a quaternary system of indium (In), gallium (Ga) and / or aluminum (Al), zinc (Zn), and oxygen (O). It is composed of compounds.
  • the composition of the second electrode and the insulating layer and the composition ratio of oxygen are defined, and the second electrode and the insulating layer can be formed of the same kind of material.
  • the second electrode and the insulating layer can be formed of the same kind of material.
  • the effects described in the present specification are merely examples and are not limited, and may have additional effects.
  • FIG. 1A and 1B are schematic partial cross-sectional views of the electronic device of the first embodiment and its modification
  • FIG. 1C is a schematic partial cross-sectional view of the electronic device of the third embodiment
  • FIG. 2 is a graph showing the results of examining the relationship between the oxygen gas partial pressure during film formation and the internal stress of the obtained IGZO film in Example 1.
  • FIG. 3A shows an example of a result obtained by obtaining a relationship between an oxygen gas introduction amount (oxygen gas partial pressure) and a work function value of the first electrode when forming the first electrode based on the sputtering method in Example 2.
  • FIG. 3B is a graph of IV curves obtained in the electronic devices of Example 2, Example 3, and Comparative Example 2.
  • FIGS. 4A and 4B are conceptual diagrams of energy diagrams in the electronic devices of Example 2 and Comparative Example 2, respectively.
  • FIGS. 4C and 4D are work functions in the electronic devices of Example 2 and Comparative Example 2, respectively. It is a conceptual diagram which shows the correlation with the difference of the value of and an energy diagram.
  • FIG. 5A and FIG. 5B are graphs showing the correlation between the internal quantum efficiency and the difference between the work function values and the correlation between the dark current and the difference between the work function values in the electronic device of Example 2, respectively.
  • 6A and 6B are graphs showing the correlation between the internal quantum efficiency and the difference between the work function values in the electronic device of Example 3, and the correlation between the dark current and the difference between the work function values, respectively.
  • FIG. 7A and 7B are schematic partial cross-sectional views of the electronic device of Example 4.
  • FIG. FIG. 8 is a schematic partial cross-sectional view of a modification of the electronic device of the fourth embodiment.
  • FIG. 9 is a scanning transmission electron microscope image of the electronic device of Example 4.
  • FIG. 10 is a diagram showing the relationship between the series resistance value of the electronic device and the value of the work function of the material constituting the p-side electrode.
  • FIG. 11A and FIG. 11B are schematic partial cross-sectional views of the electronic device of Example 6 and its modification.
  • FIG. 12 is a conceptual diagram of the solid-state imaging device according to the seventh embodiment.
  • FIG. 13 is a diagram showing the relationship between the second electrode formed on the second compound semiconductor layer made of p-type GaN and the resistance value.
  • Example 1 (Electronic Device of the Present Disclosure and Method for Producing the Same, Electronic Device of Configuration 1-C, and Insulating Material of the Present Disclosure) 3.
  • Example 2 (Modification of Example 1, Electronic Device with Configuration 1-A, Electronic Device with Configuration 1-C) 4).
  • Example 3 (another modification of Example 1, an electronic device having a first-B configuration, and an electronic device having a first-C configuration) 5.
  • Example 4 (another modification of Example 1, electronic device having configuration 2-A) 6).
  • Example 5 (Modification of Example 4) 7).
  • Example 6 (another modification of Example 1, electronic device having the configuration 2-B) 8).
  • Example 7 Solid-state imaging device of the present disclosure) 9.
  • Example 1 Electronic Device of the Present Disclosure and Method for Producing the Same, Electronic Device of Configuration 1-C, and Insulating Material of the Present Disclosure
  • Example 3 (another modification of Example 1, an electronic device having a first-B configuration, and an electronic device having a first-C configuration) 5.
  • Example 4 (another modification of Example 1, electronic device having configuration 2-
  • the oxygen gas partial pressure when forming the insulating layer based on the sputtering method is not limited, but is preferably 0.04 Pa to 0.15 Pa.
  • the temperature at the time of forming an insulating layer based on sputtering method shall be room temperature or 22 to 28 degreeC. It is preferable.
  • the electronic device can be configured to constitute a photoelectric conversion element.
  • the electronic device of the present disclosure and the electronic device obtained by the manufacturing method of the electronic device of the present disclosure including the various preferred embodiments described above are collectively referred to as “electronic device etc. of the present disclosure”).
  • the second electrode is made of In a (Ga, Al) b Zn c O d
  • the insulating layer may be made of In a (Ga, Al) b Zn c O e (where d ⁇ e). Note that the second electrode and the insulating layer are preferably in an amorphous state.
  • the insulating layer and the second electrode are indium-gallium oxide (IGO), indium-doped gallium-zinc oxide (IGZO, In-GaZnO).
  • 4 may be made of a transparent conductive material such as aluminum oxide-doped zinc oxide (AZO), indium-zinc oxide (IZO), or gallium-doped zinc oxide (GZO). it can.
  • the internal stress of the insulating layer can be a form having a compressive stress of 10 MPa to 90 MPa.
  • the light transmittance of the insulating layer with respect to light having a wavelength of 400 nm to 660 nm can be 80% or more.
  • the light transmittance of the second electrode with respect to light having a wavelength of 400 nm to 660 nm may be 75% or more.
  • the sheet resistance value of the second electrode may be 3 ⁇ 10 ⁇ / ⁇ to 1 ⁇ 10 3 ⁇ / ⁇ . .
  • the oxygen gas partial pressure (oxygen gas introduction amount) when the second electrode and the insulating layer are formed based on the sputtering method is controlled.
  • the composition ratio of oxygen (O) in the second electrode and the insulating layer can be controlled.
  • the light emitting / receiving layer is sandwiched between the first electrode and the second electrode,
  • the difference between the work function value of the second electrode and the work function value of the first electrode may be 0.4 eV or more.
  • the electronic device of the present disclosure having such a configuration is referred to as an “electronic device having the first-A configuration” for convenience.
  • the light emitting / receiving layer is sandwiched between the first electrode and the second electrode,
  • the second electrode has a laminated structure of the second B layer and the second A layer from the light emitting / receiving layer side,
  • the work function value of the second A layer of the second electrode may be lower than the work function value of the second B layer of the second electrode.
  • the electronic device of the present disclosure having such a configuration is referred to as an “electronic device having the configuration of 1-B” for convenience.
  • the difference between the work function value of the second electrode and the work function value of the first electrode is defined, the difference between the first electrode and the second electrode is determined. When a bias voltage is applied between them, the internal quantum efficiency can be improved and the generation of dark current can be suppressed.
  • the second electrode has a two-layer structure of the second A layer and the second B layer, and the work function difference between the second B layer and the second A layer is small. Since it is defined, the work function in the second electrode can be optimized, and the transfer (transfer) of the carrier becomes easier.
  • the work function value of the second electrode is set by controlling the oxygen gas partial pressure (oxygen gas introduction amount) when forming based on the sputtering method.
  • oxygen gas partial pressure oxygen gas introduction amount
  • the work function of the second electrode can be optimized.
  • the difference between the work function value of the second electrode and the work function value of the first electrode is 0.4 eV or more. Based on this difference, an internal electric field can be generated in the light emitting / receiving layer to improve the internal quantum efficiency.
  • the thickness of the second electrode is preferably 1 ⁇ 10 ⁇ 8 m to 1 ⁇ 10 ⁇ 7 m.
  • the difference between the work function value of the second electrode 2A layer and the work function value of the second electrode layer 2B is 0.1 eV to 0.2 eV. It can be set as the structure which is. Furthermore, in these configurations, the difference between the work function value of the first electrode and the work function value of the second A layer of the second electrode is preferably 0.4 eV or more. Further, in the electronic device having the first-B configuration including the preferable configuration described above, the thickness of the second electrode is 1 ⁇ 10 ⁇ 8 m to 1 ⁇ 10 ⁇ 7 m, and the second electrode The ratio of the thickness of the 2A layer and the thickness of the second B layer of the second electrode may be 9/1 to 1/9.
  • the thickness of the second B layer is smaller than the thickness of the second A layer of the second electrode.
  • the difference between the work function value of the first electrode and the work function value of the second A layer of the second electrode is set to 0.4 eV.
  • the value of the work function of the second electrode is not limited,
  • the configuration may be 4.1 eV to 4.5 eV.
  • the second electrode includes indium-gallium oxide (IGO), Indium-doped gallium-zinc oxide (IGZO, In-GaZnO 4 ), aluminum oxide-doped zinc oxide (AZO), indium-zinc oxide (IZO), or gallium-doped zinc oxide (GZO)
  • the work function value of the second electrode made of these transparent conductive materials can be 4.1 eV to 4.5 eV, for example.
  • the first electrode is composed of indium-tin oxide (ITO), indium-zinc oxide (IZO). Or a transparent conductive material such as tin oxide (SnO 2 ).
  • the value of the work function of the 1st electrode comprised from these transparent conductive materials is 4.8 eV thru
  • the oxygen gas partial pressure (oxygen gas) when the second electrode is formed by sputtering is used.
  • the work function value of the second electrode can be controlled.
  • the work function values of the second A layer and the second B layer of the second electrode are controlled by controlling the oxygen gas partial pressure (oxygen gas introduction amount) when forming the second electrode based on the sputtering method. It can be configured.
  • the oxygen content may be lower than the oxygen content of the stoichiometric composition.
  • the oxygen content of the second A layer of the second electrode can be lower than the oxygen content of the second B layer of the second electrode.
  • the work function value of the second electrode can be controlled based on the oxygen content, and the oxygen content becomes smaller than the oxygen content of the stoichiometric composition, that is, oxygen deficiency increases. As the value of the work function decreases.
  • the first electrode is formed on the substrate, and
  • the light receiving layer may be formed on the first electrode, and the second electrode may be formed on the light emitting / light receiving layer. That is, the electronic device or the like of the present disclosure has a two-terminal electronic device structure including the first electrode and the second electrode.
  • the present invention is not limited to this, and a three-terminal electronic device structure provided with a control electrode may be used, and the current flowing can be modulated by applying a voltage to the control electrode.
  • the second electrode can function as a cathode electrode (cathode) (that is, function as an electrode that extracts electrons), while the first electrode can function as an anode electrode (anode) (that is, an electrode that extracts holes). Function as). It is also possible to adopt a structure in which a plurality of electronic devices or the like having different light absorption spectra in the light emitting / receiving layers are stacked.
  • a structure in which a substrate is formed of a silicon semiconductor substrate, a drive circuit such as an electronic device or a light emitting / receiving layer is provided on the silicon semiconductor substrate, and the electronic device is stacked on the silicon semiconductor substrate is employed.
  • the light emitting / receiving layer may be in an amorphous state or a crystal It may be in a state.
  • the organic material (organic photoelectric conversion material) constituting the light emitting / receiving layer include organic semiconductor materials, organometallic compounds, and organic semiconductor fine particles, or metal oxide as the material constituting the light emitting / receiving layer. Examples thereof include a physical semiconductor, inorganic semiconductor fine particles, a material in which a core member is covered with a shell member, and an organic-inorganic hybrid compound.
  • the electronic device or the like of the present disclosure having such a configuration is referred to as “the electronic device having the first-C configuration”. Call it.
  • an organic semiconductor material specifically, an organic dye represented by quinacridone and its derivatives, a previous period represented by Alq3 [tris (8-quinolinolato) aluminum (III)] (metal on the left side of the periodic table) Dyes obtained by chelating ions with an organic material, organometallic dyes complexed with a transition metal ion typified by zinc phthalocyanine (II), and dinaphthothienothiophene (DNTT). .
  • the organometallic compound include a dye obtained by chelating the above-described periodic ions with an organic material, and an organometallic dye complexed with a transition metal ion and an organic material.
  • organic semiconductor fine particles specifically, organic dye aggregates represented by the above-mentioned quinacridone and derivatives thereof, dye aggregates obtained by chelating the precursor ions with organic materials, and complex formation with transition metal ions and organic materials And an organic metal dye aggregate, or Prussian blue obtained by crosslinking a metal ion with a cyano group and derivatives thereof, or a complex aggregate thereof.
  • metal oxide semiconductor or inorganic semiconductor fine particles specifically, ITO, IGZO, ZnO, IZO, IrO 2 , TiO 2 , SnO 2 , SiO x , karogen [for example, sulfur (S), selenium (Se), tellurium (Te)] can be given as metal karogen semiconductors (specifically, CdS, CdSe, ZnS, CdSe / CdS, CdSe / ZnS, PbSe), ZnO, CdTe, GaAs, and Si.
  • karogen for example, sulfur (S), selenium (Se), tellurium (Te)
  • a combination of a material in which a core member is covered with a shell member that is, a combination of (core member, shell member), specifically, an organic material such as (polystyrene, polyaniline), a metal material that is difficult to ionize, or a metal that is easily ionized Metal material).
  • organic-inorganic hybrid compounds include Prussian blue in which metal ions are cross-linked with cyano groups and derivatives thereof.
  • compounds in which metal ions are infinitely cross-linked with bipyridines, oxalic acid, rubeanic acid Coordination polymer (Coordination Polymer), which is a generic name of cross-linked metal ions with polyvalent ionic acids represented by
  • various chemical methods including a coating method, a physical vapor deposition method (PVD method), and a MOCVD method are used as a method for forming a light emitting / receiving layer depending on a material to be used.
  • PVD method physical vapor deposition method
  • MOCVD method metal-organic chemical vapor deposition method
  • a coating method specifically, spin coating method; dipping method; casting method; various printing methods such as screen printing method, inkjet printing method, offset printing method, gravure printing method; stamp method; spray method; air doctor Coater method, blade coater method, rod coater method, knife coater method, squeeze coater method, reverse roll coater method, transfer roll coater method, gravure coater method, kiss coater method, cast coater method, spray coater method, slit orifice coater method, calendar
  • Various coating methods such as a coater method can be exemplified.
  • examples of the solvent include nonpolar or low polarity organic solvents such as toluene, chloroform, hexane, and ethanol.
  • various vacuum deposition methods such as an electron beam heating method, a resistance heating method, and a flash deposition method; a plasma deposition method; a bipolar sputtering method, a direct current sputtering method, a direct current magnetron sputtering method, a high frequency sputtering method, a magnetron sputtering method, Various sputtering methods such as ion beam sputtering and bias sputtering; DC (direct current) method, RF method, multi-cathode method, activation reaction method, field deposition method, high-frequency ion plating method, reactive ion plating method, etc. Examples of various ion plating methods can be given.
  • the thickness of the light emitting / receiving layer is not limited.
  • the thickness may be 1 ⁇ 10 ⁇ 10 m to 5 ⁇ 10 ⁇ 7 m. .
  • polymethyl methacrylate polymethyl methacrylate
  • PMMA polymethyl methacrylate
  • PVA polyvinyl alcohol
  • PVP polyvinyl phenol
  • PES polyethersulfone
  • PC polycarbonate
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate
  • an electronic device can be incorporated or integrated into an electronic device having a curved surface.
  • various glass substrates various glass substrates with an insulating film formed on the surface, quartz substrates, quartz substrates with an insulating film formed on the surface, silicon semiconductor substrates, silicon with an insulating film formed on the surface
  • semiconductor substrates metal substrates made of various alloys such as stainless steel, and various metals.
  • the insulating film a silicon oxide-based material (for example, SiO x or spin-on glass (SOG)); silicon nitride (SiN Y ); silicon oxynitride (SiON); aluminum oxide (Al 2 O 3 ); metal oxide or Mention may be made of metal salts.
  • a conductive substrate (a substrate made of a metal such as gold or aluminum or a substrate made of highly oriented graphite) having these insulating films formed on the surface can also be used.
  • the surface of the substrate is desirably smooth, but may have a roughness that does not adversely affect the characteristics of the light emitting / receiving layer.
  • a silanol derivative is formed on the surface of the substrate by a silane coupling method, a thin film made of a thiol derivative, a carboxylic acid derivative, a phosphoric acid derivative, or the like is formed by a SAM method, or an insulating metal salt or metal is formed by a CVD method. You may improve the adhesiveness between a 1st electrode or a 2nd electrode, and a board
  • the light emitting / receiving layer can be configured of an organic photoelectric conversion material.
  • the electronic device can be configured by a photoelectric conversion element.
  • light emission / light reception in the light emission / light reception layer (generally electromagnetic waves, including visible light, ultraviolet rays, and infrared rays) is second. It may be performed via the electrode or may be performed via the first electrode. In the latter case, it is necessary to use a substrate that is transparent to the light emitted and received.
  • the electronic device of the present disclosure including the various preferable modes and configurations described above can be applied to the electronic device constituting the solid-state imaging device of the present disclosure.
  • a semiconductor optical device typified by a semiconductor laser element or a light emitting diode includes, for example, a first compound semiconductor layer having a first conductivity type, an active layer, and a second compound having a second conductivity type different from the first conductivity type. It has a laminated structure (light emitting / receiving layer) made of a semiconductor layer, a second electrode is formed on the second compound semiconductor layer, and the first compound semiconductor layer is electrically connected to the first electrode. It has a structure.
  • FIG. 13 shows the second electrode (p-side electrode) formed on the second compound semiconductor layer made of p-type GaN.
  • the relationship between the metal which comprises and resistance value is shown.
  • the black circles indicate values before annealing, and the white circles indicate values after annealing at 500 ° C.
  • the second electrode for the second compound semiconductor layer made of p-type GaN a metal having a larger work function has a lower Schottky barrier, so that good contact characteristics tend to be obtained.
  • FIG. 13 shows that the resistance value decreases as the work function value of the metal increases.
  • a platinum group such as Pd and Pt having a work function value distributed between 5 eV and 5.65 eV, Ni, Au, and the like are used as an ohmic electrode for the second compound semiconductor layer made of p-type GaN. It has been. However, there is a strong demand for further increasing the degree of freedom in selecting the material constituting the second electrode.
  • the light emitting / receiving layer is composed of a laminated structure including a first compound semiconductor layer having a first conductivity type, an active layer, and a second compound semiconductor layer having a second conductivity type different from the first conductivity type, A second electrode is formed on the second compound semiconductor layer via a contact layer, The thickness of the contact layer is a thickness of 4 atomic layers or less, The interface between the contact layer and the second compound semiconductor layer is along the xy plane, and the lattice constant along the x axis of the crystal constituting the interface layer that is the portion of the second compound semiconductor layer in contact with the contact layer is along the x 2 and z axes.
  • the lattice constant is z 2
  • the length along the x-axis in one unit of the crystal constituting the contact layer is x C ′
  • the length along the z-axis is z C ′, (Z C '/ x C ')> (z 2 / x 2 ) It can be set as the structure which satisfies these.
  • the electronic device of the present disclosure having such a configuration is referred to as an “electronic device having a configuration of 2-A” for convenience.
  • the light emitting / receiving layer is composed of a laminated structure including a first compound semiconductor layer having a first conductivity type, an active layer, and a second compound semiconductor layer having a second conductivity type different from the first conductivity type,
  • a first electrode is formed on the first compound semiconductor layer via a contact layer,
  • the thickness of the contact layer is a thickness of 4 atomic layers or less,
  • the interface between the contact layer and the first compound semiconductor layer is along the xy plane, and the lattice constant along the x axis of the crystal constituting the interface layer that is the portion of the first compound semiconductor layer in contact with the contact layer is along the x 1 and z axes.
  • the lattice constant is z 1
  • the length along the x-axis in one unit of the crystal constituting the contact layer is x C ′′
  • the length along the z-axis is z C ′′ (Z C ′′ / x C ′′)> (z 1 / x 1 ) It can be set as the structure which satisfies these.
  • the electronic device or the like of the present disclosure having such a configuration is referred to as an “electronic device having a second-B configuration” for convenience.
  • the lattice constant in the interface layer which is a part of the second compound semiconductor layer or the first compound semiconductor layer in contact with the contact layer; Since the length of one unit of crystal constituting the contact layer satisfies a predetermined relationship, a kind of distortion occurs in the contact layer, and as a result, not only can the drive voltage be reduced.
  • the second electrode or the first electrode can be formed from a material having a low work function value, and the degree of freedom in selecting the material forming the second electrode or the first electrode can be improved.
  • the thickness of the contact layer is 4 atomic layers or less. If the thickness of the contact layer exceeds 4 atomic layers, crystal defects may occur in the contact layer, which may increase the contact resistance value.
  • the contact layer may be “layered” or may be formed in an island shape (island shape) and not in a layered state.
  • the contact layer may be configured to be pseudo-lattice matched with the interface layer of the second compound semiconductor layer.
  • pseudo-matching means that the value of x C ′ is equal to the value of x 2 , and the volume of one unit of the crystal constituting the contact layer is determined from the lattice constant of the crystal constituting the contact layer. Means equal to the required volume.
  • the contact layer can be configured to be pseudo-lattice matched with the interface layer of the first compound semiconductor layer.
  • pseudo-lattice matching means that the value of x C ′′ is equal to the value of x 1 , and the volume of one unit of the crystal constituting the contact layer is determined from the lattice constant of the crystal constituting the contact layer.
  • the lattice constant along the x-axis of the crystal forming the contact layer is expressed as x C , along the z-axis.
  • the crystal structure of the crystal constituting the interface layer of the second compound semiconductor layer (or the first compound semiconductor layer) can be a hexagonal system.
  • the laminated structure is made of a GaN-based compound semiconductor, and the contact layer has the same composition as the GaN-based compound semiconductor that forms the interface layer of the second compound semiconductor layer (or the first compound semiconductor layer).
  • the GaN-based compound semiconductor may further include a GaN-based compound semiconductor containing oxygen atoms, or the stacked structure may be formed of a GaN-based compound semiconductor, and the contact layer may be a second compound.
  • a GaN-based compound semiconductor having a composition different from that of the GaN-based compound semiconductor constituting the interface layer of the semiconductor layer (or the first compound semiconductor layer) can be used.
  • the interface layer of the second compound semiconductor layer is composed of a GaN layer
  • the electronic device having the 2-A configuration or the electronic device having the 2-B configuration including the above-described various preferable configurations of the electronic device having the 2-A configuration or the electronic device having the 2-B configuration.
  • the stacked structure may be made of a GaN-based compound semiconductor, and the contact layer may be made of one material selected from the group consisting of ZnO, ZnSe, CdO, CdS, and CdSe.
  • the electronic device having the 2-A configuration (or the configuration of the 2-B configuration) including the various preferred configurations described above of the electronic device having the 2-A configuration (or the electronic device having the 2-B configuration).
  • the value of the band gap energy of the compound semiconductor constituting the contact layer is smaller than the value of the band gap energy of the compound semiconductor constituting the interface layer of the second compound semiconductor layer (or the first compound semiconductor layer). It is preferable.
  • the electronic device having the 2-A configuration or the second-B configuration including the various preferred configurations described above of the electronic device having the 2-A configuration or the electronic device having the 2-B configuration has been described.
  • the first conductivity type may be n-type
  • the second conductivity type may be p-type.
  • the laminated structure and the contact layer are preferably formed of a GaN-based compound semiconductor.
  • compound semiconductors constituting the second compound semiconductor layer other than the interface layer, the active layer, and the first compound semiconductor layer include GaN-based compound semiconductors such as GaN, AlGaN, InGaN, and AlInGaN, and constitute the active layer.
  • the compound semiconductor to be used include InGaN and AlInGaN.
  • these compound semiconductors may contain boron (B) atoms, thallium (Tl) atoms, arsenic (As) atoms, phosphorus (P) atoms, and antimony (Sb) atoms as desired.
  • Layered structure formation methods include metalorganic chemical vapor deposition (MOCVD, MOVPE), metalorganic molecular beam epitaxy (MOMBE), and hydride gas in which halogen contributes to transport or reaction. Examples thereof include a phase growth method (HVPE method) and a plasma assisted physical vapor deposition method (PPD method).
  • trimethylgallium (TMG) and triethylgallium (TEG) can be mentioned as the organic gallium source in the MOCVD method, and ammonia gas and hydrazine can be mentioned as the nitrogen source.
  • ammonia gas and hydrazine can be mentioned as the nitrogen source.
  • aluminum (Al) or indium (In) is contained as a constituent atom of the GaN-based compound semiconductor layer
  • trimethylaluminum (TMA) may be used as the Al source
  • trimethylindium (TMI) may be used as the In source. Good.
  • monosilane (SiH 4 ) may be used as the Si source
  • cyclopentadienyl magnesium, methylcyclopentadienyl magnesium, or biscyclopentadienyl magnesium (Cp 2 Mg) may be used as the Mg source.
  • lithography technology and wet etching are used as a method of etching the laminated structure to form the ridge stripe structure.
  • a combination of technologies, a combination of lithography technology and dry etching technology can be mentioned.
  • the configuration of the laminated structure itself can be a known configuration.
  • the laminated structure is formed on an electronic device manufacturing substrate (hereinafter simply referred to as “manufacturing substrate”), and the first compound semiconductor layer, the active layer, and the second compound semiconductor layer are stacked from the manufacturing substrate side.
  • Manufacturing substrate an electronic device manufacturing substrate
  • MEE migration enhanced epitaxy
  • pulsed laser Examples thereof include a deposition method (PLD method, Pulsed Laser Deposition method), a heat treatment method, and the like.
  • the active layer may be composed of a single compound semiconductor layer, a single quantum well structure (SQW structure), or It may have a multiple quantum well structure (MQW structure).
  • An active layer having a quantum well structure has a structure in which at least one well layer and a barrier layer are stacked.
  • a compound semiconductor constituting a well layer, a compound semiconductor constituting a barrier layer InGaN, GaN), (InGaN, AlInGaN), and (InGaN, InGaN) [however, the composition of InGaN constituting the well layer and the composition of InGaN constituting the barrier layer are different].
  • the barrier layer may be composed of a layer group having a plurality of compositions.
  • the first compound semiconductor layer is provided with the first conductivity type
  • the second compound semiconductor layer and the contact layer are provided with the second conductivity type.
  • impurities may be introduced into each of the first compound semiconductor layer, the second compound semiconductor layer, and the contact layer.
  • n-type impurities added to the compound semiconductor layer include silicon (Si), sulfur (S), selenium (Se), germanium (Ge), tellurium (Te), tin (Sn), carbon (C), and titanium.
  • Ti titanium
  • O oxygen
  • Pd palladium
  • Zn zinc
  • Mg magnesium
  • carbon carbon
  • Be beryllium
  • Cd cadmium
  • Ca Calcium
  • Ba barium
  • the second electrode is in contact with the second compound semiconductor layer through the contact layer, while the first electrode is electrically connected to the first compound semiconductor layer. . That is, the first electrode is formed on the first compound semiconductor layer, or the first electrode is connected to the first compound semiconductor layer via the conductive material layer and the manufacturing substrate.
  • the first electrode is in contact with the first compound semiconductor layer through the contact layer, while the second electrode is formed on the second compound semiconductor layer.
  • the second electrode may be in contact with the second compound semiconductor layer via the contact layer, and the first electrode may be in contact with the first compound semiconductor layer via the second contact layer.
  • the first electrode is, for example, gold (Au ), Silver (Ag), palladium (Pd), platinum (Pt), nickel (Ni), Al (aluminum), Ti (titanium), tungsten (W), vanadium (V), chromium (Cr), Cu (copper) ), Zn (zinc), tin (Sn), and indium (In), it is desirable to have at least one metal (including alloys) selected from the group consisting of single layer configuration or multilayer configuration, for example, Illustrate Ti / Au, Ti / Al, Ti / Pt / Au, Ti / Al / Au, Ti / Pt / Au, Ni / Au, Ni / Au / Pt, Ni / Pt, Pd / Pt, Ag / Pd be able to.
  • the transparent conductive material layer As described above, as the transparent conductive material constituting the transparent conductive material layer, the transparent conductive material containing indium atoms [specifically, indium oxide, indium tin oxide, Sn-doped ITO, In 2 O 3 , including crystalline ITO and amorphous ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium doped gallium zinc oxide (IGZO, In -GaZnO 4 ), IFO (F-doped In 2 O 3 )], tin oxide (SnO 2 ), ATO (Sb-doped SnO 2 ), FTO (F-doped SnO 2 ), zinc oxide (Including ZnO, Al-doped ZnO, B-doped ZnO, and Ga-
  • calcium (Ca), Alkaline earth metals such as barium (Ba), alkali metals such as lithium (Li) and cesium (Cs), indium (In), magnesium (Mg), silver (Ag), gold (Au), nickel (Ni), Gold-germanium (Au—Ge) and the like can also be mentioned.
  • alkali metal oxides alkali metal fluorides, alkaline earth metal oxides, alkaline earth fluorides such as Li 2 O, Cs 2 Co 3 , Cs 2 SO 4 , MgF, LiF and CaF 2. You can also.
  • a pad electrode is provided on the first electrode or the second electrode so as to be electrically connected to an external electrode or a circuit. Also good.
  • the pad electrode is at least one metal (including alloy) selected from the group consisting of Ti (titanium), aluminum (Al), Pt (platinum), Au (gold), Ni (nickel), and Pd (palladium).
  • the pad electrode may be a Ti / Pt / Au multilayer structure, a Ti / Au multilayer structure, a Ti / Pd / Au multilayer structure, a Ti / Pd / Au multilayer structure, a Ti / Ni / Au multilayer structure, A multi-layer structure exemplified by a multi-layer structure of Ti / Ni / Au / Cr / Au can also be used.
  • the manufacturing substrate may be left, or the first compound semiconductor layer, the active layer, and the second compound may be left on the manufacturing substrate.
  • the manufacturing substrate may be removed. Specifically, the first compound semiconductor layer, the active layer, the second compound semiconductor layer, the contact layer, and the second electrode are sequentially formed on the manufacturing substrate, and the second electrode is fixed to the support substrate, and then the manufacturing substrate. And the first compound semiconductor layer may be exposed.
  • the removal of the production substrate can be performed based on an etching method or a polishing method, or can be performed based on a chemical / mechanical polishing method (CMP method).
  • alkaline aqueous solution such as sodium hydroxide aqueous solution or potassium hydroxide aqueous solution, ammonia solution + hydrogen peroxide solution, sulfuric acid solution + hydrogen peroxide solution, hydrochloric acid solution + hydrogen peroxide solution, phosphoric acid solution + hydrogen peroxide solution
  • a part of the manufacturing substrate is removed by a wet etching method using a dry etching method, a dry etching method, a lift-off method using a laser, a mechanical polishing method or the like, or a combination thereof.
  • the first compound semiconductor layer may be exposed by reducing the thickness and then performing a chemical / mechanical polishing method.
  • the contact layer and the first electrode may be sequentially formed on the exposed first compound semiconductor layer.
  • the electronic device having the 2-A configuration or the electronic device having the 2-B configuration including the various preferable configurations described above of the electronic device having the 2-A configuration or the electronic device having the 2-B configuration
  • the light generated in the active layer can be emitted to the outside from the end face (side surface) of the laminated structure, or can be emitted to the outside via the second compound semiconductor layer. It can also be set as the structure radiate
  • the manufacturing substrate may be removed as described above.
  • GaN substrates and sapphire substrates GaAs substrates, SiC substrates, alumina substrates, ZnS substrates, ZnO substrates, AlN substrates, LiMgO substrates, LiGaO 2 substrates, MgAl 2 O 4 substrates, InP substrates, Si as well as GaN substrates and sapphire substrates.
  • the substrate include those having a base layer and a buffer layer formed on the surface (main surface) of these substrates.
  • the GaN substrate is preferred because of its low defect density, but it is known that the characteristics of the GaN substrate change from polar / nonpolar / semipolar depending on the growth surface. ing.
  • transparent inorganic substrates such as glass substrates and quartz substrates
  • polyester resins such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN); polycarbonate (PC) resins
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate
  • PC polycarbonate
  • PES Polyethersulfone
  • Polyolefin resin such as polystyrene, polyethylene, polypropylene
  • Polyphenylene sulfide resin Polyvinylidene fluoride resin; Tetraacetyl cellulose resin; Brominated phenoxy resin; Aramid resin; Polyimide resin; Polystyrene resin; Polysulfone resin; Acrylic resin; Epoxy resin; Fluororesin; Silicone resin; Diacetate resin; Triacetate resin; Polyvinyl chloride resin;
  • Mention may be made of a transparent plastic substrate or a film.
  • the glass substrate include a soda glass substrate, a heat resistant glass substrate, and a quartz glass
  • the support substrate may be composed of various substrates such as a GaN substrate, a sapphire substrate, a GaAs substrate, an SiC substrate, an alumina substrate, a ZnS substrate, a ZnO substrate, a LiMgO substrate, a LiGaO 2 substrate, an MgAl 2 O 4 substrate, and an InP substrate.
  • a insulating substrate made of AlN or the like, a semiconductor substrate made of Si, SiC, Ge or the like, a metal substrate, or an alloy substrate can be used, but it is preferable to use a conductive substrate.
  • a metal substrate or an alloy substrate from the viewpoints of mechanical properties, elastic deformation, plastic deformability, heat dissipation, and the like.
  • the thickness of the support substrate include 0.05 mm to 0.5 mm.
  • a known method such as a solder bonding method, a room temperature bonding method, a bonding method using an adhesive tape, a bonding method using wax bonding, or the like can be used. From the viewpoint of ensuring, it is desirable to employ a solder bonding method or a room temperature bonding method.
  • the bonding temperature may be 400 ° C. or higher.
  • a light emitting / receiving element specifically, an edge emitting semiconductor laser element, an edge emitting superluminescent diode (SLD), a surface emitting laser element (also called vertical cavity laser, VCSEL)
  • a semiconductor light emitting device such as a light emitting diode (LED), a semiconductor optical amplifier, a solar cell, and a photosensor.
  • a semiconductor optical amplifier amplifies in the state of direct light without converting an optical signal into an electrical signal, has a laser structure that eliminates the resonator effect as much as possible, and converts incident light based on the optical gain of the semiconductor optical amplifier. Amplify.
  • a resonator is configured by optimizing the light reflectance at the first end face and the light reflectance at the second end face, and light is emitted from the first end face.
  • an external resonator may be arranged.
  • the light reflectivity at the first end face is set to a very low value
  • the light reflectivity at the second end face is set to a very high value
  • the active layer is formed without forming a resonator.
  • the light generated in step 1 is reflected at the second end face and emitted from the first end face.
  • a non-reflective coating layer (AR) or a low-reflective coating layer is formed on the first end surface
  • a high-reflective coating layer (HR) is formed on the second end surface. Is formed.
  • the light reflectance at the first end face and the second end face is set to a very low value, and the light incident from the second end face is amplified without constituting the resonator, thereby the first end face. Emanates from.
  • laser oscillation is generated by resonating light between two light reflecting layers (Distributed Bragg Reflector layer, DBR layer).
  • a non-reflective coating layer (AR) or a low-reflective coating layer is formed on the light emitting end surface or the light incident end surface. Further, a highly reflective coating layer (HR) is formed on the light reflecting end face.
  • an antireflection coating layer low reflection coating layer
  • the layered structure of a kind of layer can be mentioned, It can form based on PVD methods, such as sputtering method and a vacuum evaporation method.
  • the semiconductor laser element examples include, but are not limited to, a semiconductor laser element having a ridge stripe type separated confinement heterostructure (SCH structure, separate-confinement heterostructure).
  • a semiconductor laser element having an oblique ridge stripe type separated confinement heterostructure can be cited.
  • the axis of the semiconductor laser element and the axis of the ridge stripe structure can intersect at a predetermined angle.
  • examples of the predetermined angle ⁇ include 0.1 degrees ⁇ ⁇ ⁇ 10 degrees.
  • the axis of the ridge stripe structure is a straight line connecting the bisectors at both ends of the ridge stripe structure at the light emitting end face and the bisectors at both ends of the ridge stripe structure at the light reflecting end face.
  • the axis of the semiconductor laser element refers to an axis perpendicular to the virtual vertical plane at the light emitting end face and the virtual vertical plane at the light reflecting end face.
  • the planar shape of the ridge stripe structure may be linear or curved.
  • a tapered (flared) ridge stripe type for example, a structure that is monotonously and gradually widened in a tapered shape from the light emitting end face toward the light reflecting end face, from the light emitting end face toward the light reflecting end face, from the light emitting end face toward the light reflecting end face,
  • a semiconductor laser device having a separate confinement heterostructure including a configuration in which it is first widened and exceeds a maximum width and then narrowed
  • the ridge stripe structure may be composed of a part of the second compound semiconductor layer in the thickness direction, may be composed of the second compound semiconductor layer and the active layer, or may be composed of the second compound semiconductor layer, the active layer You may be comprised from the layer and a part of thickness direction of the 1st compound semiconductor layer.
  • the semiconductor laser element is not limited to these structures.
  • Other semiconductor laser elements include semiconductor laser elements with an index guide structure, bi-section type with a light emitting region and a saturable absorption region juxtaposed in the cavity direction, and multi-section type (multi-electrode type).
  • SAL Silicon Absorber Layer
  • WI Wood Index Guide
  • the first electrode, the second electrode, and the insulating layer are formed on the basis of the sputtering method.
  • Specific examples include a magnetron sputtering method and a parallel parallel plate sputtering method, and a plasma using a DC discharge method or an RF discharge method. There may be mentioned those using the generation method.
  • Examples include a method of thermally decomposing a metal compound, a spray method, a dipping method, and various CVD methods including an MOCVD method, an electroless plating method, and an electrolytic plating method.
  • the preferred configuration of the present disclosure has a great feature that the work function can be controlled by the oxygen flow rate (oxygen gas partial pressure, oxygen gas introduction amount).
  • an optical sensor or an image sensor can be configured by the electronic device of the present disclosure.
  • the electronic device having the configuration 2-A or the electronic device having the configuration 2-B can be applied to a display device, for example. That is, as such a display device, a projector device, an image display device, a monitor device, or the like, which has an electronic device having the configuration 2-A or an electronic device having the configuration 2-B as a light source. Examples thereof include a reflective liquid crystal display device including an electronic device or an electronic device having a configuration 2-B as a light source, a head-mounted display (HMD), a head-up display (HUD), and various types of illumination. Further, an electronic device having the configuration 2-A or an electronic device having the configuration 2-B can be used as a light source of the microscope. However, the application field of the electronic device having the configuration 2-A or the electronic device having the configuration 2-B is not limited thereto.
  • Example 1 relates to an electronic device of the present disclosure, a manufacturing method thereof, an insulating material of the present disclosure, and further relates to an electronic device having a first-C configuration.
  • a schematic cross-sectional view of the electronic device of Example 1 is shown in FIG. 1A.
  • the electronic device of Example 1 constitutes a photoelectric conversion element.
  • the electronic device of Example 1 or Examples 2 to 6 described later includes a light emitting / receiving layer 20, first electrodes 31 and 91 electrically connected to the light emitting / receiving layer 20, and the light emitting / receiving layer 20.
  • Second electrodes 32 and 92 formed thereon are provided.
  • the second electrodes 32 and 92 are composed of at least a quaternary compound of indium (In), gallium (Ga) and / or aluminum (Al), zinc (Zn), and oxygen (O). That is, it consists of a conductive amorphous oxide.
  • the light emitting / receiving layer 20 includes an insulating layer 40 made of at least a quaternary compound of indium (In), gallium (Ga) and / or aluminum (Al), zinc (Zn), and oxygen (O). , 80. That is, the insulating layers 40 and 80 are also made of an insulating amorphous oxide.
  • the composition ratio of oxygen (O) in the insulating layers 40 and 80 is higher than the composition ratio of oxygen (O) in the second electrodes 32 and 92.
  • the insulating material of Example 1 (specifically, the material constituting the insulating layers 40 and 80) is indium (In), gallium (Ga) and / or aluminum (Al), and zinc (Zn). And at least a quaternary compound with oxygen (O). That is, the insulating material is also made of an insulating amorphous oxide.
  • the insulating layers 40 and 80 and the second electrodes 32 and 92 are made of indium-doped gallium-zinc oxide (IGZO, It is made of a transparent conductive material such as In—GaZnO 4 ). That is, the second electrodes 32 and 92 are made of In a (Ga, Al) b Zn c O d , and the insulating layers 40 and 80 are In a (Ga, Al) b Zn c O e (where d ⁇ e ). Note that “a”, “b”, “c”, “d”, and “e” can take various values.
  • the second electrodes 32 and 92 and the insulating layers 40 and 80 are made of indium-doped gallium-zinc oxide (IGZO), indium-gallium oxide (IGO), aluminum oxide-doped zinc oxide (AZO). , Indium-zinc oxide (IZO), or gallium-doped zinc oxide (GZO).
  • IGZO indium-doped gallium-zinc oxide
  • IGO indium-gallium oxide
  • AZO aluminum oxide-doped zinc oxide
  • IZO Indium-zinc oxide
  • GZO gallium-doped zinc oxide
  • the value of “a” is 0.05 to 0.10
  • the value of “b” is 0.10 to 0.20
  • the value of “c” is 0.10 to 0.20
  • the value of “d” is Examples of the values of 0.30 to 0.40 and “e” are 0.45 to 0.60, but are not limited to these values.
  • the first electrode 31 is made of a transparent conductive material such as indium-tin oxide (ITO), and the light emitting / receiving layer 20 is an organic photoelectric conversion material, specifically, Is made of, for example, quinacridone having a thickness of 0.1 ⁇ m.
  • the light emitting / receiving layer 20 is sandwiched between the first electrode 31 and the second electrode 32. That is, the first electrode 31, the light emitting / receiving layer 20, and the second electrode 32 are laminated in this order. More specifically, in the electronic device 10 according to the first embodiment, the second electrode 31 is formed on the substrate 11 made of a silicon semiconductor substrate, and the light emitting / receiving layer 20 is formed on the first electrode 31.
  • the second electrode 32 is formed on the light emitting / receiving layer 20. That is, the electronic device 10 of Example 1 or Examples 2 to 3 described later has a two-terminal electronic device structure including the first electrode 31 and the second electrode 32. Specifically, photoelectric conversion is performed in the light emitting / receiving layer 20. That is, the electronic device 10 according to the first embodiment or the second to third embodiments described later includes a photoelectric conversion element.
  • the material constituting the first electrode 31 include transparent conductive materials such as indium-zinc oxide (IZO) and tin oxide (SnO 2 ).
  • the light transmittance of the insulating layers 40 and 80 with respect to light with a wavelength of 400 nm to 660 nm is 80% or more, specifically, 90% with respect to light with a wavelength of 550 nm
  • 92 has a light transmittance of 75% or more, specifically, 85% for light having a wavelength of 550 nm.
  • the light transmittance of the first electrodes 31, 91, the second electrodes 32, 92, and the insulating layers 40, 80 is such that the first electrodes 31, 91, the second electrodes 32, 92, and the insulating layer are formed on a transparent glass plate.
  • the sheet resistance values of the second electrodes 32 and 92 are 3 ⁇ 10 ⁇ / ⁇ to 1 ⁇ 10 3 ⁇ / ⁇ , specifically 8 ⁇ 10 ⁇ / ⁇ . Furthermore, the sheet resistance values of the insulating layers 40 and 80 are 2 ⁇ 10 5 ⁇ / ⁇ to 5 ⁇ 10 6 ⁇ / ⁇ , specifically, 8 ⁇ 10 5 ⁇ / ⁇ (Example 1A below) 4 ⁇ 10 6 ⁇ / ⁇ (Example 1B below) It is.
  • An IGZO film was formed at room temperature (specifically, 22 ° C. to 28 ° C.) based on a sputtering method. And when the relationship between the oxygen gas partial pressure at the time of film-forming and the electroconductivity and insulation of the obtained IGZO film was investigated, it became as shown in Table 1 below. Further, FIG. 2 shows the result of examining the relationship between the oxygen gas partial pressure during film formation and the internal stress of the obtained IGZO film.
  • a parallel parallel plate sputtering apparatus or a DC magnetron sputtering apparatus was used as the sputtering apparatus, argon (Ar) gas was used as the process gas, and an InGaZnO 4 sintered body was used as the target.
  • the configuration of the insulating layer 40 made of the IGZO film, the internal stress, and the peeling state of the insulating layer 40 from the second electrode 32 were examined. The results are shown in Table 2 below.
  • the insulating layer was made of SiON formed based on the sputtering method.
  • the internal stress of the insulating layers 40 and 80 is preferably a compressive stress of 10 MPa to 90 MPa.
  • oxygen gas partial pressure oxygen gas introduction amount
  • the electrode obtained by the manufacturing method (electrode formation method in an electronic device) of the electronic device of Example 1 is an electrode for a photoelectric conversion element.
  • the electronic device 10 obtained in the manufacturing method of the electronic device of Example 1 constitutes a photoelectric conversion element.
  • a substrate 11 made of a silicon semiconductor substrate is prepared.
  • an electronic device drive circuit (not shown) and wiring 12 are provided on the substrate 11, and an interlayer insulating film 13 is formed on the surface.
  • the interlayer insulating film 13 is provided with an opening 14 where the wiring 12 is exposed at the bottom.
  • a first electrode 31 made of ITO is formed (film formation) on the interlayer insulating film 13 including the inside of the opening 14 based on a sputtering method.
  • Step-110 Next, after patterning the first electrode 31, the light emitting / receiving layer 20 made of quinacridone is formed (film formation) on the entire surface by vacuum deposition.
  • a second electrode 32 made of a conductive amorphous oxide (specifically, made of IGZO) is formed on the light emitting / receiving layer 20 based on a sputtering method, and then the second electrode 32 is formed as desired. Patterning is performed based on a well-known patterning technique.
  • the insulating layer 40 is formed (film formation) on the entire surface by changing the sputtering conditions. That is, the light emitting / receiving layer 20 is covered with the insulating layer 40 made of an insulating amorphous oxide (specifically, made of IGZO) based on a sputtering method.
  • the electronic device of Example 1 having the structure shown in FIG. 1A can be obtained.
  • the second electrode 32 is formed.
  • the portion of the insulating layer 40 to be removed is removed based on a known patterning technique.
  • the second electrode 32 is formed into a desired shape. Patterning is performed based on a known patterning technique.
  • the electronic device of Example 1 having the structure shown in FIG. 1B can be obtained. That is, the insulating layer 40 may be formed on the upper side of the second electrode 32 or may be formed on the lower side.
  • the oxygen gas partial pressure (oxygen gas introduction amount) when forming the second electrode 32 and the insulating layer 40 based on the sputtering method that is, when forming the second electrode 32 based on the sputtering method.
  • the composition ratio of oxygen (O) in the insulating layer 40 is increased.
  • the composition ratio is higher than the oxygen (O) composition ratio in the two electrodes 32.
  • the oxygen gas partial pressure when forming the insulating layer 40 based on the sputtering method is set to 0.04 Pa to 0.15 Pa.
  • the temperature at which the second electrode 32 and the insulating layer 40 are formed based on the sputtering method is set to room temperature, specifically 22 ° C. to 28 ° C.
  • a parallel parallel plate sputtering apparatus or a DC magnetron sputtering apparatus was used as the sputtering apparatus, argon (Ar) gas was used as the process gas, and an InGaZnO 4 sintered body was used as the target.
  • the composition of the second electrode and the insulating layer and the composition ratio of oxygen are defined, and the second electrode and the insulating layer can be formed of the same material.
  • An electronic device can be manufactured by a typical method, and although the second electrode and the insulating layer are made of the same material, conductivity and insulation can be imparted to each of them. Moreover, since the electronic device can be manufactured at a lower temperature process, it is possible to prevent thermal degradation of the light emitting / receiving layer, and furthermore, the film stress of the insulating layer can be suppressed, which is high. An electronic device having reliability can be provided.
  • Example 2 is a modification of Example 1, and relates to an electronic device having a first-A configuration and an electronic device having a first-C configuration. That is, in the electronic device of Example 2, the light emitting / receiving layer 20 is sandwiched between the first electrode 31 and the second electrode 32, and the work function value of the second electrode 32 and the work function of the first electrode 31 are The difference from the value is 0.4 eV or more.
  • the difference between the work function value of the second electrode 32 and the work function value of the first electrode 31 is set to 0.4 eV or more, so that the inside of the light emitting / receiving layer 20 is based on the difference of the work function values. Generate an electric field to improve internal quantum efficiency.
  • the second electrode 32 functions as a cathode electrode (cathode). That is, it functions as an electrode for extracting electrons.
  • the first electrode 31 functions as an anode electrode (anode). That is, it functions as an electrode for extracting holes.
  • the work function of IGZO constituting the second electrode 32 is 4.1 eV to 4.2 eV although it depends on the film forming conditions.
  • the work function of ITO constituting the first electrode 31 is 4.8 eV to 5.0 eV as an example, although it depends on the film forming conditions.
  • the work function value of the second electrode 32 is controlled by controlling the oxygen gas introduction amount (oxygen gas partial pressure) when forming the second electrode 32 based on the sputtering method.
  • oxygen gas partial pressure oxygen gas partial pressure
  • oxygen gas partial pressure value increases, that is, oxygen deficiency decreases.
  • the work function value of the second electrode 32 increases and the oxygen gas partial pressure value decreases, that is, as the oxygen deficiency increases, the work function value of the second electrode 32 decreases.
  • the work of the second electrode 32 is controlled by controlling the oxygen gas introduction amount (oxygen gas partial pressure) when forming the second electrode 32 based on the sputtering method.
  • the function value is controlled.
  • the oxygen content is lower than the oxygen content of the stoichiometric composition.
  • FIG. 3B shows IV curves obtained in the electronic device (photoelectric conversion element) of Example 2 and the electronic device (photoelectric conversion element) of Comparative Example 2.
  • “A” is the measurement result of the electronic device of Example 2
  • “B” is the measurement result of the electronic device of Example 3 described later
  • “C” is Comparative Example 2. It is a measurement result of the electronic device.
  • the second electrode 32 of the electronic device of Example 2 is made of ITO instead of IGZO. From FIG. 3B, it can be seen that in the electronic device of Example 2 or Example 3 to be described later, the current value increases abruptly at a reverse bias voltage of less than 1 volt (bias voltage of less than ⁇ 1 volt).
  • the values of internal quantum efficiency and on / off ratio of the electronic devices of Example 2 and Comparative Example 2 were as shown in Table 3 below.
  • the internal quantum efficiency ⁇ is a ratio of the number of generated electrons to the number of incident photons, and can be expressed by the following equation.
  • the second electrode is made of IGZO
  • the first electrode is made of ITO
  • the work function value of the second electrode is made of ITO
  • the work function value of the second electrode is made of ITO
  • the work function value of the second electrode is made of ITO
  • the work function value of the second electrode is made of ITO
  • the work function value of the second electrode is made of ITO
  • the work function value of the second electrode is made of ITO
  • the work function value of the second electrode Is 0.4 eV or more.
  • FIG. 4C A conceptual diagram of the energy diagram is shown in FIG. 4A. Accordingly, it is possible to prevent holes from the first electrode from flowing into the second electrode, and as a result, generation of dark current can be suppressed.
  • the difference between the work function value of the second electrode and the work function value of the first electrode is 0.4 eV or more, a potential gradient is generated when electrons and holes are taken out (that is, the light emitting / receiving layer). In this case, an internal electric field is
  • the result of investigating the correlation between the internal quantum efficiency and the difference between the work function values is shown in the graph of FIG. 5A, and light is irradiated at a dark current (in the measurement of Example 2, at a reverse bias voltage of 1 volt).
  • the graph of FIG. 5B shows the result of examining the correlation between the current value obtained when not) and the difference between the work function values.
  • 5A and 5B indicate the difference between the work function value of the second electrode 32 and the work function value of the first electrode 31, and the horizontal axes of FIGS.
  • a difference between the work function value of the second B layer 32B of the two electrodes 32 and the work function value of the second A layer 32A of the second electrode 32 is shown. From FIG. 5A and FIG. 5B, a clear increase in internal quantum efficiency and a clear decrease in dark current were recognized when the difference in work function value was around 0.4 eV.
  • the first electrode and the second electrode are defined.
  • a bias voltage more specifically, a reverse bias voltage
  • the work of the second electrode is controlled by controlling the oxygen gas introduction amount (oxygen gas partial pressure) when forming based on the sputtering method.
  • An electronic device capable of increasing current and suppressing generation of dark current can be manufactured by a simple manufacturing process.
  • Example 3 is a modification of Example 2, and relates to an electronic device having a first-B configuration and an electronic device having a first-C configuration. That is, in the electronic device of Example 3, the light emitting / receiving layer 20 is sandwiched between the first electrode 31 and the second electrode 32, and the second electrode 32 extends from the light emitting / receiving layer 20 side to the second B layer 32 ⁇ / b> B. In addition, the work function value of the second A layer 32A of the second electrode 32 is lower than the work function value of the second B layer 32B of the second electrode 32.
  • FIG. 1C A schematic partial cross-sectional view of the electronic device of Example 3 is shown in FIG. 1C.
  • the difference between the work function value of the second A layer 32A of the second electrode 32 and the work function value of the second B layer 32B of the second electrode 32 is 0.1 eV to 0.2 eV, more specifically. Is 0.15 eV, and the difference between the work function value of the first electrode 31 and the work function value of the second A layer 32A of the second electrode 32 is 0.4 eV or more.
  • the thickness of the second electrode 32 is 1 ⁇ 10 ⁇ 8 m to 1 ⁇ 10 ⁇ 7 m, specifically 50 nm.
  • the thickness of the second A layer 32A of the second electrode 32 and the second electrode 32 are the same.
  • the thickness ratio of the second B layer 32B is 9/1 to 1/9, specifically 9/1.
  • the work function value of the first electrode 31 and the work function value of the second A layer 32A of the second electrode 32 is set to 0.4 eV or more, the work function value Based on the difference, an internal electric field is generated in the light emitting / receiving layer to improve internal quantum efficiency.
  • the composition of the second A layer 32A is In a (Ga, Al) b Zn c O d and the composition of the second B layer 32B is In a ′ (Ga, Al) b ′ Zn c ′ O d ′.
  • FIG. 3B shows an IV curve obtained in the electronic device (photoelectric conversion element) of Example 3. Furthermore, the result of investigating the correlation between the internal quantum efficiency and the difference between the work function values is shown in the graph of FIG. 6A. Light is irradiated at a reverse bias voltage of 1 volt even in the measurement of Example 3. 6B shows the result of examining the correlation between the difference between the current value obtained when not) and the work function value. 6A and 6B, as the difference between the work function value of the second A layer of the second electrode and the work function value of the second B layer of the second electrode increases to about 0.2 eV, the internal quantum efficiency is increased. A clear increase and a clear decrease in dark current were observed.
  • the second electrode is composed of the second A layer and the second B layer, and the difference in work function between the second A layer and the second B layer is defined.
  • the work function can be optimized, and the transfer (movement) of the carrier becomes easier.
  • Example 4 is a modification of Example 1 and relates to an electronic device having a configuration of 2-A.
  • 7A and 7B are schematic partial cross-sectional views of the electronic device of Example 4.
  • FIG. 7A is a schematic partial cross-sectional view along the arrow AA in FIG. 7B, in which the electronic device is cut along a virtual plane perpendicular to the extending direction of the waveguide structure (resonator structure). It is a typical partial sectional view at the time.
  • FIG. 7B is a schematic partial cross-sectional view along the arrow BB in FIG. 7A, in which the electronic device is cut along a virtual plane parallel to the extending direction of the waveguide structure (resonator structure). It is a typical partial sectional view at the time.
  • the light emitting / receiving layer 20 includes the first compound semiconductor layer 71 having the first conductivity type, the active layer 73, and the first conductivity type. It consists of the laminated structure 70 which consists of the 2nd compound semiconductor layer 72 which has a different 2nd conductivity type.
  • the electronic device of Example 4 or Example 5 to Example 6 to be described later is composed of a semiconductor laser element, more specifically, a semiconductor laser element having a ridge stripe type separated confinement heterostructure. Yes.
  • the first conductivity type is n-type
  • the second conductivity type is p-type.
  • the electronic devices of Example 4 or Examples 5 to 6 described later include a first compound semiconductor layer 71 having an first conductivity type (specifically, an n-type in the example), an active layer 73,
  • the stacked structure 70 (the light emitting / receiving layer 20) including the second compound semiconductor layer 72 having a second conductivity type (specifically, p-type in the embodiment) different from the first conductivity type is provided.
  • the second electrode 92 is formed on the second compound semiconductor layer 72 via the contact layer 74, and the thickness of the contact layer 74 is 4 atomic layers or less. Is the thickness.
  • the interface between the contact layer 74 and the second compound semiconductor layer 72 is the xy plane, and the lattice constant (specifically) along the x-axis of the crystal constituting the interface layer 72A that is the portion of the second compound semiconductor layer 72 in contact with the contact layer 74 Specifically, the lattice constant along the a-axis) is x 2 , the lattice constant along the z-axis (specifically, the lattice constant along the c-axis) is z 2 , and the crystal constituting the contact layer 74 is 1
  • the length of the unit along the x-axis (specifically, the length along the a-axis) is x C ', and the length along the z-axis (specifically, the length along the c-axis) z C
  • the ridge stripe structure 60 is formed from a laminated structure 70 in which a first compound semiconductor layer 71, an active layer 73, and a second compound semiconductor layer 72 are laminated. And has a first end face 61 that emits light and a second end face 62 that faces the first end face 61.
  • the planar shape of the ridge stripe structure 60 is linear.
  • the ridge stripe structure 60 is formed by partially etching the second compound semiconductor layer 72 in the thickness direction.
  • the region of the active layer 73 below the ridge stripe structure 60 corresponds to a light emitting region (current injection region).
  • a high reflection coat layer (HR) is formed on the light emitting end face (first end face) 61 and the light reflecting end face (second end face), but the illustration of these coat layers is omitted.
  • the light reflectance of the light emitting end face (first end face) 61 is lower than the light reflectance of the light reflecting end face (second end face) 62.
  • the ridge stripe structure 60 and both sides thereof are covered with the insulating layer 80 described in the first embodiment.
  • the portion of the insulating layer 80 on the top surface of the contact layer 74 (second compound semiconductor layer 72 in Example 6 described later) has been removed, and the contact layer 74 (second compound in Example 6 described later).
  • a second electrode 92 is formed on the top surface of the semiconductor layer 72).
  • the second electrode 92 is made of the material described in the first embodiment.
  • the second electrode 92 and the insulating layer 80 are formed by the same method as described in the first embodiment.
  • a first electrode 91 formed by stacking a Ti layer / Pt layer / Au layer is formed on the back surface (the surface facing the main surface) of the GaN substrate 51.
  • the crystal structure of the crystal composing the interface layer 72A of the second compound semiconductor layer 72 is hexagonal, and the crystal structure of the crystal composing the contact layer 74 is also hexagonal.
  • the stacked structure 70 is made of a GaN-based compound semiconductor
  • the contact layer 74 is a GaN-based compound semiconductor having the same composition as that of the GaN-based compound semiconductor constituting the interface layer 72A of the second compound semiconductor layer 72, and GaN-based compound semiconductor containing oxygen atoms.
  • the specific structure of the laminated structure 70 is shown in Table 4 below, and the compound semiconductor layer described at the bottom is formed on a GaN substrate 51 made of an n-type GaN substrate.
  • the composition of the contact layer 74 is expressed as “p-type GaN (O)”, which indicates that the contact layer 74 is made of GaN containing oxygen atoms.
  • the active layer 73 has a quantum well structure in which a well layer made of an InGaN layer and a barrier layer made of a GaN layer are stacked. Silicon (Si), oxygen (O), or germanium (Ge) is added to the GaN substrate 51 as an n-type impurity.
  • the electronic device having the composition shown in Table 4 emits green light. That is, the emission wavelength of the electronic device of Example 4 is not less than 440 nm and not more than 600 nm, more specifically, not less than 495 nm and not more than 570 nm.
  • the interface layer 72A in the second compound semiconductor layer 72 is made of p-type GaN having a thickness of 2.5 nm constituting the second cladding layer having a superlattice structure.
  • the second cladding layer only one of the p-type AlGaN layer or the p-type GaN layer may have a modulation doping structure.
  • the first cladding layer and the second cladding layer can be composed of a quaternary InAlGaN layer as will be described later.
  • An electronic device that emits blue light can be obtained by changing the composition.
  • a GaN substrate 51 having a c-plane that is a ⁇ 0001 ⁇ plane as a main surface is prepared.
  • the main surface of the GaN substrate 51 is not limited to the c-plane which is a polar surface.
  • Non-polar surfaces such as the ⁇ 11-20 ⁇ plane A, the ⁇ 1-100 ⁇ plane M, the ⁇ 1-102 ⁇ plane, or the ⁇ 11-24 ⁇ plane or the ⁇ 11-22 ⁇ plane
  • a GaN substrate 51 having a semipolar plane such as a ⁇ 11-2n ⁇ plane, a ⁇ 10-11 ⁇ plane, and a ⁇ 10-12 ⁇ plane as a main plane can also be used.
  • the main surface of the GaN substrate 51 is cleaned by thermal cleaning or the like.
  • the buffer layer 52 is crystal-grown on the main surface of the GaN substrate 51 based on the MOCVD method.
  • a first guide layer, an active layer, a second guide layer, an electron barrier layer, and a second cladding layer are sequentially formed.
  • the contact layer 34 is formed based on the ALD method to obtain the contact layer 34 made of p-type GaN (O).
  • the contact layer 34 is formed on the interface layer 32A made of p-type GaN having a thickness of 2.5 nm.
  • the method for forming the contact layer 34 is not limited to the ALD method.
  • an etching mask is formed on the second compound semiconductor layer 72 (specifically, the contact layer 74), and the second compound semiconductor layer 72 is formed using the etching mask, for example, based on the RIE method.
  • the ridge stripe structure 60 is formed by etching partly in the thickness direction, and then the etching mask is removed.
  • the second compound semiconductor layer 72 and the active layer 73 may be etched in the thickness direction, or the second compound semiconductor layer 72, the active layer 73, and the first compound semiconductor layer 71 are partially etched in the thickness direction. May be.
  • the light emitting end face (first end face) 61 and the light reflecting end face (second end face) 62 are formed by cleaving the laminated structure 70. Thereafter, in order to connect the electrode to an external circuit or the like, a terminal or the like is formed based on a known method, and packaged or sealed, thereby completing the electronic device of Example 4.
  • the second electrode 92 is formed on the entire surface in the same manner as in [Step-120] in Example 1. Then, the second electrode 92 is patterned, and then the insulating layer 80 is formed on the entire surface. After the formation, part of the second electrode 92 may be exposed by patterning the insulating layer 80. In this way, the structure shown in FIG. 8 can be obtained. That is, the insulating layer 80 may be formed on the upper side of the second electrode 92 or may be formed on the lower side.
  • a scanning transmission electron microscope image of the obtained electronic device is shown in FIG.
  • the length along the x-axis (specifically, the length along the a-axis) in one unit of the crystal constituting the contact layer 74 measured from the scanning transmission electron microscope image is along x C ′ and z-axis.
  • the lattice constant (specifically, the lattice constant along the a axis) of the crystal constituting the interface layer 72A is x 2
  • the lattice constant along the z axis (specifically, the c axis).
  • FIG. 10 is a graph showing the relationship between the series resistance value of the electronic device having the structure shown in FIGS. 7A and 7B and the work function value of the material constituting the second electrode 92 (p-side electrode).
  • the work function value of the material constituting the second electrode 92 (p-side electrode).
  • Ti, Ni / Au, and Pd a series when a second electrode made of Ti, Ni / Au, or Pd is formed on a second cladding layer made of a p-type GaN layer, as in a conventional semiconductor laser device. Resistance value. There is a correlation between the series resistance value and the work function value.
  • the contact layer 74 of Example 4 is formed, that is, the contact layer 74 having a thickness of two atomic layers is provided between the interface layer 72A made of p-type GaN and the second electrode 92 made of ITO.
  • the actual series resistance value is about 2/3 of the series resistance value estimated from the work function value of ITO (for example, 4.8 eV to 5.0 eV, depending on the film formation conditions). It is getting smaller.
  • the drive voltage of the electronic device can be reduced by reducing the series resistance value, that is, the contact resistance value.
  • the lattice constant in the interface layer which is the portion of the second compound semiconductor layer in contact with the contact layer, and the length in one unit of the crystal constituting the contact layer are predetermined. Therefore, a kind of distortion occurs in the contact layer. As a result, not only can the drive voltage be reduced, but also, for example, a material having a low work function value such as ITO can be used. It becomes possible to constitute the electrode, and the degree of freedom of selection of the material constituting the second electrode can be improved.
  • the fifth embodiment is a modification of the fourth embodiment.
  • the laminated structure 70 is made of a GaN-based compound semiconductor, and the contact layer 74 is made of a GaN-based compound semiconductor having a composition different from that of the GaN-based compound semiconductor constituting the interface layer 72A of the second compound semiconductor layer 72.
  • the laminated structure 70 is made of a GaN-based compound semiconductor, and the contact layer 74 is made of one kind of material selected from the group consisting of ZnO, ZnSe, CdO, CdS, and CdSe.
  • the band gap energy value of the compound semiconductor constituting the contact layer 74 is smaller than the band gap energy value (GaN: 3.4 eV) of the compound semiconductor constituting the interface layer 72A of the second compound semiconductor layer 72.
  • the contact layer 74 having a thickness of two atomic layers is provided between the interface layer 72A made of p-type GaN and the second electrode 92 made of ITO, a series estimated from the work function value of ITO. With respect to the resistance value, the series resistance value of the electronic device of Example 5 was reduced to about 2/3.
  • the lattice constant in the interface layer which is the portion of the two-compound semiconductor layer in contact with the contact layer, and the length in one unit of the crystals constituting the contact layer are Since the predetermined relationship is satisfied, a kind of distortion occurs in the contact layer.
  • a material having a low work function value such as ITO can be used. It becomes possible to constitute two electrodes, and the degree of freedom of selection of the material constituting the second electrode can be improved.
  • Example 6 is a modification of Example 1 and relates to an electronic device having the configuration 2-B.
  • 11A and 11B are schematic partial cross-sectional views of the electronic device of Example 6.
  • FIG. 11A and 11B are schematic partial sectional views similar to those taken along the arrow AA in FIG. 7B, and are virtual planes perpendicular to the extending direction of the waveguide structure (resonator structure). It is a typical partial sectional view when an electronic device is cut.
  • the light emitting / receiving layer 20 is a stacked structure including a first compound semiconductor layer 71 having a first conductivity type, an active layer 73, and a second compound semiconductor layer 72 having a second conductivity type different from the first conductivity type.
  • a first electrode 91 is formed on the first compound semiconductor layer 71 via a contact layer 75,
  • the thickness of the contact layer 75 is a thickness of 4 atomic layers or less
  • the interface between the contact layer 75 and the first compound semiconductor layer 71 is the xy plane
  • the lattice constant along the x axis of the crystal constituting the interface layer 71A that is the portion of the first compound semiconductor layer 71 in contact with the contact layer 75 is x 1
  • the lattice constant along the z-axis is z 1
  • the length along the x-axis in one unit of the crystal constituting the contact layer 75 is x C ′′
  • the length along the z-axis is z C ′′ (Z C ′′ / x C ′′)> (z 1 / x 1 ) Satisfied.
  • the ridge stripe structure 60 has the same structure and configuration as the ridge stripe structure 60 in the electronic device of the fourth embodiment.
  • the second electrode 92 is made of the same material as the second electrode 32 of Example 1
  • the first electrode 91 is made of ITO, Cu, Ti, Al, Ta, or the like.
  • the crystal structure of the crystal constituting the interface layer 71A of the first compound semiconductor layer 71 is a hexagonal system.
  • the crystal structure of the crystals constituting the contact layer 75 is also hexagonal.
  • the laminated structure 70 is made of a GaN-based compound semiconductor, and the contact layer 75 is a GaN-based compound semiconductor having the same composition as the GaN-based compound semiconductor constituting the interface layer 71A of the first compound semiconductor layer 71, and further oxygen It consists of a GaN-based compound semiconductor containing atoms.
  • the composition of the laminated structure 70 is the same as that shown in Table 4 above.
  • the laminated structure 70 is made of a GaN-based compound semiconductor
  • the contact layer 75 is made of a GaN-based compound semiconductor having a composition different from that of the GaN-based compound semiconductor constituting the interface layer 71A of the first compound semiconductor layer 71.
  • the electronic device of Example 6 is the same as the [Step-400] to [Step-410] except for the formation of the contact layer 74 in [Step-400] in the electronic device manufacturing method of Example 4.
  • the insulating layer 80 is formed on the entire surface, and the portion of the insulating layer 80 located on the top surface of the second compound semiconductor layer 72 is removed.
  • the second electrode 92 is formed on the exposed second compound semiconductor layer 72 (see FIG. 11A).
  • the second electrode 92 is formed on the entire surface, and the portion of the second electrode 92 located on the top surface of the second compound semiconductor layer 72 is left.
  • a part of the insulating layer 80 may be removed to expose a part of the second electrode 92 (see FIG. 11B). Thereafter, a part of the insulating layer 80 on the first compound semiconductor layer 71 is removed, a part of the first compound semiconductor layer 71 is exposed, and on the exposed first compound semiconductor layer 71, a contact layer 75, By forming the first electrode 91, the structure shown in FIG. 11 can be obtained. Thereafter, the same step as [Step-430] in Embodiment 4 may be performed.
  • the contact layer 75 in the electronic device of Example 6 described above (Z C ′′ / x C ′′)> (z 1 / x 1 ) was satisfied.
  • the contact layer 75 having a thickness of two atomic layers was provided between the interface layer 71A and the first electrode 91, the series resistance value of the electronic device of Example 6 was a sufficiently small value.
  • the lattice constant in the interface layer which is the portion of the first compound semiconductor layer in contact with the contact layer, and the length in one unit of the crystals constituting the contact layer are Since the predetermined relationship is satisfied, a kind of distortion occurs in the contact layer, and as a result, the contact resistance value can be further reduced.
  • Example 7 relates to a solid-state imaging device of the present disclosure.
  • the solid-state imaging apparatus according to the seventh embodiment includes the electronic devices (specifically, photoelectric conversion elements) according to the first to third embodiments.
  • FIG. 12 shows a conceptual diagram of the solid-state imaging device (solid-state imaging device) of Example 7.
  • the solid-state imaging device 100 according to the seventh embodiment includes an imaging region in which the electronic devices (photoelectric conversion elements) 10 described in the first to third embodiments are arranged in a two-dimensional array on a semiconductor substrate (for example, a silicon semiconductor substrate). 101, a vertical drive circuit 102 as a peripheral circuit thereof, a column signal processing circuit 103, a horizontal drive circuit 104, an output circuit 105, a control circuit 106, and the like.
  • these circuits can be configured from well-known circuits, and can be configured using other circuit configurations (for example, various circuits used in conventional CCD imaging devices and CMOS imaging devices). Needless to say, it can be done.
  • the control circuit 106 generates a clock signal and a control signal that serve as a reference for the operation of the vertical drive circuit 102, the column signal processing circuit 103, and the horizontal drive circuit 104 based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock.
  • the generated clock signal and control signal are input to the vertical drive circuit 102, the column signal processing circuit 103, and the horizontal drive circuit 104.
  • the vertical drive circuit 102 is configured by a shift register, for example, and selectively scans each electronic device 10 in the imaging region 101 in the vertical direction sequentially in units of rows. Then, a pixel signal based on a current (signal) generated according to the amount of received light in each electronic device 10 is sent to the column signal processing circuit 103 via the vertical signal line 107.
  • the column signal processing circuit 103 is arranged, for example, for each column of the electronic devices 10, and outputs a signal output from the electronic device 10 for one row for each electronic device 10 with a black reference pixel (not shown, but an effective pixel region). Signal processing for signal removal and signal amplification.
  • a horizontal selection switch (not shown) is connected between the horizontal signal line 108 and provided.
  • the horizontal drive circuit 104 is configured by, for example, a shift register, and sequentially selects each of the column signal processing circuits 103 by sequentially outputting horizontal scanning pulses, and signals from each of the column signal processing circuits 103 are sent to the horizontal signal line 108. Output.
  • the output circuit 105 performs signal processing on the signals sequentially supplied from each of the column signal processing circuits 103 via the horizontal signal line 108 and outputs the signals.
  • the light emitting / receiving layer itself can function as a color filter, color separation is possible without providing a color filter.
  • a known color filter that transmits a specific wavelength such as red, green, blue, cyan, magenta, yellow, or the like may be disposed above the light incident side of the electronic device 10.
  • the solid-state imaging device can be a front-side irradiation type or a back-side irradiation type. Moreover, you may arrange
  • the present disclosure has been described based on the preferred embodiments, the present disclosure is not limited to these embodiments.
  • the structure and configuration of the electronic device (photoelectric conversion element), the solid-state imaging device, and the semiconductor laser element described in the examples, the manufacturing conditions and manufacturing method of the electronic device, and the materials used are examples, and can be changed as appropriate.
  • the electronic device described in Embodiments 4 to 5 and the electronic device described in Embodiment 6 can be combined.
  • the light emitting / receiving layer may be irradiated with light without applying a voltage between the first electrode and the second electrode.
  • an optical sensor or an image sensor can be configured by the electronic device of the present disclosure.
  • a semiconductor light emitting element such as a super luminescent diode (SLD), a surface emitting laser element, a light emitting diode (LED), or a semiconductor optical amplifier can be used. It can also be a solar cell or a light sensor.
  • the ridge stripe structure 60 has a linearly extending shape, but the present invention is not limited to this. Or flare shape. Specifically, for example, a structure that is monotonously and gradually widened in a tapered manner from the light emitting end face toward the light reflecting end face, first widened from the light emitting end face toward the light reflecting end face, and exceeds the maximum width. After that, it can be configured to be narrowed.
  • the semiconductor laser element may be a semiconductor laser element having an oblique ridge stripe type separated confinement heterostructure having an oblique waveguide.
  • a semiconductor laser element for example, it has a structure in which two linear ridge stripe structures are combined, and the value of the angle ⁇ at which the two ridge stripe structures intersect is, for example, 0 ⁇ ⁇ 10 (degrees) Preferably, 0 ⁇ ⁇ 6 (degrees) Is desirable.
  • the oblique ridge stripe type the reflectance of the light emitting end face coated with non-reflective coating can be made closer to the ideal value of 0%, and as a result, the laser light that circulates in the semiconductor laser element can be obtained.
  • production can be prevented and the advantage that generation
  • this indication can also take the following structures.
  • the second electrode is composed of at least a quaternary compound of indium, gallium and / or aluminum, zinc, and oxygen
  • the light emitting / receiving layer is covered with an insulating layer composed of at least a quaternary compound of indium, gallium and / or aluminum, zinc, and oxygen
  • the second electrode is made of In a (Ga, Al) b Zn c O d
  • the insulating layer and the second electrode are made of indium-gallium oxide, indium-doped gallium-zinc oxide, aluminum oxide-doped zinc oxide, indium-zinc oxide, or gallium-doped zinc oxide.
  • [A04] The electronic device according to any one of [A01] to [A03], wherein the internal stress of the insulating layer is a compressive stress of 10 MPa to 90 MPa.
  • [A05] The electronic device according to any one of [A01] to [A04], wherein the light transmittance of the insulating layer with respect to light having a wavelength of 400 nm to 660 nm is 80% or more.
  • [A06] The electronic device according to any one of [A01] to [A05], wherein the light transmittance of the second electrode with respect to light having a wavelength of 400 nm to 660 nm is 75% or more.
  • [B05] By setting the difference between the work function value of the first electrode and the work function value of the second A layer of the second electrode to 0.4 eV or more, in the light emitting / receiving layer based on the difference of the work function values
  • the electronic device according to any one of [A10] to [B04] which generates an internal electric field to improve internal quantum efficiency.
  • [B06] The electronic device according to any one of [A09] to [B05], in which a work function value of the second electrode is 4.1 eV to 4.5 eV.
  • [B07] The electronic device according to any one of [A09] to [B06], wherein the first electrode is made of indium-tin oxide, indium-zinc oxide, or tin oxide.
  • the work function value of the second electrode is controlled by controlling the amount of oxygen gas introduced when the second electrode is formed based on the sputtering method. Any one of [A09] to [B07] The electronic device described. [B09] The electronic device according to any one of [A09] to [B08], wherein the oxygen content is lower than the oxygen content of the stoichiometric composition. [A11] The electronic device according to any one of [A01] to [B09], wherein the light emitting / receiving layer is made of an organic photoelectric conversion material. [A12] The electronic device according to [A11], including a photoelectric conversion element.
  • the light emitting / receiving layer is composed of a laminated structure including a first compound semiconductor layer having a first conductivity type, an active layer, and a second compound semiconductor layer having a second conductivity type different from the first conductivity type, A second electrode is formed on the second compound semiconductor layer via a contact layer, The thickness of the contact layer is a thickness of 4 atomic layers or less, The interface between the contact layer and the second compound semiconductor layer is along the xy plane, and the lattice constant along the x axis of the crystal constituting the interface layer that is the portion of the second compound semiconductor layer in contact with the contact layer is along the x 2 and z axes.
  • the laminated structure is made of a GaN-based compound semiconductor, The electronic device according to [C03], wherein the contact layer is a GaN-based compound semiconductor having the same composition as that of the GaN-based compound semiconductor constituting the second compound semiconductor layer, and further includes a GaN-based compound semiconductor containing oxygen atoms.
  • the laminated structure is made of a GaN-based compound semiconductor, The electronic device according to [C03], wherein the contact layer is made of a GaN-based compound semiconductor having a composition different from that of the GaN-based compound semiconductor constituting the second compound semiconductor layer.
  • the laminated structure is composed of a GaN-based compound semiconductor,
  • the band gap energy value of the compound semiconductor constituting the contact layer is any of [A13] to [C06] smaller than the band gap energy value of the compound semiconductor constituting the interface layer of the second compound semiconductor layer.
  • a first electrode is formed on the first compound semiconductor layer via a second contact layer,
  • the thickness of the second contact layer is a thickness of 4 atomic layers or less
  • the interface between the second contact layer and the first compound semiconductor layer is the xy plane
  • the lattice constant along the x axis of the crystal constituting the interface layer that is the portion of the first compound semiconductor layer in contact with the second contact layer is x 1.
  • the lattice constant along the z-axis is z 1
  • the length along the x-axis in one unit of the crystal constituting the second contact layer is x C ′′
  • the length along the z-axis is z C ′′.
  • the second contact layer is a GaN-based compound semiconductor having the same composition as that of the GaN-based compound semiconductor constituting the first compound semiconductor layer, and further includes a GaN-based compound semiconductor containing oxygen atoms.
  • [D06] The electronic device according to [D04], in which the second contact layer is formed of a GaN-based compound semiconductor having a composition different from that of the GaN-based compound semiconductor constituting the first compound semiconductor layer.
  • [D07] The electronic device according to any one of [D01] to [D03], in which the second contact layer is made of one material selected from the group consisting of ZnO, ZnSe, CdO, CdS, and CdSe.
  • the value of the band gap energy of the compound semiconductor constituting the second contact layer is smaller than the value of the band gap energy of the compound semiconductor constituting the interface layer of the first compound semiconductor layer [D01] to [D07].
  • the electronic device according to any one of the above.
  • the light emitting / receiving layer is composed of a laminated structure including a first compound semiconductor layer having a first conductivity type, an active layer, and a second compound semiconductor layer having a second conductivity type different from the first conductivity type, A first electrode is formed on the first compound semiconductor layer via a contact layer, The thickness of the contact layer is a thickness of 4 atomic layers or less, The interface between the contact layer and the first compound semiconductor layer is along the xy plane, and the lattice constant along the x axis of the crystal constituting the interface layer that is the portion of the first compound semiconductor layer in contact with the contact layer is along the x 1 and z axes.
  • the laminated structure is made of a GaN-based compound semiconductor, The electronic device according to [E03], wherein the contact layer is a GaN-based compound semiconductor having the same composition as the GaN-based compound semiconductor constituting the first compound semiconductor layer, and further includes a GaN-based compound semiconductor containing oxygen atoms.
  • the laminated structure is made of a GaN-based compound semiconductor, The electronic device according to [E03], wherein the contact layer is made of a GaN-based compound semiconductor having a composition different from that of the GaN-based compound semiconductor constituting the first compound semiconductor layer.
  • the laminated structure is composed of a GaN-based compound semiconductor,
  • the band gap energy value of the compound semiconductor constituting the contact layer is any of [A14] to [E06] smaller than the band gap energy value of the compound semiconductor constituting the interface layer of the first compound semiconductor layer.
  • Solid-state imaging device A solid-state imaging device comprising the electronic device according to any one of [A01] to [A12].
  • [G01] ⁇ Method for Manufacturing Electronic Device A second electrode composed of at least a quaternary compound of indium, gallium and / or aluminum, zinc, and oxygen is formed on the light emitting / receiving layer based on a sputtering method; The light emitting / receiving layer is covered with an insulating layer composed of at least a quaternary compound of indium, gallium and / or aluminum, zinc, and oxygen based on a sputtering method.
  • a method for manufacturing an electronic device wherein the oxygen composition ratio in the insulating layer is made higher than the oxygen composition ratio in the second electrode by controlling the oxygen gas partial pressure when forming the second electrode and the insulating layer based on the sputtering method.
  • [G02] The method for manufacturing an electronic device according to [G01], in which an oxygen gas partial pressure when forming the insulating layer based on a sputtering method is set to 0.04 Pa to 0.15 Pa.
  • a temperature at which the insulating layer is formed based on a sputtering method is set to 25 ° C. to 28 ° C.
  • [G04] The electronic device manufacturing method according to any one of [G01] to [G03], in which the electronic device constitutes a photoelectric conversion element.
  • the difference between the work function value of the second electrode and the work function value of the first electrode is 0.4 eV or more
  • the difference between the work function value of the second electrode and the work function value of the first electrode is 0.4 eV or more, an internal electric field is generated in the light emitting / receiving layer based on the difference of the work function values.
  • the second electrode has a laminated structure of the second B layer and the second A layer from the light emitting / receiving layer side,
  • the work function value of layer 2A of the second electrode is lower than the work function value of layer 2B of the second electrode,
  • the work function values of the second A layer and the second B layer of the second electrode are controlled. Any one of [G01] to [G04] The manufacturing method of the electronic device of description.
  • [H06] By setting the difference between the work function value of the first electrode and the work function value of the second electrode 2A layer to 0.4 eV or more, in the light emitting / receiving layer based on the work function value difference.
  • [H08] The method of manufacturing an electronic device according to any one of [H01] to [H07], in which a work function value of the second electrode is 4.1 eV to 4.5 eV.
  • [H09] The method for manufacturing an electronic device according to any one of [H01] to [H08], wherein the first electrode is made of indium-tin oxide, indium-zinc oxide, or tin oxide.
  • Insulating material An insulating material composed of at least a quaternary compound of indium, gallium and / or aluminum, zinc, and oxygen.
  • the insulating material according to [J01] which is made of In a (Ga, Al) b Zn c O e .
  • [J03] [J01] or [J02] composed of indium-gallium oxide, indium-doped gallium-zinc oxide, aluminum oxide-doped zinc oxide, indium-zinc oxide, or gallium-doped zinc oxide Insulating material described in 1.
  • [J04] The insulating material according to any one of [J01] to [J03], wherein the internal stress of the insulating layer obtained by forming the insulating material is a compressive stress of 10 MPa to 90 MPa.
  • [J05] The insulating material according to any one of [J01] to [J04], which has a light transmittance of 80% or more for light having a wavelength of 400 nm to 660 nm.
  • DESCRIPTION OF SYMBOLS 10 ... Electronic device, 11 ... Board

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Abstract

An electronic device which is equipped with: a light-emitting/light-receiving layer (20); a first electrode (31) which is electrically connected to the light-emitting/light-receiving layer; and a second electrode (32) which is formed on the light-emitting/light-receiving layer (30). The second electrode (32) comprises at least a quaternary compound of: indium; gallium and/or aluminium; zinc; and oxygen. The light emitting/light-receiving layer (20) is coated by an insulating layer (40) that comprises at least a quaternary compound of: indium; gallium and/or aluminium; zinc; and oxygen. The composition ratio of oxygen in the insulating layer (40) is higher than the composition ratio of oxygen in the second electrode (32).

Description

電子デバイス及びその製造方法、固体撮像装置、並びに、絶縁材料Electronic device and method for manufacturing the same, solid-state imaging device, and insulating material
 本開示は、電子デバイス及びその製造方法、電子デバイスを組み込んだ固体撮像装置、並びに、絶縁材料に関する。 The present disclosure relates to an electronic device and a manufacturing method thereof, a solid-state imaging apparatus incorporating the electronic device, and an insulating material.
 例えばイメージセンサー等の光電変換素子から成る電子デバイスは、例えば、第1電極、光電変換部位を構成する発光・受光層、第2電極を順に積層することで構成されている。第2電極は透明電極であり、一方の電極で電子を捕集し、他方の電極で正孔を捕集して光電流を読み出す。発光・受光層を例えば有機材料から構成する場合、発光・受光層が水分や酸素等によって劣化することが知られている。それ故、例えば、保護層として機能する絶縁層によって第2電極を被覆することで、発光・受光層の劣化を抑制している(例えば、特開2013-118363参照)。 For example, an electronic device including a photoelectric conversion element such as an image sensor is configured, for example, by sequentially stacking a first electrode, a light emitting / receiving layer constituting a photoelectric conversion site, and a second electrode. The second electrode is a transparent electrode, which collects electrons with one electrode and collects holes with the other electrode to read out photocurrent. When the light emitting / receiving layer is made of, for example, an organic material, it is known that the light emitting / receiving layer is deteriorated by moisture or oxygen. Therefore, for example, the deterioration of the light emitting / receiving layer is suppressed by covering the second electrode with an insulating layer functioning as a protective layer (see, for example, JP-A-2013-118363).
特開2013-118363JP2013-118363A
 ところで、上記の特許公開公報に開示された技術において、絶縁層は、酸化窒化珪素層の単層から成り、あるいは又、酸化窒化珪素層(上層)/酸化アルミニウム層等(下層)の2層構成から成り、気相成長法に基づき成膜される。また、第2電極(対向電極)は、金属、金属酸化物、金属窒化物、金属硼化物、有機導電性化合物、これらの混合物等から構成されている。即ち、第2電極と絶縁層とは、全く異なる材料から構成されている。それ故、第2電極の形成と絶縁層の形成とを異なるプロセスに基づき行うことが必要とされる。即ち、第2電極の形成と絶縁層の形成とを一連のプロセスに基づき行うことができず、電子デバイスをより合理的な方法で製造することができないといった問題がある。また、絶縁層は、例えば、プラズマCVD法やALCVD法等の原子層体積法に基づき形成されるが、このときの成膜温度は150゜C~250゜Cあるいは100゜C~200゜Cである。 By the way, in the technique disclosed in the above patent publication, the insulating layer is composed of a single layer of a silicon oxynitride layer, or alternatively, a two-layer structure of a silicon oxynitride layer (upper layer) / aluminum oxide layer or the like (lower layer). The film is formed based on the vapor phase growth method. The second electrode (counter electrode) is composed of a metal, a metal oxide, a metal nitride, a metal boride, an organic conductive compound, a mixture thereof, or the like. That is, the second electrode and the insulating layer are made of completely different materials. Therefore, it is necessary to form the second electrode and the insulating layer based on different processes. That is, there is a problem that the formation of the second electrode and the formation of the insulating layer cannot be performed based on a series of processes, and the electronic device cannot be manufactured by a more rational method. The insulating layer is formed based on, for example, an atomic layer volume method such as a plasma CVD method or an ALCVD method. The film formation temperature at this time is 150 ° C. to 250 ° C. or 100 ° C. to 200 ° C. is there.
 従って、本開示の目的は、より合理的な方法で、あるいは又、より低い温度のプロセスでの製造を可能とする電子デバイスの製造方法、係る方法によって得ることが可能な電子デバイス、係る電子デバイスを組み込んだ固体撮像装置、並びに、絶縁材料を提供することにある。 Accordingly, it is an object of the present disclosure to provide an electronic device manufacturing method capable of being manufactured in a more rational method or in a lower temperature process, an electronic device obtainable by such a method, and such an electronic device It is an object of the present invention to provide a solid-state imaging device incorporating an insulating material and an insulating material.
 上記の目的を達成するための本開示の電子デバイスは、
 発光・受光層、発光・受光層に電気的に接続された第1電極、及び、発光・受光層上に形成された第2電極を備えており、
 第2電極は、インジウム(In)と、ガリウム(Ga)及び/又はアルミニウム(Al)と、亜鉛(Zn)と、酸素(O)との少なくとも四元系化合物から構成されており、
 発光・受光層は、インジウム(In)と、ガリウム(Ga)及び/又はアルミニウム(Al)と、亜鉛(Zn)と、酸素(O)との少なくとも四元系化合物から構成された絶縁層によって被覆されており、
 絶縁層における酸素(O)の組成割合は、第2電極における酸素(O)の組成割合よりも高い。
In order to achieve the above object, an electronic device of the present disclosure is provided.
A light emitting / receiving layer, a first electrode electrically connected to the light emitting / receiving layer, and a second electrode formed on the light emitting / receiving layer,
The second electrode is composed of at least a quaternary compound of indium (In), gallium (Ga) and / or aluminum (Al), zinc (Zn), and oxygen (O).
The light emitting / receiving layer is covered with an insulating layer composed of at least a quaternary compound of indium (In), gallium (Ga) and / or aluminum (Al), zinc (Zn), and oxygen (O). Has been
The composition ratio of oxygen (O) in the insulating layer is higher than the composition ratio of oxygen (O) in the second electrode.
 上記の目的を達成するための本開示の固体撮像装置は、上記の本開示の電子デバイスを備えている。 The solid-state imaging device of the present disclosure for achieving the above object includes the electronic device of the present disclosure.
 上記の目的を達成するための本開示の電子デバイスの製造方法は、
 発光・受光層上に、インジウム(In)と、ガリウム(Ga)及び/又はアルミニウム(Al)と、亜鉛(Zn)と、酸素(O)との少なくとも四元系化合物から構成された第2電極をスパッタリング法に基づき形成し、次いで、
 発光・受光層を、スパッタリング法に基づき、インジウム(In)と、ガリウム(Ga)及び/又はアルミニウム(Al)と、亜鉛(Zn)と、酸素(O)との少なくとも四元系化合物から構成された絶縁層によって被覆する、
工程を少なくとも含み、
 スパッタリング法に基づき第2電極及び絶縁層を形成する際の酸素ガス分圧(酸素ガス導入量)を制御することで、絶縁層における酸素(O)の組成割合を第2電極における酸素(O)の組成割合よりも高くする。
In order to achieve the above object, a method of manufacturing an electronic device according to the present disclosure includes:
A second electrode composed of at least a quaternary compound of indium (In), gallium (Ga) and / or aluminum (Al), zinc (Zn), and oxygen (O) on the light emitting / receiving layer. Is formed based on the sputtering method, and then
The light emitting / receiving layer is composed of at least a quaternary compound of indium (In), gallium (Ga) and / or aluminum (Al), zinc (Zn), and oxygen (O) based on a sputtering method. Covered with an insulating layer,
Including at least a step,
By controlling the oxygen gas partial pressure (oxygen gas introduction amount) when forming the second electrode and the insulating layer based on the sputtering method, the composition ratio of oxygen (O) in the insulating layer is changed to oxygen (O) in the second electrode. Higher than the composition ratio.
 上記の目的を達成するための本開示の絶縁材料は、インジウム(In)と、ガリウム(Ga)及び/又はアルミニウム(Al)と、亜鉛(Zn)と、酸素(O)との少なくとも四元系化合物から構成されている。 In order to achieve the above object, an insulating material of the present disclosure includes at least a quaternary system of indium (In), gallium (Ga) and / or aluminum (Al), zinc (Zn), and oxygen (O). It is composed of compounds.
 本開示にあっては、第2電極及び絶縁層の組成及び酸素の組成割合が規定されており、第2電極及び絶縁層を同種の材料で形成できるが故に、より合理的な方法で、あるいは又、より低い温度のプロセスで、電子デバイスを製造することが可能となるし、しかも、第2電極及び絶縁層が同種の材料であるにも拘わらず、それぞれに、導電性、絶縁性を付与することができる。尚、本明細書に記載された効果はあくまで例示であって限定されるものでは無く、また、付加的な効果があってもよい。 In the present disclosure, the composition of the second electrode and the insulating layer and the composition ratio of oxygen are defined, and the second electrode and the insulating layer can be formed of the same kind of material. In addition, it becomes possible to manufacture an electronic device by a process at a lower temperature, and even though the second electrode and the insulating layer are made of the same material, they impart conductivity and insulating properties to each. can do. Note that the effects described in the present specification are merely examples and are not limited, and may have additional effects.
図1A及び図1Bは、実施例1の電子デバイス及びその変形例の模式的な一部断面図であり、図1Cは、実施例3の電子デバイスの模式的な一部断面図である。1A and 1B are schematic partial cross-sectional views of the electronic device of the first embodiment and its modification, and FIG. 1C is a schematic partial cross-sectional view of the electronic device of the third embodiment. 図2は、実施例1において、成膜時の酸素ガス分圧と、得られたIGZO膜の内部応力との関係を調べた結果を示すグラフである。FIG. 2 is a graph showing the results of examining the relationship between the oxygen gas partial pressure during film formation and the internal stress of the obtained IGZO film in Example 1. 図3Aは、実施例2において、スパッタリング法に基づき第1電極を形成する際の酸素ガス導入量(酸素ガス分圧)と第1電極の仕事関数の値との関係を求めた結果の一例を示すグラフであり、図3Bは、実施例2、実施例3及び比較例2の電子デバイスにおいて得られたI-V曲線のグラフである。FIG. 3A shows an example of a result obtained by obtaining a relationship between an oxygen gas introduction amount (oxygen gas partial pressure) and a work function value of the first electrode when forming the first electrode based on the sputtering method in Example 2. FIG. 3B is a graph of IV curves obtained in the electronic devices of Example 2, Example 3, and Comparative Example 2. 図4A及び図4Bは、それぞれ、実施例2及び比較例2の電子デバイスにおけるエネルギーダイヤグラムの概念図であり、図4C及び図4Dは、それぞれ、実施例2及び比較例2の電子デバイスにおける仕事関数の値の差とエネルギーダイヤグラムとの相関を示す概念図である。4A and 4B are conceptual diagrams of energy diagrams in the electronic devices of Example 2 and Comparative Example 2, respectively. FIGS. 4C and 4D are work functions in the electronic devices of Example 2 and Comparative Example 2, respectively. It is a conceptual diagram which shows the correlation with the difference of the value of and an energy diagram. 図5A及び図5Bは、それぞれ、実施例2の電子デバイスにおける内部量子効率と仕事関数の値の差との相関、及び、暗電流と仕事関数の値の差との相関を示すグラフである。FIG. 5A and FIG. 5B are graphs showing the correlation between the internal quantum efficiency and the difference between the work function values and the correlation between the dark current and the difference between the work function values in the electronic device of Example 2, respectively. 図6A及び図6Bは、それぞれ、実施例3の電子デバイスにおける内部量子効率と仕事関数の値の差との相関、及び、暗電流と仕事関数の値の差との相関を示すグラフである。6A and 6B are graphs showing the correlation between the internal quantum efficiency and the difference between the work function values in the electronic device of Example 3, and the correlation between the dark current and the difference between the work function values, respectively. 図7A及び図7Bは、実施例4の電子デバイスの模式的な一部断面図である。7A and 7B are schematic partial cross-sectional views of the electronic device of Example 4. FIG. 図8は、実施例4の電子デバイスの変形例の模式的な一部断面図である。FIG. 8 is a schematic partial cross-sectional view of a modification of the electronic device of the fourth embodiment. 図9は、実施例4の電子デバイスの走査透過電子顕微鏡像である。FIG. 9 is a scanning transmission electron microscope image of the electronic device of Example 4. 図10は、電子デバイスのシリーズ抵抗値と、p側電極を構成する材料の仕事関数の値との関係を示す図である。FIG. 10 is a diagram showing the relationship between the series resistance value of the electronic device and the value of the work function of the material constituting the p-side electrode. 図11A及び図11Bは、実施例6の電子デバイス及びその変形例の模式的な一部断面図である。FIG. 11A and FIG. 11B are schematic partial cross-sectional views of the electronic device of Example 6 and its modification. 図12は、実施例7の固体撮像装置の概念図である。FIG. 12 is a conceptual diagram of the solid-state imaging device according to the seventh embodiment. 図13は、p型GaNから成る第2化合物半導体層上に形成された第2電極と抵抗値との関係を示す図である。FIG. 13 is a diagram showing the relationship between the second electrode formed on the second compound semiconductor layer made of p-type GaN and the resistance value.
 以下、図面を参照して、実施例に基づき本開示を説明するが、本開示は実施例に限定されるものではなく、実施例における種々の数値や材料は例示である。尚、説明は、以下の順序で行う。
1.本開示の電子デバイス及びその製造方法、固体撮像装置、並びに、絶縁材料、全般に関する説明
2.実施例1(本開示の電子デバイス及びその製造方法、第1-Cの構成の電子デバイス、並びに、本開示の絶縁材料)
3.実施例2(実施例1の変形、第1-Aの構成の電子デバイス、第1-Cの構成の電子デバイス)
4.実施例3(実施例1の別の変形、第1-Bの構成の電子デバイス、第1-Cの構成の電子デバイス)
5.実施例4(実施例1の更に別の変形、第2-Aの構成の電子デバイス)
6.実施例5(実施例4の変形)
7.実施例6(実施例1の更に別の変形、第2-Bの構成の電子デバイス)
8.実施例7(本開示の固体撮像装置)
9.その他
Hereinafter, although this indication is explained based on an example with reference to drawings, this indication is not limited to an example and various numerical values and materials in an example are illustrations. The description will be given in the following order.
1. 1. Description of electronic device and manufacturing method thereof, solid-state imaging device, and insulating material of the present disclosure Example 1 (Electronic Device of the Present Disclosure and Method for Producing the Same, Electronic Device of Configuration 1-C, and Insulating Material of the Present Disclosure)
3. Example 2 (Modification of Example 1, Electronic Device with Configuration 1-A, Electronic Device with Configuration 1-C)
4). Example 3 (another modification of Example 1, an electronic device having a first-B configuration, and an electronic device having a first-C configuration)
5. Example 4 (another modification of Example 1, electronic device having configuration 2-A)
6). Example 5 (Modification of Example 4)
7). Example 6 (another modification of Example 1, electronic device having the configuration 2-B)
8). Example 7 (Solid-state imaging device of the present disclosure)
9. Other
〈本開示の電子デバイス及びその製造方法、固体撮像装置、並びに、絶縁材料、全般に関する説明〉
 本開示の電子デバイスの製造方法において、絶縁層をスパッタリング法に基づき形成する際の酸素ガス分圧を、限定するものではないが、0.04Pa乃至0.15Paとすることが好ましい。そして、このような好ましい形態を含む本開示の電子デバイスの製造方法にあっては、スパッタリング法に基づき絶縁層を形成する際の温度を、室温、あるいは又、22゜C乃至28゜Cとすることが好ましい。更には、これらの好ましい形態を含む本開示の電子デバイスの製造方法において、電子デバイスは光電変換素子を構成する形態とすることができる。
<Description of Electronic Device of the Present Disclosure and Method for Manufacturing the Same, Solid-State Imaging Device, and Insulating Material>
In the method of manufacturing an electronic device according to the present disclosure, the oxygen gas partial pressure when forming the insulating layer based on the sputtering method is not limited, but is preferably 0.04 Pa to 0.15 Pa. And in the manufacturing method of the electronic device of this indication containing such a preferable form, the temperature at the time of forming an insulating layer based on sputtering method shall be room temperature or 22 to 28 degreeC. It is preferable. Furthermore, in the manufacturing method of the electronic device of the present disclosure including these preferable modes, the electronic device can be configured to constitute a photoelectric conversion element.
 本開示の電子デバイス、及び、以上に説明した各種の好ましい形態を含む本開示の電子デバイスの製造方法によって得られる電子デバイス(以下、これらを総称して、『本開示の電子デバイス等』と呼ぶ場合がある)において、
 第2電極は、Ina(Ga,Al)bZncdから成り、
 絶縁層は、Ina(Ga,Al)bZnce(但し、d<e)から成る形態とすることができる。尚、第2電極及び絶縁層は、非晶質状態にあることが好ましい。
The electronic device of the present disclosure and the electronic device obtained by the manufacturing method of the electronic device of the present disclosure including the various preferred embodiments described above (hereinafter, these are collectively referred to as “electronic device etc. of the present disclosure”). In some cases)
The second electrode is made of In a (Ga, Al) b Zn c O d ,
The insulating layer may be made of In a (Ga, Al) b Zn c O e (where d <e). Note that the second electrode and the insulating layer are preferably in an amorphous state.
 以上に説明した各種の好ましい形態を含む本開示の電子デバイス等において、絶縁層及び第2電極は、インジウム-ガリウム酸化物(IGO)、インジウム・ドープのガリウム-亜鉛酸化物(IGZO,In-GaZnO4)、酸化アルミニウム・ドープの酸化亜鉛(AZO)、インジウム-亜鉛酸化物(IZO)、又は、ガリウム・ドープの酸化亜鉛(GZO)といった、透明導電性材料から構成されている形態とすることができる。 In the electronic device or the like of the present disclosure including the various preferable embodiments described above, the insulating layer and the second electrode are indium-gallium oxide (IGO), indium-doped gallium-zinc oxide (IGZO, In-GaZnO). 4 ) may be made of a transparent conductive material such as aluminum oxide-doped zinc oxide (AZO), indium-zinc oxide (IZO), or gallium-doped zinc oxide (GZO). it can.
 更には、以上に説明した各種の好ましい形態を含む本開示の電子デバイス等において、絶縁層の内部応力は、10MPa乃至90MPaの圧縮応力である形態とすることができる。 Furthermore, in the electronic device and the like of the present disclosure including the various preferable forms described above, the internal stress of the insulating layer can be a form having a compressive stress of 10 MPa to 90 MPa.
 更には、以上に説明した各種の好ましい形態を含む本開示の電子デバイス等において、波長400nm乃至660nmの光に対する絶縁層の光透過率は80%以上である形態とすることができる。 Furthermore, in the electronic device of the present disclosure including the various preferable forms described above, the light transmittance of the insulating layer with respect to light having a wavelength of 400 nm to 660 nm can be 80% or more.
 更には、以上に説明した各種の好ましい形態を含む本開示の電子デバイス等において、波長400nm乃至660nmの光に対する第2電極の光透過率は75%以上である形態とすることができる。 Furthermore, in the electronic device of the present disclosure including the various preferable forms described above, the light transmittance of the second electrode with respect to light having a wavelength of 400 nm to 660 nm may be 75% or more.
 更には、以上に説明した各種の好ましい形態を含む本開示の電子デバイス等において、第2電極のシート抵抗値は3×10Ω/□乃至1×103Ω/□である形態とすることができる。 Furthermore, in the electronic device of the present disclosure including the various preferable forms described above, the sheet resistance value of the second electrode may be 3 × 10 Ω / □ to 1 × 10 3 Ω / □. .
 更には、以上に説明した各種の好ましい形態を含む本開示の電子デバイス等において、第2電極及び絶縁層をスパッタリング法に基づき形成する際の酸素ガス分圧(酸素ガス導入量)を制御することで、第2電極及び絶縁層における酸素(O)の組成割合が制御される形態とすることができる。 Furthermore, in the electronic device of the present disclosure including the various preferable embodiments described above, the oxygen gas partial pressure (oxygen gas introduction amount) when the second electrode and the insulating layer are formed based on the sputtering method is controlled. Thus, the composition ratio of oxygen (O) in the second electrode and the insulating layer can be controlled.
 更には、以上に説明した各種の好ましい形態を含む本開示の電子デバイス等において、
 発光・受光層は、第1電極及び第2電極によって挟まれており、
 第2電極の仕事関数の値と第1電極の仕事関数の値との差は0.4eV以上である構成とすることができる。尚、このような構成の本開示の電子デバイス等を、便宜上、『第1-Aの構成の電子デバイス』と呼ぶ。
Furthermore, in the electronic device of the present disclosure including the various preferred embodiments described above,
The light emitting / receiving layer is sandwiched between the first electrode and the second electrode,
The difference between the work function value of the second electrode and the work function value of the first electrode may be 0.4 eV or more. Note that the electronic device of the present disclosure having such a configuration is referred to as an “electronic device having the first-A configuration” for convenience.
 あるいは又、以上に説明した各種の好ましい形態を含む本開示の電子デバイス等において、
 発光・受光層は、第1電極及び第2電極によって挟まれており、
 第2電極は、発光・受光層側から、第2B層及び第2A層の積層構造を有し、
 第2電極の第2A層の仕事関数の値は、第2電極の第2B層の仕事関数の値よりも低い構成とすることができる。尚、このような構成の本開示の電子デバイス等を、便宜上、『第1-Bの構成の電子デバイス』と呼ぶ。
Alternatively, in the electronic device and the like of the present disclosure including the various preferable modes described above,
The light emitting / receiving layer is sandwiched between the first electrode and the second electrode,
The second electrode has a laminated structure of the second B layer and the second A layer from the light emitting / receiving layer side,
The work function value of the second A layer of the second electrode may be lower than the work function value of the second B layer of the second electrode. Note that the electronic device of the present disclosure having such a configuration is referred to as an “electronic device having the configuration of 1-B” for convenience.
 第1-Aの構成の電子デバイスにあっては、第2電極の仕事関数の値と第1電極の仕事関数の値との差が規定されているので、第1電極と第2電極との間にバイアス電圧を印加したとき、内部量子効率の向上を図ることができるし、また、暗電流の発生を抑制することが可能となる。また、第1-Bの構成の電子デバイスにあっては、第2電極が第2A層及び第2B層の2層構造を有し、しかも、第2B層と第2A層の仕事関数の差が規定されているので、第2電極における仕事関数の最適化を図ることができ、キャリアの授受(移動)が一層容易になる。そして、第1-Aの構成の電子デバイスの製造にあっては、スパッタリング法に基づき形成する際の酸素ガス分圧(酸素ガス導入量)を制御することで第2電極の仕事関数の値を制御することができる結果、仕事関数の値の差に基づき発光・受光層において大きな内部電界を発生させることができ、内部量子効率の向上を図ることができるし、また、暗電流の発生を抑制することが可能な電子デバイスを、簡素な製造プロセスで製造することができる。第1-Bの構成の電子デバイスの製造にあっては、スパッタリング法に基づき形成する際の酸素ガス分圧(酸素ガス導入量)を制御することで第2電極の第2A層及び第2B層の仕事関数の値を制御することができる結果、第2電極の仕事関数の最適化を図ることができる。 In the electronic device having the configuration 1-A, since the difference between the work function value of the second electrode and the work function value of the first electrode is defined, the difference between the first electrode and the second electrode is determined. When a bias voltage is applied between them, the internal quantum efficiency can be improved and the generation of dark current can be suppressed. In the electronic device having the configuration 1-B, the second electrode has a two-layer structure of the second A layer and the second B layer, and the work function difference between the second B layer and the second A layer is small. Since it is defined, the work function in the second electrode can be optimized, and the transfer (transfer) of the carrier becomes easier. In the manufacture of the electronic device having the configuration 1-A, the work function value of the second electrode is set by controlling the oxygen gas partial pressure (oxygen gas introduction amount) when forming based on the sputtering method. As a result of control, it is possible to generate a large internal electric field in the light emitting / receiving layer based on the difference in the work function value, improve internal quantum efficiency, and suppress the generation of dark current The electronic device that can be manufactured can be manufactured by a simple manufacturing process. In the manufacture of the electronic device having the configuration 1-B, the second A layer and the second B layer of the second electrode are controlled by controlling the oxygen gas partial pressure (oxygen gas introduction amount) when forming based on the sputtering method. As a result, the work function of the second electrode can be optimized.
 そして、第1-Aの構成の電子デバイスにあっては、第2電極の仕事関数の値と第1電極の仕事関数の値との差を0.4eV以上とすることで、仕事関数の値の差に基づき発光・受光層において内部電界を発生させ、内部量子効率の向上を図る構成とすることができる。第1-Aの構成の電子デバイスにおいて、第2電極の厚さを1×10-8m乃至1×10-7mとすることが好ましい。 In the electronic device having the configuration 1-A, the difference between the work function value of the second electrode and the work function value of the first electrode is 0.4 eV or more. Based on this difference, an internal electric field can be generated in the light emitting / receiving layer to improve the internal quantum efficiency. In the electronic device having the configuration 1-A, the thickness of the second electrode is preferably 1 × 10 −8 m to 1 × 10 −7 m.
 また、第1-Bの構成の電子デバイスにおいて、第2電極の第2A層の仕事関数の値と第2電極の第2B層の仕事関数の値との差は、0.1eV乃至0.2eVである構成とすることができる。更には、これらの構成にあっては、第1電極の仕事関数の値と第2電極の第2A層の仕事関数の値との差は0.4eV以上であることが好ましい。更には、以上に説明した好ましい構成を含む第1-Bの構成の電子デバイスにおいて、第2電極の厚さは1×10-8m乃至1×10-7mであり、第2電極の第2A層の厚さと第2電極の第2B層の厚さの割合は9/1乃至1/9である構成とすることができる。尚、発光・受光層に対する酸素原子や酸素分子の影響を少なくするために、第2電極の第2A層の厚さよりも第2B層の厚さは薄いことが、より好ましい。更には、以上に説明した好ましい構成を含む第1-Bの構成の電子デバイスにおいて、第1電極の仕事関数の値と第2電極の第2A層の仕事関数の値との差を0.4eV以上とすることで、仕事関数の値の差に基づき発光・受光層において内部電界を発生させ、内部量子効率の向上を図ることが好ましい。 In the electronic device having the configuration 1-B, the difference between the work function value of the second electrode 2A layer and the work function value of the second electrode layer 2B is 0.1 eV to 0.2 eV. It can be set as the structure which is. Furthermore, in these configurations, the difference between the work function value of the first electrode and the work function value of the second A layer of the second electrode is preferably 0.4 eV or more. Further, in the electronic device having the first-B configuration including the preferable configuration described above, the thickness of the second electrode is 1 × 10 −8 m to 1 × 10 −7 m, and the second electrode The ratio of the thickness of the 2A layer and the thickness of the second B layer of the second electrode may be 9/1 to 1/9. In order to reduce the influence of oxygen atoms and oxygen molecules on the light emitting / receiving layer, it is more preferable that the thickness of the second B layer is smaller than the thickness of the second A layer of the second electrode. Further, in the electronic device having the first-B configuration including the preferable configuration described above, the difference between the work function value of the first electrode and the work function value of the second A layer of the second electrode is set to 0.4 eV. With the above, it is preferable to improve the internal quantum efficiency by generating an internal electric field in the light emitting / receiving layer based on the difference in the work function values.
 更には、以上に説明した好ましい構成を含む第1-Aの構成の電子デバイスあるいは第1-Bの構成の電子デバイスにおいて、第2電極の仕事関数の値は、限定するものではないが、例えば、4.1eV乃至4.5eVである構成とすることができる。 Furthermore, in the electronic device having the first-A configuration or the electronic device having the first-B configuration including the preferred configuration described above, the value of the work function of the second electrode is not limited, The configuration may be 4.1 eV to 4.5 eV.
 更には、以上に説明した好ましい構成を含む第1-Aの構成の電子デバイスあるいは第1-Bの構成の電子デバイスにおいて、前述したとおり、第2電極は、インジウム-ガリウム酸化物(IGO)、インジウム・ドープのガリウム-亜鉛酸化物(IGZO,In-GaZnO4)、酸化アルミニウム・ドープの酸化亜鉛(AZO)、インジウム-亜鉛酸化物(IZO)、又は、ガリウム・ドープの酸化亜鉛(GZO)といった、透明導電性材料から構成されている構成とすることができ、これらの透明導電性材料から構成された第2電極の仕事関数の値は、例えば、4.1eV乃至4.5eVである。また、これらの好ましい構成を含む第1-Aの構成の電子デバイスあるいは第1-Bの構成の電子デバイスにおいて、第1電極は、インジウム-スズ酸化物(ITO)、インジウム-亜鉛酸化物(IZO)、又は、酸化錫(SnO2)といった、透明導電性材料から構成されている構成とすることができる。尚、これらの透明導電性材料から構成された第1電極の仕事関数の値は、例えば、4.8eV乃至5.0eVである。 Furthermore, in the electronic device having the first-A configuration including the preferred configuration described above or the electronic device having the first-B configuration, as described above, the second electrode includes indium-gallium oxide (IGO), Indium-doped gallium-zinc oxide (IGZO, In-GaZnO 4 ), aluminum oxide-doped zinc oxide (AZO), indium-zinc oxide (IZO), or gallium-doped zinc oxide (GZO) The work function value of the second electrode made of these transparent conductive materials can be 4.1 eV to 4.5 eV, for example. Further, in the electronic device having the 1-A configuration or the 1-B configuration including these preferable configurations, the first electrode is composed of indium-tin oxide (ITO), indium-zinc oxide (IZO). Or a transparent conductive material such as tin oxide (SnO 2 ). In addition, the value of the work function of the 1st electrode comprised from these transparent conductive materials is 4.8 eV thru | or 5.0 eV, for example.
 更には、以上に説明した好ましい構成を含む第1-Aの構成の電子デバイスあるいは第1-Bの構成の電子デバイスにおいて、第2電極をスパッタリング法に基づき形成する際の酸素ガス分圧(酸素ガス導入量)を制御することで、第2電極の仕事関数の値が制御される構成とすることができる。また、第2電極をスパッタリング法に基づき形成する際の酸素ガス分圧(酸素ガス導入量)を制御することで、第2電極の第2A層及び第2B層の仕事関数の値が制御される構成とすることができる。第2電極において、酸素の含有率は化学量論組成の酸素含有率よりも少ない構成とすることができる。あるいは又、第2電極の第2A層の酸素の含有率は、第2電極の第2B層の酸素の含有率よりも低い構成とすることができる。そして、酸素の含有率に基づいて第2電極の仕事関数の値を制御することができ、酸素の含有率が化学量論組成の酸素含有率よりも少なくなる程、即ち、酸素欠損が多くなる程、仕事関数の値は小さくなる。 Further, in the electronic device having the first-A configuration or the first-B configuration including the preferred configuration described above, the oxygen gas partial pressure (oxygen gas) when the second electrode is formed by sputtering is used. By controlling the gas introduction amount), the work function value of the second electrode can be controlled. Further, the work function values of the second A layer and the second B layer of the second electrode are controlled by controlling the oxygen gas partial pressure (oxygen gas introduction amount) when forming the second electrode based on the sputtering method. It can be configured. In the second electrode, the oxygen content may be lower than the oxygen content of the stoichiometric composition. Alternatively, the oxygen content of the second A layer of the second electrode can be lower than the oxygen content of the second B layer of the second electrode. Then, the work function value of the second electrode can be controlled based on the oxygen content, and the oxygen content becomes smaller than the oxygen content of the stoichiometric composition, that is, oxygen deficiency increases. As the value of the work function decreases.
 以上に説明した好ましい構成を含む第1-Aの構成の電子デバイスあるいは第1-Bの構成の電子デバイスにおいて、具体的には、例えば、第1電極が基板上に形成されており、発光・受光層が第1電極上に形成されており、第2電極が発光・受光層上に形成されている構成とすることができる。即ち、本開示の電子デバイス等は、第1電極及び第2電極を備えた2端子型電子デバイス構造を有する。但し、これに限定するものではなく、更に制御電極を備えた3端子型電子デバイス構造としてもよく、制御電極への電圧の印加によって、流れる電流の変調を行うことが可能となる。3端子型電子デバイス構造として、具体的には、所謂ボトムゲート/ボトムコンタクト型、ボトムゲート/トップコンタクト型、トップゲート/ボトムコンタクト型、トップゲート/トップコンタクト型の電界効果型トランジスタ(FET)と同じ構成、構造を挙げることができる。尚、第2電極をカソード電極(陰極)として機能させる(即ち、電子を取り出す電極として機能させる)ことができる一方、第1電極をアノード電極(陽極)として機能させる(即ち、正孔を取り出す電極として機能させる)ことができる。発光・受光層が異なる光吸収スペクトルを有する電子デバイス等を複数、積層した構造を採用することもできる。また、例えば、基板をシリコン半導体基板から構成し、このシリコン半導体基板に電子デバイス等の駆動回路や、発光・受光層を設けておき、このシリコン半導体基板に電子デバイス等を積層した構造を採用することもできる。 In the electronic device having the first-A configuration or the first-B configuration including the preferred configuration described above, specifically, for example, the first electrode is formed on the substrate, and The light receiving layer may be formed on the first electrode, and the second electrode may be formed on the light emitting / light receiving layer. That is, the electronic device or the like of the present disclosure has a two-terminal electronic device structure including the first electrode and the second electrode. However, the present invention is not limited to this, and a three-terminal electronic device structure provided with a control electrode may be used, and the current flowing can be modulated by applying a voltage to the control electrode. Specifically, as a three-terminal electronic device structure, a so-called bottom gate / bottom contact type, bottom gate / top contact type, top gate / bottom contact type, top gate / top contact type field effect transistor (FET) and The same structure and structure can be mentioned. The second electrode can function as a cathode electrode (cathode) (that is, function as an electrode that extracts electrons), while the first electrode can function as an anode electrode (anode) (that is, an electrode that extracts holes). Function as). It is also possible to adopt a structure in which a plurality of electronic devices or the like having different light absorption spectra in the light emitting / receiving layers are stacked. In addition, for example, a structure in which a substrate is formed of a silicon semiconductor substrate, a drive circuit such as an electronic device or a light emitting / receiving layer is provided on the silicon semiconductor substrate, and the electronic device is stacked on the silicon semiconductor substrate is employed. You can also
 以上に説明した好ましい構成を含む第1-Aの構成の電子デバイスあるいは第1-Bの構成を含む本開示の電子デバイス等において、発光・受光層は、アモルファス状態であってもよいし、結晶状態であってもよい。発光・受光層を構成する有機材料(有機光電変換材料)として、有機半導体材料、有機金属化合物、有機半導体微粒子を挙げることができるし、あるいは又、発光・受光層を構成する材料として、金属酸化物半導体、無機半導体微粒子、コア部材がシェル部材で被覆された材料、有機-無機ハイブリッド化合物を挙げることができる。尚、このような構成の本開示の電子デバイス等(第1-Aの構成の電子デバイス、第1-Bの構成の電子デバイスを含む)を、便宜上、『第1-Cの構成の電子デバイス』と呼ぶ。 In the electronic device having the first-A configuration including the preferred configuration described above or the electronic device of the present disclosure including the first-B configuration, the light emitting / receiving layer may be in an amorphous state or a crystal It may be in a state. Examples of the organic material (organic photoelectric conversion material) constituting the light emitting / receiving layer include organic semiconductor materials, organometallic compounds, and organic semiconductor fine particles, or metal oxide as the material constituting the light emitting / receiving layer. Examples thereof include a physical semiconductor, inorganic semiconductor fine particles, a material in which a core member is covered with a shell member, and an organic-inorganic hybrid compound. For the sake of convenience, the electronic device or the like of the present disclosure having such a configuration (including the electronic device having the first-A configuration and the electronic device having the first-B configuration) is referred to as “the electronic device having the first-C configuration”. Call it.
 ここで、有機半導体材料として、具体的には、キナクリドン及びその誘導体に代表される有機色素、Alq3[tris(8-quinolinolato)aluminum(III)]に代表される前周期(周期表の左側の金属を指す)イオンを有機材料でキレート化した色素、フタロシアニン亜鉛(II)に代表される遷移金属イオンと有機材料によって錯形成された有機金属色素、ジナフトチエノチオフェン(DNTT)等を挙げることができる。 Here, as an organic semiconductor material, specifically, an organic dye represented by quinacridone and its derivatives, a previous period represented by Alq3 [tris (8-quinolinolato) aluminum (III)] (metal on the left side of the periodic table) Dyes obtained by chelating ions with an organic material, organometallic dyes complexed with a transition metal ion typified by zinc phthalocyanine (II), and dinaphthothienothiophene (DNTT). .
 また、有機金属化合物として、具体的には、上述した前周期イオンを有機材料でキレート化した色素、遷移金属イオンと有機材料によって錯形成された有機金属色素を挙げることができる。有機半導体微粒子として、具体的には、前述したキナクリドン及びその誘導体に代表される有機色素の会合体、前周期イオンを有機材料でキレート化した色素の会合体、遷移金属イオンと有機材料によって錯形成された有機金属色素の会合体、あるいは又、金属イオンをシアノ基で架橋したプルシアンブルー及びその誘導体、あるいは又、これらの複合会合体を挙げることができる。 Specific examples of the organometallic compound include a dye obtained by chelating the above-described periodic ions with an organic material, and an organometallic dye complexed with a transition metal ion and an organic material. As organic semiconductor fine particles, specifically, organic dye aggregates represented by the above-mentioned quinacridone and derivatives thereof, dye aggregates obtained by chelating the precursor ions with organic materials, and complex formation with transition metal ions and organic materials And an organic metal dye aggregate, or Prussian blue obtained by crosslinking a metal ion with a cyano group and derivatives thereof, or a complex aggregate thereof.
 金属酸化物半導体あるいは無機半導体微粒子として、具体的には、ITO、IGZO、ZnO、IZO、IrO2、TiO2、SnO2、SiOX、カルゴゲン[例えば、硫黄(S)、セレン(Se)、テルル(Te)]を含む金属カルゴゲン半導体(具体的には、CdS、CdSe、ZnS、CdSe/CdS、CdSe/ZnS、PbSe)、ZnO、CdTe、GaAs、及び、Siを挙げることができる。 As the metal oxide semiconductor or inorganic semiconductor fine particles, specifically, ITO, IGZO, ZnO, IZO, IrO 2 , TiO 2 , SnO 2 , SiO x , karogen [for example, sulfur (S), selenium (Se), tellurium (Te)] can be given as metal karogen semiconductors (specifically, CdS, CdSe, ZnS, CdSe / CdS, CdSe / ZnS, PbSe), ZnO, CdTe, GaAs, and Si.
 コア部材がシェル部材で被覆された材料、即ち、(コア部材,シェル部材)の組合せとして、具体的には、(ポリスチレン,ポリアニリン)といった有機材料や、(イオン化し難い金属材料,イオン化し易い金属材料)といった金属材料を挙げることができる。有機-無機ハイブリッド化合物として、具体的には、金属イオンをシアノ基で架橋したプルシアンブルー及びその誘導体を挙げることができるし、その他、ビピリジン類で金属イオンを無限架橋したもの、シュウ酸、ルベアン酸に代表される多価イオン酸で金属イオンを架橋したものの総称である配位高分子(Coordination Polymer)を挙げることができる。 As a combination of a material in which a core member is covered with a shell member, that is, a combination of (core member, shell member), specifically, an organic material such as (polystyrene, polyaniline), a metal material that is difficult to ionize, or a metal that is easily ionized Metal material). Specific examples of organic-inorganic hybrid compounds include Prussian blue in which metal ions are cross-linked with cyano groups and derivatives thereof. In addition, compounds in which metal ions are infinitely cross-linked with bipyridines, oxalic acid, rubeanic acid Coordination polymer (Coordination Polymer), which is a generic name of cross-linked metal ions with polyvalent ionic acids represented by
 第1-Cの構成の電子デバイスにおいて、発光・受光層の形成方法として、使用する材料にも依るが、塗布法、物理的気相成長法(PVD法);MOCVD法を含む各種の化学的気相成長法(CVD法)を挙げることができる。ここで、塗布法として、具体的には、スピンコート法;浸漬法;キャスト法;スクリーン印刷法やインクジェット印刷法、オフセット印刷法、グラビア印刷法といった各種印刷法;スタンプ法;スプレー法;エアドクタコーター法、ブレードコーター法、ロッドコーター法、ナイフコーター法、スクイズコーター法、リバースロールコーター法、トランスファーロールコーター法、グラビアコーター法、キスコーター法、キャストコーター法、スプレーコーター法、スリットオリフィスコーター法、カレンダーコーター法といった各種コーティング法を例示することができる。尚、塗布法においては、溶媒として、トルエン、クロロホルム、ヘキサン、エタノールといった無極性又は極性の低い有機溶媒を例示することができる。また、PVD法として、電子ビーム加熱法、抵抗加熱法、フラッシュ蒸着等の各種真空蒸着法;プラズマ蒸着法;2極スパッタリング法、直流スパッタリング法、直流マグネトロンスパッタリング法、高周波スパッタリング法、マグネトロンスパッタリング法、イオンビームスパッタリング法、バイアススパッタリング法等の各種スパッタリング法;DC(direct current)法、RF法、多陰極法、活性化反応法、電界蒸着法、高周波イオンプレーティング法、反応性イオンプレーティング法等の各種イオンプレーティング法を挙げることができる。 In the electronic device having the 1st-C structure, various chemical methods including a coating method, a physical vapor deposition method (PVD method), and a MOCVD method are used as a method for forming a light emitting / receiving layer depending on a material to be used. A vapor phase growth method (CVD method) can be mentioned. Here, as a coating method, specifically, spin coating method; dipping method; casting method; various printing methods such as screen printing method, inkjet printing method, offset printing method, gravure printing method; stamp method; spray method; air doctor Coater method, blade coater method, rod coater method, knife coater method, squeeze coater method, reverse roll coater method, transfer roll coater method, gravure coater method, kiss coater method, cast coater method, spray coater method, slit orifice coater method, calendar Various coating methods such as a coater method can be exemplified. In the coating method, examples of the solvent include nonpolar or low polarity organic solvents such as toluene, chloroform, hexane, and ethanol. Further, as the PVD method, various vacuum deposition methods such as an electron beam heating method, a resistance heating method, and a flash deposition method; a plasma deposition method; a bipolar sputtering method, a direct current sputtering method, a direct current magnetron sputtering method, a high frequency sputtering method, a magnetron sputtering method, Various sputtering methods such as ion beam sputtering and bias sputtering; DC (direct current) method, RF method, multi-cathode method, activation reaction method, field deposition method, high-frequency ion plating method, reactive ion plating method, etc. Examples of various ion plating methods can be given.
 また、第1-Cの構成の電子デバイスにおいて、発光・受光層の厚さは、限定するものではないが、例えば、1×10-10m乃至5×10-7mを例示することができる。 Further, in the electronic device having the first-C configuration, the thickness of the light emitting / receiving layer is not limited. For example, the thickness may be 1 × 10 −10 m to 5 × 10 −7 m. .
 更には、第1-Cの構成の電子デバイスにおいて、基板として、ポリメチルメタクリレート(ポリメタクリル酸メチル,PMMA)やポリビニルアルコール(PVA)、ポリビニルフェノール(PVP)、ポリエーテルスルホン(PES)、ポリイミド、ポリカーボネート(PC)、ポリエチレンテレフタレート(PET)、ポリエチレンナフタレート(PEN)に例示される有機ポリマー(高分子材料から構成された可撓性を有するプラスチック・フィルムやプラスチック・シート、プラスチック基板といった高分子材料の形態を有する)を挙げることができる。このような可撓性を有する高分子材料から構成された基板を使用すれば、例えば曲面形状を有する電子機器への電子デバイスの組込みあるいは一体化が可能となる。あるいは又、基板として、各種ガラス基板や、表面に絶縁膜が形成された各種ガラス基板、石英基板、表面に絶縁膜が形成された石英基板、シリコン半導体基板、表面に絶縁膜が形成されたシリコン半導体基板、ステンレス鋼等の各種合金や各種金属から成る金属基板を挙げることができる。尚、絶縁膜として、酸化ケイ素系材料(例えば、SiOXやスピンオンガラス(SOG));窒化ケイ素(SiNY);酸窒化ケイ素(SiON);酸化アルミニウム(Al23);金属酸化物や金属塩を挙げることができる。また、表面にこれらの絶縁膜が形成された導電性基板(金やアルミニウム等の金属から成る基板、高配向性グラファイトから成る基板)を用いることもできる。基板の表面は、平滑であることが望ましいが、発光・受光層の特性に悪影響を及ぼさない程度のラフネスがあっても構わない。基板の表面にシランカップリング法によるシラノール誘導体を形成したり、SAM法等によりチオール誘導体、カルボン酸誘導体、リン酸誘導体等から成る薄膜を形成したり、CVD法等により絶縁性の金属塩や金属錯体から成る薄膜を形成することで、第1電極や第2電極と基板との間の密着性を向上させてもよい。 Furthermore, in the electronic device having the 1-C configuration, as a substrate, polymethyl methacrylate (polymethyl methacrylate, PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyethersulfone (PES), polyimide, Organic polymers such as polycarbonate (PC), polyethylene terephthalate (PET), and polyethylene naphthalate (PEN) (polymer materials such as flexible plastic films, plastic sheets and plastic substrates made of polymer materials) Can be included). By using a substrate made of such a flexible polymer material, for example, an electronic device can be incorporated or integrated into an electronic device having a curved surface. Alternatively, as a substrate, various glass substrates, various glass substrates with an insulating film formed on the surface, quartz substrates, quartz substrates with an insulating film formed on the surface, silicon semiconductor substrates, silicon with an insulating film formed on the surface Examples include semiconductor substrates, metal substrates made of various alloys such as stainless steel, and various metals. As the insulating film, a silicon oxide-based material (for example, SiO x or spin-on glass (SOG)); silicon nitride (SiN Y ); silicon oxynitride (SiON); aluminum oxide (Al 2 O 3 ); metal oxide or Mention may be made of metal salts. In addition, a conductive substrate (a substrate made of a metal such as gold or aluminum or a substrate made of highly oriented graphite) having these insulating films formed on the surface can also be used. The surface of the substrate is desirably smooth, but may have a roughness that does not adversely affect the characteristics of the light emitting / receiving layer. A silanol derivative is formed on the surface of the substrate by a silane coupling method, a thin film made of a thiol derivative, a carboxylic acid derivative, a phosphoric acid derivative, or the like is formed by a SAM method, or an insulating metal salt or metal is formed by a CVD method. You may improve the adhesiveness between a 1st electrode or a 2nd electrode, and a board | substrate by forming the thin film which consists of a complex.
 更には、以上に説明した各種の好ましい形態、構成を含む本開示の電子デバイス等において、発光・受光層は、有機光電変換材料から成る構成とすることができる。 Furthermore, in the electronic device and the like of the present disclosure including the various preferable modes and configurations described above, the light emitting / receiving layer can be configured of an organic photoelectric conversion material.
 更には、以上に説明した各種の好ましい形態、構成を含む本開示の電子デバイス等において、電子デバイスは光電変換素子から成る構成とすることができる。 Furthermore, in the electronic device and the like of the present disclosure including the various preferable forms and configurations described above, the electronic device can be configured by a photoelectric conversion element.
 以上に説明した各種の好ましい形態、構成を含む本開示の電子デバイス等において、発光・受光層における光(広くは電磁波であり、可視光、紫外線、赤外線を含む)の発光・受光は、第2電極を介して行われてもよいし、第1電極を介して行われてもよい。後者の場合、発光・受光する光に対して透明な基板を用いる必要がある。 In the electronic device of the present disclosure including the various preferable modes and configurations described above, light emission / light reception in the light emission / light reception layer (generally electromagnetic waves, including visible light, ultraviolet rays, and infrared rays) is second. It may be performed via the electrode or may be performed via the first electrode. In the latter case, it is necessary to use a substrate that is transparent to the light emitted and received.
 以上に説明した各種の好ましい形態、構成を含む本開示の電子デバイス等を本開示の固体撮像装置を構成する電子デバイスに対して適用することができる。 The electronic device of the present disclosure including the various preferable modes and configurations described above can be applied to the electronic device constituting the solid-state imaging device of the present disclosure.
 半導体レーザ素子や発光ダイオードに代表される半導体光デバイスは、例えば、第1導電型を有する第1化合物半導体層、活性層、及び、第1導電型とは異なる第2導電型を有する第2化合物半導体層から成る積層構造体(発光・受光層)を有し、第2化合物半導体層上には第2電極が形成されており、第1化合物半導体層は電気的に第1電極に接続された構造を有する。 A semiconductor optical device typified by a semiconductor laser element or a light emitting diode includes, for example, a first compound semiconductor layer having a first conductivity type, an active layer, and a second compound having a second conductivity type different from the first conductivity type. It has a laminated structure (light emitting / receiving layer) made of a semiconductor layer, a second electrode is formed on the second compound semiconductor layer, and the first compound semiconductor layer is electrically connected to the first electrode. It has a structure.
 図13(出典:Ishikawa, et.al., J. Appl. Phys. 81. 1315(1997))に、p型GaNから成る第2化合物半導体層上に形成された第2電極(p側電極)を構成する金属と抵抗値との関係を示す。尚、黒丸印はアニール処理前の値を示し、白丸印は500゜Cでのアニール処理後の値を示す。p型GaNから成る第2化合物半導体層に対する第2電極は、仕事関数の値が大きい金属の方が、より低いショットキバリアを有するため、良好なコンタクト特性が得られる傾向がある。図13から、金属の仕事関数の値が増加するに従い、抵抗値が低下することが判る。そして、このことから、一般に、p型GaNから成る第2化合物半導体層に対するオーミック電極として、仕事関数の値が5eV乃至5.65eVに分布するPd、Pt等の白金族やNi、Au等が用いられている。しかしながら、第2電極を構成する材料の選択自由度を一層高くすることに強い要望がある。 FIG. 13 (Source: Ishikawa, et.al., J. Appl. Phys. 81. 1315 (1997)) shows the second electrode (p-side electrode) formed on the second compound semiconductor layer made of p-type GaN. The relationship between the metal which comprises and resistance value is shown. The black circles indicate values before annealing, and the white circles indicate values after annealing at 500 ° C. As for the second electrode for the second compound semiconductor layer made of p-type GaN, a metal having a larger work function has a lower Schottky barrier, so that good contact characteristics tend to be obtained. FIG. 13 shows that the resistance value decreases as the work function value of the metal increases. Therefore, in general, a platinum group such as Pd and Pt having a work function value distributed between 5 eV and 5.65 eV, Ni, Au, and the like are used as an ohmic electrode for the second compound semiconductor layer made of p-type GaN. It has been. However, there is a strong demand for further increasing the degree of freedom in selecting the material constituting the second electrode.
 このような要望に対処するために、以上に説明した各種の好ましい形態を含む本開示の電子デバイス等において、
 発光・受光層は、第1導電型を有する第1化合物半導体層、活性層、及び、第1導電型とは異なる第2導電型を有する第2化合物半導体層から成る積層構造体から成り、
 第2化合物半導体層上には、コンタクト層を介して、第2電極が形成されており、
 コンタクト層の厚さは、4原子層以下の厚さであり、
 コンタクト層と第2化合物半導体層の界面をxy平面、コンタクト層と接する第2化合物半導体層の部分である界面層を構成する結晶のx軸に沿った格子定数をx2、z軸に沿った格子定数をz2、コンタクト層を構成する結晶の1ユニットにおけるx軸に沿った長さをxC’、z軸に沿った長さをzC’としたとき、
(zC’/xC’)>(z2/x2
を満足する構成とすることができる。尚、このような構成の本開示の電子デバイス等を、便宜上、『第2-Aの構成の電子デバイス』と呼ぶ。
In order to cope with such a demand, in the electronic device of the present disclosure including the various preferable modes described above,
The light emitting / receiving layer is composed of a laminated structure including a first compound semiconductor layer having a first conductivity type, an active layer, and a second compound semiconductor layer having a second conductivity type different from the first conductivity type,
A second electrode is formed on the second compound semiconductor layer via a contact layer,
The thickness of the contact layer is a thickness of 4 atomic layers or less,
The interface between the contact layer and the second compound semiconductor layer is along the xy plane, and the lattice constant along the x axis of the crystal constituting the interface layer that is the portion of the second compound semiconductor layer in contact with the contact layer is along the x 2 and z axes. When the lattice constant is z 2 , the length along the x-axis in one unit of the crystal constituting the contact layer is x C ′, and the length along the z-axis is z C ′,
(Z C '/ x C ')> (z 2 / x 2 )
It can be set as the structure which satisfies these. Note that the electronic device of the present disclosure having such a configuration is referred to as an “electronic device having a configuration of 2-A” for convenience.
 あるいは又、このような要望に対処するために、以上に説明した各種の好ましい形態を含む本開示の電子デバイス等において、
 発光・受光層は、第1導電型を有する第1化合物半導体層、活性層、及び、第1導電型とは異なる第2導電型を有する第2化合物半導体層から成る積層構造体から成り、
 第1化合物半導体層上には、コンタクト層を介して、第1電極が形成されており、
 コンタクト層の厚さは、4原子層以下の厚さであり、
 コンタクト層と第1化合物半導体層の界面をxy平面、コンタクト層と接する第1化合物半導体層の部分である界面層を構成する結晶のx軸に沿った格子定数をx1、z軸に沿った格子定数をz1、コンタクト層を構成する結晶の1ユニットにおけるx軸に沿った長さをxC”、z軸に沿った長さをzC”としたとき、
(zC”/xC”)>(z1/x1
を満足する構成とすることができる。尚、このような構成の本開示の電子デバイス等を、便宜上、『第2-Bの構成の電子デバイス』と呼ぶ。
Alternatively, in order to cope with such a demand, in the electronic device of the present disclosure including the various preferable modes described above,
The light emitting / receiving layer is composed of a laminated structure including a first compound semiconductor layer having a first conductivity type, an active layer, and a second compound semiconductor layer having a second conductivity type different from the first conductivity type,
A first electrode is formed on the first compound semiconductor layer via a contact layer,
The thickness of the contact layer is a thickness of 4 atomic layers or less,
The interface between the contact layer and the first compound semiconductor layer is along the xy plane, and the lattice constant along the x axis of the crystal constituting the interface layer that is the portion of the first compound semiconductor layer in contact with the contact layer is along the x 1 and z axes. When the lattice constant is z 1 , the length along the x-axis in one unit of the crystal constituting the contact layer is x C ″, and the length along the z-axis is z C
(Z C ″ / x C ″)> (z 1 / x 1 )
It can be set as the structure which satisfies these. Note that the electronic device or the like of the present disclosure having such a configuration is referred to as an “electronic device having a second-B configuration” for convenience.
 第2-Aの構成の電子デバイスあるいは第2-Bの構成の電子デバイスにあっては、コンタクト層と接する第2化合物半導体層あるいは第1化合物半導体層の部分である界面層における格子定数と、コンタクト層を構成する結晶の1ユニットにおける長さとが、所定の関係を満足しているが故に、コンタクト層には一種の歪みが発生し、その結果、駆動電圧の低減を図ることができるだけでなく、仕事関数の値の低い材料から第2電極あるいは第1電極を構成することが可能となり、第2電極あるいは第1電極を構成する材料の選択自由度を向上させることができる。 In the electronic device having the configuration 2-A or the electronic device having the configuration 2-B, the lattice constant in the interface layer which is a part of the second compound semiconductor layer or the first compound semiconductor layer in contact with the contact layer; Since the length of one unit of crystal constituting the contact layer satisfies a predetermined relationship, a kind of distortion occurs in the contact layer, and as a result, not only can the drive voltage be reduced. The second electrode or the first electrode can be formed from a material having a low work function value, and the degree of freedom in selecting the material forming the second electrode or the first electrode can be improved.
 第2-Aの構成の電子デバイスあるいは第2-Bの構成の電子デバイスにおいて、コンタクト層の厚さは、4原子層以下の厚さである。コンタクト層の厚さが4原子層を超える厚さであると、コンタクト層に結晶欠陥が発生し、コンタクト抵抗値の増加に繋がる虞がある。コンタクト層は、「層状」であってもよいし、アイランド状(島状)に形成され、層状には形成されていない状態にあってもよい。 In the electronic device having the configuration 2-A or the electronic device having the configuration 2-B, the thickness of the contact layer is 4 atomic layers or less. If the thickness of the contact layer exceeds 4 atomic layers, crystal defects may occur in the contact layer, which may increase the contact resistance value. The contact layer may be “layered” or may be formed in an island shape (island shape) and not in a layered state.
 第2-Aの構成の電子デバイスにおいて、コンタクト層は、第2化合物半導体層の界面層に対して疑似格子整合している構成とすることができる。ここで、疑似格子整合しているとは、xC’の値とx2の値は等しく、しかも、コンタクト層を構成する結晶の1ユニットの体積は、コンタクト層を構成する結晶の格子定数から求められる体積と等しいことを意味する。即ち、このような構成の第2-Aの構成の電子デバイスにおいて、コンタクト層を構成する結晶のx軸に沿った格子定数をxC、z軸に沿った格子定数をzCとしたとき、
2=xC’<xC
C’>zC
を満足する構成とすることができる。尚、「x2=xC’」と表現しているが、この式は、算術的に厳密に等しいだけでなく、
0.90≦xC’/x2≦1.10
である場合を包含する。
In the electronic device having the configuration 2-A, the contact layer may be configured to be pseudo-lattice matched with the interface layer of the second compound semiconductor layer. Here, pseudo-matching means that the value of x C ′ is equal to the value of x 2 , and the volume of one unit of the crystal constituting the contact layer is determined from the lattice constant of the crystal constituting the contact layer. Means equal to the required volume. That is, in the electronic device having the configuration 2-A having such a configuration, when the lattice constant along the x axis of the crystal constituting the contact layer is x C and the lattice constant along the z axis is z C ,
x 2 = x C '<x C
z C '> z C
It can be set as the structure which satisfies these. Although expressed as “x 2 = x C ′”, this expression is not only mathematically strictly equal,
0.90 ≦ x C ′ / x 2 ≦ 1.10
Is included.
 また、第2-Bの構成の電子デバイスにおいて、コンタクト層は、第1化合物半導体層の界面層に対して疑似格子整合している構成とすることができる。ここで、疑似格子整合しているとは、xC”の値とx1の値は等しく、しかも、コンタクト層を構成する結晶の1ユニットの体積は、コンタクト層を構成する結晶の格子定数から求められる体積と等しいことを意味する。即ち、このような構成の第2-Bの構成の電子デバイスにおいて、コンタクト層を構成する結晶のx軸に沿った格子定数をxC、z軸に沿った格子定数をzCとしたとき、
1=xC”<xC
C”>zC
を満足する構成とすることができる。尚、「x1=xC”」と表現しているが、この式は、算術的に厳密に等しいだけでなく、
0.90≦xC”/x1≦1.10
である場合を包含する。
Further, in the electronic device having the configuration 2-B, the contact layer can be configured to be pseudo-lattice matched with the interface layer of the first compound semiconductor layer. Here, pseudo-lattice matching means that the value of x C ″ is equal to the value of x 1 , and the volume of one unit of the crystal constituting the contact layer is determined from the lattice constant of the crystal constituting the contact layer. In other words, in the electronic device having the configuration 2-B, the lattice constant along the x-axis of the crystal forming the contact layer is expressed as x C , along the z-axis. When the lattice constant is z C ,
x 1 = x C ″ <x C
z C ”> z C
It can be set as the structure which satisfies these. Although expressed as “x 1 = x C ”, this expression is not only strictly arithmetically equal,
0.90 ≦ x C ″ / x 1 ≦ 1.10
Is included.
 第2-Aの構成の電子デバイス(あるいは第2-Bの構成の電子デバイス)の上記の好ましい構成を含む第2-Aの構成の電子デバイス(あるいは第2-Bの構成の電子デバイス)において、第2化合物半導体層(あるいは第1化合物半導体層)の界面層を構成する結晶の結晶構造は六方晶系である構成とすることができる。そして、このような構成において、積層構造体は、GaN系化合物半導体から成り、コンタクト層は、第2化合物半導体層(あるいは第1化合物半導体層)の界面層を構成するGaN系化合物半導体と同じ組成のGaN系化合物半導体であって、更に、酸素原子を含むGaN系化合物半導体から成る構成とすることができ、あるいは又、積層構造体は、GaN系化合物半導体から成り、コンタクト層は、第2化合物半導体層(あるいは第1化合物半導体層)の界面層を構成するGaN系化合物半導体と異なる組成のGaN系化合物半導体から成る構成とすることができる。ここで、後者の場合、具体的には、第2化合物半導体層(あるいは第1化合物半導体層)の界面層はGaN層から成り、コンタクト層は、
(a)AlXGaYInZN(但し、X+Y+Z=1,0≦X≦1,0≦Y≦1,0≦Z≦1)から成る構成
(b)AlXGaYInZST(但し、X+Y+Z=1,0≦X≦1,0≦Y≦1,0≦Z≦1,0<S≦1,0<T≦1)から成る構成
(c)AlXGaYInZS1-S(但し、X+Y+Z=1,0≦X≦1,0≦Y≦1,0≦Z≦1,0≦S<1)から成る構成
(d)AlXGaYInZSAs1-S(但し、X+Y+Z=1,0≦X≦1,0≦Y≦1,0≦Z≦1,0≦S<1)から構成
(e)AlXGaYInZSSb1-S(但し、X+Y+Z=1,0≦X≦1,0≦Y≦1,0≦Z≦1,0≦S<1)から成る構成
を挙げることができる。GaN系化合物半導体に酸素原子が含まれるか否かは、例えば、透過電子顕微鏡付属エネルギー分散型X線分析法や三次元アトムプローブ法によって測定することができる。
In the electronic device having the 2-A configuration (or the electronic device having the 2-B configuration) including the above-described preferable configuration of the electronic device having the 2-A configuration (or the electronic device having the 2-B configuration) The crystal structure of the crystal constituting the interface layer of the second compound semiconductor layer (or the first compound semiconductor layer) can be a hexagonal system. In such a configuration, the laminated structure is made of a GaN-based compound semiconductor, and the contact layer has the same composition as the GaN-based compound semiconductor that forms the interface layer of the second compound semiconductor layer (or the first compound semiconductor layer). The GaN-based compound semiconductor may further include a GaN-based compound semiconductor containing oxygen atoms, or the stacked structure may be formed of a GaN-based compound semiconductor, and the contact layer may be a second compound. A GaN-based compound semiconductor having a composition different from that of the GaN-based compound semiconductor constituting the interface layer of the semiconductor layer (or the first compound semiconductor layer) can be used. In the latter case, specifically, the interface layer of the second compound semiconductor layer (or the first compound semiconductor layer) is composed of a GaN layer, and the contact layer is
(A) Al X Ga Y In Z N ( where, X + Y + Z = 1,0 ≦ X ≦ 1,0 ≦ Y ≦ 1,0 ≦ Z ≦ 1) consisting of structure (b) Al X Ga Y In Z N S O T (where X + Y + Z = 1, 0 ≦ X ≦ 1, 0 ≦ Y ≦ 1, 0 ≦ Z ≦ 1, 0 <S ≦ 1, 0 <T ≦ 1) (c) Al X Ga Y In Z N S P 1-S (where, X + Y + Z = 1,0 ≦ X ≦ 1,0 ≦ Y ≦ 1,0 ≦ Z ≦ 1,0 ≦ S <1) consisting of structure (d) Al X Ga Y In Z N S As 1-S (where, X + Y + Z = 1,0 ≦ X ≦ 1,0 ≦ Y ≦ 1,0 ≦ Z ≦ 1,0 ≦ S <1) consists (e) Al X Ga Y In Z N S Sb 1-S (where X + Y + Z = 1, 0 ≦ X ≦ 1, 0 ≦ Y ≦ 1, 0 ≦ Z ≦ 1, 0 ≦ S <1) can be exemplified. Whether or not oxygen atoms are contained in the GaN-based compound semiconductor can be measured by, for example, an energy dispersive X-ray analysis method attached to a transmission electron microscope or a three-dimensional atom probe method.
 あるいは又、第2-Aの構成の電子デバイスあるいは第2-Bの構成の電子デバイスの上記の各種の好ましい構成を含む第2-Aの構成の電子デバイスあるいは第2-Bの構成の電子デバイスにおいて、積層構造体は、GaN系化合物半導体から成り、コンタクト層は、ZnO、ZnSe、CdO、CdS及びCdSeから成る群から選択された1種類の材料から成る構成とすることができる。 Alternatively, the electronic device having the 2-A configuration or the electronic device having the 2-B configuration including the above-described various preferable configurations of the electronic device having the 2-A configuration or the electronic device having the 2-B configuration. The stacked structure may be made of a GaN-based compound semiconductor, and the contact layer may be made of one material selected from the group consisting of ZnO, ZnSe, CdO, CdS, and CdSe.
 第2-Aの構成の電子デバイス(あるいは第2-Bの構成の電子デバイス)の以上に説明した各種の好ましい構成を含む第2-Aの構成の電子デバイス(あるいは第2-Bの構成の電子デバイス)において、コンタクト層を構成する化合物半導体のバンドギャップエネルギーの値は、第2化合物半導体層(あるいは第1化合物半導体層)の界面層を構成する化合物半導体のバンドギャップエネルギーの値よりも小さいことが好ましい。 The electronic device having the 2-A configuration (or the configuration of the 2-B configuration) including the various preferred configurations described above of the electronic device having the 2-A configuration (or the electronic device having the 2-B configuration). In the electronic device), the value of the band gap energy of the compound semiconductor constituting the contact layer is smaller than the value of the band gap energy of the compound semiconductor constituting the interface layer of the second compound semiconductor layer (or the first compound semiconductor layer). It is preferable.
 更には、第2-Aの構成の電子デバイスあるいは第2-Bの構成の電子デバイスの以上に説明した各種の好ましい構成を含む第2-Aの構成の電子デバイスあるいは第2-Bの構成の電子デバイスにおいて、第1導電型はn型であり、第2導電型はp型である構成とすることができる。 Further, the electronic device having the 2-A configuration or the second-B configuration including the various preferred configurations described above of the electronic device having the 2-A configuration or the electronic device having the 2-B configuration has been described. In the electronic device, the first conductivity type may be n-type, and the second conductivity type may be p-type.
 上述したとおり、第2-Aの構成の電子デバイスあるいは第2-Bの構成の電子デバイスにおいて、積層構造体やコンタクト層はGaN系化合物半導体から構成することが好ましいが、第2化合物半導体層の界面層以外の第2化合物半導体層の部分、活性層、第1化合物半導体層を構成する化合物半導体として、GaN、AlGaN、InGaN、AlInGaNといったGaN系化合物半導体を挙げることができるし、活性層を構成する化合物半導体として、InGaN、AlInGaNを挙げることができる。更には、これらの化合物半導体に、所望に応じて、ホウ素(B)原子やタリウム(Tl)原子、ヒ素(As)原子、リン(P)原子、アンチモン(Sb)原子が含まれていてもよい。積層構造体の形成方法(成膜方法)として、有機金属化学的気相成長法(MOCVD法、MOVPE法)や有機金属分子線エピタキシー法(MOMBE法)、ハロゲンが輸送あるいは反応に寄与するハイドライド気相成長法(HVPE法)、プラズマアシステッド物理的気相成長法(PPD法)を挙げることができる。ここで、MOCVD法における有機ガリウム源として、トリメチルガリウム(TMG)やトリエチルガリウム(TEG)を挙げることができるし、窒素源として、アンモニアガスやヒドラジンを挙げることができる。また、GaN系化合物半導体層の構成原子としてアルミニウム(Al)あるいはインジウム(In)が含まれる場合、Al源としてトリメチルアルミニウム(TMA)を用いればよいし、In源としてトリメチルインジウム(TMI)を用いればよい。更には、Si源としてモノシラン(SiH4)を用いればよいし、Mg源としてシクロペンタジエニルマグネシウムやメチルシクロペンタジエニルマグネシウム、ビスシクロペンタジエニルマグネシウム(Cp2Mg)を用いればよい。第1化合物半導体層、活性層及び第2化合物半導体層から成る積層構造体からリッジストライプ構造を形成する場合、リッジストライプ構造を形成するために積層構造体をエッチングする方法として、リソグラフィ技術とウェットエッチング技術の組合せ、リソグラフィ技術とドライエッチング技術の組合せを挙げることができる。積層構造体の構成、それ自体は、周知の構成とすることができる。積層構造体は電子デバイス製造用基板(以下、単に『製造用基板』と呼ぶ)上に形成されており、製造用基板側から、第1化合物半導体層、活性層及び第2化合物半導体層が積層された構造を有する。コンタクト層の形成方法として、上記の積層構造体の形成方法の他、原子層堆積法(ALD法, Atomic Layer Deposition 法)、マイグレーション・エンハンスト・エピタキシー法(MEE法, Migration-Enhanced Epitaxy)、パルスレーザー堆積法(PLD法, Pulsed Laser Deposition 法)、熱処理法等を挙げることができる。 As described above, in the electronic device having the configuration 2-A or the electronic device having the configuration 2-B, the laminated structure and the contact layer are preferably formed of a GaN-based compound semiconductor. Examples of compound semiconductors constituting the second compound semiconductor layer other than the interface layer, the active layer, and the first compound semiconductor layer include GaN-based compound semiconductors such as GaN, AlGaN, InGaN, and AlInGaN, and constitute the active layer. Examples of the compound semiconductor to be used include InGaN and AlInGaN. Furthermore, these compound semiconductors may contain boron (B) atoms, thallium (Tl) atoms, arsenic (As) atoms, phosphorus (P) atoms, and antimony (Sb) atoms as desired. . Layered structure formation methods (film formation methods) include metalorganic chemical vapor deposition (MOCVD, MOVPE), metalorganic molecular beam epitaxy (MOMBE), and hydride gas in which halogen contributes to transport or reaction. Examples thereof include a phase growth method (HVPE method) and a plasma assisted physical vapor deposition method (PPD method). Here, trimethylgallium (TMG) and triethylgallium (TEG) can be mentioned as the organic gallium source in the MOCVD method, and ammonia gas and hydrazine can be mentioned as the nitrogen source. Further, when aluminum (Al) or indium (In) is contained as a constituent atom of the GaN-based compound semiconductor layer, trimethylaluminum (TMA) may be used as the Al source, and trimethylindium (TMI) may be used as the In source. Good. Furthermore, monosilane (SiH 4 ) may be used as the Si source, and cyclopentadienyl magnesium, methylcyclopentadienyl magnesium, or biscyclopentadienyl magnesium (Cp 2 Mg) may be used as the Mg source. In the case of forming a ridge stripe structure from a laminated structure composed of a first compound semiconductor layer, an active layer, and a second compound semiconductor layer, as a method of etching the laminated structure to form the ridge stripe structure, lithography technology and wet etching are used. A combination of technologies, a combination of lithography technology and dry etching technology can be mentioned. The configuration of the laminated structure itself can be a known configuration. The laminated structure is formed on an electronic device manufacturing substrate (hereinafter simply referred to as “manufacturing substrate”), and the first compound semiconductor layer, the active layer, and the second compound semiconductor layer are stacked from the manufacturing substrate side. Has a structured. As a method for forming a contact layer, in addition to the above-described stacked structure forming method, atomic layer deposition (ALD, Atomic Layer Deposition), migration enhanced epitaxy (MEE, Migration-Enhanced Epitaxy), pulsed laser Examples thereof include a deposition method (PLD method, Pulsed Laser Deposition method), a heat treatment method, and the like.
 第2-Aの構成の電子デバイスあるいは第2-Bの構成の電子デバイスにおいて、活性層は、単一の化合物半導体層から構成されていてもよいし、単一量子井戸構造(SQW構造)あるいは多重量子井戸構造(MQW構造)を有していてもよい。量子井戸構造を有する活性層は、井戸層及び障壁層が、少なくとも1層、積層された構造を有するが、(井戸層を構成する化合物半導体,障壁層を構成する化合物半導体)の組合せとして、(InGaN,GaN)や(InGaN,AlInGaN)、(InGaN,InGaN)[但し、井戸層を構成するInGaNの組成と障壁層を構成するInGaNの組成とは異なる]を例示することができる。更には、障壁層は複数の組成を有する層群で構成されていてもよい。 In the electronic device having the configuration 2-A or the electronic device having the configuration 2-B, the active layer may be composed of a single compound semiconductor layer, a single quantum well structure (SQW structure), or It may have a multiple quantum well structure (MQW structure). An active layer having a quantum well structure has a structure in which at least one well layer and a barrier layer are stacked. However, as a combination of (a compound semiconductor constituting a well layer, a compound semiconductor constituting a barrier layer), InGaN, GaN), (InGaN, AlInGaN), and (InGaN, InGaN) [however, the composition of InGaN constituting the well layer and the composition of InGaN constituting the barrier layer are different]. Furthermore, the barrier layer may be composed of a layer group having a plurality of compositions.
 第2-Aの構成の電子デバイスあるいは第2-Bの構成の電子デバイスにおいて、第1化合物半導体層に第1導電型を付与し、第2化合物半導体層及びコンタクト層に第2導電型を付与するためには、第1化合物半導体層、第2化合物半導体層及びコンタクト層のそれぞれに、不純物を導入すればよい。化合物半導体層に添加されるn型不純物として、例えば、ケイ素(Si)、硫黄(S)、セレン(Se)、ゲルマニウム(Ge)、テルル(Te)、錫(Sn)、炭素(C)、チタン(Ti)、酸素(O)、パラジウム(Pd)を挙げることができるし、p型不純物として、亜鉛(Zn)、マグネシウム(Mg)、炭素(C)、ベリリウム(Be)、カドミウム(Cd)、カルシウム(Ca)、バリウム(Ba)を挙げることができる。 In the electronic device having the 2-A configuration or the electronic device having the 2-B configuration, the first compound semiconductor layer is provided with the first conductivity type, and the second compound semiconductor layer and the contact layer are provided with the second conductivity type. For this purpose, impurities may be introduced into each of the first compound semiconductor layer, the second compound semiconductor layer, and the contact layer. Examples of n-type impurities added to the compound semiconductor layer include silicon (Si), sulfur (S), selenium (Se), germanium (Ge), tellurium (Te), tin (Sn), carbon (C), and titanium. (Ti), oxygen (O), palladium (Pd), and as p-type impurities, zinc (Zn), magnesium (Mg), carbon (C), beryllium (Be), cadmium (Cd), Calcium (Ca) and barium (Ba) can be mentioned.
 第2-Aの構成の電子デバイスにおいて、第2電極は、コンタクト層を介して第2化合物半導体層と接している一方、第1電極は、電気的に第1化合物半導体層に接続されている。即ち、第1電極は、第1化合物半導体層上に形成されており、あるいは又、第1電極は、導電材料層や製造用基板を介して第1化合物半導体層に接続されている。また、第2-Bの構成の電子デバイスにおいて、第1電極は、コンタクト層を介して第1化合物半導体層と接している一方、第2電極は、第2化合物半導体層上に形成されている。尚、第2電極は、コンタクト層を介して第2化合物半導体層と接しており、第1電極は、第2のコンタクト層を介して第1化合物半導体層と接している構成とすることもできる。 In the electronic device having the configuration 2-A, the second electrode is in contact with the second compound semiconductor layer through the contact layer, while the first electrode is electrically connected to the first compound semiconductor layer. . That is, the first electrode is formed on the first compound semiconductor layer, or the first electrode is connected to the first compound semiconductor layer via the conductive material layer and the manufacturing substrate. In the electronic device having the configuration 2-B, the first electrode is in contact with the first compound semiconductor layer through the contact layer, while the second electrode is formed on the second compound semiconductor layer. . The second electrode may be in contact with the second compound semiconductor layer via the contact layer, and the first electrode may be in contact with the first compound semiconductor layer via the second contact layer. .
 第2-Aの構成の電子デバイスあるいは第2-Bの構成の電子デバイスにおいて、第1導電型をn型、第2導電型をp型とする場合、第1電極は、例えば、金(Au)、銀(Ag)、パラジウム(Pd)、白金(Pt)、ニッケル(Ni)、Al(アルミニウム)、Ti(チタン)、タングステン(W)、バナジウム(V)、クロム(Cr)、Cu(銅)、Zn(亜鉛)、錫(Sn)及びインジウム(In)から成る群から選択された少なくとも1種類の金属(合金を含む)を含む、単層構成又は多層構成を有することが望ましく、例えば、Ti/Au、Ti/Al、Ti/Pt/Au、Ti/Al/Au、Ti/Pt/Au、Ni/Au、Ni/Au/Pt、Ni/Pt、Pd/Pt、Ag/Pdを例示することができる。尚、多層構成における「/」の前の層ほど、より活性層側に位置する。以下の説明においても同様である。 In the electronic device having the configuration 2-A or the electronic device having the configuration 2-B, when the first conductivity type is n-type and the second conductivity type is p-type, the first electrode is, for example, gold (Au ), Silver (Ag), palladium (Pd), platinum (Pt), nickel (Ni), Al (aluminum), Ti (titanium), tungsten (W), vanadium (V), chromium (Cr), Cu (copper) ), Zn (zinc), tin (Sn), and indium (In), it is desirable to have at least one metal (including alloys) selected from the group consisting of single layer configuration or multilayer configuration, for example, Illustrate Ti / Au, Ti / Al, Ti / Pt / Au, Ti / Al / Au, Ti / Pt / Au, Ni / Au, Ni / Au / Pt, Ni / Pt, Pd / Pt, Ag / Pd be able to. In addition, the layer before “/” in the multilayer structure is located closer to the active layer side. The same applies to the following description.
 あるいは又、第2-Aの構成の電子デバイスあるいは第2-Bの構成の電子デバイスにおいて、第1電極をn型の導電型を有する第1化合物半導体層上に形成する場合、第1電極を透明導電性材料層から構成してもよい。透明導電性材料層を構成する透明導電性材料として、前述したとおり、インジウム原子を含む透明導電性材料[具体的には、酸化インジウム、インジウム-錫酸化物(ITO,Indium Tin Oxide,SnドープのIn23、結晶性ITO及びアモルファスITOを含む)、インジウム-亜鉛酸化物(IZO,Indium Zinc Oxide)、インジウム-ガリウム酸化物(IGO)、インジウム・ドープのガリウム-亜鉛酸化物(IGZO,In-GaZnO4)、IFO(FドープのIn23)]を挙げることができるし、酸化錫(SnO2)、ATO(SbドープのSnO2)、FTO(FドープのSnO2)、酸化亜鉛(ZnO、AlドープのZnOやBドープのZnO、GaドープのZnOを含む)、酸化アンチモン、スピネル型酸化物、YbFe24構造を有する酸化物を例示することができる。あるいは又、第1電極や第2電極として、ガリウム酸化物、チタン酸化物、ニオブ酸化物、ニッケル酸化物等を母層とする透明導電性材料層を挙げることもできる。 Alternatively, in the electronic device having the configuration 2-A or the electronic device having the configuration 2-B, when the first electrode is formed on the first compound semiconductor layer having the n-type conductivity type, You may comprise from a transparent conductive material layer. As described above, as the transparent conductive material constituting the transparent conductive material layer, the transparent conductive material containing indium atoms [specifically, indium oxide, indium tin oxide, Sn-doped ITO, In 2 O 3 , including crystalline ITO and amorphous ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium doped gallium zinc oxide (IGZO, In -GaZnO 4 ), IFO (F-doped In 2 O 3 )], tin oxide (SnO 2 ), ATO (Sb-doped SnO 2 ), FTO (F-doped SnO 2 ), zinc oxide (Including ZnO, Al-doped ZnO, B-doped ZnO, and Ga-doped ZnO), antimony oxide, spinel oxide, YbFe 2 O An oxide having a four structure can be exemplified. Alternatively, as the first electrode and the second electrode, a transparent conductive material layer having a base layer of gallium oxide, titanium oxide, niobium oxide, nickel oxide, or the like can be given.
 あるいは又、第2-Aの構成の電子デバイスあるいは第2-Bの構成の電子デバイスにおいて、第1電極を構成する光透過性が良好で仕事関数の値が小さい材料として、カルシウム(Ca)、バリウム(Ba)等のアルカリ土類金属、リチウム(Li)、セシウム(Cs)等のアルカリ金属、インジウム(In)、マグネシウム(Mg)、銀(Ag)、金(Au)、ニッケル(Ni)、金-ゲルマニウム(Au-Ge)等を挙げることもできる。更には、Li2O、Cs2Co3、Cs2SO4、MgF、LiFやCaF2等のアルカリ金属酸化物、アルカリ金属フッ化物、アルカリ土類金属酸化物、アルカリ土類フッ化物を挙げることもできる。 Alternatively, in the electronic device having the configuration 2-A or the electronic device having the configuration 2-B, as a material having a good light transmittance and a small work function value constituting the first electrode, calcium (Ca), Alkaline earth metals such as barium (Ba), alkali metals such as lithium (Li) and cesium (Cs), indium (In), magnesium (Mg), silver (Ag), gold (Au), nickel (Ni), Gold-germanium (Au—Ge) and the like can also be mentioned. Furthermore, mention may be made of alkali metal oxides, alkali metal fluorides, alkaline earth metal oxides, alkaline earth fluorides such as Li 2 O, Cs 2 Co 3 , Cs 2 SO 4 , MgF, LiF and CaF 2. You can also.
 第2-Aの構成の電子デバイスあるいは第2-Bの構成の電子デバイスにおいて、第1電極や第2電極上に、外部の電極あるいは回路と電気的に接続するために、パッド電極を設けてもよい。パッド電極は、Ti(チタン)、アルミニウム(Al)、Pt(白金)、Au(金)、Ni(ニッケル)、Pd(パラジウム)から成る群から選択された少なくとも1種類の金属(合金を含む)を含む、単層構成又は多層構成を有することが望ましい。あるいは又、パッド電極を、Ti/Pt/Auの多層構成、Ti/Auの多層構成、Ti/Pd/Auの多層構成、Ti/Pd/Auの多層構成、Ti/Ni/Auの多層構成、Ti/Ni/Au/Cr/Auの多層構成に例示される多層構成とすることもできる。 In the electronic device having the configuration 2-A or the electronic device having the configuration 2-B, a pad electrode is provided on the first electrode or the second electrode so as to be electrically connected to an external electrode or a circuit. Also good. The pad electrode is at least one metal (including alloy) selected from the group consisting of Ti (titanium), aluminum (Al), Pt (platinum), Au (gold), Ni (nickel), and Pd (palladium). It is desirable to have a single layer configuration or a multi-layer configuration including Alternatively, the pad electrode may be a Ti / Pt / Au multilayer structure, a Ti / Au multilayer structure, a Ti / Pd / Au multilayer structure, a Ti / Pd / Au multilayer structure, a Ti / Ni / Au multilayer structure, A multi-layer structure exemplified by a multi-layer structure of Ti / Ni / Au / Cr / Au can also be used.
 第2-Aの構成の電子デバイスあるいは第2-Bの構成の電子デバイスにおいて、製造用基板を残したままとしてもよいし、製造用基板上に第1化合物半導体層、活性層、第2化合物半導体層、コンタクト層、第2電極等を順次形成した後、製造用基板を除去してもよい。具体的には、製造用基板上に第1化合物半導体層、活性層、第2化合物半導体層、コンタクト層、第2電極を順次形成し、第2電極を支持基板に固定した後、製造用基板を除去して、第1化合物半導体層を露出させればよい。製造用基板の除去は、エッチング法や研磨法に基づき行う形態とすることができるし、あるいは又、化学的/機械的研磨法(CMP法)に基づき行う形態とすることができる。尚、先ず、水酸化ナトリウム水溶液や水酸化カリウム水溶液等のアルカリ水溶液、アンモニア溶液+過酸化水素水、硫酸溶液+過酸化水素水、塩酸溶液+過酸化水素水、リン酸溶液+過酸化水素水等を用いたウェットエッチング法や、ドライエッチング法、レーザを用いたリフトオフ法、機械研磨法等によって、あるいは、これらの組合せによって、製造用基板の一部の除去を行い、あるいは、製造用基板の厚さを薄くし、次いで、化学的/機械的研磨法を実行することで、第1化合物半導体層を露出させてもよい。この場合、第2-Bの構成の電子デバイスにあっては、露出した第1化合物半導体層の上にコンタクト層、第1電極を、順次、形成してもよい。 In the electronic device having the configuration 2-A or the electronic device having the configuration 2-B, the manufacturing substrate may be left, or the first compound semiconductor layer, the active layer, and the second compound may be left on the manufacturing substrate. After sequentially forming the semiconductor layer, the contact layer, the second electrode, etc., the manufacturing substrate may be removed. Specifically, the first compound semiconductor layer, the active layer, the second compound semiconductor layer, the contact layer, and the second electrode are sequentially formed on the manufacturing substrate, and the second electrode is fixed to the support substrate, and then the manufacturing substrate. And the first compound semiconductor layer may be exposed. The removal of the production substrate can be performed based on an etching method or a polishing method, or can be performed based on a chemical / mechanical polishing method (CMP method). First, alkaline aqueous solution such as sodium hydroxide aqueous solution or potassium hydroxide aqueous solution, ammonia solution + hydrogen peroxide solution, sulfuric acid solution + hydrogen peroxide solution, hydrochloric acid solution + hydrogen peroxide solution, phosphoric acid solution + hydrogen peroxide solution A part of the manufacturing substrate is removed by a wet etching method using a dry etching method, a dry etching method, a lift-off method using a laser, a mechanical polishing method or the like, or a combination thereof. The first compound semiconductor layer may be exposed by reducing the thickness and then performing a chemical / mechanical polishing method. In this case, in the electronic device having the second-B configuration, the contact layer and the first electrode may be sequentially formed on the exposed first compound semiconductor layer.
 第2-Aの構成の電子デバイスあるいは第2-Bの構成の電子デバイスの以上に説明した各種の好ましい構成を含む第2-Aの構成の電子デバイスあるいは第2-Bの構成の電子デバイスにあっては、活性層において生成した光は、積層構造体の端面(側面)から外部に出射される構成とすることができるし、第2化合物半導体層を介して外部に出射される構成とすることもできるし、第1化合物半導体層を介して外部に出射される構成とすることもできる。第1化合物半導体層側から光が外部に出射される構成の電子デバイスにあっては、場合によっては、前述したとおり、製造用基板を除去してもよい。 The electronic device having the 2-A configuration or the electronic device having the 2-B configuration including the various preferable configurations described above of the electronic device having the 2-A configuration or the electronic device having the 2-B configuration In this case, the light generated in the active layer can be emitted to the outside from the end face (side surface) of the laminated structure, or can be emitted to the outside via the second compound semiconductor layer. It can also be set as the structure radiate | emitted outside through a 1st compound semiconductor layer. In an electronic device configured to emit light from the first compound semiconductor layer side, the manufacturing substrate may be removed as described above.
 製造用基板として、GaN基板やサファイア基板の他にも、GaAs基板、SiC基板、アルミナ基板、ZnS基板、ZnO基板、AlN基板、LiMgO基板、LiGaO2基板、MgAl24基板、InP基板、Si基板、これらの基板の表面(主面)に下地層やバッファ層が形成されたものを挙げることができる。主に、GaN系化合物半導体層を基板に形成する場合、GaN基板が欠陥密度の少なさから好まれるが、GaN基板は成長面によって、極性/無極性/半極性と特性が変わることが知られている。 In addition to GaN substrates and sapphire substrates, GaAs substrates, SiC substrates, alumina substrates, ZnS substrates, ZnO substrates, AlN substrates, LiMgO substrates, LiGaO 2 substrates, MgAl 2 O 4 substrates, InP substrates, Si as well as GaN substrates and sapphire substrates. Examples of the substrate include those having a base layer and a buffer layer formed on the surface (main surface) of these substrates. Mainly, when a GaN-based compound semiconductor layer is formed on a substrate, the GaN substrate is preferred because of its low defect density, but it is known that the characteristics of the GaN substrate change from polar / nonpolar / semipolar depending on the growth surface. ing.
 あるいは又、製造用基板として、上述した各種の基板以外にも、ガラス基板、石英基板といった透明無機基板、ポリエチレンテレフタレート(PET)やポリエチレンナフタレート(PEN)等のポリエステル樹脂;ポリカーボネート(PC)樹脂;ポリエーテルスルホン(PES)樹脂;ポリスチレン、ポリエチレン、ポリプロピレン等のポリオレフィン樹脂;ポリフェニレンサルファイド樹脂;ポリフッ化ビニリデン樹脂;テトラアセチルセルロース樹脂;ブロム化フェノキシ樹脂;アラミド樹脂;ポリイミド樹脂;ポリスチレン樹脂;ポリアリレート樹脂;ポリスルフォン樹脂;アクリル樹脂;エポキシ樹脂;フッ素樹脂;シリコーン樹脂;ジアセテート樹脂;トリアセテート樹脂;ポリ塩化ビニル樹脂;環状ポリオレフィン樹脂等の透明プラスチック基板やフィルムを挙げることができる。ガラス基板として、例えば、ソーダガラス基板、耐熱ガラス基板、石英ガラス基板を挙げることができる。 Alternatively, as the production substrate, in addition to the above-mentioned various substrates, transparent inorganic substrates such as glass substrates and quartz substrates, polyester resins such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN); polycarbonate (PC) resins; Polyethersulfone (PES) resin; Polyolefin resin such as polystyrene, polyethylene, polypropylene; Polyphenylene sulfide resin; Polyvinylidene fluoride resin; Tetraacetyl cellulose resin; Brominated phenoxy resin; Aramid resin; Polyimide resin; Polystyrene resin; Polysulfone resin; Acrylic resin; Epoxy resin; Fluororesin; Silicone resin; Diacetate resin; Triacetate resin; Polyvinyl chloride resin; Mention may be made of a transparent plastic substrate or a film. Examples of the glass substrate include a soda glass substrate, a heat resistant glass substrate, and a quartz glass substrate.
 支持基板は、例えば、GaN基板、サファイア基板、GaAs基板、SiC基板、アルミナ基板、ZnS基板、ZnO基板、LiMgO基板、LiGaO2基板、MgAl24基板、InP基板といった各種の基板から構成すればよいし、あるいは又、AlN等から成る絶縁性基板、Si、SiC、Ge等から成る半導体基板、金属製基板や合金製基板から構成することもできるが、導電性を有する基板を用いることが好ましく、あるいは又、機械的特性、弾性変形、塑性変形性、放熱性等の観点から金属製基板や合金製基板を用いることが好ましい。支持基板の厚さとして、例えば、0.05mm乃至0.5mmを例示することができる。第2電極の支持基板への固定方法として、半田接合法、常温接合法、粘着テープを用いた接合法、ワックス接合を用いた接合法等、既知の方法を用いることができるが、導電性の確保という観点からは半田接合法あるいは常温接合法を採用することが望ましい。例えば導電性基板であるシリコン半導体基板を支持基板として使用する場合、熱膨張係数の違いによる反りを抑制するために、400゜C以下の低温で接合可能な方法を採用することが望ましい。支持基板としてGaN基板を使用する場合、接合温度が400゜C以上であってもよい。 The support substrate may be composed of various substrates such as a GaN substrate, a sapphire substrate, a GaAs substrate, an SiC substrate, an alumina substrate, a ZnS substrate, a ZnO substrate, a LiMgO substrate, a LiGaO 2 substrate, an MgAl 2 O 4 substrate, and an InP substrate. Alternatively, an insulating substrate made of AlN or the like, a semiconductor substrate made of Si, SiC, Ge or the like, a metal substrate, or an alloy substrate can be used, but it is preferable to use a conductive substrate. Alternatively, it is preferable to use a metal substrate or an alloy substrate from the viewpoints of mechanical properties, elastic deformation, plastic deformability, heat dissipation, and the like. Examples of the thickness of the support substrate include 0.05 mm to 0.5 mm. As a method for fixing the second electrode to the support substrate, a known method such as a solder bonding method, a room temperature bonding method, a bonding method using an adhesive tape, a bonding method using wax bonding, or the like can be used. From the viewpoint of ensuring, it is desirable to employ a solder bonding method or a room temperature bonding method. For example, when a silicon semiconductor substrate which is a conductive substrate is used as a support substrate, it is desirable to employ a method capable of bonding at a low temperature of 400 ° C. or lower in order to suppress warping due to a difference in thermal expansion coefficient. When a GaN substrate is used as the support substrate, the bonding temperature may be 400 ° C. or higher.
 第2-Aの構成の電子デバイスあるいは第2-Bの構成の電子デバイスの以上に説明した各種の好ましい構成を含む第2-Aの構成の電子デバイスあるいは第2-Bの構成の電子デバイスにおいて、電子デバイスとして、発光・受光素子、具体的には、端面発光型の半導体レーザ素子、端面発光型のスーパールミネッセントダイオード(SLD)、面発光レーザ素子(垂直共振器レーザ、VCSELとも呼ばれる)、発光ダイオード(LED)といった半導体発光素子、あるいは、半導体光増幅器を挙げることができるし、太陽電池や光センサーを挙げることもできる。半導体光増幅器は、光信号を電気信号に変換せず、直接光の状態で増幅するものであり、共振器効果を極力排除したレーザ構造を有し、半導体光増幅器の光利得に基づき入射光を増幅する。半導体レーザ素子にあっては、第1端面における光反射率と第2端面における光反射率との最適化を図ることで、共振器が構成され、光は第1端面から出射される。あるいは、外部共振器を配置してもよい。一方、スーパールミネッセントダイオードにあっては、第1端面における光反射率を非常に低い値とし、第2端面における光反射率を非常に高い値とし、共振器を構成することなく、活性層で生成した光が第2端面において反射され、第1端面から出射される。半導体レーザ素子及びスーパールミネッセントダイオードにおいて、第1端面には、無反射コート層(AR)あるいは低反射コート層が形成されているし、第2端面には、高反射コート層(HR)が形成されている。また、半導体光増幅器にあっては、第1端面及び第2端面における光反射率を非常に低い値とし、共振器を構成することなく、第2端面から入射した光を増幅して第1端面から出射する。面発光レーザ素子にあっては、2つの光反射層(Distributed Bragg Reflector 層、DBR層)の間で光を共振させることによってレーザ発振が生じる。 In the electronic device having the 2-A configuration or the electronic device having the 2-B configuration including the various preferable configurations described above of the electronic device having the 2-A configuration or the electronic device having the 2-B configuration As an electronic device, a light emitting / receiving element, specifically, an edge emitting semiconductor laser element, an edge emitting superluminescent diode (SLD), a surface emitting laser element (also called vertical cavity laser, VCSEL) And a semiconductor light emitting device such as a light emitting diode (LED), a semiconductor optical amplifier, a solar cell, and a photosensor. A semiconductor optical amplifier amplifies in the state of direct light without converting an optical signal into an electrical signal, has a laser structure that eliminates the resonator effect as much as possible, and converts incident light based on the optical gain of the semiconductor optical amplifier. Amplify. In the semiconductor laser element, a resonator is configured by optimizing the light reflectance at the first end face and the light reflectance at the second end face, and light is emitted from the first end face. Alternatively, an external resonator may be arranged. On the other hand, in the superluminescent diode, the light reflectivity at the first end face is set to a very low value, the light reflectivity at the second end face is set to a very high value, and the active layer is formed without forming a resonator. The light generated in step 1 is reflected at the second end face and emitted from the first end face. In the semiconductor laser element and the super luminescent diode, a non-reflective coating layer (AR) or a low-reflective coating layer is formed on the first end surface, and a high-reflective coating layer (HR) is formed on the second end surface. Is formed. Further, in the semiconductor optical amplifier, the light reflectance at the first end face and the second end face is set to a very low value, and the light incident from the second end face is amplified without constituting the resonator, thereby the first end face. Emanates from. In the surface emitting laser element, laser oscillation is generated by resonating light between two light reflecting layers (Distributed Bragg Reflector layer, DBR layer).
 一般に、光出射端面あるいは光入射端面には、無反射コート層(AR)あるいは低反射コート層が形成されている。また、光反射端面には、高反射コート層(HR)が形成されている。無反射コート層(低反射コート層)として、酸化チタン層、酸化タンタル層、酸化ジルコニウム層、酸化シリコン層、酸化アルミニウム層、窒化アルミニウム層、及び、窒化ケイ素層から成る群から選択された少なくとも2種類の層の積層構造を挙げることができ、スパッタリング法や真空蒸着法等のPVD法に基づき形成することができる。 Generally, a non-reflective coating layer (AR) or a low-reflective coating layer is formed on the light emitting end surface or the light incident end surface. Further, a highly reflective coating layer (HR) is formed on the light reflecting end face. As an antireflection coating layer (low reflection coating layer), at least 2 selected from the group consisting of a titanium oxide layer, a tantalum oxide layer, a zirconium oxide layer, a silicon oxide layer, an aluminum oxide layer, an aluminum nitride layer, and a silicon nitride layer The layered structure of a kind of layer can be mentioned, It can form based on PVD methods, such as sputtering method and a vacuum evaporation method.
 半導体レーザ素子として、限定するものではないが、リッジストライプ型の分離閉じ込めヘテロ構造(SCH構造、Separate Confinement Heterostructure)を有する半導体レーザ素子を挙げることができる。あるいは又、斜めリッジストライプ型の分離閉じ込めヘテロ構造を有する半導体レーザ素子を挙げることができる。即ち、半導体レーザ素子の軸線とリッジストライプ構造の軸線とは、所定の角度で交わっている構成とすることができる。ここで、所定の角度φとして、0.1度≦φ≦10度を例示することができる。リッジストライプ構造の軸線とは、光出射端面におけるリッジストライプ構造の両端の二等分点と、光反射端面におけるリッジストライプ構造の両端の二等分点とを結ぶ直線である。また、半導体レーザ素子の軸線とは、光出射端面における仮想垂直面及び光反射端面における仮想垂直面と直交する軸線を指す。リッジストライプ構造の平面形状は、直線状であってもよいし、湾曲していてもよい。あるいは又、テーパー状(フレア状)のリッジストライプ型(例えば、光出射端面から光反射端面に向かって、単調に、テーパー状に緩やかに広げられる構成、光出射端面から光反射端面に向かって、先ず広げられ、最大幅を超えた後、狭められる構成を含む)の分離閉じ込めヘテロ構造を有する半導体レーザ素子を挙げることができる。リッジストライプ構造は、第2化合物半導体層の厚さ方向の一部から構成されていてもよいし、第2化合物半導体層及び活性層から構成されていてもよいし、第2化合物半導体層、活性層、及び、第1化合物半導体層の厚さ方向の一部分から構成されていてもよい。但し、半導体レーザ素子は、これらの構造に限定するものではない。半導体レーザ素子として、その他、インデックス・ガイド構造の半導体レーザ素子や、共振器方向に発光領域と可飽和吸収領域とを並置したバイ・セクション(Bi Section)型、マルチセクション型(多電極型)の半導体レーザ素子、発光領域と可飽和吸収領域とを垂直方向に配置したSAL(Saturable Absorber Layer)型や、リッジストライプ構造に沿って可飽和吸収領域を設けたWI(Weakly Index guide)型の半導体レーザ素子を挙げることもできる。 Examples of the semiconductor laser element include, but are not limited to, a semiconductor laser element having a ridge stripe type separated confinement heterostructure (SCH structure, separate-confinement heterostructure). Alternatively, a semiconductor laser element having an oblique ridge stripe type separated confinement heterostructure can be cited. In other words, the axis of the semiconductor laser element and the axis of the ridge stripe structure can intersect at a predetermined angle. Here, examples of the predetermined angle φ include 0.1 degrees ≦ φ ≦ 10 degrees. The axis of the ridge stripe structure is a straight line connecting the bisectors at both ends of the ridge stripe structure at the light emitting end face and the bisectors at both ends of the ridge stripe structure at the light reflecting end face. The axis of the semiconductor laser element refers to an axis perpendicular to the virtual vertical plane at the light emitting end face and the virtual vertical plane at the light reflecting end face. The planar shape of the ridge stripe structure may be linear or curved. Alternatively, a tapered (flared) ridge stripe type (for example, a structure that is monotonously and gradually widened in a tapered shape from the light emitting end face toward the light reflecting end face, from the light emitting end face toward the light reflecting end face, First, a semiconductor laser device having a separate confinement heterostructure (including a configuration in which it is first widened and exceeds a maximum width and then narrowed) can be given. The ridge stripe structure may be composed of a part of the second compound semiconductor layer in the thickness direction, may be composed of the second compound semiconductor layer and the active layer, or may be composed of the second compound semiconductor layer, the active layer You may be comprised from the layer and a part of thickness direction of the 1st compound semiconductor layer. However, the semiconductor laser element is not limited to these structures. Other semiconductor laser elements include semiconductor laser elements with an index guide structure, bi-section type with a light emitting region and a saturable absorption region juxtaposed in the cavity direction, and multi-section type (multi-electrode type). Semiconductor laser element, SAL (Saturable Absorber Layer) type in which light emitting region and saturable absorption region are arranged in the vertical direction, or WI (Weakly Index Guide) type semiconductor laser in which saturable absorption region is provided along a ridge stripe structure An element can also be mentioned.
 第1電極、第2電極、絶縁層をスパッタリング法に基づき形成するが、具体的には、マグネトロンスパッタリング法や平行並板スパッタリング法を挙げることができ、DC放電方式あるいはRF放電方式を用いたプラズマ発生形成方式を用いるものを挙げることができる。あるいは又、第1電極を形成する方法として、第1電極を構成する材料にも依るが、真空蒸着法や反応性蒸着法、電子ビーム蒸着法、イオンプレーティング法といったPVD法、パイロゾル法、有機金属化合物を熱分解する方法、スプレー法、ディップ法、MOCVD法を含む各種のCVD法、無電解メッキ法、電解メッキ法を挙げることができる。尚、本開示の好ましい構成にあっては、酸素流量(酸素ガス分圧、酸素ガス導入量)によって仕事関数を制御することができるという大きな特徴を有する。 The first electrode, the second electrode, and the insulating layer are formed on the basis of the sputtering method. Specific examples include a magnetron sputtering method and a parallel parallel plate sputtering method, and a plasma using a DC discharge method or an RF discharge method. There may be mentioned those using the generation method. Alternatively, as a method of forming the first electrode, depending on the material constituting the first electrode, a vacuum deposition method, a reactive deposition method, an electron beam deposition method, an ion plating method, a PVD method, a pyrosol method, an organic method, etc. Examples include a method of thermally decomposing a metal compound, a spray method, a dipping method, and various CVD methods including an MOCVD method, an electroless plating method, and an electrolytic plating method. The preferred configuration of the present disclosure has a great feature that the work function can be controlled by the oxygen flow rate (oxygen gas partial pressure, oxygen gas introduction amount).
 本開示の電子デバイスによって、テレビカメラ等の撮像装置(固体撮像装置)以外にも、光センサーやイメージセンサーを構成することができる。 In addition to an imaging device (solid-state imaging device) such as a TV camera, an optical sensor or an image sensor can be configured by the electronic device of the present disclosure.
 また、第2-Aの構成の電子デバイスあるいは第2-Bの構成の電子デバイスは、例えば、表示装置に適用することができる。即ち、このような表示装置として、第2-Aの構成の電子デバイスあるいは第2-Bの構成の電子デバイスを光源として備えたプロジェクター装置や画像表示装置、モニター装置、第2-Aの構成の電子デバイスあるいは第2-Bの構成の電子デバイスを光源として備えた反射型液晶表示装置、ヘッドマウントディスプレイ(HMD)、ヘッドアップディスプレイ(HUD)、各種照明を挙げることができる。また、第2-Aの構成の電子デバイスあるいは第2-Bの構成の電子デバイスを顕微鏡の光源として用いることができる。但し、第2-Aの構成の電子デバイスあるいは第2-Bの構成の電子デバイスの適用分野はこれらに限定するものではない。 Further, the electronic device having the configuration 2-A or the electronic device having the configuration 2-B can be applied to a display device, for example. That is, as such a display device, a projector device, an image display device, a monitor device, or the like, which has an electronic device having the configuration 2-A or an electronic device having the configuration 2-B as a light source. Examples thereof include a reflective liquid crystal display device including an electronic device or an electronic device having a configuration 2-B as a light source, a head-mounted display (HMD), a head-up display (HUD), and various types of illumination. Further, an electronic device having the configuration 2-A or an electronic device having the configuration 2-B can be used as a light source of the microscope. However, the application field of the electronic device having the configuration 2-A or the electronic device having the configuration 2-B is not limited thereto.
 実施例1は、本開示の電子デバイス及びその製造方法、本開示の絶縁材料に関し、更には、第1-Cの構成の電子デバイスに関する。実施例1の電子デバイスの模式的な断面図を図1Aに示す。実施例1の電子デバイスは光電変換素子を構成する。 Example 1 relates to an electronic device of the present disclosure, a manufacturing method thereof, an insulating material of the present disclosure, and further relates to an electronic device having a first-C configuration. A schematic cross-sectional view of the electronic device of Example 1 is shown in FIG. 1A. The electronic device of Example 1 constitutes a photoelectric conversion element.
 実施例1あるいは後述する実施例2~実施例6の電子デバイスは、発光・受光層20、発光・受光層20に電気的に接続された第1電極31,91、及び、発光・受光層20上に形成された第2電極32,92を備えている。第2電極32,92は、インジウム(In)と、ガリウム(Ga)及び/又はアルミニウム(Al)と、亜鉛(Zn)と、酸素(O)との少なくとも四元系化合物から構成されている。即ち、導電性の非晶質酸化物から成る。発光・受光層20は、インジウム(In)と、ガリウム(Ga)及び/又はアルミニウム(Al)と、亜鉛(Zn)と、酸素(O)との少なくとも四元系化合物から構成された絶縁層40,80によって被覆されている。即ち、絶縁層40,80も、絶縁性の非晶質酸化物から成る。そして、絶縁層40,80における酸素(O)の組成割合は、第2電極32,92における酸素(O)の組成割合よりも高い。また、実施例1の絶縁材料(具体的には、絶縁層40,80を構成する材料)は、インジウム(In)と、ガリウム(Ga)及び/又はアルミニウム(Al)と、亜鉛(Zn)と、酸素(O)との少なくとも四元系化合物から構成されている。即ち、絶縁材料も、絶縁性の非晶質酸化物から成る。 The electronic device of Example 1 or Examples 2 to 6 described later includes a light emitting / receiving layer 20, first electrodes 31 and 91 electrically connected to the light emitting / receiving layer 20, and the light emitting / receiving layer 20. Second electrodes 32 and 92 formed thereon are provided. The second electrodes 32 and 92 are composed of at least a quaternary compound of indium (In), gallium (Ga) and / or aluminum (Al), zinc (Zn), and oxygen (O). That is, it consists of a conductive amorphous oxide. The light emitting / receiving layer 20 includes an insulating layer 40 made of at least a quaternary compound of indium (In), gallium (Ga) and / or aluminum (Al), zinc (Zn), and oxygen (O). , 80. That is, the insulating layers 40 and 80 are also made of an insulating amorphous oxide. The composition ratio of oxygen (O) in the insulating layers 40 and 80 is higher than the composition ratio of oxygen (O) in the second electrodes 32 and 92. The insulating material of Example 1 (specifically, the material constituting the insulating layers 40 and 80) is indium (In), gallium (Ga) and / or aluminum (Al), and zinc (Zn). And at least a quaternary compound with oxygen (O). That is, the insulating material is also made of an insulating amorphous oxide.
 より具体的には、実施例1あるいは後述する実施例2~実施例6の電子デバイスにおいて、絶縁層40,80及び第2電極32,92は、インジウム・ドープのガリウム-亜鉛酸化物(IGZO,In-GaZnO4)といった、透明導電性材料から構成されている。即ち、第2電極32,92は、Ina(Ga,Al)bZncdから成り、絶縁層40,80は、Ina(Ga,Al)bZnce(但し、d<e)から成る。尚、「a」、「b」、「c」、「d」、「e」は種々の値を取り得る。尚、第2電極32,92や絶縁層40,80を、インジウム・ドープのガリウム-亜鉛酸化物(IGZO)の他、インジウム-ガリウム酸化物(IGO)、酸化アルミニウム・ドープの酸化亜鉛(AZO)、インジウム-亜鉛酸化物(IZO)、又は、ガリウム・ドープの酸化亜鉛(GZO)から構成することもできる。尚、「a」の値として0.05乃至0.10、「b」の値として0.10乃至0.20、「c」の値として0.10乃至0.20、「d」の値として0.30乃至0.40、「e」の値として0.45乃至0.60を例示することができるが、これらの値に限定するものではない。 More specifically, in the electronic devices of Example 1 or Examples 2 to 6 described later, the insulating layers 40 and 80 and the second electrodes 32 and 92 are made of indium-doped gallium-zinc oxide (IGZO, It is made of a transparent conductive material such as In—GaZnO 4 ). That is, the second electrodes 32 and 92 are made of In a (Ga, Al) b Zn c O d , and the insulating layers 40 and 80 are In a (Ga, Al) b Zn c O e (where d <e ). Note that “a”, “b”, “c”, “d”, and “e” can take various values. The second electrodes 32 and 92 and the insulating layers 40 and 80 are made of indium-doped gallium-zinc oxide (IGZO), indium-gallium oxide (IGO), aluminum oxide-doped zinc oxide (AZO). , Indium-zinc oxide (IZO), or gallium-doped zinc oxide (GZO). The value of “a” is 0.05 to 0.10, the value of “b” is 0.10 to 0.20, the value of “c” is 0.10 to 0.20, and the value of “d” is Examples of the values of 0.30 to 0.40 and “e” are 0.45 to 0.60, but are not limited to these values.
 また、実施例1の電子デバイス10において、第1電極31は、例えば、インジウム-スズ酸化物(ITO)といった透明導電性材料から成り、発光・受光層20は、有機光電変換材料、具体的には、例えば、厚さ0.1μmのキナクリドンから成る。発光・受光層20は、第1電極31と第2電極32によって挟まれている。即ち、第1電極31、発光・受光層20、第2電極32が、この順に積層されている。即ち、より具体的には、実施例1の電子デバイス10において、第2電極31が、シリコン半導体基板から成る基板11上に形成されており、発光・受光層20は第1電極31上に形成されており、第2電極32は発光・受光層20上に形成されている。即ち、実施例1あるいは後述する実施例2~実施例3の電子デバイス10は、第1電極31及び第2電極32を備えた2端子型電子デバイス構造を有する。発光・受光層20においては、具体的には、光電変換が行われる。即ち、実施例1あるいは後述する実施例2~実施例3の電子デバイス10は光電変換素子から成る。また、第1電極31を構成する材料として、その他、インジウム-亜鉛酸化物(IZO)、酸化錫(SnO2)といった透明導電性材料を挙げることができる。 In the electronic device 10 of the first embodiment, the first electrode 31 is made of a transparent conductive material such as indium-tin oxide (ITO), and the light emitting / receiving layer 20 is an organic photoelectric conversion material, specifically, Is made of, for example, quinacridone having a thickness of 0.1 μm. The light emitting / receiving layer 20 is sandwiched between the first electrode 31 and the second electrode 32. That is, the first electrode 31, the light emitting / receiving layer 20, and the second electrode 32 are laminated in this order. More specifically, in the electronic device 10 according to the first embodiment, the second electrode 31 is formed on the substrate 11 made of a silicon semiconductor substrate, and the light emitting / receiving layer 20 is formed on the first electrode 31. The second electrode 32 is formed on the light emitting / receiving layer 20. That is, the electronic device 10 of Example 1 or Examples 2 to 3 described later has a two-terminal electronic device structure including the first electrode 31 and the second electrode 32. Specifically, photoelectric conversion is performed in the light emitting / receiving layer 20. That is, the electronic device 10 according to the first embodiment or the second to third embodiments described later includes a photoelectric conversion element. In addition, examples of the material constituting the first electrode 31 include transparent conductive materials such as indium-zinc oxide (IZO) and tin oxide (SnO 2 ).
 更には、波長400nm乃至660nmの光に対する絶縁層40,80の光透過率は80%以上、具体的には、波長550nmの光において90%であり、波長400nm乃至660nmの光に対する第2電極32,92の光透過率は75%以上、具体的には、波長550nmの光において85%である。第1電極31,91や第2電極32,92、絶縁層40,80の光透過率は、透明なガラス板の上に第1電極31,91や第2電極32,92、絶縁層を成膜することで、測定することができる。また、第2電極32,92のシート抵抗値は3×10Ω/□乃至1×103Ω/□、具体的には、8×10Ω/□である。更には、絶縁層40,80のシート抵抗値は2×105Ω/□乃至5×106Ω/□、具体的には、
8×105Ω/□(下記の実施例1A)
4×106Ω/□(下記の実施例1B)
である。
Furthermore, the light transmittance of the insulating layers 40 and 80 with respect to light with a wavelength of 400 nm to 660 nm is 80% or more, specifically, 90% with respect to light with a wavelength of 550 nm, and the second electrode 32 with respect to light with a wavelength of 400 nm to 660 nm. , 92 has a light transmittance of 75% or more, specifically, 85% for light having a wavelength of 550 nm. The light transmittance of the first electrodes 31, 91, the second electrodes 32, 92, and the insulating layers 40, 80 is such that the first electrodes 31, 91, the second electrodes 32, 92, and the insulating layer are formed on a transparent glass plate. It can be measured by forming a film. The sheet resistance values of the second electrodes 32 and 92 are 3 × 10 Ω / □ to 1 × 10 3 Ω / □, specifically 8 × 10 Ω / □. Furthermore, the sheet resistance values of the insulating layers 40 and 80 are 2 × 10 5 Ω / □ to 5 × 10 6 Ω / □, specifically,
8 × 10 5 Ω / □ (Example 1A below)
4 × 10 6 Ω / □ (Example 1B below)
It is.
 室温(具体的には、22゜C乃至28゜C)において、スパッタリング法に基づきIGZO膜を成膜した。そして、成膜時の酸素ガス分圧と、得られたIGZO膜の導電性、絶縁性との関係を調べたところ、以下の表1のとおりとなった。また、成膜時の酸素ガス分圧と、得られたIGZO膜の内部応力との関係を調べた結果を図2に示す。スパッタリング装置として、平行並板スパッタリング装置あるいはDCマグネトロンスパッタリング装置を用い、プロセスガスとしてアルゴン(Ar)ガスを使用し、ターゲットとしてInGaZnO4焼結体を用いた。以下において説明する第2電極32,92、絶縁層40,80の形成においても同様である。内部応力は、市販の薄膜ストレス測定装置を用いて、周知の方法に基づき測定した。また、Siウェハ上に成膜して応力測定した各試料を30秒間アセトンに浸漬した後、光学顕微鏡(倍率5倍)を用いて絶縁層の状態を観察した。その結果を下記の表2の「剥離状態」の欄に示す。尚、浸漬試験結果において、絶縁層に浸漬前後で変化が無いものを「剥離無し」とし、絶縁層の一部でも剥がれたものは「剥離有り」とした。 An IGZO film was formed at room temperature (specifically, 22 ° C. to 28 ° C.) based on a sputtering method. And when the relationship between the oxygen gas partial pressure at the time of film-forming and the electroconductivity and insulation of the obtained IGZO film was investigated, it became as shown in Table 1 below. Further, FIG. 2 shows the result of examining the relationship between the oxygen gas partial pressure during film formation and the internal stress of the obtained IGZO film. A parallel parallel plate sputtering apparatus or a DC magnetron sputtering apparatus was used as the sputtering apparatus, argon (Ar) gas was used as the process gas, and an InGaZnO 4 sintered body was used as the target. The same applies to the formation of the second electrodes 32 and 92 and the insulating layers 40 and 80 described below. The internal stress was measured based on a well-known method using a commercially available thin film stress measuring device. In addition, each sample, which was formed on a Si wafer and subjected to stress measurement, was immersed in acetone for 30 seconds, and then the state of the insulating layer was observed using an optical microscope (5 times magnification). The result is shown in the column of “peeled state” in Table 2 below. In the results of the immersion test, the case where there was no change in the insulating layer before and after immersion was designated as “no peeling”, and the case where even a part of the insulating layer was peeled was designated as “with peeling”.
[表1]
酸素ガス分圧
0.003Pa以下          導電性
0.004Pa乃至0.02Pa    半導体
0.04Pa以上           絶縁性
[Table 1]
Oxygen gas partial pressure 0.003 Pa or less Conductivity 0.004 Pa to 0.02 Pa Semiconductor 0.04 Pa or more Insulative
 また、IGZO膜から成る絶縁層40の構成と、内部応力、第2電極32からの絶縁層40の剥離状態を調べた。その結果を、以下の表2に示す。比較例1にあっては、絶縁層をスパッタリング法に基づき形成されたSiONから構成した。 Further, the configuration of the insulating layer 40 made of the IGZO film, the internal stress, and the peeling state of the insulating layer 40 from the second electrode 32 were examined. The results are shown in Table 2 below. In Comparative Example 1, the insulating layer was made of SiON formed based on the sputtering method.
[表2]
        絶縁層の厚さ  内部応力(圧縮応力)  剥離状態
実施例1A   100nm    65MPa      剥離無し
実施例1B   100nm    24MPa      剥離無し
比較例1    200nm   200MPa      剥離有り
[Table 2]
Insulating layer thickness Internal stress (compressive stress) Peeling state Example 1A 100 nm 65 MPa No peeling Example 1B 100 nm 24 MPa No peeling Comparative Example 1 200 nm 200 MPa With peeling
 また、種々の試験結果から、絶縁層40,80の内部応力を、10MPa乃至90MPaの圧縮応力とすることが好ましいことが判った。そして、そのためには、また、導電性、絶縁性の制御のためには、第2電極32,92及び絶縁層40,80をスパッタリング法に基づき形成する際の酸素ガス分圧(酸素ガス導入量)を制御することで、第2電極32,92及び絶縁層40,80における酸素(O)の組成割合を制御することが好ましいことが判った。即ち、絶縁層40,80の成膜時、酸素ガス分圧を0.04Pa乃至0.15Paとすることが好ましいことが判った。 Also, from various test results, it was found that the internal stress of the insulating layers 40 and 80 is preferably a compressive stress of 10 MPa to 90 MPa. For this purpose, in order to control conductivity and insulation, oxygen gas partial pressure (oxygen gas introduction amount) when the second electrodes 32 and 92 and the insulating layers 40 and 80 are formed by sputtering is used. ) Is preferably controlled to control the composition ratio of oxygen (O) in the second electrodes 32 and 92 and the insulating layers 40 and 80. That is, it was found that the oxygen gas partial pressure is preferably 0.04 Pa to 0.15 Pa when forming the insulating layers 40 and 80.
 以下、実施例1の電子デバイスの製造方法を、説明する。尚、実施例1の電子デバイスの製造方法(電子デバイスにおける電極形成方法)によって得られる電極は、光電変換素子用の電極である。実施例1の電子デバイスの製造方法において得られる電子デバイス10は光電変換素子を構成する。 Hereinafter, a method for manufacturing the electronic device of Example 1 will be described. In addition, the electrode obtained by the manufacturing method (electrode formation method in an electronic device) of the electronic device of Example 1 is an electrode for a photoelectric conversion element. The electronic device 10 obtained in the manufacturing method of the electronic device of Example 1 constitutes a photoelectric conversion element.
  [工程-100]
 シリコン半導体基板から成る基板11を準備する。ここで、基板11には、例えば、電子デバイスの駆動回路(図示せず)、配線12が設けられており、表面には層間絶縁膜13が形成されている。層間絶縁膜13には、底部に配線12が露出した開口部14が設けられている。そして、開口部14内を含む層間絶縁膜13上に、スパッタリング法に基づき、ITOから成る第1電極31を形成(成膜)する。
[Step-100]
A substrate 11 made of a silicon semiconductor substrate is prepared. Here, for example, an electronic device drive circuit (not shown) and wiring 12 are provided on the substrate 11, and an interlayer insulating film 13 is formed on the surface. The interlayer insulating film 13 is provided with an opening 14 where the wiring 12 is exposed at the bottom. Then, a first electrode 31 made of ITO is formed (film formation) on the interlayer insulating film 13 including the inside of the opening 14 based on a sputtering method.
  [工程-110]
 次いで、第1電極31のパターニングを行った後、全面に、真空蒸着法にて、キナクリドンから成る発光・受光層20を形成(成膜)する。
[Step-110]
Next, after patterning the first electrode 31, the light emitting / receiving layer 20 made of quinacridone is formed (film formation) on the entire surface by vacuum deposition.
  [工程-120]
 その後、発光・受光層20上に、スパッタリング法に基づき、導電性の非晶質酸化物から成る(具体的には、IGZOから成る)第2電極32を形成した後、第2電極32を所望の形状に周知のパターニング技術に基づきパターニングする。次いで、スパッタリング条件を変更して、絶縁層40を全面に形成(成膜)する。即ち、発光・受光層20を、スパッタリング法に基づき、絶縁性の非晶質酸化物から成る(具体的には、IGZOから成る)絶縁層40によって被覆する。こうして、図1Aに示す構造を有する実施例1の電子デバイスを得ることができる。
[Step-120]
Thereafter, a second electrode 32 made of a conductive amorphous oxide (specifically, made of IGZO) is formed on the light emitting / receiving layer 20 based on a sputtering method, and then the second electrode 32 is formed as desired. Patterning is performed based on a well-known patterning technique. Next, the insulating layer 40 is formed (film formation) on the entire surface by changing the sputtering conditions. That is, the light emitting / receiving layer 20 is covered with the insulating layer 40 made of an insulating amorphous oxide (specifically, made of IGZO) based on a sputtering method. Thus, the electronic device of Example 1 having the structure shown in FIG. 1A can be obtained.
 あるいは又、発光・受光層20上に、スパッタリング法に基づき、絶縁性の非晶質酸化物から成る(具体的には、IGZOから成る)絶縁層40を形成した後、第2電極32を形成すべき絶縁層40の部分を、周知のパターニング技術に基づき除去する。次いで、スパッタリング条件を変更して、全面に、導電性の非晶質酸化物から成る(具体的には、IGZOから成る)第2電極32を形成した後、第2電極32を所望の形状に周知のパターニング技術に基づきパターニングする。こうして、図1Bに示す構造を有する実施例1の電子デバイスを得ることができる。即ち、絶縁層40は、第2電極32の上側に形成されていてもよいし、下側に形成されていてもよい。 Alternatively, after the insulating layer 40 made of an insulating amorphous oxide (specifically, made of IGZO) is formed on the light emitting / receiving layer 20 based on the sputtering method, the second electrode 32 is formed. The portion of the insulating layer 40 to be removed is removed based on a known patterning technique. Next, after changing the sputtering conditions to form the second electrode 32 made of a conductive amorphous oxide (specifically, made of IGZO) on the entire surface, the second electrode 32 is formed into a desired shape. Patterning is performed based on a known patterning technique. Thus, the electronic device of Example 1 having the structure shown in FIG. 1B can be obtained. That is, the insulating layer 40 may be formed on the upper side of the second electrode 32 or may be formed on the lower side.
 尚、スパッタリング法に基づき第2電極32及び絶縁層40を形成する際の酸素ガス分圧(酸素ガス導入量)を制御することで、即ち、スパッタリング法に基づき第2電極32を形成する際の酸素ガス分圧(酸素ガス導入量)よりも、絶縁層40を形成する際の酸素ガス分圧(酸素ガス導入量)を増加させることで、絶縁層40における酸素(O)の組成割合を第2電極32における酸素(O)の組成割合よりも高くする。また、絶縁層40をスパッタリング法に基づき形成する際の酸素ガス分圧を、0.04Pa乃至0.15Paとする。更には、スパッタリング法に基づき第2電極32及び絶縁層40を形成する際の温度を、室温、具体的には、22゜C乃至28゜Cとする。スパッタリング装置として、平行並板スパッタリング装置あるいはDCマグネトロンスパッタリング装置を用い、プロセスガスとしてアルゴン(Ar)ガスを使用し、ターゲットとしてInGaZnO4焼結体を用いた。 In addition, by controlling the oxygen gas partial pressure (oxygen gas introduction amount) when forming the second electrode 32 and the insulating layer 40 based on the sputtering method, that is, when forming the second electrode 32 based on the sputtering method. By increasing the oxygen gas partial pressure (oxygen gas introduction amount) at the time of forming the insulating layer 40 rather than the oxygen gas partial pressure (oxygen gas introduction amount), the composition ratio of oxygen (O) in the insulating layer 40 is increased. The composition ratio is higher than the oxygen (O) composition ratio in the two electrodes 32. The oxygen gas partial pressure when forming the insulating layer 40 based on the sputtering method is set to 0.04 Pa to 0.15 Pa. Further, the temperature at which the second electrode 32 and the insulating layer 40 are formed based on the sputtering method is set to room temperature, specifically 22 ° C. to 28 ° C. A parallel parallel plate sputtering apparatus or a DC magnetron sputtering apparatus was used as the sputtering apparatus, argon (Ar) gas was used as the process gas, and an InGaZnO 4 sintered body was used as the target.
 以上のように、実施例1にあっては、第2電極及び絶縁層の組成及び酸素の組成割合が規定されており、第2電極及び絶縁層を同種の材料で形成できるが故に、より合理的な方法で電子デバイスの製造が可能となるし、第2電極及び絶縁層が同種の材料であるにも拘わらず、それぞれに、導電性、絶縁性を付与することができる。しかも、より低い温度のプロセスで電子デバイスの製造が可能となるので、発光・受光層の熱劣化を防止することができるし、更には、絶縁層の膜ストレスを抑制することができるので、高い信頼性を有する電子デバイスを提供することができる。 As described above, in Example 1, the composition of the second electrode and the insulating layer and the composition ratio of oxygen are defined, and the second electrode and the insulating layer can be formed of the same material. An electronic device can be manufactured by a typical method, and although the second electrode and the insulating layer are made of the same material, conductivity and insulation can be imparted to each of them. Moreover, since the electronic device can be manufactured at a lower temperature process, it is possible to prevent thermal degradation of the light emitting / receiving layer, and furthermore, the film stress of the insulating layer can be suppressed, which is high. An electronic device having reliability can be provided.
 実施例2は、実施例1の変形であり、第1-Aの構成の電子デバイス及び第1-Cの構成の電子デバイスに関する。即ち、実施例2の電子デバイスにおいて、発光・受光層20は、第1電極31及び第2電極32によって挟まれており、第2電極32の仕事関数の値と第1電極31の仕事関数の値との差は0.4eV以上である。ここで、第2電極32の仕事関数の値と第1電極31の仕事関数の値との差を0.4eV以上とすることで、仕事関数の値の差に基づき発光・受光層20において内部電界を発生させ、内部量子効率の向上を図る。第2電極32はカソード電極(陰極)として機能する。即ち、電子を取り出す電極として機能する。一方、第1電極31はアノード電極(陽極)として機能する。即ち、正孔を取り出す電極として機能する。ここで、第2電極32を構成するIGZOの仕事関数は、成膜条件にも依るが、4.1eV乃至4.2eVである。また、第1電極31を構成するITOの仕事関数は、成膜条件にも依るが、一例として、4.8eV乃至5.0eVである。 Example 2 is a modification of Example 1, and relates to an electronic device having a first-A configuration and an electronic device having a first-C configuration. That is, in the electronic device of Example 2, the light emitting / receiving layer 20 is sandwiched between the first electrode 31 and the second electrode 32, and the work function value of the second electrode 32 and the work function of the first electrode 31 are The difference from the value is 0.4 eV or more. Here, the difference between the work function value of the second electrode 32 and the work function value of the first electrode 31 is set to 0.4 eV or more, so that the inside of the light emitting / receiving layer 20 is based on the difference of the work function values. Generate an electric field to improve internal quantum efficiency. The second electrode 32 functions as a cathode electrode (cathode). That is, it functions as an electrode for extracting electrons. On the other hand, the first electrode 31 functions as an anode electrode (anode). That is, it functions as an electrode for extracting holes. Here, the work function of IGZO constituting the second electrode 32 is 4.1 eV to 4.2 eV although it depends on the film forming conditions. In addition, the work function of ITO constituting the first electrode 31 is 4.8 eV to 5.0 eV as an example, although it depends on the film forming conditions.
 具体的には、スパッタリング法に基づき第2電極32を形成する際の酸素ガス導入量(酸素ガス分圧)を制御することで、第2電極32の仕事関数の値を制御する。酸素ガス分圧と第2電極32の仕事関数の値との関係を求めた結果の一例を図3Aのグラフに示すが、酸素ガス分圧の値が高くなるに従い、即ち、酸素欠損が少なくなる程、第2電極32の仕事関数の値は高くなり、酸素ガス分圧の値が低くなるに従い、即ち、酸素欠損が多くなる程、第2電極32の仕事関数の値は低くなっている。 Specifically, the work function value of the second electrode 32 is controlled by controlling the oxygen gas introduction amount (oxygen gas partial pressure) when forming the second electrode 32 based on the sputtering method. An example of the result of obtaining the relationship between the oxygen gas partial pressure and the work function value of the second electrode 32 is shown in the graph of FIG. 3A. As the oxygen gas partial pressure value increases, that is, oxygen deficiency decreases. As the work function value of the second electrode 32 increases and the oxygen gas partial pressure value decreases, that is, as the oxygen deficiency increases, the work function value of the second electrode 32 decreases.
 このように、実施例2の電子デバイスにあっては、第2電極32をスパッタリング法に基づき形成する際の酸素ガス導入量(酸素ガス分圧)を制御することで、第2電極32の仕事関数の値が制御される。尚、第2電極32において、酸素の含有率は化学量論組成の酸素含有率よりも少ない。 Thus, in the electronic device of Example 2, the work of the second electrode 32 is controlled by controlling the oxygen gas introduction amount (oxygen gas partial pressure) when forming the second electrode 32 based on the sputtering method. The function value is controlled. In the second electrode 32, the oxygen content is lower than the oxygen content of the stoichiometric composition.
 実施例2の電子デバイス(光電変換素子)及び比較例2の電子デバイス(光電変換素子)において得られたI-V曲線を図3Bに示す。尚、図3B中、「A」は、実施例2の電子デバイスの測定結果であり、「B」は、後述する実施例3の電子デバイスの測定結果であり、「C」は、比較例2の電子デバイスの測定結果である。ここで、比較例2の電子デバイスは、実施例2の電子デバイスの第2電極32を、IGZOの代わりにITOから構成したものである。図3Bから、実施例2あるいは後述する実施例3の電子デバイスにあっては、逆バイアス電圧1ボルト弱(バイアス電圧-1ボルト弱)において、急激に電流値が増加していることが判る。実施例2及び比較例2の電子デバイスの内部量子効率の値、オン/オフ比の値は、以下の表3のとおりであった。尚、内部量子効率ηは、入射フォトン数に対する生成された電子数の比であり、以下の式で表すことができる。 FIG. 3B shows IV curves obtained in the electronic device (photoelectric conversion element) of Example 2 and the electronic device (photoelectric conversion element) of Comparative Example 2. In FIG. 3B, “A” is the measurement result of the electronic device of Example 2, “B” is the measurement result of the electronic device of Example 3 described later, and “C” is Comparative Example 2. It is a measurement result of the electronic device. Here, in the electronic device of Comparative Example 2, the second electrode 32 of the electronic device of Example 2 is made of ITO instead of IGZO. From FIG. 3B, it can be seen that in the electronic device of Example 2 or Example 3 to be described later, the current value increases abruptly at a reverse bias voltage of less than 1 volt (bias voltage of less than −1 volt). The values of internal quantum efficiency and on / off ratio of the electronic devices of Example 2 and Comparative Example 2 were as shown in Table 3 below. The internal quantum efficiency η is a ratio of the number of generated electrons to the number of incident photons, and can be expressed by the following equation.
η={(h・c)/(q・λ)}(I/P)=(1.24/λ)(I/P)
ここで、
h:プランク定数
c:光速
q:電子の電荷
λ:入射光の波長(μm)
I:明電流であり、実施例1の測定にあっては、逆バイアス電圧1ボルトにおいて得られる電流値(アンペア/cm2
P:入射光のパワー(アンペア/cm2
である。
η = {(h · c) / (q · λ)} (I / P) = (1.24 / λ) (I / P)
here,
h: Planck's constant c: speed of light q: charge of electron λ: wavelength of incident light (μm)
I: Bright current. In the measurement of Example 1, the current value (ampere / cm 2 ) obtained at a reverse bias voltage of 1 volt
P: power of incident light (ampere / cm 2 )
It is.
[表3]
      内部量子効率(%)  オン/オフ比
実施例2  39         2.6
実施例3  55         3.4
比較例2   5.4       1.4
[Table 3]
Internal quantum efficiency (%) On / off ratio Example 2 39 2.6
Example 3 55 3.4
Comparative Example 2 5.4 1.4
 比較例2の電子デバイスにあっては、第1電極及び第2電極を共にITOから構成しているので、エネルギーダイヤグラムの概念図を図4Bに示すように、第2電極の仕事関数の値と第1電極の仕事関数の値との差は無い。従って、第2電極からの正孔が第1電極に流入し易く、その結果、暗電流が増加する。また、第2電極の仕事関数の値と第1電極の仕事関数の値との差が無いので、電子及び正孔の取り出し時、電位勾配が存在せず(即ち、発光・受光層において内部電界が発生せず)、電子及び正孔の円滑な取り出しが困難となる(図4Dの概念図を参照)。一方、実施例2の電子デバイスにあっては、第2電極をIGZOから構成し、第1電極をITOから構成しており、第2電極の仕事関数の値と第1電極の仕事関数の値との差は、0.4eV以上である。エネルギーダイヤグラムの概念図を図4Aに示す。従って、第1電極からの正孔が第2電極に流入することを防ぐことができる結果、暗電流の発生を抑制することができる。また、第2電極の仕事関数の値と第1電極の仕事関数の値との差が0.4eV以上あるので、電子及び正孔の取り出し時、電位勾配が発生し(即ち、発光・受光層において内部電界が発生し)、この電位勾配を応用して電子及び正孔の円滑な取り出しを行うことができる(図4Cの概念図を参照)。 In the electronic device of Comparative Example 2, since both the first electrode and the second electrode are made of ITO, a conceptual diagram of an energy diagram is shown in FIG. There is no difference from the work function value of the first electrode. Therefore, the holes from the second electrode easily flow into the first electrode, and as a result, the dark current increases. In addition, since there is no difference between the work function value of the second electrode and the work function value of the first electrode, there is no potential gradient when taking out electrons and holes (that is, the internal electric field in the light emitting / receiving layer). Therefore, it is difficult to smoothly extract electrons and holes (see the conceptual diagram in FIG. 4D). On the other hand, in the electronic device of Example 2, the second electrode is made of IGZO, the first electrode is made of ITO, the work function value of the second electrode and the work function value of the first electrode. Is 0.4 eV or more. A conceptual diagram of the energy diagram is shown in FIG. 4A. Accordingly, it is possible to prevent holes from the first electrode from flowing into the second electrode, and as a result, generation of dark current can be suppressed. In addition, since the difference between the work function value of the second electrode and the work function value of the first electrode is 0.4 eV or more, a potential gradient is generated when electrons and holes are taken out (that is, the light emitting / receiving layer). In this case, an internal electric field is generated), and this potential gradient can be applied to smoothly extract electrons and holes (see the conceptual diagram in FIG. 4C).
 更には、内部量子効率と仕事関数の値の差との相関を調べた結果を図5Aのグラフに示し、暗電流(実施例2の測定にあっては、逆バイアス電圧1ボルトにおいて光を照射しないときに得られる電流値)と仕事関数の値の差との相関を調べた結果を図5Bのグラフに示す。尚、図5A及び図5Bの横軸は、第2電極32の仕事関数の値と第1電極31の仕事関数の値との差を示し、後述する図6A及び図6Bの横軸は、第2電極32の第2B層32Bの仕事関数の値と第2電極32の第2A層32Aの仕事関数の値との差を示す。図5A及び図5Bから、仕事関数の値の差が0.4eV付近を境にして、内部量子効率の明確な増加、暗電流の明確な低下が認められた。 Furthermore, the result of investigating the correlation between the internal quantum efficiency and the difference between the work function values is shown in the graph of FIG. 5A, and light is irradiated at a dark current (in the measurement of Example 2, at a reverse bias voltage of 1 volt). The graph of FIG. 5B shows the result of examining the correlation between the current value obtained when not) and the difference between the work function values. 5A and 5B indicate the difference between the work function value of the second electrode 32 and the work function value of the first electrode 31, and the horizontal axes of FIGS. A difference between the work function value of the second B layer 32B of the two electrodes 32 and the work function value of the second A layer 32A of the second electrode 32 is shown. From FIG. 5A and FIG. 5B, a clear increase in internal quantum efficiency and a clear decrease in dark current were recognized when the difference in work function value was around 0.4 eV.
 以上のように、実施例2の電子デバイスにあっては、第2電極の仕事関数の値と第1電極の仕事関数の値との差が規定されているので、第1電極と第2電極との間にバイアス電圧(より具体的には、逆バイアス電圧)を印加したとき、仕事関数の値の差に基づき発光・受光層において大きな内部電界を発生させることができる結果、内部量子効率の向上を図ることができるし、即ち、光電流の増加を図ることができるし、また、暗電流の発生を抑制することが可能となる。実施例2の電子デバイスの製造方法(第2電極の形成方法)にあっては、スパッタリング法に基づき形成する際の酸素ガス導入量(酸素ガス分圧)を制御することで第2電極の仕事関数の値を制御することができる結果、仕事関数の値の差に基づき発光・受光層において大きな内部電界を発生させることができるので、内部量子効率の向上を図ることができるし、即ち、光電流の増加を図ることができるし、また、暗電流の発生を抑制することが可能な電子デバイスを、簡素な製造プロセスで製造することができる。 As described above, in the electronic device of Example 2, since the difference between the work function value of the second electrode and the work function value of the first electrode is defined, the first electrode and the second electrode are defined. When a bias voltage (more specifically, a reverse bias voltage) is applied between the two, a large internal electric field can be generated in the light emitting / receiving layer based on the difference in the work function value. The improvement can be achieved, that is, the photocurrent can be increased, and the generation of dark current can be suppressed. In the electronic device manufacturing method (second electrode forming method) of Example 2, the work of the second electrode is controlled by controlling the oxygen gas introduction amount (oxygen gas partial pressure) when forming based on the sputtering method. As a result of controlling the function value, it is possible to generate a large internal electric field in the light emitting / receiving layer based on the difference in the work function value, so that the internal quantum efficiency can be improved. An electronic device capable of increasing current and suppressing generation of dark current can be manufactured by a simple manufacturing process.
 実施例3は、実施例2の変形であり、第1-Bの構成の電子デバイス及び第1-Cの構成の電子デバイスに関する。即ち、実施例3の電子デバイスにおいて、発光・受光層20は、第1電極31及び第2電極32によって挟まれており、第2電極32は、発光・受光層20側から、第2B層32B及び第2A層32Aの積層構造を有し、第2電極32の第2A層32Aの仕事関数の値は、第2電極32の第2B層32Bの仕事関数の値よりも低い。実施例3の電子デバイスの模式的な一部断面図を図1Cに示す。 Example 3 is a modification of Example 2, and relates to an electronic device having a first-B configuration and an electronic device having a first-C configuration. That is, in the electronic device of Example 3, the light emitting / receiving layer 20 is sandwiched between the first electrode 31 and the second electrode 32, and the second electrode 32 extends from the light emitting / receiving layer 20 side to the second B layer 32 </ b> B. In addition, the work function value of the second A layer 32A of the second electrode 32 is lower than the work function value of the second B layer 32B of the second electrode 32. A schematic partial cross-sectional view of the electronic device of Example 3 is shown in FIG. 1C.
 具体的には、第2電極32の第2A層32Aの仕事関数の値と第2電極32の第2B層32Bの仕事関数の値との差は、0.1eV乃至0.2eV、より具体的には、0.15eVであり、第1電極31の仕事関数の値と第2電極32の第2A層32Aの仕事関数の値との差は0.4eV以上である。また、第2電極32の厚さは、1×10-8m乃至1×10-7m、具体的には、50nmであり、第2電極32の第2A層32Aの厚さと第2電極32の第2B層32Bの厚さの割合は9/1乃至1/9、具体的には、9/1である。実施例3にあっても、第1電極31の仕事関数の値と第2電極32の第2A層32Aの仕事関数の値との差を0.4eV以上とすることで、仕事関数の値の差に基づき発光・受光層において内部電界を発生させ、内部量子効率の向上を図る。ここで、第2A層32Aの組成をIna(Ga,Al)bZncdとし、第2B層32Bの組成をIna'(Ga,Al)b'Znc'd'としたとき、a=a’,b=b’,c=c’であり、更には、d<d’である。実施例3の電子デバイスの内部量子効率の値、オン/オフ比の値を、上記の表3に示す。また、実施例3の電子デバイス(光電変換素子)において得られたI-V曲線を図3Bに示す。更には、内部量子効率と仕事関数の値の差との相関を調べた結果を図6Aのグラフに示し、暗電流(実施例3の測定にあっても、逆バイアス電圧1ボルトにおいて光を照射しないときに得られる電流値)と仕事関数の値の差との相関を調べた結果を図6Bのグラフに示す。図6A及び図6Bから、第2電極の第2A層の仕事関数の値と第2電極の第2B層の仕事関数の値との差が約0.2eV付近まで増加するに従い、内部量子効率の明確な増加、暗電流の明確な低下が認められた。 Specifically, the difference between the work function value of the second A layer 32A of the second electrode 32 and the work function value of the second B layer 32B of the second electrode 32 is 0.1 eV to 0.2 eV, more specifically. Is 0.15 eV, and the difference between the work function value of the first electrode 31 and the work function value of the second A layer 32A of the second electrode 32 is 0.4 eV or more. The thickness of the second electrode 32 is 1 × 10 −8 m to 1 × 10 −7 m, specifically 50 nm. The thickness of the second A layer 32A of the second electrode 32 and the second electrode 32 are the same. The thickness ratio of the second B layer 32B is 9/1 to 1/9, specifically 9/1. Even in the third embodiment, by setting the difference between the work function value of the first electrode 31 and the work function value of the second A layer 32A of the second electrode 32 to 0.4 eV or more, the work function value Based on the difference, an internal electric field is generated in the light emitting / receiving layer to improve internal quantum efficiency. Here, when the composition of the second A layer 32A is In a (Ga, Al) b Zn c O d and the composition of the second B layer 32B is In a ′ (Ga, Al) b ′ Zn c ′ O d ′. , A = a ′, b = b ′, c = c ′, and d <d ′. The values of the internal quantum efficiency and the on / off ratio of the electronic device of Example 3 are shown in Table 3 above. Further, FIG. 3B shows an IV curve obtained in the electronic device (photoelectric conversion element) of Example 3. Furthermore, the result of investigating the correlation between the internal quantum efficiency and the difference between the work function values is shown in the graph of FIG. 6A. Light is irradiated at a reverse bias voltage of 1 volt even in the measurement of Example 3. 6B shows the result of examining the correlation between the difference between the current value obtained when not) and the work function value. 6A and 6B, as the difference between the work function value of the second A layer of the second electrode and the work function value of the second B layer of the second electrode increases to about 0.2 eV, the internal quantum efficiency is increased. A clear increase and a clear decrease in dark current were observed.
 実施例3の電子デバイスの製造方法(電子デバイスにおける電極形成方法)にあっては、実施例1の[工程-120]と同様の工程において、例えば、図3Aのグラフに示したように、スパッタリング法に基づき形成する際の酸素ガス導入量を制御することで、第2電極32の第2A層32A及び第2B層32Bの仕事関数の値を制御する。 In the manufacturing method of the electronic device of Example 3 (electrode formation method in the electronic device), in the same step as [Step-120] of Example 1, for example, as shown in the graph of FIG. By controlling the amount of oxygen gas introduced when forming based on the method, the work function values of the second A layer 32A and the second B layer 32B of the second electrode 32 are controlled.
 実施例3の電子デバイスにあっては、第2電極が第2A層と第2B層から構成され、しかも、第2A層と第2B層の仕事関数の差が規定されているので、第2電極における仕事関数の最適化を図ることができ、キャリアの授受(移動)が一層容易になる。 In the electronic device of Example 3, the second electrode is composed of the second A layer and the second B layer, and the difference in work function between the second A layer and the second B layer is defined. The work function can be optimized, and the transfer (movement) of the carrier becomes easier.
 実施例4は、実施例1の変形であり、第2-Aの構成の電子デバイス等に関する。実施例4の電子デバイスの模式的な一部断面図を図7A及び図7Bに示す。尚、図7Aは、図7Bの矢印A-Aに沿った模式的な一部断面図であり、導波路構造(共振器構造)の延びる方向に対して垂直な仮想平面で電子デバイスを切断したときの模式的な一部断面図である。また、図7Bは、図7Aの矢印B-Bに沿った模式的な一部断面図であり、導波路構造(共振器構造)の延びる方向に対して平行な仮想平面で電子デバイスを切断したときの模式的な一部断面図である。 Example 4 is a modification of Example 1 and relates to an electronic device having a configuration of 2-A. 7A and 7B are schematic partial cross-sectional views of the electronic device of Example 4. FIG. FIG. 7A is a schematic partial cross-sectional view along the arrow AA in FIG. 7B, in which the electronic device is cut along a virtual plane perpendicular to the extending direction of the waveguide structure (resonator structure). It is a typical partial sectional view at the time. FIG. 7B is a schematic partial cross-sectional view along the arrow BB in FIG. 7A, in which the electronic device is cut along a virtual plane parallel to the extending direction of the waveguide structure (resonator structure). It is a typical partial sectional view at the time.
 実施例4あるいは後述する実施例5~実施例6の電子デバイスにおいて、発光・受光層20は、第1導電型を有する第1化合物半導体層71、活性層73、及び、第1導電型とは異なる第2導電型を有する第2化合物半導体層72から成る積層構造体70から成る。具体的には、実施例4あるいは後述する実施例5~実施例6の電子デバイスは、半導体レーザ素子、より具体的には、リッジストライプ型の分離閉じ込めヘテロ構造を有する半導体レーザ素子から構成されている。そして、第1導電型はn型であり、第2導電型はp型である。即ち、実施例4あるいは後述する実施例5~実施例6の電子デバイスは、第1導電型(具体的には、実施例においてはn型)を有する第1化合物半導体層71、活性層73、及び、第1導電型とは異なる第2導電型(具体的には、実施例においてはp型)を有する第2化合物半導体層72から成る積層構造体70(発光・受光層20)を有する。 In the electronic device of Example 4 or Examples 5 to 6 to be described later, the light emitting / receiving layer 20 includes the first compound semiconductor layer 71 having the first conductivity type, the active layer 73, and the first conductivity type. It consists of the laminated structure 70 which consists of the 2nd compound semiconductor layer 72 which has a different 2nd conductivity type. Specifically, the electronic device of Example 4 or Example 5 to Example 6 to be described later is composed of a semiconductor laser element, more specifically, a semiconductor laser element having a ridge stripe type separated confinement heterostructure. Yes. The first conductivity type is n-type, and the second conductivity type is p-type. That is, the electronic devices of Example 4 or Examples 5 to 6 described later include a first compound semiconductor layer 71 having an first conductivity type (specifically, an n-type in the example), an active layer 73, In addition, the stacked structure 70 (the light emitting / receiving layer 20) including the second compound semiconductor layer 72 having a second conductivity type (specifically, p-type in the embodiment) different from the first conductivity type is provided.
 そして、実施例4の電子デバイスにおいて、第2化合物半導体層72上には、コンタクト層74を介して、第2電極92が形成されており、コンタクト層74の厚さは、4原子層以下の厚さである。また、コンタクト層74と第2化合物半導体層72の界面をxy平面、コンタクト層74と接する第2化合物半導体層72の部分である界面層72Aを構成する結晶のx軸に沿った格子定数(具体的には、a軸に沿った格子定数)をx2、z軸に沿った格子定数(具体的には、c軸に沿った格子定数)をz2、コンタクト層74を構成する結晶の1ユニットにおけるx軸に沿った長さ(具体的には、a軸に沿った長さ)をxC’、z軸に沿った長さ(具体的には、c軸に沿った長さ)をzC’としたとき、
(zC’/xC’)>(z2/x2
を満足する。
In the electronic device of Example 4, the second electrode 92 is formed on the second compound semiconductor layer 72 via the contact layer 74, and the thickness of the contact layer 74 is 4 atomic layers or less. Is the thickness. In addition, the interface between the contact layer 74 and the second compound semiconductor layer 72 is the xy plane, and the lattice constant (specifically) along the x-axis of the crystal constituting the interface layer 72A that is the portion of the second compound semiconductor layer 72 in contact with the contact layer 74 Specifically, the lattice constant along the a-axis) is x 2 , the lattice constant along the z-axis (specifically, the lattice constant along the c-axis) is z 2 , and the crystal constituting the contact layer 74 is 1 The length of the unit along the x-axis (specifically, the length along the a-axis) is x C ', and the length along the z-axis (specifically, the length along the c-axis) z C '
(Z C '/ x C ')> (z 2 / x 2 )
Satisfied.
 実施例4あるいは後述する実施例5~実施例6の電子デバイスにおいて、リッジストライプ構造60は、第1化合物半導体層71、活性層73及び第2化合物半導体層72が積層された積層構造体70から成り、光を出射する第1端面61、及び、第1端面61と対向する第2端面62を有する。図示した例では、リッジストライプ構造60の平面形状は、直線状である。また、リッジストライプ構造60は、第2化合物半導体層72を厚さ方向に一部エッチングすることで形成されている。リッジストライプ構造60の下方の活性層73の領域が、発光領域(電流注入領域)に相当する。光出射端面(第1端面)61及び光反射端面(第2端面)には高反射コート層(HR)が形成されているが、これらのコート層の図示は省略している。尚、光出射端面(第1端面)61の光反射率は、光反射端面(第2端面)62の光反射率よりも低い。リッジストライプ構造60及びその両側は、実施例1において説明した絶縁層80で被覆されている。コンタクト層74(後述する実施例6においては、第2化合物半導体層72)の頂面上の絶縁層80の部分は除去されており、コンタクト層74(後述する実施例6においては、第2化合物半導体層72)の頂面には、第2電極92が形成されている。ここで、実施例4の電子デバイスにおいて、第2電極92は、実施例1において説明した材料から成る。また、第2電極92、絶縁層80は、実施例1において説明したと同様の方法で形成されている。GaN基板51の裏面(主面と対向する面)には、Ti層/Pt層/Au層が積層されて成る第1電極91が形成されている。 In the electronic device of Example 4 or Examples 5 to 6 to be described later, the ridge stripe structure 60 is formed from a laminated structure 70 in which a first compound semiconductor layer 71, an active layer 73, and a second compound semiconductor layer 72 are laminated. And has a first end face 61 that emits light and a second end face 62 that faces the first end face 61. In the illustrated example, the planar shape of the ridge stripe structure 60 is linear. The ridge stripe structure 60 is formed by partially etching the second compound semiconductor layer 72 in the thickness direction. The region of the active layer 73 below the ridge stripe structure 60 corresponds to a light emitting region (current injection region). A high reflection coat layer (HR) is formed on the light emitting end face (first end face) 61 and the light reflecting end face (second end face), but the illustration of these coat layers is omitted. The light reflectance of the light emitting end face (first end face) 61 is lower than the light reflectance of the light reflecting end face (second end face) 62. The ridge stripe structure 60 and both sides thereof are covered with the insulating layer 80 described in the first embodiment. The portion of the insulating layer 80 on the top surface of the contact layer 74 (second compound semiconductor layer 72 in Example 6 described later) has been removed, and the contact layer 74 (second compound in Example 6 described later). A second electrode 92 is formed on the top surface of the semiconductor layer 72). Here, in the electronic device of the fourth embodiment, the second electrode 92 is made of the material described in the first embodiment. The second electrode 92 and the insulating layer 80 are formed by the same method as described in the first embodiment. A first electrode 91 formed by stacking a Ti layer / Pt layer / Au layer is formed on the back surface (the surface facing the main surface) of the GaN substrate 51.
 ここで、実施例4の電子デバイスにおいて、第2化合物半導体層72の界面層72Aを構成する結晶の結晶構造は六方晶系であり、コンタクト層74を構成する結晶の結晶構造も六方晶系である。また、積層構造体70は、GaN系化合物半導体から成り、コンタクト層74は、第2化合物半導体層72の界面層72Aを構成するGaN系化合物半導体と同じ組成のGaN系化合物半導体であって、更に、酸素原子を含むGaN系化合物半導体から成る。積層構造体70の具体的な構成を、以下の表4に示すが、最下段に記載された化合物半導体層がn型GaN基板から成るGaN基板51上に形成されている。コンタクト層74の組成を「p型GaN(O)」と表現しているが、これは、コンタクト層74が、酸素原子を含むGaNから成ることを示している。活性層73は、InGaN層から成る井戸層と、GaN層から成る障壁層とが積層された量子井戸構造を有する。GaN基板51には、n型不純物としてシリコン(Si)、酸素(O)又はゲルマニウム(Ge)が添加されている。表4に示す組成の電子デバイスは緑色を出射する。即ち、実施例4の電子デバイスの発光波長は、440nm以上、600nm以下、より具体的には、495nm以上、570nm以下である。第2化合物半導体層72における界面層72Aは、超格子構造を有する第2クラッド層を構成する厚さ2.5nmのp型GaNから成る。第2クラッド層にあっては、p型AlGaN層あるいはp型GaN層の一方のみを変調ドーピング構造としてもよい。また、第1クラッド層や第2クラッド層を、後述するように、4元InAlGaN層から構成することもできる。尚、組成を変更することで、青色を出射する電子デバイスを得ることができる。 Here, in the electronic device of Example 4, the crystal structure of the crystal composing the interface layer 72A of the second compound semiconductor layer 72 is hexagonal, and the crystal structure of the crystal composing the contact layer 74 is also hexagonal. is there. The stacked structure 70 is made of a GaN-based compound semiconductor, and the contact layer 74 is a GaN-based compound semiconductor having the same composition as that of the GaN-based compound semiconductor constituting the interface layer 72A of the second compound semiconductor layer 72, and GaN-based compound semiconductor containing oxygen atoms. The specific structure of the laminated structure 70 is shown in Table 4 below, and the compound semiconductor layer described at the bottom is formed on a GaN substrate 51 made of an n-type GaN substrate. The composition of the contact layer 74 is expressed as “p-type GaN (O)”, which indicates that the contact layer 74 is made of GaN containing oxygen atoms. The active layer 73 has a quantum well structure in which a well layer made of an InGaN layer and a barrier layer made of a GaN layer are stacked. Silicon (Si), oxygen (O), or germanium (Ge) is added to the GaN substrate 51 as an n-type impurity. The electronic device having the composition shown in Table 4 emits green light. That is, the emission wavelength of the electronic device of Example 4 is not less than 440 nm and not more than 600 nm, more specifically, not less than 495 nm and not more than 570 nm. The interface layer 72A in the second compound semiconductor layer 72 is made of p-type GaN having a thickness of 2.5 nm constituting the second cladding layer having a superlattice structure. In the second cladding layer, only one of the p-type AlGaN layer or the p-type GaN layer may have a modulation doping structure. Further, the first cladding layer and the second cladding layer can be composed of a quaternary InAlGaN layer as will be described later. An electronic device that emits blue light can be obtained by changing the composition.
[表4]
Figure JPOXMLDOC01-appb-I000001
[Table 4]
Figure JPOXMLDOC01-appb-I000001
 以下、実施例4の電子デバイスの製造方法の概要を説明する。 Hereinafter, the outline of the manufacturing method of the electronic device of Example 4 will be described.
  [工程-400]
 例えば、{0001}面であるc面を主面として有するGaN基板51を準備する。但し、GaN基板51の主面は、極性面であるc面に限定するものではない。{11-20}面であるA面、{1-100}面であるM面、{1-102}面といった無極性面、あるいは又、{11-24}面や{11-22}面を含む{11-2n}面、{10-11}面、{10-12}面といった半極性面を主面として有するGaN基板51を用いることもできる。そして、先ず、サーマルクリーニング等によって、GaN基板51の主面を清浄化する。次いで、このGaN基板51の主面の上に、MOCVD法に基づき、バッファ層52を結晶成長させる。続いて、第1クラッド層を成長させた後、第1ガイド層、活性層、第2ガイド層、電子障壁層、第2クラッド層を、順次、形成する。その後、コンタクト層34をALD法に基づき形成することで、p型GaN(O)から成るコンタクト層34を得る。コンタクト層34は、厚さ2.5nmのp型GaNから成る界面層32Aの上に形成される。尚、コンタクト層34の形成方法は、ALD法に限定するものではない。
[Step-400]
For example, a GaN substrate 51 having a c-plane that is a {0001} plane as a main surface is prepared. However, the main surface of the GaN substrate 51 is not limited to the c-plane which is a polar surface. Non-polar surfaces such as the {11-20} plane A, the {1-100} plane M, the {1-102} plane, or the {11-24} plane or the {11-22} plane A GaN substrate 51 having a semipolar plane such as a {11-2n} plane, a {10-11} plane, and a {10-12} plane as a main plane can also be used. First, the main surface of the GaN substrate 51 is cleaned by thermal cleaning or the like. Next, the buffer layer 52 is crystal-grown on the main surface of the GaN substrate 51 based on the MOCVD method. Subsequently, after the first cladding layer is grown, a first guide layer, an active layer, a second guide layer, an electron barrier layer, and a second cladding layer are sequentially formed. Thereafter, the contact layer 34 is formed based on the ALD method to obtain the contact layer 34 made of p-type GaN (O). The contact layer 34 is formed on the interface layer 32A made of p-type GaN having a thickness of 2.5 nm. The method for forming the contact layer 34 is not limited to the ALD method.
  [工程-410]
 次に、第2化合物半導体層72(具体的には、コンタクト層74)の上にエッチング用マスクを形成し、このエッチング用マスクを用いて、例えばRIE法に基づき、第2化合物半導体層72を厚さ方向に一部分、エッチングすることで、リッジストライプ構造60を形成した後、エッチング用マスクを除去する。第2化合物半導体層72及び活性層73を厚さ方向にエッチングしてもよいし、第2化合物半導体層72、活性層73、及び、第1化合物半導体層71を厚さ方向に一部分、エッチングしてもよい。
[Step-410]
Next, an etching mask is formed on the second compound semiconductor layer 72 (specifically, the contact layer 74), and the second compound semiconductor layer 72 is formed using the etching mask, for example, based on the RIE method. The ridge stripe structure 60 is formed by etching partly in the thickness direction, and then the etching mask is removed. The second compound semiconductor layer 72 and the active layer 73 may be etched in the thickness direction, or the second compound semiconductor layer 72, the active layer 73, and the first compound semiconductor layer 71 are partially etched in the thickness direction. May be.
  [工程-420]
 その後、実施例1の[工程-120]と同様にして、全面に絶縁層80を形成した後、第2化合物半導体層72(具体的には、コンタクト層74)の頂面上に位置する絶縁層80の部分を除去する。そして、露出した第2化合物半導体層72(具体的には、コンタクト層74)の上に、実施例1の[工程-120]と同様にして、第2電極92を形成する。また、GaN基板51の裏面側を例えばラッピング及びポリッシングすることで、GaN基板51の厚さを100μm程度にした後、GaN基板51の裏面に第1電極91を形成する。
[Step-420]
Thereafter, in the same manner as in [Step-120] in Example 1, an insulating layer 80 is formed on the entire surface, and then the insulating layer located on the top surface of the second compound semiconductor layer 72 (specifically, the contact layer 74) is formed. Part of layer 80 is removed. Then, the second electrode 92 is formed on the exposed second compound semiconductor layer 72 (specifically, the contact layer 74) in the same manner as in [Step-120] of the first embodiment. In addition, the first electrode 91 is formed on the back surface of the GaN substrate 51 after, for example, lapping and polishing the back surface side of the GaN substrate 51 to reduce the thickness of the GaN substrate 51 to about 100 μm.
  [工程-430]
 次いで、積層構造体70を劈開することで光出射端面(第1端面)61や光反射端面(第2端面)62を形成する。その後、電極を外部の回路等に接続するために端子等を周知の方法に基づき形成し、パッケージや封止することで、実施例4の電子デバイスを完成させる。
[Step-430]
Next, the light emitting end face (first end face) 61 and the light reflecting end face (second end face) 62 are formed by cleaving the laminated structure 70. Thereafter, in order to connect the electrode to an external circuit or the like, a terminal or the like is formed based on a known method, and packaged or sealed, thereby completing the electronic device of Example 4.
 尚、[工程-420]において、実施例1の[工程-120]と同様にして、全面に第2電極92を形成した後、第2電極92をパターニングし、次いで、全面に絶縁層80を形成した後、絶縁層80をパターニングすることで、第2電極92の一部を露出させてもよい。こうして,図8に示す構造を得ることができる。即ち、絶縁層80は、第2電極92の上側に形成されていてもよいし、下側に形成されていてもよい。 In [Step-420], the second electrode 92 is formed on the entire surface in the same manner as in [Step-120] in Example 1. Then, the second electrode 92 is patterned, and then the insulating layer 80 is formed on the entire surface. After the formation, part of the second electrode 92 may be exposed by patterning the insulating layer 80. In this way, the structure shown in FIG. 8 can be obtained. That is, the insulating layer 80 may be formed on the upper side of the second electrode 92 or may be formed on the lower side.
 得られた電子デバイスの走査透過電子顕微鏡像を図9に示す。走査透過電子顕微鏡像から測定されるコンタクト層74を構成する結晶の1ユニットにおけるx軸に沿った長さ(具体的には、a軸に沿った長さ)をxC’、z軸に沿った長さ(具体的には、c軸に沿った長さ)zC’は、
C’/2=0.17nm
C’/2=0.31nm
であった。一方、界面層72Aを構成する結晶のx軸に沿った格子定数(具体的には、a軸に沿った格子定数)をx2、z軸に沿った格子定数(具体的には、c軸に沿った格子定数)z2は、
2/2 =0.17nm
2/2 =0.27nm
であった。即ち、
(zC’/xC’)>(z2/x2
を満足している。しかも、コンタクト層74は、第2化合物半導体層72の界面層72Aに対して疑似格子整合している。即ち、コンタクト層74を構成する結晶のx軸に沿った格子定数をxC、z軸に沿った格子定数をzCとしたとき、
2=xC’<xC
C’>zC
を満足している。
A scanning transmission electron microscope image of the obtained electronic device is shown in FIG. The length along the x-axis (specifically, the length along the a-axis) in one unit of the crystal constituting the contact layer 74 measured from the scanning transmission electron microscope image is along x C ′ and z-axis. Z c ′ (specifically, the length along the c-axis) is
x C '/2=0.17 nm
z C '/2=0.31 nm
Met. On the other hand, the lattice constant (specifically, the lattice constant along the a axis) of the crystal constituting the interface layer 72A is x 2 , and the lattice constant along the z axis (specifically, the c axis). Z 2 is the lattice constant along
x 2/2 = 0.17nm
z 2/2 = 0.27nm
Met. That is,
(Z C '/ x C ')> (z 2 / x 2 )
Is satisfied. In addition, the contact layer 74 is pseudo-lattice matched with the interface layer 72 A of the second compound semiconductor layer 72. That is, when the lattice constant along the x axis of the crystal constituting the contact layer 74 is x C and the lattice constant along the z axis is z C ,
x 2 = x C '<x C
z C '> z C
Is satisfied.
 図7A及び図7Bに示した構造を有する電子デバイスのシリーズ抵抗値と、第2電極92(p側電極)を構成する材料の仕事関数の値との関係のグラフを図10に示す。Ti、Ni/Au、Pdに関しては、従来の半導体レーザ素子と同様に、p型GaN層から成る第2クラッド層上に、Ti、Ni/AuあるいはPdから成る第2電極を形成したときのシリーズ抵抗値である。シリーズ抵抗値と仕事関数の値には相関が見られる。一方、実施例4のコンタクト層74を形成した場合、即ち、2原子層の厚さを有するコンタクト層74を、p型GaNから成る界面層72AとITOから成る第2電極92との間に設けた場合、ITOの仕事関数の値(成膜条件にも依るが、一例として、4.8eV乃至5.0eV)から推測されるシリーズ抵抗値に対して、実際のシリーズ抵抗値は2/3程度に小さくなっている。そして、シリーズ抵抗値の低下、即ち、コンタクト抵抗値の低下によって、電子デバイスの駆動電圧の低減を図ることができる。 FIG. 10 is a graph showing the relationship between the series resistance value of the electronic device having the structure shown in FIGS. 7A and 7B and the work function value of the material constituting the second electrode 92 (p-side electrode). Regarding Ti, Ni / Au, and Pd, a series when a second electrode made of Ti, Ni / Au, or Pd is formed on a second cladding layer made of a p-type GaN layer, as in a conventional semiconductor laser device. Resistance value. There is a correlation between the series resistance value and the work function value. On the other hand, when the contact layer 74 of Example 4 is formed, that is, the contact layer 74 having a thickness of two atomic layers is provided between the interface layer 72A made of p-type GaN and the second electrode 92 made of ITO. In this case, the actual series resistance value is about 2/3 of the series resistance value estimated from the work function value of ITO (for example, 4.8 eV to 5.0 eV, depending on the film formation conditions). It is getting smaller. The drive voltage of the electronic device can be reduced by reducing the series resistance value, that is, the contact resistance value.
 以上のとおり、実施例4の電子デバイスにあっては、コンタクト層と接する第2化合物半導体層の部分である界面層における格子定数と、コンタクト層を構成する結晶の1ユニットにおける長さとが、所定の関係を満足しているが故に、コンタクト層には一種の歪みが発生し、その結果、駆動電圧の低減を図ることができるだけでなく、例えば、ITOといった仕事関数の値の低い材料から第2電極を構成することが可能となり、第2電極を構成する材料の選択自由度を向上させることができる。 As described above, in the electronic device of Example 4, the lattice constant in the interface layer, which is the portion of the second compound semiconductor layer in contact with the contact layer, and the length in one unit of the crystal constituting the contact layer are predetermined. Therefore, a kind of distortion occurs in the contact layer. As a result, not only can the drive voltage be reduced, but also, for example, a material having a low work function value such as ITO can be used. It becomes possible to constitute the electrode, and the degree of freedom of selection of the material constituting the second electrode can be improved.
 実施例5は、実施例4の変形である。実施例5において、積層構造体70は、GaN系化合物半導体から成り、コンタクト層74は、第2化合物半導体層72の界面層72Aを構成するGaN系化合物半導体と異なる組成のGaN系化合物半導体から成る。あるいは又、積層構造体70は、GaN系化合物半導体から成り、コンタクト層74は、ZnO、ZnSe、CdO、CdS及びCdSeから成る群から選択された1種類の材料から成る。尚、コンタクト層74を構成する化合物半導体のバンドギャップエネルギーの値は、第2化合物半導体層72の界面層72Aを構成する化合物半導体のバンドギャップエネルギーの値(GaN:3.4eV)よりも小さい。第2化合物半導体層72の界面層72Aを構成するGaN系化合物半導体(具体的には、GaN)と異なる組成のGaN系化合物半導体として、具体的には、コンタクト層74は、
(a)AlXGaYInZN(但し、X+Y+Z=1,0≦X≦1,0≦Y≦1,0≦Z≦1)から成る構成
(b)AlXGaYInZST(但し、X+Y+Z=1,0≦X≦1,0≦Y≦1,0≦Z≦1,0<S≦1,0<T≦1)から成る構成
(c)AlXGaYInZS1-S(但し、X+Y+Z=1,0≦X≦1,0≦Y≦1,0≦Z≦1,0≦S<1)から成る構成
(d)AlXGaYInZSAs1-S(但し、X+Y+Z=1,0≦X≦1,0≦Y≦1,0≦Z≦1,0≦S<1)から構成
(e)AlXGaYInZSSb1-S(但し、X+Y+Z=1,0≦X≦1,0≦Y≦1,0≦Z≦1,0≦S<1)から成る構成
を挙げることができる。尚、これらの材料のバンドギャップエネルギーの値は、いずれも、例えば、3.3eVと、3.4eVよりも小さい。
The fifth embodiment is a modification of the fourth embodiment. In Example 5, the laminated structure 70 is made of a GaN-based compound semiconductor, and the contact layer 74 is made of a GaN-based compound semiconductor having a composition different from that of the GaN-based compound semiconductor constituting the interface layer 72A of the second compound semiconductor layer 72. . Alternatively, the laminated structure 70 is made of a GaN-based compound semiconductor, and the contact layer 74 is made of one kind of material selected from the group consisting of ZnO, ZnSe, CdO, CdS, and CdSe. The band gap energy value of the compound semiconductor constituting the contact layer 74 is smaller than the band gap energy value (GaN: 3.4 eV) of the compound semiconductor constituting the interface layer 72A of the second compound semiconductor layer 72. As a GaN-based compound semiconductor having a composition different from that of the GaN-based compound semiconductor (specifically, GaN) constituting the interface layer 72A of the second compound semiconductor layer 72, specifically, the contact layer 74 includes:
(A) Al X Ga Y In Z N ( where, X + Y + Z = 1,0 ≦ X ≦ 1,0 ≦ Y ≦ 1,0 ≦ Z ≦ 1) consisting of structure (b) Al X Ga Y In Z N S O T (where X + Y + Z = 1, 0 ≦ X ≦ 1, 0 ≦ Y ≦ 1, 0 ≦ Z ≦ 1, 0 <S ≦ 1, 0 <T ≦ 1) (c) Al X Ga Y In Z N S P 1-S (where, X + Y + Z = 1,0 ≦ X ≦ 1,0 ≦ Y ≦ 1,0 ≦ Z ≦ 1,0 ≦ S <1) consisting of structure (d) Al X Ga Y In Z N S As 1-S (where, X + Y + Z = 1,0 ≦ X ≦ 1,0 ≦ Y ≦ 1,0 ≦ Z ≦ 1,0 ≦ S <1) consists (e) Al X Ga Y In Z N S Sb 1-S (where X + Y + Z = 1, 0 ≦ X ≦ 1, 0 ≦ Y ≦ 1, 0 ≦ Z ≦ 1, 0 ≦ S <1) can be exemplified. In addition, the value of the band gap energy of these materials is all smaller than, for example, 3.3 eV and 3.4 eV.
 以上に説明した実施例5の電子デバイスにおけるコンタクト層74にあっても、
(zC’/xC’)>(z2/x2
を満足していた。しかも、コンタクト層74は、第2化合物半導体層72の界面層72Aに対して疑似格子整合していた。即ち、コンタクト層74を構成する結晶のx軸に沿った格子定数をxC、z軸に沿った格子定数をzCとしたとき、
2=xC’<xC
C’>zC
を満足していた。また、2原子層の厚さを有するコンタクト層74を、p型GaNから成る界面層72AとITOから成る第2電極92との間に設けた場合、ITOの仕事関数の値から推測されるシリーズ抵抗値に対して、実施例5の電子デバイスのシリーズ抵抗値は2/3程度に小さくなっていた。
Even in the contact layer 74 in the electronic device of Example 5 described above,
(Z C '/ x C ')> (z 2 / x 2 )
Was satisfied. In addition, the contact layer 74 is pseudo-lattice matched with the interface layer 72 A of the second compound semiconductor layer 72. That is, when the lattice constant along the x axis of the crystal constituting the contact layer 74 is x C and the lattice constant along the z axis is z C ,
x 2 = x C '<x C
z C '> z C
Was satisfied. Further, when the contact layer 74 having a thickness of two atomic layers is provided between the interface layer 72A made of p-type GaN and the second electrode 92 made of ITO, a series estimated from the work function value of ITO. With respect to the resistance value, the series resistance value of the electronic device of Example 5 was reduced to about 2/3.
 即ち、以上のとおり、実施例5の電子デバイスにあっても、コンタクト層と接する2化合物半導体層の部分である界面層における格子定数と、コンタクト層を構成する結晶の1ユニットにおける長さとが、所定の関係を満足しているが故に、コンタクト層には一種の歪みが発生し、その結果、駆動電圧の低減を図ることができるだけでなく、例えば、ITOといった仕事関数の値の低い材料から第2電極を構成することが可能となり、第2電極を構成する材料の選択自由度を向上させることができる。 That is, as described above, even in the electronic device of Example 5, the lattice constant in the interface layer, which is the portion of the two-compound semiconductor layer in contact with the contact layer, and the length in one unit of the crystals constituting the contact layer are Since the predetermined relationship is satisfied, a kind of distortion occurs in the contact layer. As a result, not only can the drive voltage be reduced, but also a material having a low work function value such as ITO can be used. It becomes possible to constitute two electrodes, and the degree of freedom of selection of the material constituting the second electrode can be improved.
 実施例6は、実施例1の変形であり、第2-Bの構成の電子デバイス等に関する。実施例6の電子デバイスの模式的な一部断面図を図11A及び図11Bに示す。尚、図11A及び図11Bは、図7Bの矢印A-Aに沿ったと同様の模式的な一部断面図であり、導波路構造(共振器構造)の延びる方向に対して垂直な仮想平面で電子デバイスを切断したときの模式的な一部断面図である。 Example 6 is a modification of Example 1 and relates to an electronic device having the configuration 2-B. 11A and 11B are schematic partial cross-sectional views of the electronic device of Example 6. FIG. 11A and 11B are schematic partial sectional views similar to those taken along the arrow AA in FIG. 7B, and are virtual planes perpendicular to the extending direction of the waveguide structure (resonator structure). It is a typical partial sectional view when an electronic device is cut.
 実施例6の電子デバイスにおいて、
 発光・受光層20は、第1導電型を有する第1化合物半導体層71、活性層73、及び、第1導電型とは異なる第2導電型を有する第2化合物半導体層72から成る積層構造体70から成り、
 第1化合物半導体層71上には、コンタクト層75を介して、第1電極91が形成されており、
 コンタクト層75の厚さは、4原子層以下の厚さであり、
 コンタクト層75と第1化合物半導体層71の界面をxy平面、コンタクト層75と接する第1化合物半導体層71の部分である界面層71Aを構成する結晶のx軸に沿った格子定数をx1、z軸に沿った格子定数をz1、コンタクト層75を構成する結晶の1ユニットにおけるx軸に沿った長さをxC”、z軸に沿った長さをzC”としたとき、
(zC”/xC”)>(z1/x1
を満足する。
In the electronic device of Example 6,
The light emitting / receiving layer 20 is a stacked structure including a first compound semiconductor layer 71 having a first conductivity type, an active layer 73, and a second compound semiconductor layer 72 having a second conductivity type different from the first conductivity type. 70
A first electrode 91 is formed on the first compound semiconductor layer 71 via a contact layer 75,
The thickness of the contact layer 75 is a thickness of 4 atomic layers or less,
The interface between the contact layer 75 and the first compound semiconductor layer 71 is the xy plane, and the lattice constant along the x axis of the crystal constituting the interface layer 71A that is the portion of the first compound semiconductor layer 71 in contact with the contact layer 75 is x 1 , When the lattice constant along the z-axis is z 1 , the length along the x-axis in one unit of the crystal constituting the contact layer 75 is x C ″, and the length along the z-axis is z C
(Z C ″ / x C ″)> (z 1 / x 1 )
Satisfied.
 リッジストライプ構造60は、実施例4の電子デバイスにおけるリッジストライプ構造60と同様の構造、構成を有する。ここで、実施例6において、第2電極92は、実施例1の第2電極32と同じ材料から成り、第1電極91は、ITO、Cu、Ti、Al、Ta等から成る。 The ridge stripe structure 60 has the same structure and configuration as the ridge stripe structure 60 in the electronic device of the fourth embodiment. Here, in Example 6, the second electrode 92 is made of the same material as the second electrode 32 of Example 1, and the first electrode 91 is made of ITO, Cu, Ti, Al, Ta, or the like.
 第1化合物半導体層71の界面層71Aを構成する結晶の結晶構造は六方晶系である。また、コンタクト層75を構成する結晶の結晶構造も六方晶系である。積層構造体70は、GaN系化合物半導体から成り、コンタクト層75は、第1化合物半導体層71の界面層71Aを構成するGaN系化合物半導体と同じ組成のGaN系化合物半導体であって、更に、酸素原子を含むGaN系化合物半導体から成る。積層構造体70の組成は、上記の表4に示したと同様である。あるいは又、積層構造体70は、GaN系化合物半導体から成り、コンタクト層75は、第1化合物半導体層71の界面層71Aを構成するGaN系化合物半導体と異なる組成のGaN系化合物半導体から成る。 The crystal structure of the crystal constituting the interface layer 71A of the first compound semiconductor layer 71 is a hexagonal system. The crystal structure of the crystals constituting the contact layer 75 is also hexagonal. The laminated structure 70 is made of a GaN-based compound semiconductor, and the contact layer 75 is a GaN-based compound semiconductor having the same composition as the GaN-based compound semiconductor constituting the interface layer 71A of the first compound semiconductor layer 71, and further oxygen It consists of a GaN-based compound semiconductor containing atoms. The composition of the laminated structure 70 is the same as that shown in Table 4 above. Alternatively, the laminated structure 70 is made of a GaN-based compound semiconductor, and the contact layer 75 is made of a GaN-based compound semiconductor having a composition different from that of the GaN-based compound semiconductor constituting the interface layer 71A of the first compound semiconductor layer 71.
 実施例6の電子デバイスは、実施例4の電子デバイスの製造方法において、[工程-400]でのコンタクト層74の形成を除き、[工程-400]~[工程-410]と同様の工程を実行し、[工程-420]と同様の工程において、全面に絶縁層80を形成し、第2化合物半導体層72の頂面上に位置する絶縁層80の部分を除去する。そして、露出した第2化合物半導体層72の上に第2電極92を形成する(図11A参照)。あるいは又、全面に第2電極92を形成し、第2化合物半導体層72の頂面上に位置する第2電極92の部分を残す。そして、全面に絶縁層80を形成した後、絶縁層80の一部を除去し、第2電極92の一部を露出させてもよい(図11B参照)。その後、第1化合物半導体層71の上の絶縁層80の一部を除去し、第1化合物半導体層71の一部を露出させ、露出した第1化合物半導体層71の上に、コンタクト層75、第1電極91を形成することで、図11に示した構造を得ることができる。その後、実施例4の[工程-430]と同様の工程を実行すればよい。 The electronic device of Example 6 is the same as the [Step-400] to [Step-410] except for the formation of the contact layer 74 in [Step-400] in the electronic device manufacturing method of Example 4. In the same step as [Step-420], the insulating layer 80 is formed on the entire surface, and the portion of the insulating layer 80 located on the top surface of the second compound semiconductor layer 72 is removed. Then, the second electrode 92 is formed on the exposed second compound semiconductor layer 72 (see FIG. 11A). Alternatively, the second electrode 92 is formed on the entire surface, and the portion of the second electrode 92 located on the top surface of the second compound semiconductor layer 72 is left. Then, after the insulating layer 80 is formed on the entire surface, a part of the insulating layer 80 may be removed to expose a part of the second electrode 92 (see FIG. 11B). Thereafter, a part of the insulating layer 80 on the first compound semiconductor layer 71 is removed, a part of the first compound semiconductor layer 71 is exposed, and on the exposed first compound semiconductor layer 71, a contact layer 75, By forming the first electrode 91, the structure shown in FIG. 11 can be obtained. Thereafter, the same step as [Step-430] in Embodiment 4 may be performed.
 以上に説明した実施例6の電子デバイスにおけるコンタクト層75にあっても、
(zC”/xC”)>(z1/x1
を満足していた。しかも、コンタクト層75は、第1化合物半導体層71の界面層71Aに対して疑似格子整合していた。即ち、コンタクト層75を構成する結晶のx軸に沿った格子定数をxC、z軸に沿った格子定数をzCとしたとき、
1=xC”<xC
C”>zC
を満足していた。また、2原子層の厚さを有するコンタクト層75を界面層71Aと第1電極91との間に設けたので、実施例6の電子デバイスのシリーズ抵抗値は充分に小さな値であった。
Even in the contact layer 75 in the electronic device of Example 6 described above,
(Z C ″ / x C ″)> (z 1 / x 1 )
Was satisfied. In addition, the contact layer 75 is pseudo-lattice matched with the interface layer 71 A of the first compound semiconductor layer 71. That is, when the lattice constant along the x axis of the crystal constituting the contact layer 75 is x C and the lattice constant along the z axis is z C ,
x 1 = x C ″ <x C
z C ”> z C
Was satisfied. In addition, since the contact layer 75 having a thickness of two atomic layers was provided between the interface layer 71A and the first electrode 91, the series resistance value of the electronic device of Example 6 was a sufficiently small value.
 即ち、以上のとおり、実施例6の電子デバイスにあっても、コンタクト層と接する第1化合物半導体層の部分である界面層における格子定数と、コンタクト層を構成する結晶の1ユニットにおける長さとが、所定の関係を満足しているが故に、コンタクト層には一種の歪みが発生し、その結果、コンタクト抵抗値の一層の低下を図ることができる。 That is, as described above, even in the electronic device of Example 6, the lattice constant in the interface layer, which is the portion of the first compound semiconductor layer in contact with the contact layer, and the length in one unit of the crystals constituting the contact layer are Since the predetermined relationship is satisfied, a kind of distortion occurs in the contact layer, and as a result, the contact resistance value can be further reduced.
 実施例7は、本開示の固体撮像装置に関する。実施例7の固体撮像装置は、実施例1~実施例3の電子デバイス(具体的には、光電変換素子)を備えている。 Example 7 relates to a solid-state imaging device of the present disclosure. The solid-state imaging apparatus according to the seventh embodiment includes the electronic devices (specifically, photoelectric conversion elements) according to the first to third embodiments.
 図12に、実施例7の固体撮像装置(固体撮像素子)の概念図を示す。実施例7の固体撮像装置100は、半導体基板(例えばシリコン半導体基板)上に、実施例1~実施例3において説明した電子デバイス(光電変換素子)10が2次元アレイ状に配列された撮像領域101、並びに、その周辺回路としての垂直駆動回路102、カラム信号処理回路103、水平駆動回路104、出力回路105及び制御回路106等から構成されている。尚、これらの回路は周知の回路から構成することができるし、また、他の回路構成(例えば、従来のCCD撮像装置やCMOS撮像装置にて用いられる各種の回路)を用いて構成することができることは云うまでもない。 FIG. 12 shows a conceptual diagram of the solid-state imaging device (solid-state imaging device) of Example 7. The solid-state imaging device 100 according to the seventh embodiment includes an imaging region in which the electronic devices (photoelectric conversion elements) 10 described in the first to third embodiments are arranged in a two-dimensional array on a semiconductor substrate (for example, a silicon semiconductor substrate). 101, a vertical drive circuit 102 as a peripheral circuit thereof, a column signal processing circuit 103, a horizontal drive circuit 104, an output circuit 105, a control circuit 106, and the like. Note that these circuits can be configured from well-known circuits, and can be configured using other circuit configurations (for example, various circuits used in conventional CCD imaging devices and CMOS imaging devices). Needless to say, it can be done.
 制御回路106は、垂直同期信号、水平同期信号及びマスタクロックに基づいて、垂直駆動回路102、カラム信号処理回路103及び水平駆動回路104の動作の基準となるクロック信号や制御信号を生成する。そして、生成されたクロック信号や制御信号は、垂直駆動回路102、カラム信号処理回路103及び水平駆動回路104に入力される。 The control circuit 106 generates a clock signal and a control signal that serve as a reference for the operation of the vertical drive circuit 102, the column signal processing circuit 103, and the horizontal drive circuit 104 based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock. The generated clock signal and control signal are input to the vertical drive circuit 102, the column signal processing circuit 103, and the horizontal drive circuit 104.
 垂直駆動回路102は、例えば、シフトレジスタによって構成され、撮像領域101の各電子デバイス10を行単位で順次垂直方向に選択走査する。そして、各電子デバイス10における受光量に応じて生成した電流(信号)に基づく画素信号は、垂直信号線107を介してカラム信号処理回路103に送られる。 The vertical drive circuit 102 is configured by a shift register, for example, and selectively scans each electronic device 10 in the imaging region 101 in the vertical direction sequentially in units of rows. Then, a pixel signal based on a current (signal) generated according to the amount of received light in each electronic device 10 is sent to the column signal processing circuit 103 via the vertical signal line 107.
 カラム信号処理回路103は、例えば、電子デバイス10の列毎に配置されており、1行分の電子デバイス10から出力される信号を電子デバイス10毎に黒基準画素(図示しないが、有効画素領域の周囲に形成される)からの信号によって、ノイズ除去や信号増幅の信号処理を行う。カラム信号処理回路103の出力段には、水平選択スイッチ(図示せず)が水平信号線108との間に接続されて設けられる。 The column signal processing circuit 103 is arranged, for example, for each column of the electronic devices 10, and outputs a signal output from the electronic device 10 for one row for each electronic device 10 with a black reference pixel (not shown, but an effective pixel region). Signal processing for signal removal and signal amplification. At the output stage of the column signal processing circuit 103, a horizontal selection switch (not shown) is connected between the horizontal signal line 108 and provided.
 水平駆動回路104は、例えばシフトレジスタによって構成され、水平走査パルスを順次出力することによって、カラム信号処理回路103の各々を順次選択し、カラム信号処理回路103の各々から信号を水平信号線108に出力する。 The horizontal drive circuit 104 is configured by, for example, a shift register, and sequentially selects each of the column signal processing circuits 103 by sequentially outputting horizontal scanning pulses, and signals from each of the column signal processing circuits 103 are sent to the horizontal signal line 108. Output.
 出力回路105は、カラム信号処理回路103の各々から水平信号線108を介して順次供給される信号に対し、信号処理を行って出力する。 The output circuit 105 performs signal processing on the signals sequentially supplied from each of the column signal processing circuits 103 via the horizontal signal line 108 and outputs the signals.
 発光・受光層を構成する材料にも依るが、発光・受光層それ自体がカラーフィルターとしても機能する構成とすることができるので、カラーフィルターを配設しなくとも色分離が可能である。但し、場合によっては、電子デバイス10の光入射側の上方には、例えば、赤色、緑色、青色、シアン色、マゼンダ色、黄色等の特定波長を透過させる周知のカラーフィルターを配設してもよい。また、固体撮像装置は、表面照射型とすることもできるし、裏面照射型とすることもできる。また、必要に応じて、電子デバイス10への光の入射を制御するためのシャッターを配設してもよい。 Although depending on the material constituting the light emitting / receiving layer, since the light emitting / receiving layer itself can function as a color filter, color separation is possible without providing a color filter. However, in some cases, a known color filter that transmits a specific wavelength such as red, green, blue, cyan, magenta, yellow, or the like may be disposed above the light incident side of the electronic device 10. Good. Further, the solid-state imaging device can be a front-side irradiation type or a back-side irradiation type. Moreover, you may arrange | position the shutter for controlling incidence | injection of the light to the electronic device 10 as needed.
 以上、本開示を好ましい実施例に基づき説明したが、本開示はこれらの実施例に限定されるものではない。実施例にて説明した電子デバイス(光電変換素子)や固体撮像装置、半導体レーザ素子の構造や構成、電子デバイスの製造条件、製造方法、使用した材料は例示であり、適宜変更することができる。実施例4~実施例5において説明した電子デバイスと、実施例6において説明した電子デバイスとを、組み合わせることができる。本開示の電子デバイスを太陽電池として機能させる場合には、第1電極と第2電極との間に電圧を印加しない状態で発光・受光層に光を照射すればよい。また、本開示の電子デバイスによって、テレビカメラ等の撮像装置(固体撮像装置)以外にも、光センサーやイメージセンサーを構成することができる。また、半導体レーザ素子以外にも、電子デバイスとして、その他、スーパールミネッセントダイオード(SLD)、面発光レーザ素子、発光ダイオード(LED)といった半導体発光素子、あるいは、半導体光増幅器とすることもできるし、太陽電池や光センサーとすることもできる。 Although the present disclosure has been described based on the preferred embodiments, the present disclosure is not limited to these embodiments. The structure and configuration of the electronic device (photoelectric conversion element), the solid-state imaging device, and the semiconductor laser element described in the examples, the manufacturing conditions and manufacturing method of the electronic device, and the materials used are examples, and can be changed as appropriate. The electronic device described in Embodiments 4 to 5 and the electronic device described in Embodiment 6 can be combined. When the electronic device of the present disclosure is to function as a solar cell, the light emitting / receiving layer may be irradiated with light without applying a voltage between the first electrode and the second electrode. In addition to an imaging device (solid-state imaging device) such as a television camera, an optical sensor or an image sensor can be configured by the electronic device of the present disclosure. In addition to the semiconductor laser element, as an electronic device, a semiconductor light emitting element such as a super luminescent diode (SLD), a surface emitting laser element, a light emitting diode (LED), or a semiconductor optical amplifier can be used. It can also be a solar cell or a light sensor.
 また、実施例4~実施例6にあっては、リッジストライプ構造60は、直線状に延びている形状としたが、これに限定するものでもないし、一定幅で延びているだけでなく、テーパー状あるいはフレア状としてもよい。具体的には、例えば、光出射端面から光反射端面に向かって、単調に、テーパー状に緩やかに広げられる構成、光出射端面から光反射端面に向かって、先ず広げられ、最大幅を超えた後、狭められる構成とすることができる。 In the fourth to sixth embodiments, the ridge stripe structure 60 has a linearly extending shape, but the present invention is not limited to this. Or flare shape. Specifically, for example, a structure that is monotonously and gradually widened in a tapered manner from the light emitting end face toward the light reflecting end face, first widened from the light emitting end face toward the light reflecting end face, and exceeds the maximum width. After that, it can be configured to be narrowed.
 更には、半導体レーザ素子を、斜め導波路を有する斜めリッジストライプ型の分離閉じ込めヘテロ構造の半導体レーザ素子とすることもできる。このような半導体レーザ素子にあっては、例えば、直線状の2つのリッジストライプ構造が組み合わされた構造を有し、2つのリッジストライプ構造の交差する角度φの値は、例えば、
0<φ≦10(度)
好ましくは、
0<φ≦6(度)
とすることが望ましい。斜めリッジストライプ型を採用することで、無反射コートされた光出射端面の反射率を、より0%の理想値に近づけることができ、その結果、半導体レーザ素子内で周回してしまうレーザ光の発生を防ぐことができ、メインの誘導放出光に付随する副次的な誘導放出光の生成を抑制できるといった利点を得ることができる。
Furthermore, the semiconductor laser element may be a semiconductor laser element having an oblique ridge stripe type separated confinement heterostructure having an oblique waveguide. In such a semiconductor laser element, for example, it has a structure in which two linear ridge stripe structures are combined, and the value of the angle φ at which the two ridge stripe structures intersect is, for example,
0 <φ ≦ 10 (degrees)
Preferably,
0 <φ ≦ 6 (degrees)
Is desirable. By adopting the oblique ridge stripe type, the reflectance of the light emitting end face coated with non-reflective coating can be made closer to the ideal value of 0%, and as a result, the laser light that circulates in the semiconductor laser element can be obtained. Generation | occurrence | production can be prevented and the advantage that generation | occurrence | production of the secondary induced emission light accompanying the main induced emission light can be suppressed can be acquired.
 尚、本開示は、以下のような構成を取ることもできる。
[A01]《電子デバイス》
 発光・受光層、発光・受光層に電気的に接続された第1電極、及び、発光・受光層上に形成された第2電極を備えており、
 第2電極は、インジウムと、ガリウム及び/又はアルミニウムと、亜鉛と、酸素との少なくとも四元系化合物から構成されており、
 発光・受光層は、インジウムと、ガリウム及び/又はアルミニウムと、亜鉛と、酸素との少なくとも四元系化合物から構成された絶縁層によって被覆されており、
 絶縁層における酸素の組成割合は、第2電極における酸素の組成割合よりも高い電子デバイス。
[A02]第2電極は、Ina(Ga,Al)bZncdから成り、
 絶縁層は、Ina(Ga,Al)bZnce(但し、d<e)から成る[A01]に記載の電子デバイス。
[A03]絶縁層及び第2電極は、インジウム-ガリウム酸化物、インジウム・ドープのガリウム-亜鉛酸化物、酸化アルミニウム・ドープの酸化亜鉛、インジウム-亜鉛酸化物、又は、ガリウム・ドープの酸化亜鉛から構成されている[A01]又は[A02]に記載の電子デバイス。
[A04]絶縁層の内部応力は、10MPa乃至90MPaの圧縮応力である[A01]乃至[A03]のいずれか1項に記載の電子デバイス。
[A05]波長400nm乃至660nmの光に対する絶縁層の光透過率は80%以上である[A01]乃至[A04]のいずれか1項に記載の電子デバイス。
[A06]波長400nm乃至660nmの光に対する第2電極の光透過率は75%以上である[A01]乃至[A05]のいずれか1項に記載の電子デバイス。
[A07]第2電極のシート抵抗値は、3×10Ω/□乃至1×103Ω/□である[A01]乃至[A06]のいずれか1項に記載の電子デバイス。
[A08]第2電極及び絶縁層をスパッタリング法に基づき形成する際の酸素ガス分圧を制御することで、第2電極及び絶縁層における酸素の組成割合が制御される[A01]乃至[A07]のいずれか1項に記載の電子デバイス。
[A09]《第1-Aの構成》
 発光・受光層は、第1電極及び第2電極によって挟まれており、
 第2電極の仕事関数の値と第1電極の仕事関数の値との差は0.4eV以上である[A01]乃至[A08]のいずれか1項に記載の電子デバイス。
[B01]第2電極の仕事関数の値と第1電極の仕事関数の値との差を0.4eV以上とすることで、仕事関数の値の差に基づき発光・受光層において内部電界を発生させ、内部量子効率の向上を図る[A09]に記載の電子デバイス。
[A10]《第1-Bの構成》
 発光・受光層は、第1電極及び第2電極によって挟まれており、
 第2電極は、発光・受光層側から、第2B層及び第2A層の積層構造を有し、
 第2電極の第2A層の仕事関数の値は、第2電極の第2B層の仕事関数の値よりも低い[A01]乃至[A08]のいずれか1項に記載の電子デバイス。
[B02]第2電極の第2A層の仕事関数の値と第2電極の第2B層の仕事関数の値との差は、0.1eV乃至0.2eVである[A10]に記載の電子デバイス。
[B03]第1電極の仕事関数の値と第2電極の第2A層の仕事関数の値との差は0.4eV以上である[A10]又は[B02]に記載の電子デバイス。
[B04]第2電極の厚さは1×10-8m乃至1×10-7mであり、
 第2電極の第2A層の厚さと第2電極の第2B層の厚さの割合は9/1乃至1/9である[A10]乃至[B03]のいずれか1項に記載の電子デバイス。
[B05]第1電極の仕事関数の値と第2電極の第2A層の仕事関数の値との差を0.4eV以上とすることで、仕事関数の値の差に基づき発光・受光層において内部電界を発生させ、内部量子効率の向上を図る[A10]乃至[B04]のいずれか1項に記載の電子デバイス。
[B06]第2電極の仕事関数の値は4.1eV乃至4.5eVである[A09]乃至[B05]のいずれか1項に記載の電子デバイス。
[B07]第1電極は、インジウム-スズ酸化物、インジウム-亜鉛酸化物、又は、酸化錫から構成されている[A09]乃至[B06]のいずれか1項に記載の電子デバイス。
[B08]第2電極をスパッタリング法に基づき形成する際の酸素ガス導入量を制御することで、第2電極の仕事関数の値が制御される[A09]乃至[B07]のいずれか1項に記載の電子デバイス。
[B09]酸素の含有率が化学量論組成の酸素含有率よりも少ない[A09]乃至[B08]のいずれか1項に記載の電子デバイス。
[A11]発光・受光層は、有機光電変換材料から成る[A01]乃至[B09]のいずれか1項に記載の電子デバイス。
[A12]光電変換素子から成る[A11]に記載の電子デバイス。
[A13]《第2-Aの構成》
 発光・受光層は、第1導電型を有する第1化合物半導体層、活性層、及び、第1導電型とは異なる第2導電型を有する第2化合物半導体層から成る積層構造体から成り、
 第2化合物半導体層上には、コンタクト層を介して、第2電極が形成されており、
 コンタクト層の厚さは、4原子層以下の厚さであり、
 コンタクト層と第2化合物半導体層の界面をxy平面、コンタクト層と接する第2化合物半導体層の部分である界面層を構成する結晶のx軸に沿った格子定数をx2、z軸に沿った格子定数をz2、コンタクト層を構成する結晶の1ユニットにおけるx軸に沿った長さをxC’、z軸に沿った長さをzC’としたとき、
(zC’/xC’)>(z2/x2
を満足する[A01]乃至[A08]のいずれか1項に記載の電子デバイス。
[C01]コンタクト層は、第2化合物半導体層の界面層に対して疑似格子整合している[A13]に記載の電子デバイス。
[C02]コンタクト層を構成する結晶のx軸に沿った格子定数をxC、z軸に沿った格子定数をzCとしたとき、
2=xC’<xC
C’>zC
を満足する[C01]に記載の電子デバイス。
[C03]第2化合物半導体層の界面層を構成する結晶の結晶構造は六方晶系であり、
 コンタクト層を構成する結晶の結晶構造は六方晶系である[A13]乃至[C02]のいずれか1項に記載の電子デバイス。
[C04]積層構造体は、GaN系化合物半導体から成り、
 コンタクト層は、第2化合物半導体層を構成するGaN系化合物半導体と同じ組成のGaN系化合物半導体であって、更に、酸素原子を含むGaN系化合物半導体から成る[C03]に記載の電子デバイス。
[C05]積層構造体は、GaN系化合物半導体から成り、
 コンタクト層は、第2化合物半導体層を構成するGaN系化合物半導体と異なる組成のGaN系化合物半導体から成る[C03]に記載の電子デバイス。
[C06]積層構造体は、GaN系化合物半導体から成り、
 コンタクト層は、ZnO、ZnSe、CdO、CdS及びCdSeから成る群から選択された1種類の材料から成る[A13]乃至[C02]のいずれか1項に記載の電子デバイス。
[C07]コンタクト層を構成する化合物半導体のバンドギャップエネルギーの値は、第2化合物半導体層の界面層を構成する化合物半導体のバンドギャップエネルギーの値よりも小さい[A13]乃至[C06]のいずれか1項に記載の電子デバイス。
[C08]第1導電型はn型であり、第2導電型はp型である[A13]乃至[C07]のいずれか1項に記載の電子デバイス。
[D01]
 第1化合物半導体層上には、第2のコンタクト層を介して、第1電極が形成されており、
 第2のコンタクト層の厚さは、4原子層以下の厚さであり、
 第2のコンタクト層と第1化合物半導体層の界面をxy平面、第2のコンタクト層と接する第1化合物半導体層の部分である界面層を構成する結晶のx軸に沿った格子定数をx1、z軸に沿った格子定数をz1、第2のコンタクト層を構成する結晶の1ユニットにおけるx軸に沿った長さをxC”、z軸に沿った長さをzC”としたとき、
(zC”/xC”)>(z1/x1
を満足する[A13]乃至[C08]のいずれか1項に記載の電子デバイス。
[D02]第2のコンタクト層は、第1化合物半導体層の界面層に対して疑似格子整合している[D01]に記載の電子デバイス。
[D03]第2のコンタクト層を構成する結晶のx軸に沿った格子定数をxC、z軸に沿った格子定数をzCとしたとき、
1=xC”<xC
C”>zC
を満足する[D02]に記載の電子デバイス。
[D04]第1化合物半導体層の界面層を構成する結晶の結晶構造は六方晶系であり、
 第2のコンタクト層を構成する結晶の結晶構造は六方晶系である[D01]乃至[D03]のいずれか1項に記載の電子デバイス。
[D05]第2のコンタクト層は、第1化合物半導体層を構成するGaN系化合物半導体と同じ組成のGaN系化合物半導体であって、更に、酸素原子を含むGaN系化合物半導体から成る[D04]に記載の電子デバイス。
[D06]第2のコンタクト層は、第1化合物半導体層を構成するGaN系化合物半導体と異なる組成のGaN系化合物半導体から成る[D04]に記載の電子デバイス。
[D07]第2のコンタクト層は、ZnO、ZnSe、CdO、CdS及びCdSeから成る群から選択された1種類の材料から成る[D01]乃至[D03]のいずれか1項に記載の電子デバイス。
[D08]第2のコンタクト層を構成する化合物半導体のバンドギャップエネルギーの値は、第1化合物半導体層の界面層を構成する化合物半導体のバンドギャップエネルギーの値よりも小さい[D01]乃至[D07]のいずれか1項に記載の電子デバイス。
[A14]《第2-Bの構成》
 発光・受光層は、第1導電型を有する第1化合物半導体層、活性層、及び、第1導電型とは異なる第2導電型を有する第2化合物半導体層から成る積層構造体から成り、
 第1化合物半導体層上には、コンタクト層を介して、第1電極が形成されており、
 コンタクト層の厚さは、4原子層以下の厚さであり、
 コンタクト層と第1化合物半導体層の界面をxy平面、コンタクト層と接する第1化合物半導体層の部分である界面層を構成する結晶のx軸に沿った格子定数をx1、z軸に沿った格子定数をz1、コンタクト層を構成する結晶の1ユニットにおけるx軸に沿った長さをxC”、z軸に沿った長さをzC”としたとき、
(zC”/xC”)>(z1/x1
を満足する[A01]乃至[A08]のいずれか1項に記載の電子デバイス。
[E01]コンタクト層は、第1化合物半導体層の界面層に対して疑似格子整合している[A14]に記載の電子デバイス。
[E02]コンタクト層を構成する結晶のx軸に沿った格子定数をxC、z軸に沿った格子定数をzCとしたとき、
1=xC”<xC
C”>zC
を満足する[E01]に記載の電子デバイス。
[E03]第1化合物半導体層の界面層を構成する結晶の結晶構造は六方晶系であり、
 コンタクト層を構成する結晶の結晶構造は六方晶系である[A14]乃至[E02]のいずれか1項に記載の電子デバイス。
[E04]積層構造体は、GaN系化合物半導体から成り、
 コンタクト層は、第1化合物半導体層を構成するGaN系化合物半導体と同じ組成のGaN系化合物半導体であって、更に、酸素原子を含むGaN系化合物半導体から成る[E03]に記載の電子デバイス。
[E05]積層構造体は、GaN系化合物半導体から成り、
 コンタクト層は、第1化合物半導体層を構成するGaN系化合物半導体と異なる組成のGaN系化合物半導体から成る[E03]に記載の電子デバイス。
[E06]積層構造体は、GaN系化合物半導体から成り、
 コンタクト層は、ZnO、ZnSe、CdO、CdS及びCdSeから成る群から選択された1種類の材料から成る[A14]乃至[E02]のいずれか1項に記載の電子デバイス。
[E07]コンタクト層を構成する化合物半導体のバンドギャップエネルギーの値は、第1化合物半導体層の界面層を構成する化合物半導体のバンドギャップエネルギーの値よりも小さい[A14]乃至[E06]のいずれか1項に記載の電子デバイス。
[E08]第1導電型はn型であり、第2導電型はp型である[A14]乃至[E07]のいずれか1項に記載の電子デバイス。
[F01]《固体撮像装置》
 [A01]乃至[A12]のいずれか1項に記載の電子デバイスを備えた固体撮像装置。
[G01]《電子デバイスの製造方法》
 発光・受光層上に、インジウムと、ガリウム及び/又はアルミニウムと、亜鉛と、酸素との少なくとも四元系化合物から構成された第2電極をスパッタリング法に基づき形成し、次いで、
 発光・受光層を、スパッタリング法に基づき、インジウムと、ガリウム及び/又はアルミニウムと、亜鉛と、酸素との少なくとも四元系化合物から構成された絶縁層によって被覆する、
工程を少なくとも含み、
 スパッタリング法に基づき第2電極及び絶縁層を形成する際の酸素ガス分圧を制御することで、絶縁層における酸素の組成割合を第2電極における酸素の組成割合よりも高くする電子デバイスの製造方法。
[G02]絶縁層をスパッタリング法に基づき形成する際の酸素ガス分圧を0.04Pa乃至0.15Paとする[G01]に記載の電子デバイスの製造方法。
[G03]スパッタリング法に基づき絶縁層を形成する際の温度を25゜C乃至28゜Cとする[G01]又は[G02]に記載の電子デバイスの製造方法。
[G04]電子デバイスは光電変換素子を構成する[G01]乃至[G03]のいずれか1項に記載の電子デバイスの製造方法。
[H01]第2電極の仕事関数の値と第1電極の仕事関数の値との差は0.4eV以上であり、
 スパッタリング法に基づき形成する際の酸素ガス導入量を制御することで、第2電極の仕事関数の値を制御する[G01]乃至[G04]のいずれか1項に記載の電子デバイスの製造方法。
[H02]第2電極の仕事関数の値と第1電極の仕事関数の値との差を0.4eV以上とすることで、仕事関数の値の差に基づき発光・受光層において内部電界を発生させ、内部量子効率の向上を図る[H01]に記載の電子デバイスの製造方法。
[H03]第2電極は、発光・受光層側から、第2B層及び第2A層の積層構造を有し、
 第2電極の第2A層の仕事関数の値は、第2電極の第2B層の仕事関数の値よりも低く、
 スパッタリング法に基づき形成する際の酸素ガス導入量を制御することで、第2電極の第2A層及び第2B層の仕事関数の値を制御する[G01]乃至[G04]のいずれか1項に記載の電子デバイスの製造方法。
[H04]第2電極の第2A層の仕事関数の値と第2電極の第2B層の仕事関数の値との差は、0.1eV乃至0.2eVである[H03]に記載の電子デバイスの製造方法。
[H05]第2電極の厚さは1×10-8m乃至1×10-7mであり、
 第2電極の第2A層の厚さと第2電極の第2B層の厚さの割合は9/1乃至1/9である[H03]又は[H04]に記載の電子デバイスの製造方法。
[H06]第1電極の仕事関数の値と第2電極の第2A層の仕事関数の値との差を0.4eV以上とすることで、仕事関数の値の差に基づき発光・受光層において内部電界を発生させ、内部量子効率の向上を図る[H03]乃至[H05]のいずれか1項に記載の電子デバイスの製造方法。
[H07]第2電極において、酸素の含有率は化学量論組成の酸素含有率よりも少ない[H01]乃至[H06]のいずれか1項に記載の電子デバイスの製造方法。
[H08]第2電極の仕事関数の値は4.1eV乃至4.5eVである[H01]乃至[H07]のいずれか1項に記載の電子デバイスの製造方法。
[H09]第1電極は、インジウム-スズ酸化物、インジウム-亜鉛酸化物、又は、酸化錫から構成されている[H01]乃至[H08]のいずれか1項に記載の電子デバイスの製造方法。
[J01]《絶縁材料》
 インジウムと、ガリウム及び/又はアルミニウムと、亜鉛と、酸素との少なくとも四元系化合物から構成された絶縁材料。
[J02]Ina(Ga,Al)bZnceから成る[J01]に記載の絶縁材料。
[J03]インジウム-ガリウム酸化物、インジウム・ドープのガリウム-亜鉛酸化物、酸化アルミニウム・ドープの酸化亜鉛、インジウム-亜鉛酸化物、又は、ガリウム・ドープの酸化亜鉛から成る[J01]又は[J02]に記載の絶縁材料。
[J04]絶縁材料を成膜して得られた絶縁層の内部応力は、10MPa乃至90MPaの圧縮応力である[J01]乃至[J03]のいずれか1項に記載の絶縁材料。
[J05]波長400nm乃至660nmの光に対する光透過率は80%以上である[J01]乃至[J04]のいずれか1項に記載の絶縁材料。
In addition, this indication can also take the following structures.
[A01] << Electronic device >>
A light emitting / receiving layer, a first electrode electrically connected to the light emitting / receiving layer, and a second electrode formed on the light emitting / receiving layer,
The second electrode is composed of at least a quaternary compound of indium, gallium and / or aluminum, zinc, and oxygen,
The light emitting / receiving layer is covered with an insulating layer composed of at least a quaternary compound of indium, gallium and / or aluminum, zinc, and oxygen,
An electronic device in which the composition ratio of oxygen in the insulating layer is higher than the composition ratio of oxygen in the second electrode.
[A02] The second electrode is made of In a (Ga, Al) b Zn c O d ,
The electronic device according to [A01], wherein the insulating layer is made of In a (Ga, Al) b Zn c O e (where d <e).
[A03] The insulating layer and the second electrode are made of indium-gallium oxide, indium-doped gallium-zinc oxide, aluminum oxide-doped zinc oxide, indium-zinc oxide, or gallium-doped zinc oxide. The electronic device according to [A01] or [A02] configured.
[A04] The electronic device according to any one of [A01] to [A03], wherein the internal stress of the insulating layer is a compressive stress of 10 MPa to 90 MPa.
[A05] The electronic device according to any one of [A01] to [A04], wherein the light transmittance of the insulating layer with respect to light having a wavelength of 400 nm to 660 nm is 80% or more.
[A06] The electronic device according to any one of [A01] to [A05], wherein the light transmittance of the second electrode with respect to light having a wavelength of 400 nm to 660 nm is 75% or more.
[A07] The electronic device according to any one of [A01] to [A06], in which a sheet resistance value of the second electrode is 3 × 10Ω / □ to 1 × 10 3 Ω / □.
[A08] The composition ratio of oxygen in the second electrode and the insulating layer is controlled by controlling the oxygen gas partial pressure when forming the second electrode and the insulating layer based on the sputtering method. [A01] to [A07] The electronic device according to any one of the above.
[A09] << Configuration 1-A >>
The light emitting / receiving layer is sandwiched between the first electrode and the second electrode,
The electronic device according to any one of [A01] to [A08], wherein a difference between a work function value of the second electrode and a work function value of the first electrode is 0.4 eV or more.
[B01] By setting the difference between the work function value of the second electrode and the work function value of the first electrode to 0.4 eV or more, an internal electric field is generated in the light emitting / receiving layer based on the difference of the work function values. The electronic device according to [A09], which improves internal quantum efficiency.
[A10] << Configuration 1-B >>
The light emitting / receiving layer is sandwiched between the first electrode and the second electrode,
The second electrode has a laminated structure of the second B layer and the second A layer from the light emitting / receiving layer side,
The electronic device according to any one of [A01] to [A08], in which a work function value of the second A layer of the second electrode is lower than a work function value of the second B layer of the second electrode.
[B02] The electronic device according to [A10], wherein a difference between a work function value of the second A layer of the second electrode and a work function value of the second B layer of the second electrode is 0.1 eV to 0.2 eV. .
[B03] The electronic device according to [A10] or [B02], in which a difference between a work function value of the first electrode and a work function value of the second A layer of the second electrode is 0.4 eV or more.
[B04] The thickness of the second electrode is 1 × 10 −8 m to 1 × 10 −7 m,
The electronic device according to any one of [A10] to [B03], wherein the ratio of the thickness of the second A layer of the second electrode to the thickness of the second B layer of the second electrode is 9/1 to 1/9.
[B05] By setting the difference between the work function value of the first electrode and the work function value of the second A layer of the second electrode to 0.4 eV or more, in the light emitting / receiving layer based on the difference of the work function values The electronic device according to any one of [A10] to [B04], which generates an internal electric field to improve internal quantum efficiency.
[B06] The electronic device according to any one of [A09] to [B05], in which a work function value of the second electrode is 4.1 eV to 4.5 eV.
[B07] The electronic device according to any one of [A09] to [B06], wherein the first electrode is made of indium-tin oxide, indium-zinc oxide, or tin oxide.
[B08] The work function value of the second electrode is controlled by controlling the amount of oxygen gas introduced when the second electrode is formed based on the sputtering method. Any one of [A09] to [B07] The electronic device described.
[B09] The electronic device according to any one of [A09] to [B08], wherein the oxygen content is lower than the oxygen content of the stoichiometric composition.
[A11] The electronic device according to any one of [A01] to [B09], wherein the light emitting / receiving layer is made of an organic photoelectric conversion material.
[A12] The electronic device according to [A11], including a photoelectric conversion element.
[A13] << Configuration 2-A >>
The light emitting / receiving layer is composed of a laminated structure including a first compound semiconductor layer having a first conductivity type, an active layer, and a second compound semiconductor layer having a second conductivity type different from the first conductivity type,
A second electrode is formed on the second compound semiconductor layer via a contact layer,
The thickness of the contact layer is a thickness of 4 atomic layers or less,
The interface between the contact layer and the second compound semiconductor layer is along the xy plane, and the lattice constant along the x axis of the crystal constituting the interface layer that is the portion of the second compound semiconductor layer in contact with the contact layer is along the x 2 and z axes. When the lattice constant is z 2 , the length along the x-axis in one unit of the crystal constituting the contact layer is x C ′, and the length along the z-axis is z C ′,
(Z C '/ x C ')> (z 2 / x 2 )
[A01] to [A08] according to any one of [A01] to [A08].
[C01] The electronic device according to [A13], wherein the contact layer is pseudo-lattice matched with the interface layer of the second compound semiconductor layer.
[C02] When the lattice constant along the x-axis of the crystal constituting the contact layer is x C and the lattice constant along the z-axis is z C ,
x 2 = x C '<x C
z C '> z C
The electronic device according to [C01], wherein:
[C03] The crystal structure of the crystal constituting the interface layer of the second compound semiconductor layer is a hexagonal system,
The electronic device according to any one of [A13] to [C02], in which a crystal structure of a crystal forming the contact layer is a hexagonal system.
[C04] The laminated structure is made of a GaN-based compound semiconductor,
The electronic device according to [C03], wherein the contact layer is a GaN-based compound semiconductor having the same composition as that of the GaN-based compound semiconductor constituting the second compound semiconductor layer, and further includes a GaN-based compound semiconductor containing oxygen atoms.
[C05] The laminated structure is made of a GaN-based compound semiconductor,
The electronic device according to [C03], wherein the contact layer is made of a GaN-based compound semiconductor having a composition different from that of the GaN-based compound semiconductor constituting the second compound semiconductor layer.
[C06] The laminated structure is composed of a GaN-based compound semiconductor,
The electronic device according to any one of [A13] to [C02], wherein the contact layer is made of one material selected from the group consisting of ZnO, ZnSe, CdO, CdS, and CdSe.
[C07] The band gap energy value of the compound semiconductor constituting the contact layer is any of [A13] to [C06] smaller than the band gap energy value of the compound semiconductor constituting the interface layer of the second compound semiconductor layer. The electronic device according to Item 1.
[C08] The electronic device according to any one of [A13] to [C07], in which the first conductivity type is n-type and the second conductivity type is p-type.
[D01]
A first electrode is formed on the first compound semiconductor layer via a second contact layer,
The thickness of the second contact layer is a thickness of 4 atomic layers or less,
The interface between the second contact layer and the first compound semiconductor layer is the xy plane, and the lattice constant along the x axis of the crystal constituting the interface layer that is the portion of the first compound semiconductor layer in contact with the second contact layer is x 1. , The lattice constant along the z-axis is z 1 , the length along the x-axis in one unit of the crystal constituting the second contact layer is x C ″, and the length along the z-axis is z C ″. When
(Z C ″ / x C ″)> (z 1 / x 1 )
The electronic device according to any one of [A13] to [C08] that satisfies the above.
[D02] The electronic device according to [D01], in which the second contact layer is pseudo-lattice matched with the interface layer of the first compound semiconductor layer.
[D03] When the lattice constant along the x-axis of the crystal constituting the second contact layer is x C and the lattice constant along the z-axis is z C ,
x 1 = x C ″ <x C
z C ”> z C
The electronic device according to [D02], which satisfies:
[D04] The crystal structure of the crystal constituting the interface layer of the first compound semiconductor layer is a hexagonal system,
The electronic device according to any one of [D01] to [D03], in which a crystal structure of a crystal forming the second contact layer is a hexagonal system.
[D05] The second contact layer is a GaN-based compound semiconductor having the same composition as that of the GaN-based compound semiconductor constituting the first compound semiconductor layer, and further includes a GaN-based compound semiconductor containing oxygen atoms. The electronic device described.
[D06] The electronic device according to [D04], in which the second contact layer is formed of a GaN-based compound semiconductor having a composition different from that of the GaN-based compound semiconductor constituting the first compound semiconductor layer.
[D07] The electronic device according to any one of [D01] to [D03], in which the second contact layer is made of one material selected from the group consisting of ZnO, ZnSe, CdO, CdS, and CdSe.
[D08] The value of the band gap energy of the compound semiconductor constituting the second contact layer is smaller than the value of the band gap energy of the compound semiconductor constituting the interface layer of the first compound semiconductor layer [D01] to [D07]. The electronic device according to any one of the above.
[A14] << Configuration 2-B >>
The light emitting / receiving layer is composed of a laminated structure including a first compound semiconductor layer having a first conductivity type, an active layer, and a second compound semiconductor layer having a second conductivity type different from the first conductivity type,
A first electrode is formed on the first compound semiconductor layer via a contact layer,
The thickness of the contact layer is a thickness of 4 atomic layers or less,
The interface between the contact layer and the first compound semiconductor layer is along the xy plane, and the lattice constant along the x axis of the crystal constituting the interface layer that is the portion of the first compound semiconductor layer in contact with the contact layer is along the x 1 and z axes. When the lattice constant is z 1 , the length along the x-axis in one unit of the crystal constituting the contact layer is x C ″, and the length along the z-axis is z C
(Z C ″ / x C ″)> (z 1 / x 1 )
[A01] to [A08] according to any one of [A01] to [A08].
[E01] The electronic device according to [A14], wherein the contact layer is pseudo-lattice matched with the interface layer of the first compound semiconductor layer.
[E02] When the lattice constant along the x-axis of the crystal constituting the contact layer is x C and the lattice constant along the z-axis is z C ,
x 1 = x C ″ <x C
z C ”> z C
The electronic device according to [E01], wherein:
[E03] The crystal structure of the crystal constituting the interface layer of the first compound semiconductor layer is a hexagonal system,
The electronic device according to any one of [A14] to [E02], wherein a crystal structure of a crystal forming the contact layer is a hexagonal system.
[E04] The laminated structure is made of a GaN-based compound semiconductor,
The electronic device according to [E03], wherein the contact layer is a GaN-based compound semiconductor having the same composition as the GaN-based compound semiconductor constituting the first compound semiconductor layer, and further includes a GaN-based compound semiconductor containing oxygen atoms.
[E05] The laminated structure is made of a GaN-based compound semiconductor,
The electronic device according to [E03], wherein the contact layer is made of a GaN-based compound semiconductor having a composition different from that of the GaN-based compound semiconductor constituting the first compound semiconductor layer.
[E06] The laminated structure is composed of a GaN-based compound semiconductor,
The electronic device according to any one of [A14] to [E02], wherein the contact layer is made of one material selected from the group consisting of ZnO, ZnSe, CdO, CdS, and CdSe.
[E07] The band gap energy value of the compound semiconductor constituting the contact layer is any of [A14] to [E06] smaller than the band gap energy value of the compound semiconductor constituting the interface layer of the first compound semiconductor layer. The electronic device according to Item 1.
[E08] The electronic device according to any one of [A14] to [E07], wherein the first conductivity type is an n-type and the second conductivity type is a p-type.
[F01] << Solid-state imaging device >>
A solid-state imaging device comprising the electronic device according to any one of [A01] to [A12].
[G01] << Method for Manufacturing Electronic Device >>
A second electrode composed of at least a quaternary compound of indium, gallium and / or aluminum, zinc, and oxygen is formed on the light emitting / receiving layer based on a sputtering method;
The light emitting / receiving layer is covered with an insulating layer composed of at least a quaternary compound of indium, gallium and / or aluminum, zinc, and oxygen based on a sputtering method.
Including at least a step,
A method for manufacturing an electronic device, wherein the oxygen composition ratio in the insulating layer is made higher than the oxygen composition ratio in the second electrode by controlling the oxygen gas partial pressure when forming the second electrode and the insulating layer based on the sputtering method. .
[G02] The method for manufacturing an electronic device according to [G01], in which an oxygen gas partial pressure when forming the insulating layer based on a sputtering method is set to 0.04 Pa to 0.15 Pa.
[G03] The method for manufacturing an electronic device according to [G01] or [G02], wherein a temperature at which the insulating layer is formed based on a sputtering method is set to 25 ° C. to 28 ° C.
[G04] The electronic device manufacturing method according to any one of [G01] to [G03], in which the electronic device constitutes a photoelectric conversion element.
[H01] The difference between the work function value of the second electrode and the work function value of the first electrode is 0.4 eV or more,
The method for manufacturing an electronic device according to any one of [G01] to [G04], wherein the work function value of the second electrode is controlled by controlling the amount of oxygen gas introduced when forming based on a sputtering method.
[H02] By setting the difference between the work function value of the second electrode and the work function value of the first electrode to 0.4 eV or more, an internal electric field is generated in the light emitting / receiving layer based on the difference of the work function values. The method for manufacturing an electronic device according to [H01], which improves internal quantum efficiency.
[H03] The second electrode has a laminated structure of the second B layer and the second A layer from the light emitting / receiving layer side,
The work function value of layer 2A of the second electrode is lower than the work function value of layer 2B of the second electrode,
By controlling the amount of oxygen gas introduced when forming based on the sputtering method, the work function values of the second A layer and the second B layer of the second electrode are controlled. Any one of [G01] to [G04] The manufacturing method of the electronic device of description.
[H04] The electronic device according to [H03], wherein the difference between the work function value of the second electrode 2A layer and the work function value of the second electrode layer 2B is 0.1 eV to 0.2 eV. Manufacturing method.
[H05] The thickness of the second electrode is 1 × 10 −8 m to 1 × 10 −7 m,
The method of manufacturing an electronic device according to [H03] or [H04], wherein the ratio of the thickness of the second electrode 2A layer to the thickness of the second electrode layer 2B is 9/1 to 1/9.
[H06] By setting the difference between the work function value of the first electrode and the work function value of the second electrode 2A layer to 0.4 eV or more, in the light emitting / receiving layer based on the work function value difference. The method for manufacturing an electronic device according to any one of [H03] to [H05], wherein an internal electric field is generated to improve internal quantum efficiency.
[H07] The method for manufacturing an electronic device according to any one of [H01] to [H06], wherein the oxygen content in the second electrode is smaller than the oxygen content in the stoichiometric composition.
[H08] The method of manufacturing an electronic device according to any one of [H01] to [H07], in which a work function value of the second electrode is 4.1 eV to 4.5 eV.
[H09] The method for manufacturing an electronic device according to any one of [H01] to [H08], wherein the first electrode is made of indium-tin oxide, indium-zinc oxide, or tin oxide.
[J01] << Insulating material >>
An insulating material composed of at least a quaternary compound of indium, gallium and / or aluminum, zinc, and oxygen.
[J02] The insulating material according to [J01], which is made of In a (Ga, Al) b Zn c O e .
[J03] [J01] or [J02] composed of indium-gallium oxide, indium-doped gallium-zinc oxide, aluminum oxide-doped zinc oxide, indium-zinc oxide, or gallium-doped zinc oxide Insulating material described in 1.
[J04] The insulating material according to any one of [J01] to [J03], wherein the internal stress of the insulating layer obtained by forming the insulating material is a compressive stress of 10 MPa to 90 MPa.
[J05] The insulating material according to any one of [J01] to [J04], which has a light transmittance of 80% or more for light having a wavelength of 400 nm to 660 nm.
10・・・電子デバイス、11・・・基板、12・・・配線、13・・・層間絶縁膜、14・・・開口部、20・・・発光・受光層、31,91・・・第1電極、32,92・・・第2電極、32A・・・第2電極の第2A層、32B・・・第2電極の第2B層、40,80・・・絶縁層、51・・・GaN基板、52・・・バッファ層、60・・・リッジストライプ構造、61・・・光出射端面(第1端面)、62・・・光反射端面(第2端面)、70・・・積層構造体、71・・・第1化合物半導体層、71A・・・第1化合物半導体層の界面層、72・・・第2化合物半導体層、72A・・・第2化合物半導体層の界面層、73・・・活性層、74,75・・・コンタクト層、100・・・固体撮像装置、101・・・撮像領域、102・・・垂直駆動回路、103・・・カラム信号処理回路、104・・・水平駆動回路、105・・・出力回路、106・・・制御回路、107・・・垂直信号線、108・・・水平信号線 DESCRIPTION OF SYMBOLS 10 ... Electronic device, 11 ... Board | substrate, 12 ... Wiring, 13 ... Interlayer insulation film, 14 ... Opening part, 20 ... Light emitting / light-receiving layer, 31 and 91 ... 1st 1 electrode, 32, 92 ... 2nd electrode, 32A ... 2nd A layer of 2nd electrode, 32B ... 2nd B layer of 2nd electrode, 40, 80 ... insulating layer, 51 ... GaN substrate, 52 ... buffer layer, 60 ... ridge stripe structure, 61 ... light emitting end face (first end face), 62 ... light reflecting end face (second end face), 70 ... laminated structure 71, the first compound semiconductor layer, 71 A, the interface layer of the first compound semiconductor layer, 72, the second compound semiconductor layer, 72 A, the interface layer of the second compound semiconductor layer, 73. ..Active layer, 74, 75... Contact layer, 100... Solid imaging device, 101. ... Vertical drive circuit, 103 ... Column signal processing circuit, 104 ... Horizontal drive circuit, 105 ... Output circuit, 106 ... Control circuit, 107 ... Vertical signal line, 108 ... Horizontal signal line

Claims (20)

  1.  発光・受光層、発光・受光層に電気的に接続された第1電極、及び、発光・受光層上に形成された第2電極を備えており、
     第2電極は、インジウムと、ガリウム及び/又はアルミニウムと、亜鉛と、酸素との少なくとも四元系化合物から構成されており、
     発光・受光層は、インジウムと、ガリウム及び/又はアルミニウムと、亜鉛と、酸素との少なくとも四元系化合物から構成された絶縁層によって被覆されており、
     絶縁層における酸素の組成割合は、第2電極における酸素の組成割合よりも高い電子デバイス。
    A light emitting / receiving layer, a first electrode electrically connected to the light emitting / receiving layer, and a second electrode formed on the light emitting / receiving layer,
    The second electrode is composed of at least a quaternary compound of indium, gallium and / or aluminum, zinc, and oxygen,
    The light emitting / receiving layer is covered with an insulating layer composed of at least a quaternary compound of indium, gallium and / or aluminum, zinc, and oxygen,
    An electronic device in which the composition ratio of oxygen in the insulating layer is higher than the composition ratio of oxygen in the second electrode.
  2.  第2電極は、Ina(Ga,Al)bZncdから成り、
     絶縁層は、Ina(Ga,Al)bZnce(但し、d<e)から成る請求項1に記載の電子デバイス。
    The second electrode is made of In a (Ga, Al) b Zn c O d ,
    The electronic device according to claim 1, wherein the insulating layer is made of In a (Ga, Al) b Zn c O e (where d <e).
  3.  絶縁層及び第2電極は、インジウム-ガリウム酸化物、インジウム・ドープのガリウム-亜鉛酸化物、酸化アルミニウム・ドープの酸化亜鉛、インジウム-亜鉛酸化物、又は、ガリウム・ドープの酸化亜鉛から構成されている請求項1に記載の電子デバイス。 The insulating layer and the second electrode are composed of indium-gallium oxide, indium-doped gallium-zinc oxide, aluminum oxide-doped zinc oxide, indium-zinc oxide, or gallium-doped zinc oxide. The electronic device according to claim 1.
  4.  絶縁層の内部応力は、10MPa乃至90MPaの圧縮応力である請求項1に記載の電子デバイス。 2. The electronic device according to claim 1, wherein the internal stress of the insulating layer is a compressive stress of 10 MPa to 90 MPa.
  5.  波長400nm乃至660nmの光に対する絶縁層の光透過率は80%以上である請求項1に記載の電子デバイス。 The electronic device according to claim 1, wherein the light transmittance of the insulating layer with respect to light having a wavelength of 400 nm to 660 nm is 80% or more.
  6.  波長400nm乃至660nmの光に対する第2電極の光透過率は75%以上である請求項1に記載の電子デバイス。 The electronic device according to claim 1, wherein the light transmittance of the second electrode with respect to light having a wavelength of 400 nm to 660 nm is 75% or more.
  7.  第2電極のシート抵抗値は、3×10Ω/□乃至1×103Ω/□である請求項1に記載の電子デバイス。 The electronic device according to claim 1, wherein the sheet resistance value of the second electrode is 3 × 10 Ω / □ to 1 × 10 3 Ω / □.
  8.  第2電極及び絶縁層をスパッタリング法に基づき形成する際の酸素ガス分圧を制御することで、第2電極及び絶縁層における酸素の組成割合が制御される請求項1に記載の電子デバイス。 2. The electronic device according to claim 1, wherein the composition ratio of oxygen in the second electrode and the insulating layer is controlled by controlling an oxygen gas partial pressure when forming the second electrode and the insulating layer based on a sputtering method.
  9.  発光・受光層は、第1電極及び第2電極によって挟まれており、
     第2電極の仕事関数の値と第1電極の仕事関数の値との差は0.4eV以上である請求項1に記載の電子デバイス。
    The light emitting / receiving layer is sandwiched between the first electrode and the second electrode,
    The electronic device according to claim 1, wherein a difference between a work function value of the second electrode and a work function value of the first electrode is 0.4 eV or more.
  10.  発光・受光層は、第1電極及び第2電極によって挟まれており、
     第2電極は、発光・受光層側から、第2B層及び第2A層の積層構造を有し、
     第2電極の第2A層の仕事関数の値は、第2電極の第2B層の仕事関数の値よりも低い請求項1に記載の電子デバイス。
    The light emitting / receiving layer is sandwiched between the first electrode and the second electrode,
    The second electrode has a laminated structure of the second B layer and the second A layer from the light emitting / receiving layer side,
    2. The electronic device according to claim 1, wherein the work function value of the second A layer of the second electrode is lower than the work function value of the second B layer of the second electrode.
  11.  発光・受光層は、有機光電変換材料から成る請求項1に記載の電子デバイス。 The electronic device according to claim 1, wherein the light emitting / receiving layer is made of an organic photoelectric conversion material.
  12.  光電変換素子から成る請求項11に記載の電子デバイス。 The electronic device according to claim 11, comprising a photoelectric conversion element.
  13.  発光・受光層は、第1導電型を有する第1化合物半導体層、活性層、及び、第1導電型とは異なる第2導電型を有する第2化合物半導体層から成る積層構造体から成り、
     第2化合物半導体層上には、コンタクト層を介して、第2電極が形成されており、
     コンタクト層の厚さは、4原子層以下の厚さであり、
     コンタクト層と第2化合物半導体層の界面をxy平面、コンタクト層と接する第2化合物半導体層の部分である界面層を構成する結晶のx軸に沿った格子定数をx2、z軸に沿った格子定数をz2、コンタクト層を構成する結晶の1ユニットにおけるx軸に沿った長さをxC’、z軸に沿った長さをzC’としたとき、
    (zC’/xC’)>(z2/x2
    を満足する請求項1に記載の電子デバイス。
    The light emitting / receiving layer is composed of a laminated structure including a first compound semiconductor layer having a first conductivity type, an active layer, and a second compound semiconductor layer having a second conductivity type different from the first conductivity type,
    A second electrode is formed on the second compound semiconductor layer via a contact layer,
    The thickness of the contact layer is a thickness of 4 atomic layers or less,
    The interface between the contact layer and the second compound semiconductor layer is along the xy plane, and the lattice constant along the x axis of the crystal constituting the interface layer that is the portion of the second compound semiconductor layer in contact with the contact layer is along the x 2 and z axes. When the lattice constant is z 2 , the length along the x-axis in one unit of the crystal constituting the contact layer is x C ′, and the length along the z-axis is z C ′,
    (Z C '/ x C ')> (z 2 / x 2 )
    The electronic device according to claim 1, wherein:
  14.  発光・受光層は、第1導電型を有する第1化合物半導体層、活性層、及び、第1導電型とは異なる第2導電型を有する第2化合物半導体層から成る積層構造体から成り、
     第1化合物半導体層上には、コンタクト層を介して、第1電極が形成されており、
     コンタクト層の厚さは、4原子層以下の厚さであり、
     コンタクト層と第1化合物半導体層の界面をxy平面、コンタクト層と接する第1化合物半導体層の部分である界面層を構成する結晶のx軸に沿った格子定数をx1、z軸に沿った格子定数をz1、コンタクト層を構成する結晶の1ユニットにおけるx軸に沿った長さをxC”、z軸に沿った長さをzC”としたとき、
    (zC”/xC”)>(z1/x1
    を満足する請求項1に記載の電子デバイス。
    The light emitting / receiving layer is composed of a laminated structure including a first compound semiconductor layer having a first conductivity type, an active layer, and a second compound semiconductor layer having a second conductivity type different from the first conductivity type,
    A first electrode is formed on the first compound semiconductor layer via a contact layer,
    The thickness of the contact layer is a thickness of 4 atomic layers or less,
    The interface between the contact layer and the first compound semiconductor layer is along the xy plane, and the lattice constant along the x axis of the crystal constituting the interface layer that is the portion of the first compound semiconductor layer in contact with the contact layer is along the x 1 and z axes. When the lattice constant is z 1 , the length along the x-axis in one unit of the crystal constituting the contact layer is x C ″, and the length along the z-axis is z C
    (Z C ″ / x C ″)> (z 1 / x 1 )
    The electronic device according to claim 1, wherein:
  15.  請求項1乃至請求項12のいずれか1項に記載の電子デバイスを備えた固体撮像装置。 A solid-state imaging device comprising the electronic device according to any one of claims 1 to 12.
  16.  発光・受光層上に、インジウムと、ガリウム及び/又はアルミニウムと、亜鉛と、酸素との少なくとも四元系化合物から構成された第2電極をスパッタリング法に基づき形成し、次いで、
     発光・受光層を、スパッタリング法に基づき、インジウムと、ガリウム及び/又はアルミニウムと、亜鉛と、酸素との少なくとも四元系化合物から構成された絶縁層によって被覆する、
    工程を少なくとも含み、
     スパッタリング法に基づき第2電極及び絶縁層を形成する際の酸素ガス分圧を制御することで、絶縁層における酸素の組成割合を第2電極における酸素の組成割合よりも高くする電子デバイスの製造方法。
    A second electrode composed of at least a quaternary compound of indium, gallium and / or aluminum, zinc, and oxygen is formed on the light emitting / receiving layer based on a sputtering method;
    The light emitting / receiving layer is covered with an insulating layer composed of at least a quaternary compound of indium, gallium and / or aluminum, zinc, and oxygen based on a sputtering method.
    Including at least a step,
    A method for manufacturing an electronic device, wherein the oxygen composition ratio in the insulating layer is made higher than the oxygen composition ratio in the second electrode by controlling the oxygen gas partial pressure when forming the second electrode and the insulating layer based on the sputtering method. .
  17.  絶縁層をスパッタリング法に基づき形成する際の酸素ガス分圧を0.04Pa乃至0.15Paとする請求項16に記載の電子デバイスの製造方法。 The method for manufacturing an electronic device according to claim 16, wherein an oxygen gas partial pressure when forming the insulating layer based on a sputtering method is 0.04 Pa to 0.15 Pa.
  18.  スパッタリング法に基づき絶縁層を形成する際の温度を22゜C乃至28゜Cとする請求項16に記載の電子デバイスの製造方法。 The method for manufacturing an electronic device according to claim 16, wherein a temperature at which the insulating layer is formed based on a sputtering method is set to 22 ° C to 28 ° C.
  19.  電子デバイスは光電変換素子を構成する請求項16に記載の電子デバイスの製造方法。 The electronic device manufacturing method according to claim 16, wherein the electronic device constitutes a photoelectric conversion element.
  20.  インジウムと、ガリウム及び/又はアルミニウムと、亜鉛と、酸素との少なくとも四元系化合物から構成された絶縁材料。 An insulating material composed of at least a quaternary compound of indium, gallium and / or aluminum, zinc, and oxygen.
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