WO2016004645A1 - Procédé, système et appareil de synchronisation d'horloge ieee1588 sur la base d'une liaison e1 - Google Patents

Procédé, système et appareil de synchronisation d'horloge ieee1588 sur la base d'une liaison e1 Download PDF

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Publication number
WO2016004645A1
WO2016004645A1 PCT/CN2014/082620 CN2014082620W WO2016004645A1 WO 2016004645 A1 WO2016004645 A1 WO 2016004645A1 CN 2014082620 W CN2014082620 W CN 2014082620W WO 2016004645 A1 WO2016004645 A1 WO 2016004645A1
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WIPO (PCT)
Prior art keywords
conversion device
clock
link
delay
link delay
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PCT/CN2014/082620
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English (en)
Chinese (zh)
Inventor
尹二飞
薛百华
张洪雁
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北京东土科技股份有限公司
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Publication of WO2016004645A1 publication Critical patent/WO2016004645A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter

Definitions

  • FIG. 1 is a structural diagram of transmitting a PTP 4 packet carrying an Ethernet bearer on a Synchronous Digital Hierarchy (SDH) network in the prior art, and the master clock device transmits a PTP packet to the slave clock device through the SDH network.
  • An Ethernet and E1 conversion device is added to the transmission link, and the primary clock device transmits the PTP message to the Ethernet and E1 conversion device, and the device converts the PTP message into an E1 message through the SDH network.
  • the E1 packet is converted into a PTP packet and sent to the slave clock device, so that the clock synchronization message sent by the corresponding clock device passes through a process similar to the above process. Transfer to the master clock device.
  • FIG. 2 is a specific structural diagram of clock synchronization based on an E1 link in the prior art, and FIG. 2 is basically similar to FIG. 1.
  • a PTP packet is transmitted in an SDH network
  • the timestamp in the PTP packet is in and out of the Ethernet.
  • the master the PHY from the clock device is tagged.
  • the master-slave clock device performs clock synchronization, it needs to ensure the link delay from the master clock device to the slave clock device, and the link delay from the slave clock device to the master clock device.
  • the clock synchronization packet is converted into an Ethernet packet, the clock synchronization report is used.
  • the text can be sent immediately, and the data transmission rate of the E1 link is slow.
  • the clock synchronization message After the clock synchronization message is converted into an E1 message, it needs to wait until the time of sending the message, and the waiting time needs to be based on the current E1 chain.
  • the waiting time Depending on the transmission condition of the path, the waiting time is not fixed, so the delay is also called the jitter delay.
  • the jitter delay causes the link delay of the master clock device to the slave clock device to be incompatible with the link delay from the clock device to the master clock device, and the jitter delay cannot be separated from the link delay.
  • An embodiment of the present invention provides an IEEE1588 clock synchronization method based on an E1 link.
  • the first conversion device maintains clock synchronization with the master clock device, and the second conversion device synchronizes with the slave clock, the first conversion device and the second conversion device.
  • the method is used to implement conversion between an Ethernet packet and an E1 packet. The method includes:
  • the second switching device determines, according to the time t2 of each timestamp t1 of the plurality of E1 messages, a link delay between the first switching device and the second converting device, where the multiple E1 packets are first
  • the conversion device sends the Sync message sent by the master clock device, and each of the ⁇ 1 ⁇ text carries at least one timestamp tl;
  • the second conversion device receives the link delay of the second conversion device sent by the first conversion device to the first conversion device, where the link delay of the second conversion device to the first conversion device is the first
  • the conversion device is determined according to each timestamp t3 carried in the plurality of E1 messages sent by the second conversion device, and the time t4 of receiving the timestamp t3 of each E1 message;
  • the second converting device causes the slave clock device to delay its own clock according to the determined link delay between the first converting device and the second converting device.
  • the link delay of the first conversion device to send the second conversion device to the first conversion device includes:
  • the second switching device When receiving the Delay_Req message sent from the clock device, the second switching device sends a plurality of E1 messages to the first switching device, and adds at least one timestamp t3 to each corresponding E1 message;
  • the first converting device determines, according to each time t4 of receiving the timestamp t3 in each E1 message, a link delay of the second converting device to the first converting device, and determining the determined second converting device to the first
  • the link delay of the conversion device is sent to the second conversion device.
  • the second conversion device causes the slave clock device to delay the link between the first conversion device and the second conversion device according to the determination.
  • the timing of its own clock includes:
  • the second conversion device adjusts its own clock according to the determined link delay between the first conversion device and the second conversion device, and sends the adjusted clock information to the slave clock device, so that the slave clock device
  • the clock information adjusts its own clock
  • the second conversion device sends the determined link delay between the first conversion device and the second conversion device to the slave clock device, so that the slave clock device delays the link between the first conversion device and the second conversion device. , adjust your own clock.
  • the adjustment of the clock according to the link delay between the first conversion device and the second conversion device includes:
  • the link delay of the backup determines the average link delay
  • the method further includes: the second conversion device and the first conversion device split the clock synchronization into a plurality of small segments, and insert the Transmitted in multiple E1 messages carrying timestamps; or,
  • the second converting device and the first converting device insert information of other messages into a plurality of E1 messages carrying timestamps for transmission.
  • An embodiment of the present invention provides an IEEE 1588 clock synchronization apparatus based on an E1 link, where the apparatus includes: a link delay determination module, configured to receive, according to a time t2 of each timestamp t1 of the plurality of E1 messages, Determining, by the first switching device, the Sync message sent by the master clock device, and sending each of the E1 messages to the first link device, and each of the E1 ⁇ Carry at least one timestamp tl;
  • a receiving module configured to receive a link delay sent by the first switching device to the first switching device, where the link delay of the self to the first switching device is the second converting device according to the second
  • Each timestamp t3 carried in the plurality of E1 packets sent by the switching device, and the time t4 at which the timestamp t3 of each E1 packet is received is determined.
  • the clock synchronization module is configured to enable the slave clock device to time its own clock according to the determined link delay between itself and the second conversion device.
  • the clock synchronization module is specifically configured to perform the clock on the clock according to the determined first conversion device and its own link delay. Adjusting, and transmitting the adjusted clock information to the slave clock device, so that the slave clock device adjusts its own clock according to the clock information; or, sending the determined first conversion device and its own link delay to the slave clock device The slave clock device adjusts its own clock according to the delay of the first switching device and its own link.
  • the clock synchronization module is specifically configured to determine the link delay from the first conversion device to itself, and to the first Converting the link delay of the device to determine an average link delay; determining a time offset between the master clock device and the slave clock device according to the determined link delay of the first conversion device to itself and the average link delay; Time offset, adjust its own clock.
  • the device further includes: a sending module, configured to split the clock synchronization packet into multiple segments and insert the plurality of E1 packets carrying the timestamp The message is sent in the text; or the information of other messages is inserted into multiple E1 messages carrying timestamps.
  • a sending module configured to split the clock synchronization packet into multiple segments and insert the plurality of E1 packets carrying the timestamp The message is sent in the text; or the information of other messages is inserted into multiple E1 messages carrying timestamps.
  • An embodiment of the present invention provides an IEEE1588 clock synchronization method, system, and apparatus based on an E1 link, where a second conversion device that maintains clock synchronization with a slave clock device is configured according to each of a plurality of received E1 messages.
  • Time At time t2 of t1 determining a link delay between the first conversion device and the second conversion device, and receiving a link from the second conversion device to the first conversion device sent by the first conversion device that is synchronized with the main clock.
  • the delay according to the determined link delay between the first conversion device and the second conversion device, causes the slave clock device to time its own clock.
  • the clock is synchronized by the second switching device that is synchronized with the clock, and the switching device adds a timestamp to the incoming and outgoing synchronization packets, and determines the chain by sending multiple time-stamped E1 packets.
  • the delay of the road avoids the influence of delay jitter of the E1 link and improves the accuracy of clock synchronization.
  • FIG. 1 is a structural diagram of a prior art transmission of an Ethernet bearer on an SDH network
  • FIG. 3 is a structural diagram of an IEEE1588 clock synchronization system based on an E1 link according to an embodiment of the present invention
  • FIG. 4 is an E1 link-based IEEE1588 based on the system architecture diagram shown in FIG. 3 according to an embodiment of the present invention
  • Clock synchronization process
  • FIG. 4 is a schematic diagram of an assembly manner of an E1 ⁇ ⁇ ⁇ text according to an embodiment of the present invention
  • 4C is a schematic diagram of another assembly manner of an E1 ⁇ ⁇ ⁇ text according to an embodiment of the present invention.
  • FIG. 5 is a detailed process of an IEEE1588 clock synchronization based on an E1 link according to an embodiment of the present invention
  • FIG. 6 is a structural diagram of an IEEE1588 clock synchronization apparatus based on an E1 link according to an embodiment of the present invention.
  • DETAILED DESCRIPTION OF THE INVENTION In order to avoid the delay caused by the jitter of the E1 link and improve the accuracy of the clock synchronization, the embodiment of the present invention provides an IEEE1588 clock synchronization method, system and device based on the E1 link.
  • FIG. 3 is a structural diagram of an IEEE1588 clock synchronization system based on an E1 link according to an embodiment of the present invention, where the system includes: a master clock device 31, a first Ethernet and E1 conversion device 32, a second Ethernet, and an E1 conversion device. 33 and slave clock device 34.
  • the master clock device 31 maintains clock synchronization with the first Ethernet and E1 conversion device 32
  • the second Ethernet and El conversion device 33 and the slave clock device 34 maintain clock synchronization.
  • a high-precision clock is provided in the first Ethernet and E1 conversion device 32 and the second Ethernet and E1 conversion device 33, by which the high-precision clock is maintained. Synchronize the clock between the conversion device and the master and slave clock devices.
  • the first Ethernet and the E1 conversion device 32 receives the Ethernet packet sent by the master clock device 31, and determines whether the Ethernet packet is a Sync packet. When determining that the Ethernet packet is a Sync packet, the first Ethernet And the E1 conversion device 32 sends a plurality of consecutive E1 messages, and when sending each E1 message, adds at least one timestamp t1 to each E1 message, and each timestamp tl is added with the timestamp. Current time.
  • the second Ethernet and E1 conversion device 33 records the time t2 at which each time stamp t1 in each E1 message is received, and determines the first Ethernet and E1 conversion device 32 according to each pair of corresponding t2 and t1.
  • the link delay of the second Ethernet and E1 conversion device 33 is not limited to
  • the first Ethernet and E1 conversion device 32 converts the received Sync message into multiple The E1 message is sent to the second Ethernet and E1 conversion device 33, and the Sync message is forwarded to the slave clock device 34 via the second Ethernet and E1 conversion device 33.
  • the second Ethernet and E1 conversion device 33 when it is determined that the Delay_Req message transmitted from the clock device 34 is received, transmits a plurality of consecutive E1 messages to the first Ethernet and E1 conversion device 32, and transmits each E1 message.
  • At the time of the text at least one time stamp t3 is added to each E1 4 ⁇ text, and each time stamp t3 is the current time when the time stamp is added.
  • the first Ethernet and E1 conversion device 32 records the time t4 at which each time stamp t3 in each E1 packet is received by the second Ethernet and E1 conversion device 33, and the second is determined according to each pair of corresponding t4 and t3.
  • the link delay between the Ethernet and El conversion device 33 to the first Ethernet and E1 conversion device 32, the first Ethernet and E1 conversion device 32 will determine the second Ethernet and E1 conversion device 33 to the first Ethernet and
  • the link delay of the E1 conversion device 32 is sent to the master clock device 31.
  • the delay_resp message sent by the master clock device 31 is received, the determined second Ethernet and E1 conversion device 33 is converted to the first Ethernet and E1.
  • the link delay of device 32 is sent to the second Ethernet and E1 conversion device 33.
  • the second Ethernet and E1 conversion device 33 causes the slave clock device to time its own clock in accordance with the determined link delay between the first Ethernet and E1 conversion device 32 and the second Ethernet and E1 conversion device 33.
  • the first Ethernet and E1 conversion device and the FPGA of the second Ethernet and E1 conversion device add a time stamp to the E1 4 at the exit of E1.
  • the slave clock device since the clock synchronization is maintained between the clock device and the second Ethernet and the E1 conversion device, the slave clock device may be the second Ethernet and E1 conversion when the clock is clocked by itself. The device adjusts its own clock first, and then adjusts the clock of the slave clock device to itself. Alternatively, the second Ethernet and E1 conversion device sends the corresponding link delay information to the slave clock device, so that the slave clock device can The link delay information adjusts to its own clock.
  • the second conversion device causes the slave clock device to perform a timing delay on the clock according to the determined link delay between the first conversion device and the second conversion device, including:
  • the second conversion device adjusts its own clock according to the determined link delay between the first conversion device and the second conversion device, and sends the adjusted clock information to the slave clock device, so that the slave clock device
  • the clock information adjusts its own clock
  • the second conversion device sends the determined link delay between the first conversion device and the second conversion device to the slave clock device, so that the slave clock device delays the link between the first conversion device and the second conversion device. , adjust your own clock.
  • the adjusted clock information is sent to the second Ethernet and E1 conversion device, and the second Ethernet and E1 conversion device according to the adjusted clock information, Adjust your own clock.
  • FIG. 4A is a schematic diagram of an IEEE1588 clock synchronization process based on an E1 link according to the system architecture diagram shown in FIG. 3 according to the embodiment of the present invention. The process includes the following steps:
  • the first Ethernet and the E1 conversion device receive the Ethernet packet sent by the master clock device, determine whether the Ethernet packet is a Sync packet, and when the determination result is yes, proceed to step S402; otherwise, directly convert the report. Send after the text.
  • the first Ethernet and the E1 conversion device send multiple E1 packets, and when sending each E1 packet, add at least one timestamp t1 to the E1 packet, and each timestamp tl is currently added. The moment of the stamp.
  • the second Ethernet and the E1 conversion device receive the multiple E1 packets sent by the first Ethernet and the E1 conversion device, and determine, according to the time instant of receiving the timestamp tl in each E1 packet, At time t2, the second Ethernet and E1 conversion device determines a link delay between the first Ethernet and the E1 conversion device to the second Ethernet and the E1 conversion device according to the determined plurality of corresponding t2 and 11.
  • step S404 When the second Ethernet and the E1 conversion device receives the Ethernet packet sent by the clock device, determine whether the Ethernet packet is a Delay_Req packet, and if the determination result is yes, proceed to step S405; otherwise, directly convert The 4 ⁇ text is sent after.
  • S405 The second Ethernet and the E1 conversion device send the E1 packet, and when sending each E1 packet, add at least one timestamp t3 to the E1 packet, where each timestamp t3 is currently added. The moment of the stamp.
  • the first Ethernet and the E1 conversion device receive the multiple E1 messages sent by the second Ethernet and the E1 conversion device, and determine, according to the time instant of receiving the timestamp t3 in each E1 message, that each timestamp is received. At time t4, the first Ethernet and E1 conversion device determines a link delay between the second Ethernet and E1 conversion device to the first Ethernet and the E1 conversion device according to the determined plurality of corresponding t4 and t3.
  • the first Ethernet and the E1 conversion device receive the Ethernet packet sent by the master clock, and determine whether the Ethernet packet is a Delay_Resp packet. If the judgment result is yes, proceed to step S407; otherwise, directly convert the packet. Rear Send.
  • the first Ethernet and E1 conversion device sends the determined link delay between the second Ethernet and E1 conversion device to the first Ethernet and the E1 conversion device to the second Ethernet and E1 conversion device.
  • the second Ethernet and E1 conversion device adjusts its own clock according to the determined link delay between the first conversion device and the second conversion device, and sends the adjusted clock information to the slave clock device.
  • the slave clock device adjusts its own clock based on the clock information.
  • the peer in order to reduce the E1 link delay jitter when performing clock synchronization, when the first Ethernet and E1 conversion device and the second Ethernet and E1 conversion device determine that the clock synchronization message is received, The peer sends multiple E1 packets, and carries at least one current timestamp information in each E1 packet sent. To effectively reduce the E1 link delay jitter, multiple E1 packets are sent. continuously.
  • the method further includes:
  • the second conversion device and the first conversion device synchronize clocks, and the plurality of segments are inserted into a plurality of E1 messages carrying a time stamp;
  • the second converting device and the first converting device insert information of other messages into a plurality of E1 messages carrying timestamps for transmission.
  • the remaining bytes of the E1 message used to send the timestamp can be used to send clock synchronization messages, and can also be used to send other Ethernet packets.
  • each E1 packet carries at most 3 timestamps.
  • the E1 packet carries three timestamps, the E1 packet has 7 bytes remaining.
  • the E1 packet carries one or two timestamps, The E1 packet has more bytes than the timestamp. In the embodiment of the present invention, other bytes except the timestamp are used in the E1 packet.
  • the E1 message can be assembled in several forms.
  • Figure 4A a schematic diagram of the assembly mode of the E1 message. After ST0 in the figure, three 8-byte timestamps (origin timestamp) are successively placed, and each timestamp is the time at which the timestamp is currently placed. The remaining 7 bytes are used to transfer other Ethernet data.
  • FIG. 4C another schematic diagram of the assembly mode of the E1 message is followed by an 8-byte timestamp (origin timestamp) followed by two bytes of Ethernet data (data), and then Is an 8-byte timestamp ( origintimestamp ), followed by two bytes of Ethernet data (data ), then an 8-byte timestamp ( origintimestamp ), followed by three-byte Ethernet data (data), thus encapsulating three timestamps into one E1.
  • 8-byte timestamp oil timestamp
  • origintimestamp origintimestamp
  • origintimestamp origintimestamp
  • three-byte Ethernet data data
  • the El message when the El message carries only one timestamp, it is an 8-byte timestamp after ST0, and the next 23 bytes are used to transmit Ethernet data; or E1 4 ⁇ last 8 bytes are time stamps, and the remaining 23 bytes are used to send Ethernet message data and so on.
  • the E1 packet may be assembled in other manners, as long as the position of each time stamp in the packet is fixed.
  • the E1 packet used for carrying the timestamp can also be used for transmitting the Ethernet packet.
  • the Ethernet packet is split into multiple segments, and each segment is inserted into the E1 packet for transmission. If the current E1 packet carries the timestamp information, after the Ethernet packet is inserted, there is still a spare location, and the free location is set to invalid data. For example, when the binary data is used, the spare position is all ones. If the current E1 packet does not carry the timestamp information, after the Ethernet packet is inserted, the location carrying the timestamp information or the location carrying the message information is free, and the vacant location is set to invalid data.
  • the second Ethernet and E1 conversion device determines each timestamp t1 carried in the E1 message, and according to the time t2 of receiving the timestamp t1 carried in each El message, Determining a link delay of the first Ethernet and the El conversion device to the second Ethernet and the E1 conversion device, the first Ethernet and E1 conversion device determining each timestamp t3 carried in the E1 message, and receiving according to At time t4 of the time stamp t3 carried in each El message, the link delay of the second Ethernet and E1 conversion device to the first Ethernet and E1 conversion device can be determined.
  • the determining a link delay of the first converting device to the second converting device includes:
  • the determining a link delay of the second conversion device to the first conversion device includes:
  • the second Ethernet and E1 conversion device will receive multiple timestamps, in order to effectively reduce the E1 link delay jitter to the clock.
  • the effect of synchronization in the embodiment of the invention, when the second Ethernet and E1 conversion device determines the link delay of the first Ethernet and E1 conversion device to the second Ethernet and E1 conversion device, and the first Ethernet and After the E1 conversion device determines the link delay of the second Ethernet and E1 conversion device to the first Ethernet and the E1 conversion device, the thousands of maximum and minimum values in the link delay are removed, and the remaining links are removed.
  • the delay can be considered as the ability to basically reflect the E1 link delay, taking the average of the remaining link delays, which is the chain between the first Ethernet and E1 conversion device and the second Ethernet and E1 conversion device. Road delay.
  • the slave clock counter When the link delay between the first Ethernet and E1 conversion device and the second Ethernet and E1 conversion device is determined, the slave clock counters its own clock including:
  • the first Ethernet and E1 conversion device sends multiple E1 messages to the second Ethernet and E1 conversion device, and carries at least one E1 packet in each E1 message.
  • the timestamp information which carries a total of 2000 timestamps
  • the E1 4 ⁇ text can carry three timestamps, which can carry two timestamps, and can also carry a timestamp.
  • the second Ethernet and E1 conversion device determines 2000 timestamps t2 according to the time when each timestamp is received, the difference between each t2 and tl can determine 2000 delayl, that is, the first Ethernet and E1.
  • the delay of converting the device to the second Ethernet and E1 conversion device removes the largest 20% (400) in 2000 delayl, the smallest 20% (400), based on the average of the remaining 60% delayl, The delay of the first Ethernet and E1 conversion device to the second Ethernet and E1 conversion device is determined.
  • FIG. 5 is a detailed process of the IEEE 1588 clock synchronization based on the E1 link according to an embodiment of the present invention.
  • the Sync message is taken as an example. The process includes the following steps:
  • the second Ethernet and the E1 conversion device receive the E1 packet, and when the E1 packet carries the timestamp, the step S502, the other byte part is performed, and the step is performed for the timestamp byte part of the E1 packet. S504.
  • S503 Determine a time difference t2-tl of each timestamp message, determine each delay, determine thousands of maximum and minimum values in the plurality of delayns, determine an average value of the remaining delay, and use the average as the first ether.
  • the switching device by performing clock synchronization with the second switching device that is synchronized with the clock from the clock, the switching device time stamps the incoming and outgoing synchronization packets, and determines the delay of the link by sending multiple E1 packets. Therefore, the influence of delay jitter of the E1 link is avoided, and the accuracy of clock synchronization is improved.
  • the first Ethernet and E1 conversion device When the first Ethernet and E1 conversion device receives the Ethernet packet sent by the master clock device, according to the type of the packet, when the packet is determined to be a Sync packet in the clock synchronization packet, the first Ethernet and The FPGA in the E1 conversion device sends multiple E1 packets, and carries at least one timestamp tl in each E1 packet, and multiple El packets carry 2000 timestamps tl. And the first Ethernet and El conversion device splits the received Sync message into a plurality of small segments, and inserts each small segment into the E1 ⁇ ⁇ text to send.
  • the second Ethernet and E1 conversion device receives each E1 message sent by the first Ethernet and E1 conversion device, according to
  • each receive timestamp t2 is determined by the FPGA of the second Ethernet and E1 conversion device. For the Ethernet in the ⁇ ⁇ ⁇ • In the ⁇ ⁇ section, the second Ethernet and El conversion device repackages the Ethernet ⁇ section and sends it to its own CPU for processing, and then converts the processed message to the slave clock device.
  • the second Ethernet and E1 conversion device determines the link delay delay of each of the first Ethernet and E1 conversion devices to the second Ethernet and E1 conversion device according to the difference between each pair of transceiver timestamps t2 and 11, second Ethernet and E1 conversion equipment in the obtained 2000 delay, remove the maximum and minimum delay of each of 20%, determine the average of the remaining 1200 delay, the average as the first Ethernet and E1 conversion equipment to the first The link delay delayl of the two Ethernet and E1 conversion devices.
  • the second Ethernet and the El conversion device receive the Ethernet packet sent from the clock device, according to the type of the packet, when the packet is determined to be a Delay_Req packet in the clock synchronization packet, the second Ethernet and the E1 are The FPGA in the conversion device sends multiple E1 packets, and carries at least one timestamp t3 in each E1 packet, and multiple El packets carry 2,000 timestamps t3. And the second Ethernet and E3 conversion device splits the received Delay_Req message into multiple segments, and inserts each '', segment into the E1 message to send.
  • the first Ethernet and the E1 conversion device receive each E1 packet sent by the second Ethernet and the E1 conversion device, and determine whether the E1 packet carries a timestamp according to whether the location of the E1 packet carrying the timestamp is valid data. When it is determined that the E1 packet carries a timestamp, for each timestamp byte portion in the packet, each receiving time is determined by the FPGA of the first Ethernet and E1 conversion device according to the time at which each timestamp is received. Poke t4.
  • the first Ethernet and E1 conversion device determines a link delay delay2n of each second Ethernet and E1 conversion device to the first Ethernet and E1 conversion device according to the difference between each pair of transceiver timestamps t4 and t3, first Ethernet and E1 conversion equipment in the obtained 2000 delay2n, remove the maximum and minimum delay of each 20%, determine the average of the remaining 1200 delay, the average as the second Ethernet and E1 conversion equipment to the first The link delay delay2 of an Ethernet and E1 conversion device.
  • the first Ethernet and the E1 conversion device When the first Ethernet and the E1 conversion device receive the Ethernet packet sent by the master clock device, according to the type of the packet, when the packet is determined to be a Delay_Resp packet in the clock synchronization packet, the first Ethernet and The E1 conversion device transmits the determined link delay delay2 of the second Ethernet and E1 conversion device to the first Ethernet and E1 conversion device to the second Ethernet and E1 conversion device.
  • the second Ethernet and E1 conversion device determines the first Ethernet and E1 conversion device and the second Ethernet and E1 conversion device according to the delayl determined by itself and the average value of delay2 sent by the received first Ethernet and E1 conversion device.
  • the link delay between delays is the first Ethernet and E1 conversion device and the second Ethernet and E1 conversion device according to the delayl determined by itself and the average value of delay2 sent by the received first Ethernet and E1 conversion device. The link delay between delays.
  • the second Ethernet and E1 conversion device determines the link delay delay between the first Ethernet and E1 conversion device and the second Ethernet and E1 conversion device, due to clock synchronization between the own clock and the slave clock device, Clock synchronization between the first Ethernet and E1 conversion device and the master clock setting, so the time between the master clock device and the slave clock device
  • the deviation is the time offset between the first Ethernet and El conversion device and the second Ethernet and El conversion device.
  • the time deviation is the difference between delay 1 and delay, that is, the difference between the link delay and the average link delay between the first conversion device and the second conversion device.
  • the clock is adjusted according to the time offset, and the self-adjusted clock information is sent to the slave clock device, so that the slave clock device adjusts its own clock according to the clock information.
  • the second Ethernet and E1 conversion device determines the link delay delay between the first Ethernet and E1 conversion device and the second Ethernet and E1 conversion device, the first Ethernet and E1 conversion device and the first The link delay delay between the two Ethernet and E1 conversion devices is sent to the slave clock device, and the slave slave device delays the link delay between the first Ethernet and E1 conversion device and the second Ethernet and E1 conversion device, Adjusting its own clock, and since the clock between the slave clock device and the second Ethernet and E1 conversion device remains synchronized, the slave clock device transmits the adjusted clock information to the second Ethernet and E1 conversion device, The second Ethernet and E1 conversion device adjusts its own clock according to the adjusted clock information.
  • FIG. 6 is a structural diagram of an IEEE1588 clock synchronization apparatus based on an E1 link according to an embodiment of the present invention, where the apparatus includes:
  • the link delay determining module 61 is configured to determine, according to the time t2 of each timestamp t1 of the plurality of E1 messages, the link delay of the first switching device to the self, wherein the multiple E1 messages are
  • the first switching device sends the Sync packet sent by the master clock device, and each E1 packet carries at least one timestamp tl;
  • the receiving module 62 is configured to receive a link delay sent by the first switching device to the first switching device, where the link delay of the self to the first switching device is the first converting device according to the first Each timestamp t3 carried in the plurality of E1 messages sent by the second switching device, and the time t4 of receiving the timestamp t3 of each E1 message are determined; the clock synchronization module 63 is configured to enable the slave clock device to determine The link delay between itself and the second switching device, the timing of its own clock.
  • the clock synchronization module 63 is specifically configured to adjust a clock of the first conversion device and its own link delay, and send the adjusted clock information to the slave clock device, so that the slave clock device is configured according to the clock device.
  • the clock information adjusts its own clock; or, the determined first conversion device and its own link delay are sent to the slave clock device, so that the slave clock device delays according to the first conversion device and its own link. The clock is adjusted.
  • the clock synchronization module 63 is specifically configured to determine an average link delay according to the determined link delay of the first conversion device to itself and a link delay of the first conversion device to the first conversion device; Converting the link delay of the device to itself and the average link delay, determining the time offset between the master clock device and the slave clock device; adjusting the clock according to the determined time offset.
  • the device also includes:
  • the sending module 64 is configured to split the clock synchronization packet into multiple small segments, and insert the information into multiple E1 packets carrying the timestamp, or insert the information of other packets into the multiple E1 packets carrying the timestamp. Sent in.
  • the link delay determining module 61 is specifically configured to remove the thousands of maximum and maximum of the determined multiple link delays.
  • the small value determines the link delay of the first conversion device to the second conversion device according to the average value of the link delays after the maximum value and the minimum value are removed.
  • An embodiment of the present invention provides an IEEE1588 clock synchronization method, system, and apparatus based on an E1 link, where a second conversion device that maintains clock synchronization with a slave clock device is configured according to each of a plurality of received E1 messages.
  • a second conversion device that maintains clock synchronization with a slave clock device is configured according to each of a plurality of received E1 messages.
  • determining a link delay between the first conversion device and the second conversion device and receiving a chain of the second conversion device sent by the first conversion device that is synchronized with the master clock to the first conversion device
  • the path delay causes the slave clock device to time its own clock according to the determined link delay between the first conversion device and the second conversion device.
  • the clock is synchronized by the second switching device that is synchronized with the clock, and the switching device adds a timestamp to the incoming and outgoing synchronization packets, and determines the chain by sending multiple time-stamped E1 packets.
  • the delay of the road avoids the influence of delay jitter of the E1 link and improves the accuracy of clock synchronization.
  • modules in the devices of the embodiments can be adaptively changed and placed in one or more devices different from the embodiment.
  • the modules or units or components of the embodiments may be combined into one module or unit or component, and further they may be divided into a plurality of sub-modules or sub-units or sub-components.
  • any combination of the features disclosed in the specification, including the accompanying claims, the abstract and the drawings, and any methods so disclosed may be employed. Or combine all the processes or units of the device.
  • Each feature disclosed in the specification (including the accompanying claims, the abstract and the drawings) may be replaced by alternative features that provide the same, equivalent, or similar purpose, unless otherwise stated.
  • the various component embodiments of the present invention may be implemented in hardware, or in a software module running on one or more processors, or in a combination thereof.
  • a microprocessor or digital signal processor can be used in practice to implement an E1 link-based IEEE 1588 clock synchronization apparatus and system, terminal device and system in accordance with an embodiment of the present invention.
  • the invention can also be implemented as a device or device program (e.g., a computer program and a computer program product) for performing some or all of the methods described herein.
  • Such a program implementing the present invention may be stored on a computer readable shield or may be in the form of one or more signals. Such signals may be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

La présente invention concerne un procédé, un système et un appareil de synchronisation d'horloge IEEE1588 sur la base d'une liaison E1, qui sont utilisés pour améliorer la précision d'une synchronisation d'horloge. Selon le procédé, un second dispositif de conversion conservant une synchronisation d'horloge avec un dispositif d'horloge esclave détermine un retard de liaison d'un premier dispositif de conversion au second dispositif de conversion selon un instant t2 de chaque estampille temporelle t1 dans de multiples paquets E1 reçus, reçoit un retard de liaison, envoyé par le premier dispositif de conversion conservant la synchronisation d'horloge avec une horloge maître, du second dispositif de conversion au premier dispositif de conversion, et réalise une synchronisation temporelle sur une horloge du dispositif d'horloge esclave selon le retard de liaison déterminé entre le premier dispositif de conversion et le second dispositif de conversion. Du fait que que la synchronisation d'horloge est réalisée par le second dispositif de conversion conservant la synchronisation d'horloge avec l'horloge esclave, des estampilles temporelles sont attachées à des paquets de synchronisation entrants et sortants au niveau du dispositif de conversion, et un retard de liaison est déterminé par un envoi de multiples paquets E1 transportant des estampilles temporelles, de sorte que l'influence causée par une gigue de délai de la liaison E1 soit évitée et que la précision de la synchronisation d'horloge soit améliorée.
PCT/CN2014/082620 2014-07-09 2014-07-21 Procédé, système et appareil de synchronisation d'horloge ieee1588 sur la base d'une liaison e1 WO2016004645A1 (fr)

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CN107786319A (zh) * 2016-08-25 2018-03-09 南京中兴新软件有限责任公司 一种时间同步方法及装置
CN106385299B (zh) * 2016-09-22 2018-02-02 国家电网公司 智能变电站维护业务类信息背景流的主从时钟同步方法
CN112202519A (zh) * 2020-08-26 2021-01-08 浙江双成电气有限公司 控制报文传输延时抖动的方法
CN112751641B (zh) * 2020-12-31 2022-10-21 网络通信与安全紫金山实验室 一种tsn网络时间同步方法、设备及储存介质

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